projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
PR26044, Some targets can't be compiled with GCC 10 (tilepro)
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
ab382d64
AM		 12020-05-28 Alan Modra <amodra@gmail.com>
2
3 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
4 immediates.
5 (print_insn_ns32k): Revert last change.
6
151f5de4
NC		 72020-05-28 Nick Clifton <nickc@redhat.com>
8
9 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
10 static.
11
25e1eca8
SL		 122020-05-26 Sandra Loosemore <sandra@codesourcery.com>
13
14 Fix extraction of signed constants in nios2 disassembler (again).
15
16 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
17 extractions of signed fields.
18
57b17940
SSF		 192020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
20
21 * s390-opc.txt: Relocate vector load/store instructions with
22 additional alignment parameter and change architecture level
23 constraint from z14 to z13.
24
d96bf37b
AM		 252020-05-21 Alan Modra <amodra@gmail.com>
26
27 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
28 * sparc-dis.c: Likewise.
29 * tic4x-dis.c: Likewise.
30 * xtensa-dis.c: Likewise.
31 * bpf-desc.c: Regenerate.
32 * epiphany-desc.c: Regenerate.
33 * fr30-desc.c: Regenerate.
34 * frv-desc.c: Regenerate.
35 * ip2k-desc.c: Regenerate.
36 * iq2000-desc.c: Regenerate.
37 * lm32-desc.c: Regenerate.
38 * m32c-desc.c: Regenerate.
39 * m32r-desc.c: Regenerate.
40 * mep-asm.c: Regenerate.
41 * mep-desc.c: Regenerate.
42 * mt-desc.c: Regenerate.
43 * or1k-desc.c: Regenerate.
44 * xc16x-desc.c: Regenerate.
45 * xstormy16-desc.c: Regenerate.
46
8f595e9b
NC		 472020-05-20 Nelson Chu <nelson.chu@sifive.com>
48
49 * riscv-opc.c (riscv_ext_version_table): The table used to store
50 all information about the supported spec and the corresponding ISA
51 versions. Currently, only Zicsr is supported to verify the
52 correctness of Z sub extension settings. Others will be supported
53 in the future patches.
54 (struct isa_spec_t, isa_specs): List for all supported ISA spec
55 classes and the corresponding strings.
56 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
57 spec class by giving a ISA spec string.
58 * riscv-opc.c (struct priv_spec_t): New structure.
59 (struct priv_spec_t priv_specs): List for all supported privilege spec
60 classes and the corresponding strings.
61 (riscv_get_priv_spec_class): New function. Get the corresponding
62 privilege spec class by giving a spec string.
63 (riscv_get_priv_spec_name): New function. Get the corresponding
64 privilege spec string by giving a CSR version class.
65 * riscv-dis.c: Updated since DECLARE_CSR is changed.
66 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
67 according to the chosen version. Build a hash table riscv_csr_hash to
68 store the valid CSR for the chosen pirv verison. Dump the direct
69 CSR address rather than it's name if it is invalid.
70 (parse_riscv_dis_option_without_args): New function. Parse the options
71 without arguments.
72 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
73 parse the options without arguments first, and then handle the options
74 with arguments. Add the new option -Mpriv-spec, which has argument.
75 * riscv-dis.c (print_riscv_disassembler_options): Add description
76 about the new OBJDUMP option.
77
3d205eb4
PB		 782020-05-19 Peter Bergner <bergner@linux.ibm.com>
79
80 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
81 WC values on POWER10 sync, dcbf and wait instructions.
82 (insert_pl, extract_pl): New functions.
83 (L2OPT, LS, WC): Use insert_ls and extract_ls.
84 (LS3): New , 3-bit L for sync.
85 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
86 (SC2, PL): New, 2-bit SC and PL for sync and wait.
87 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
88 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
89 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
90 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
91 <wait>: Enable PL operand on POWER10.
92 <dcbf>: Enable L3OPT operand on POWER10.
93 <sync>: Enable SC2 operand on POWER10.
94
a501eb44
SH		 952020-05-19 Stafford Horne <shorne@gmail.com>
96
97 PR 25184
98 * or1k-asm.c: Regenerate.
99 * or1k-desc.c: Regenerate.
100 * or1k-desc.h: Regenerate.
101 * or1k-dis.c: Regenerate.
102 * or1k-ibld.c: Regenerate.
103 * or1k-opc.c: Regenerate.
104 * or1k-opc.h: Regenerate.
105 * or1k-opinst.c: Regenerate.
106
3b646889
AM		 1072020-05-11 Alan Modra <amodra@gmail.com>
108
109 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
110 xsmaxcqp, xsmincqp.
111
9cc4ce88
AM		 1122020-05-11 Alan Modra <amodra@gmail.com>
113
114 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
115 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
116
5d57bc3f
AM		 1172020-05-11 Alan Modra <amodra@gmail.com>
118
119 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
120
66ef5847
AM		 1212020-05-11 Alan Modra <amodra@gmail.com>
122
123 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
124 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
125
4f3e9537
PB		 1262020-05-11 Peter Bergner <bergner@linux.ibm.com>
127
128 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
129 mnemonics.
130
ec40e91c
AM		 1312020-05-11 Alan Modra <amodra@gmail.com>
132
133 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
134 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
135 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
136 (prefix_opcodes): Add xxeval.
137
d7e97a76
AM		 1382020-05-11 Alan Modra <amodra@gmail.com>
139
140 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
141 xxgenpcvwm, xxgenpcvdm.
142
fdefed7c
AM		 1432020-05-11 Alan Modra <amodra@gmail.com>
144
145 * ppc-opc.c (MP, VXVAM_MASK): Define.
146 (VXVAPS_MASK): Use VXVA_MASK.
147 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
148 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
149 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
150 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
151
aa3c112f
AM		 1522020-05-11 Alan Modra <amodra@gmail.com>
153 Peter Bergner <bergner@linux.ibm.com>
154
155 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
156 New functions.
157 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
158 YMSK2, XA6a, XA6ap, XB6a entries.
159 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
160 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
161 (PPCVSX4): Define.
162 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
163 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
164 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
165 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
166 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
167 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
168 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
169 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
170 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
171 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
172 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
173 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
174 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
175 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
176
6edbfd3b
AM		 1772020-05-11 Alan Modra <amodra@gmail.com>
178
179 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
180 (insert_xts, extract_xts): New functions.
181 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
182 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
183 (VXRC_MASK, VXSH_MASK): Define.
184 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
185 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
186 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
187 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
188 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
189 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
190 xxblendvh, xxblendvw, xxblendvd, xxpermx.
191
c7d7aea2
AM		 1922020-05-11 Alan Modra <amodra@gmail.com>
193
194 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
195 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
196 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
197 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
198 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
199
94ba9882
AM		 2002020-05-11 Alan Modra <amodra@gmail.com>
201
202 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
203 (XTP, DQXP, DQXP_MASK): Define.
204 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
205 (prefix_opcodes): Add plxvp and pstxvp.
206
f4791f1a
AM		 2072020-05-11 Alan Modra <amodra@gmail.com>
208
209 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
210 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
211 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
212
3ff0a5ba
PB		 2132020-05-11 Peter Bergner <bergner@linux.ibm.com>
214
215 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
216
afef4fe9
PB		 2172020-05-11 Peter Bergner <bergner@linux.ibm.com>
218
219 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
220 (L1OPT): Define.
221 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
222
1224c05d
PB		 2232020-05-11 Peter Bergner <bergner@linux.ibm.com>
224
225 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
226
6bbb0c05
AM		 2272020-05-11 Alan Modra <amodra@gmail.com>
228
229 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
230
7c1f4227
AM		 2312020-05-11 Alan Modra <amodra@gmail.com>
232
233 * ppc-dis.c (ppc_opts): Add "power10" entry.
234 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
235 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
236
73199c2b
NC		 2372020-05-11 Nick Clifton <nickc@redhat.com>
238
239 * po/fr.po: Updated French translation.
240
09c1e68a
AC		 2412020-04-30 Alex Coplan <alex.coplan@arm.com>
242
243 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
244 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
245 (operand_general_constraint_met_p): validate
246 AARCH64_OPND_UNDEFINED.
247 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
248 for FLD_imm16_2.
249 * aarch64-asm-2.c: Regenerated.
250 * aarch64-dis-2.c: Regenerated.
251 * aarch64-opc-2.c: Regenerated.
252
9654d51a
NC		 2532020-04-29 Nick Clifton <nickc@redhat.com>
254
255 PR 22699
256 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
257 and SETRC insns.
258
c2e71e57
NC		 2592020-04-29 Nick Clifton <nickc@redhat.com>
260
261 * po/sv.po: Updated Swedish translation.
262
5c936ef5
NC		 2632020-04-29 Nick Clifton <nickc@redhat.com>
264
265 PR 22699
266 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
267 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
268 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
269 IMM0_8U case.
270
bb2a1453
AS		 2712020-04-21 Andreas Schwab <schwab@linux-m68k.org>
272
273 PR 25848
274 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
275 cmpi only on m68020up and cpu32.
276
c2e5c986
SD		 2772020-04-20 Sudakshina Das <sudi.das@arm.com>
278
279 * aarch64-asm.c (aarch64_ins_none): New.
280 * aarch64-asm.h (ins_none): New declaration.
281 * aarch64-dis.c (aarch64_ext_none): New.
282 * aarch64-dis.h (ext_none): New declaration.
283 * aarch64-opc.c (aarch64_print_operand): Update case for
284 AARCH64_OPND_BARRIER_PSB.
285 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
286 (AARCH64_OPERANDS): Update inserter/extracter for
287 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
288 * aarch64-asm-2.c: Regenerated.
289 * aarch64-dis-2.c: Regenerated.
290 * aarch64-opc-2.c: Regenerated.
291
8a6e1d1d
SD		 2922020-04-20 Sudakshina Das <sudi.das@arm.com>
293
294 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
295 (aarch64_feature_ras, RAS): Likewise.
296 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
297 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
298 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
299 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
300 * aarch64-asm-2.c: Regenerated.
301 * aarch64-dis-2.c: Regenerated.
302 * aarch64-opc-2.c: Regenerated.
303
e409955d
FS		 3042020-04-17 Fredrik Strupe <fredrik@strupe.net>
305
306 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
307 (print_insn_neon): Support disassembly of conditional
308 instructions.
309
c54a9b56
DF		 3102020-02-16 David Faust <david.faust@oracle.com>
311
312 * bpf-desc.c: Regenerate.
313 * bpf-desc.h: Likewise.
314 * bpf-opc.c: Regenerate.
315 * bpf-opc.h: Likewise.
316
bb651e8b
CL		 3172020-04-07 Lili Cui <lili.cui@intel.com>
318
319 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
320 (prefix_table): New instructions (see prefixes above).
321 (rm_table): Likewise
322 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
323 CPU_ANY_TSXLDTRK_FLAGS.
324 (cpu_flags): Add CpuTSXLDTRK.
325 * i386-opc.h (enum): Add CpuTSXLDTRK.
326 (i386_cpu_flags): Add cputsxldtrk.
327 * i386-opc.tbl: Add XSUSPLDTRK insns.
328 * i386-init.h: Regenerate.
329 * i386-tbl.h: Likewise.
330
4b27d27c
L		 3312020-04-02 Lili Cui <lili.cui@intel.com>
332
333 * i386-dis.c (prefix_table): New instructions serialize.
334 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
335 CPU_ANY_SERIALIZE_FLAGS.
336 (cpu_flags): Add CpuSERIALIZE.
337 * i386-opc.h (enum): Add CpuSERIALIZE.
338 (i386_cpu_flags): Add cpuserialize.
339 * i386-opc.tbl: Add SERIALIZE insns.
340 * i386-init.h: Regenerate.
341 * i386-tbl.h: Likewise.
342
832a5807
AM		 3432020-03-26 Alan Modra <amodra@gmail.com>
344
345 * disassemble.h (opcodes_assert): Declare.
346 (OPCODES_ASSERT): Define.
347 * disassemble.c: Don't include assert.h. Include opintl.h.
348 (opcodes_assert): New function.
349 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
350 (bfd_h8_disassemble): Reduce size of data array. Correctly
351 calculate maxlen. Omit insn decoding when insn length exceeds
352 maxlen. Exit from nibble loop when looking for E, before
353 accessing next data byte. Move processing of E outside loop.
354 Replace tests of maxlen in loop with assertions.
355
4c4addbe
AM		 3562020-03-26 Alan Modra <amodra@gmail.com>
357
358 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
359
a18cd0ca
AM		 3602020-03-25 Alan Modra <amodra@gmail.com>
361
362 * z80-dis.c (suffix): Init mybuf.
363
57cb32b3
AM		 3642020-03-22 Alan Modra <amodra@gmail.com>
365
366 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
367 successflly read from section.
368
beea5cc1
AM		 3692020-03-22 Alan Modra <amodra@gmail.com>
370
371 * arc-dis.c (find_format): Use ISO C string concatenation rather
372 than line continuation within a string. Don't access needs_limm
373 before testing opcode != NULL.
374
03704c77
AM		 3752020-03-22 Alan Modra <amodra@gmail.com>
376
377 * ns32k-dis.c (print_insn_arg): Update comment.
378 (print_insn_ns32k): Reduce size of index_offset array, and
379 initialize, passing -1 to print_insn_arg for args that are not
380 an index. Don't exit arg loop early. Abort on bad arg number.
381
d1023b5d
AM		 3822020-03-22 Alan Modra <amodra@gmail.com>
383
384 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
385 * s12z-opc.c: Formatting.
386 (operands_f): Return an int.
387 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
388 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
389 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
390 (exg_sex_discrim): Likewise.
391 (create_immediate_operand, create_bitfield_operand),
392 (create_register_operand_with_size, create_register_all_operand),
393 (create_register_all16_operand, create_simple_memory_operand),
394 (create_memory_operand, create_memory_auto_operand): Don't
395 segfault on malloc failure.
396 (z_ext24_decode): Return an int status, negative on fail, zero
397 on success.
398 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
399 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
400 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
401 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
402 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
403 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
404 (loop_primitive_decode, shift_decode, psh_pul_decode),
405 (bit_field_decode): Similarly.
406 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
407 to return value, update callers.
408 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
409 Don't segfault on NULL operand.
410 (decode_operation): Return OP_INVALID on first fail.
411 (decode_s12z): Check all reads, returning -1 on fail.
412
340f3ac8
AM		 4132020-03-20 Alan Modra <amodra@gmail.com>
414
415 * metag-dis.c (print_insn_metag): Don't ignore status from
416 read_memory_func.
417
fe90ae8a
AM		 4182020-03-20 Alan Modra <amodra@gmail.com>
419
420 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
421 Initialize parts of buffer not written when handling a possible
422 2-byte insn at end of section. Don't attempt decoding of such
423 an insn by the 4-byte machinery.
424
833d919c
AM		 4252020-03-20 Alan Modra <amodra@gmail.com>
426
427 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
428 partially filled buffer. Prevent lookup of 4-byte insns when
429 only VLE 2-byte insns are possible due to section size. Print
430 ".word" rather than ".long" for 2-byte leftovers.
431
327ef784
NC		 4322020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
433
434 PR 25641
435 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
436
1673df32
JB		 4372020-03-13 Jan Beulich <jbeulich@suse.com>
438
439 * i386-dis.c (X86_64_0D): Rename to ...
440 (X86_64_0E): ... this.
441
384f3689
L		 4422020-03-09 H.J. Lu <hongjiu.lu@intel.com>
443
444 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
445 * Makefile.in: Regenerated.
446
865e2027
JB		 4472020-03-09 Jan Beulich <jbeulich@suse.com>
448
449 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
450 3-operand pseudos.
451 * i386-tbl.h: Re-generate.
452
2f13234b
JB		 4532020-03-09 Jan Beulich <jbeulich@suse.com>
454
455 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
456 vprot*, vpsha*, and vpshl*.
457 * i386-tbl.h: Re-generate.
458
3fabc179
JB		 4592020-03-09 Jan Beulich <jbeulich@suse.com>
460
461 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
462 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
463 * i386-tbl.h: Re-generate.
464
3677e4c1
JB		 4652020-03-09 Jan Beulich <jbeulich@suse.com>
466
467 * i386-gen.c (set_bitfield): Ignore zero-length field names.
468 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
469 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
470 * i386-tbl.h: Re-generate.
471
4c4898e8
JB		 4722020-03-09 Jan Beulich <jbeulich@suse.com>
473
474 * i386-gen.c (struct template_arg, struct template_instance,
475 struct template_param, struct template, templates,
476 parse_template, expand_templates): New.
477 (process_i386_opcodes): Various local variables moved to
478 expand_templates. Call parse_template and expand_templates.
479 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
480 * i386-tbl.h: Re-generate.
481
bc49bfd8
JB		 4822020-03-06 Jan Beulich <jbeulich@suse.com>
483
484 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
485 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
486 register and memory source templates. Replace VexW= by VexW*
487 where applicable.
488 * i386-tbl.h: Re-generate.
489
4873e243
JB		 4902020-03-06 Jan Beulich <jbeulich@suse.com>
491
492 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
493 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
494 * i386-tbl.h: Re-generate.
495
672a349b
JB		 4962020-03-06 Jan Beulich <jbeulich@suse.com>
497
498 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
499 * i386-tbl.h: Re-generate.
500
4ed21b58
JB		 5012020-03-06 Jan Beulich <jbeulich@suse.com>
502
503 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
504 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
505 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
506 VexW0 on SSE2AVX variants.
507 (vmovq): Drop NoRex64 from XMM/XMM variants.
508 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
509 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
510 applicable use VexW0.
511 * i386-tbl.h: Re-generate.
512
643bb870
JB		 5132020-03-06 Jan Beulich <jbeulich@suse.com>
514
515 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
516 * i386-opc.h (Rex64): Delete.
517 (struct i386_opcode_modifier): Remove rex64 field.
518 * i386-opc.tbl (crc32): Drop Rex64.
519 Replace Rex64 with Size64 everywhere else.
520 * i386-tbl.h: Re-generate.
521
a23b33b3
JB		 5222020-03-06 Jan Beulich <jbeulich@suse.com>
523
524 * i386-dis.c (OP_E_memory): Exclude recording of used address
525 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
526 addressed memory operands for MPX insns.
527
a0497384
JB		 5282020-03-06 Jan Beulich <jbeulich@suse.com>
529
530 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
531 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
532 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
533 (ptwrite): Split into non-64-bit and 64-bit forms.
534 * i386-tbl.h: Re-generate.
535
b630c145
JB		 5362020-03-06 Jan Beulich <jbeulich@suse.com>
537
538 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
539 template.
540 * i386-tbl.h: Re-generate.
541
a847e322
JB		 5422020-03-04 Jan Beulich <jbeulich@suse.com>
543
544 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
545 (prefix_table): Move vmmcall here. Add vmgexit.
546 (rm_table): Replace vmmcall entry by prefix_table[] escape.
547 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
548 (cpu_flags): Add CpuSEV_ES entry.
549 * i386-opc.h (CpuSEV_ES): New.
550 (union i386_cpu_flags): Add cpusev_es field.
551 * i386-opc.tbl (vmgexit): New.
552 * i386-init.h, i386-tbl.h: Re-generate.
553
3cd7f3e3
L		 5542020-03-03 H.J. Lu <hongjiu.lu@intel.com>
555
556 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
557 with MnemonicSize.
558 * i386-opc.h (IGNORESIZE): New.
559 (DEFAULTSIZE): Likewise.
560 (IgnoreSize): Removed.
561 (DefaultSize): Likewise.
562 (MnemonicSize): New.
563 (i386_opcode_modifier): Replace ignoresize/defaultsize with
564 mnemonicsize.
565 * i386-opc.tbl (IgnoreSize): New.
566 (DefaultSize): Likewise.
567 * i386-tbl.h: Regenerated.
568
b8ba1385
SB		 5692020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
570
571 PR 25627
572 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
573 instructions.
574
10d97a0f
L		 5752020-03-03 H.J. Lu <hongjiu.lu@intel.com>
576
577 PR gas/25622
578 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
579 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
580 * i386-tbl.h: Regenerated.
581
dc1e8a47
AM		 5822020-02-26 Alan Modra <amodra@gmail.com>
583
584 * aarch64-asm.c: Indent labels correctly.
585 * aarch64-dis.c: Likewise.
586 * aarch64-gen.c: Likewise.
587 * aarch64-opc.c: Likewise.
588 * alpha-dis.c: Likewise.
589 * i386-dis.c: Likewise.
590 * nds32-asm.c: Likewise.
591 * nfp-dis.c: Likewise.
592 * visium-dis.c: Likewise.
593
265b4673
CZ		 5942020-02-25 Claudiu Zissulescu <claziss@gmail.com>
595
596 * arc-regs.h (int_vector_base): Make it available for all ARC
597 CPUs.
598
bd0cf5a6
NC		 5992020-02-20 Nelson Chu <nelson.chu@sifive.com>
600
601 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
602 changed.
603
fa164239
JW		 6042020-02-19 Nelson Chu <nelson.chu@sifive.com>
605
606 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
607 c.mv/c.li if rs1 is zero.
608
272a84b1
L		 6092020-02-17 H.J. Lu <hongjiu.lu@intel.com>
610
611 * i386-gen.c (cpu_flag_init): Replace CpuABM with
612 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
613 CPU_POPCNT_FLAGS.
614 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
615 * i386-opc.h (CpuABM): Removed.
616 (CpuPOPCNT): New.
617 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
618 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
619 popcnt. Remove CpuABM from lzcnt.
620 * i386-init.h: Regenerated.
621 * i386-tbl.h: Likewise.
622
1f730c46
JB		 6232020-02-17 Jan Beulich <jbeulich@suse.com>
624
625 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
626 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
627 VexW1 instead of open-coding them.
628 * i386-tbl.h: Re-generate.
629
c8f8eebc
JB		 6302020-02-17 Jan Beulich <jbeulich@suse.com>
631
632 * i386-opc.tbl (AddrPrefixOpReg): Define.
633 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
634 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
635 templates. Drop NoRex64.
636 * i386-tbl.h: Re-generate.
637
b9915cbc
JB		 6382020-02-17 Jan Beulich <jbeulich@suse.com>
639
640 PR gas/6518
641 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
642 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
643 into Intel syntax instance (with Unpsecified) and AT&T one
644 (without).
645 (vcvtneps2bf16): Likewise, along with folding the two so far
646 separate ones.
647 * i386-tbl.h: Re-generate.
648
ce504911
L		 6492020-02-16 H.J. Lu <hongjiu.lu@intel.com>
650
651 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
652 CPU_ANY_SSE4A_FLAGS.
653
dabec65d
AM		 6542020-02-17 Alan Modra <amodra@gmail.com>
655
656 * i386-gen.c (cpu_flag_init): Correct last change.
657
af5c13b0
L		 6582020-02-16 H.J. Lu <hongjiu.lu@intel.com>
659
660 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
661 CPU_ANY_SSE4_FLAGS.
662
6867aac0
L		 6632020-02-14 H.J. Lu <hongjiu.lu@intel.com>
664
665 * i386-opc.tbl (movsx): Remove Intel syntax comments.
666 (movzx): Likewise.
667
65fca059
JB		 6682020-02-14 Jan Beulich <jbeulich@suse.com>
669
670 PR gas/25438
671 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
672 destination for Cpu64-only variant.
673 (movzx): Fold patterns.
674 * i386-tbl.h: Re-generate.
675
7deea9aa
JB		 6762020-02-13 Jan Beulich <jbeulich@suse.com>
677
678 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
679 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
680 CPU_ANY_SSE4_FLAGS entry.
681 * i386-init.h: Re-generate.
682
6c0946d0
JB		 6832020-02-12 Jan Beulich <jbeulich@suse.com>
684
685 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
686 with Unspecified, making the present one AT&T syntax only.
687 * i386-tbl.h: Re-generate.
688
ddb56fe6
JB		 6892020-02-12 Jan Beulich <jbeulich@suse.com>
690
691 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
692 * i386-tbl.h: Re-generate.
693
5990e377
JB		 6942020-02-12 Jan Beulich <jbeulich@suse.com>
695
696 PR gas/24546
697 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
698 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
699 Amd64 and Intel64 templates.
700 (call, jmp): Likewise for far indirect variants. Dro
701 Unspecified.
702 * i386-tbl.h: Re-generate.
703
50128d0c
JB		 7042020-02-11 Jan Beulich <jbeulich@suse.com>
705
706 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
707 * i386-opc.h (ShortForm): Delete.
708 (struct i386_opcode_modifier): Remove shortform field.
709 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
710 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
711 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
712 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
713 Drop ShortForm.
714 * i386-tbl.h: Re-generate.
715
1e05b5c4
JB		 7162020-02-11 Jan Beulich <jbeulich@suse.com>
717
718 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
719 fucompi): Drop ShortForm from operand-less templates.
720 * i386-tbl.h: Re-generate.
721
2f5dd314
AM		 7222020-02-11 Alan Modra <amodra@gmail.com>
723
724 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
725 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
726 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
727 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
728 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
729
5aae9ae9
MM		 7302020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
731
732 * arm-dis.c (print_insn_cde): Define 'V' parse character.
733 (cde_opcodes): Add VCX* instructions.
734
4934a27c
MM		 7352020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
736 Matthew Malcomson <matthew.malcomson@arm.com>
737
738 * arm-dis.c (struct cdeopcode32): New.
739 (CDE_OPCODE): New macro.
740 (cde_opcodes): New disassembly table.
741 (regnames): New option to table.
742 (cde_coprocs): New global variable.
743 (print_insn_cde): New
744 (print_insn_thumb32): Use print_insn_cde.
745 (parse_arm_disassembler_options): Parse coprocN args.
746
4b5aaf5f
L		 7472020-02-10 H.J. Lu <hongjiu.lu@intel.com>
748
749 PR gas/25516
750 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
751 with ISA64.
752 * i386-opc.h (AMD64): Removed.
753 (Intel64): Likewose.
754 (AMD64): New.
755 (INTEL64): Likewise.
756 (INTEL64ONLY): Likewise.
757 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
758 * i386-opc.tbl (Amd64): New.
759 (Intel64): Likewise.
760 (Intel64Only): Likewise.
761 Replace AMD64 with Amd64. Update sysenter/sysenter with
762 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
763 * i386-tbl.h: Regenerated.
764
9fc0b501
SB		 7652020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
766
767 PR 25469
768 * z80-dis.c: Add support for GBZ80 opcodes.
769
c5d7be0c
AM		 7702020-02-04 Alan Modra <amodra@gmail.com>
771
772 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
773
44e4546f
AM		 7742020-02-03 Alan Modra <amodra@gmail.com>
775
776 * m32c-ibld.c: Regenerate.
777
b2b1453a
AM		 7782020-02-01 Alan Modra <amodra@gmail.com>
779
780 * frv-ibld.c: Regenerate.
781
4102be5c
JB		 7822020-01-31 Jan Beulich <jbeulich@suse.com>
783
784 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
785 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
786 (OP_E_memory): Replace xmm_mdq_mode case label by
787 vex_scalar_w_dq_mode one.
788 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
789
825bd36c
JB		 7902020-01-31 Jan Beulich <jbeulich@suse.com>
791
792 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
793 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
794 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
795 (intel_operand_size): Drop vex_w_dq_mode case label.
796
c3036ed0
RS		 7972020-01-31 Richard Sandiford <richard.sandiford@arm.com>
798
799 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
800 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
801
0c115f84
AM		 8022020-01-30 Alan Modra <amodra@gmail.com>
803
804 * m32c-ibld.c: Regenerate.
805
bd434cc4
JM		 8062020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
807
808 * bpf-opc.c: Regenerate.
809
aeab2b26
JB		 8102020-01-30 Jan Beulich <jbeulich@suse.com>
811
812 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
813 (dis386): Use them to replace C2/C3 table entries.
814 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
815 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
816 ones. Use Size64 instead of DefaultSize on Intel64 ones.
817 * i386-tbl.h: Re-generate.
818
62b3f548
JB		 8192020-01-30 Jan Beulich <jbeulich@suse.com>
820
821 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
822 forms.
823 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
824 DefaultSize.
825 * i386-tbl.h: Re-generate.
826
1bd8ae10
AM		 8272020-01-30 Alan Modra <amodra@gmail.com>
828
829 * tic4x-dis.c (tic4x_dp): Make unsigned.
830
bc31405e
L		 8312020-01-27 H.J. Lu <hongjiu.lu@intel.com>
832 Jan Beulich <jbeulich@suse.com>
833
834 PR binutils/25445
835 * i386-dis.c (MOVSXD_Fixup): New function.
836 (movsxd_mode): New enum.
837 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
838 (intel_operand_size): Handle movsxd_mode.
839 (OP_E_register): Likewise.
840 (OP_G): Likewise.
841 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
842 register on movsxd. Add movsxd with 16-bit destination register
843 for AMD64 and Intel64 ISAs.
844 * i386-tbl.h: Regenerated.
845
7568c93b
TC		 8462020-01-27 Tamar Christina <tamar.christina@arm.com>
847
848 PR 25403
849 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
850 * aarch64-asm-2.c: Regenerate
851 * aarch64-dis-2.c: Likewise.
852 * aarch64-opc-2.c: Likewise.
853
c006a730
JB		 8542020-01-21 Jan Beulich <jbeulich@suse.com>
855
856 * i386-opc.tbl (sysret): Drop DefaultSize.
857 * i386-tbl.h: Re-generate.
858
c906a69a
JB		 8592020-01-21 Jan Beulich <jbeulich@suse.com>
860
861 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
862 Dword.
863 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
864 * i386-tbl.h: Re-generate.
865
26916852
NC		 8662020-01-20 Nick Clifton <nickc@redhat.com>
867
868 * po/de.po: Updated German translation.
869 * po/pt_BR.po: Updated Brazilian Portuguese translation.
870 * po/uk.po: Updated Ukranian translation.
871
4d6cbb64
AM		 8722020-01-20 Alan Modra <amodra@gmail.com>
873
874 * hppa-dis.c (fput_const): Remove useless cast.
875
2bddb71a
AM		 8762020-01-20 Alan Modra <amodra@gmail.com>
877
878 * arm-dis.c (print_insn_arm): Wrap 'T' value.
879
1b1bb2c6
NC		 8802020-01-18 Nick Clifton <nickc@redhat.com>
881
882 * configure: Regenerate.
883 * po/opcodes.pot: Regenerate.
884
ae774686
NC		 8852020-01-18 Nick Clifton <nickc@redhat.com>
886
887 Binutils 2.34 branch created.
888
07f1f3aa
CB		 8892020-01-17 Christian Biesinger <cbiesinger@google.com>
890
891 * opintl.h: Fix spelling error (seperate).
892
42e04b36
L		 8932020-01-17 H.J. Lu <hongjiu.lu@intel.com>
894
895 * i386-opc.tbl: Add {vex} pseudo prefix.
896 * i386-tbl.h: Regenerated.
897
2da2eaf4
AV		 8982020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
899
900 PR 25376
901 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
902 (neon_opcodes): Likewise.
903 (select_arm_features): Make sure we enable MVE bits when selecting
904 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
905 any architecture.
906
d0849eed
JB		 9072020-01-16 Jan Beulich <jbeulich@suse.com>
908
909 * i386-opc.tbl: Drop stale comment from XOP section.
910
9cf70a44
JB		 9112020-01-16 Jan Beulich <jbeulich@suse.com>
912
913 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
914 (extractps): Add VexWIG to SSE2AVX forms.
915 * i386-tbl.h: Re-generate.
916
4814632e
JB		 9172020-01-16 Jan Beulich <jbeulich@suse.com>
918
919 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
920 Size64 from and use VexW1 on SSE2AVX forms.
921 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
922 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
923 * i386-tbl.h: Re-generate.
924
aad09917
AM		 9252020-01-15 Alan Modra <amodra@gmail.com>
926
927 * tic4x-dis.c (tic4x_version): Make unsigned long.
928 (optab, optab_special, registernames): New file scope vars.
929 (tic4x_print_register): Set up registernames rather than
930 malloc'd registertable.
931 (tic4x_disassemble): Delete optable and optable_special. Use
932 optab and optab_special instead. Throw away old optab,
933 optab_special and registernames when info->mach changes.
934
7a6bf3be
SB		 9352020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
936
937 PR 25377
938 * z80-dis.c (suffix): Use .db instruction to generate double
939 prefix.
940
ca1eaac0
AM		 9412020-01-14 Alan Modra <amodra@gmail.com>
942
943 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
944 values to unsigned before shifting.
945
1d67fe3b
TT		 9462020-01-13 Thomas Troeger <tstroege@gmx.de>
947
948 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
949 flow instructions.
950 (print_insn_thumb16, print_insn_thumb32): Likewise.
951 (print_insn): Initialize the insn info.
952 * i386-dis.c (print_insn): Initialize the insn info fields, and
953 detect jumps.
954
5e4f7e05
CZ		 9552012-01-13 Claudiu Zissulescu <claziss@gmail.com>
956
957 * arc-opc.c (C_NE): Make it required.
958
b9fe6b8a
CZ		 9592012-01-13 Claudiu Zissulescu <claziss@gmail.com>
960
961 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
962 reserved register name.
963
90dee485
AM		 9642020-01-13 Alan Modra <amodra@gmail.com>
965
966 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
967 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
968
febda64f
AM		 9692020-01-13 Alan Modra <amodra@gmail.com>
970
971 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
972 result of wasm_read_leb128 in a uint64_t and check that bits
973 are not lost when copying to other locals. Use uint32_t for
974 most locals. Use PRId64 when printing int64_t.
975
df08b588
AM		 9762020-01-13 Alan Modra <amodra@gmail.com>
977
978 * score-dis.c: Formatting.
979 * score7-dis.c: Formatting.
980
b2c759ce
AM		 9812020-01-13 Alan Modra <amodra@gmail.com>
982
983 * score-dis.c (print_insn_score48): Use unsigned variables for
984 unsigned values. Don't left shift negative values.
985 (print_insn_score32): Likewise.
986 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
987
5496abe1
AM		 9882020-01-13 Alan Modra <amodra@gmail.com>
989
990 * tic4x-dis.c (tic4x_print_register): Remove dead code.
991
202e762b
AM		 9922020-01-13 Alan Modra <amodra@gmail.com>
993
994 * fr30-ibld.c: Regenerate.
995
7ef412cf
AM		 9962020-01-13 Alan Modra <amodra@gmail.com>
997
998 * xgate-dis.c (print_insn): Don't left shift signed value.
999 (ripBits): Formatting, use 1u.
1000
7f578b95
AM		 10012020-01-10 Alan Modra <amodra@gmail.com>
1002
1003 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1004 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
1005
441af85b
AM		 10062020-01-10 Alan Modra <amodra@gmail.com>
1007
1008 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1009 and XRREG value earlier to avoid a shift with negative exponent.
1010 * m10200-dis.c (disassemble): Similarly.
1011
bce58db4
NC		 10122020-01-09 Nick Clifton <nickc@redhat.com>
1013
1014 PR 25224
1015 * z80-dis.c (ld_ii_ii): Use correct cast.
1016
40c75bc8
SB		 10172020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1018
1019 PR 25224
1020 * z80-dis.c (ld_ii_ii): Use character constant when checking
1021 opcode byte value.
1022
d835a58b
JB		 10232020-01-09 Jan Beulich <jbeulich@suse.com>
1024
1025 * i386-dis.c (SEP_Fixup): New.
1026 (SEP): Define.
1027 (dis386_twobyte): Use it for sysenter/sysexit.
1028 (enum x86_64_isa): Change amd64 enumerator to value 1.
1029 (OP_J): Compare isa64 against intel64 instead of amd64.
1030 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1031 forms.
1032 * i386-tbl.h: Re-generate.
1033
030a2e78
AM		 10342020-01-08 Alan Modra <amodra@gmail.com>
1035
1036 * z8k-dis.c: Include libiberty.h
1037 (instr_data_s): Make max_fetched unsigned.
1038 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1039 Don't exceed byte_info bounds.
1040 (output_instr): Make num_bytes unsigned.
1041 (unpack_instr): Likewise for nibl_count and loop.
1042 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1043 idx unsigned.
1044 * z8k-opc.h: Regenerate.
1045
bb82aefe
SV		 10462020-01-07 Shahab Vahedi <shahab@synopsys.com>
1047
1048 * arc-tbl.h (llock): Use 'LLOCK' as class.
1049 (llockd): Likewise.
1050 (scond): Use 'SCOND' as class.
1051 (scondd): Likewise.
1052 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1053 (scondd): Likewise.
1054
cc6aa1a6
AM		 10552020-01-06 Alan Modra <amodra@gmail.com>
1056
1057 * m32c-ibld.c: Regenerate.
1058
660e62b1
AM		 10592020-01-06 Alan Modra <amodra@gmail.com>
1060
1061 PR 25344
1062 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1063 Peek at next byte to prevent recursion on repeated prefix bytes.
1064 Ensure uninitialised "mybuf" is not accessed.
1065 (print_insn_z80): Don't zero n_fetch and n_used here,..
1066 (print_insn_z80_buf): ..do it here instead.
1067
c9ae58fe
AM		 10682020-01-04 Alan Modra <amodra@gmail.com>
1069
1070 * m32r-ibld.c: Regenerate.
1071
5f57d4ec
AM		 10722020-01-04 Alan Modra <amodra@gmail.com>
1073
1074 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1075
2c5c1196
AM		 10762020-01-04 Alan Modra <amodra@gmail.com>
1077
1078 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1079
2e98c6c5
AM		 10802020-01-04 Alan Modra <amodra@gmail.com>
1081
1082 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1083
567dfba2
JB		 10842020-01-03 Jan Beulich <jbeulich@suse.com>
1085
5437a02a
JB		 1086 * aarch64-tbl.h (aarch64_opcode_table): Use
1087 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1088
10892020-01-03 Jan Beulich <jbeulich@suse.com>
1090
1091 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 1092 forms of SUDOT and USDOT.
1093
8c45011a
JB		 10942020-01-03 Jan Beulich <jbeulich@suse.com>
1095
5437a02a 1096 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 1097 uzip{1,2}.
1098 * opcodes/aarch64-dis-2.c: Re-generate.
1099
f4950f76
JB		 11002020-01-03 Jan Beulich <jbeulich@suse.com>
1101
5437a02a 1102 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 1103 FMMLA encoding.
1104 * opcodes/aarch64-dis-2.c: Re-generate.
1105
6655dba2
SB		 11062020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1107
1108 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1109
b14ce8bf
AM		 11102020-01-01 Alan Modra <amodra@gmail.com>
1111
1112 Update year range in copyright notice of all files.
1113
0b114740 1114For older changes see ChangeLog-2019
3499769a 1115\f
0b114740 1116Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 1117
1118Copying and distribution of this file, with or without modification,
1119are permitted in any medium without royalty provided the copyright
1120notice and this notice are preserved.
1121
1122Local Variables:
1123mode: change-log
1124left-margin: 8
1125fill-column: 74
1126version-control: never
1127End:
GDB Binutils - Deliverables
This page took 0.296633 seconds and 4 git commands to generate.