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x86: Add GC testcases with property sections
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
535b785f
AM		 12017-05-18 Alan Modra <amodra@gmail.com>
2
3 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
4 * aarch64-dis.c: Likewise.
5 * aarch64-gen.c: Likewise.
6 * aarch64-opc.c: Likewise.
7
25499ac7
MR		 82017-05-15 Maciej W. Rozycki <macro@imgtec.com>
9 Matthew Fortune <matthew.fortune@imgtec.com>
10
11 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
12 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
13 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
14 (print_insn_arg) <OP_REG28>: Add handler.
15 (validate_insn_args) <OP_REG28>: Handle.
16 (print_mips16_insn_arg): Handle MIPS16 instructions that require
17 32-bit encoding and 9-bit immediates.
18 (print_insn_mips16): Handle MIPS16 instructions that require
19 32-bit encoding and MFC0/MTC0 operand decoding.
20 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
21 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
22 (RD_C0, WR_C0, E2, E2MT): New macros.
23 (mips16_opcodes): Add entries for MIPS16e2 instructions:
24 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
25 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
26 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
27 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
28 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
29 instructions, "swl", "swr", "sync" and its "sync_acquire",
30 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
31 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
32 regular/extended entries for original MIPS16 ISA revision
33 instructions whose extended forms are subdecoded in the MIPS16e2
34 ISA revision: "li", "sll" and "srl".
35
fdfb4752
MR		 362017-05-15 Maciej W. Rozycki <macro@imgtec.com>
37
38 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
39 reference in CP0 move operand decoding.
40
a4f89915
MR		 412017-05-12 Maciej W. Rozycki <macro@imgtec.com>
42
43 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
44 type to hexadecimal.
45 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
46
99e2d67a
MR		 472017-05-11 Maciej W. Rozycki <macro@imgtec.com>
48
49 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
50 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
51 "sync_rmb" and "sync_wmb" as aliases.
52 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
53 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
54
53a346d8
CZ		 552017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
56
57 * arc-dis.c (parse_option): Update quarkse_em option..
58 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
59 QUARKSE1.
60 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
61
f91d48de
KC		 622017-05-03 Kito Cheng <kito.cheng@gmail.com>
63
64 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
65
43e379d7
MC		 662017-05-01 Michael Clark <michaeljclark@mac.com>
67
68 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
69 register.
70
a4ddc54e
MR		 712017-05-02 Maciej W. Rozycki <macro@imgtec.com>
72
73 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
74 and branches and not synthetic data instructions.
75
fe50e98c
BE		 762017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
77
78 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
79
126124cc
CZ		 802017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
81
82 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
83 * arc-opc.c (insert_r13el): New function.
84 (R13_EL): Define.
85 * arc-tbl.h: Add new enter/leave variants.
86
be6a24d8
CZ		 872017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
88
89 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
90
0348fd79
MR		 912017-04-25 Maciej W. Rozycki <macro@imgtec.com>
92
93 * mips-dis.c (print_mips_disassembler_options): Add
94 `no-aliases'.
95
6e3d1f07
MR		 962017-04-25 Maciej W. Rozycki <macro@imgtec.com>
97
98 * mips16-opc.c (AL): New macro.
99 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
100 of "ld" and "lw" as aliases.
101
957f6b39
TC		 1022017-04-24 Tamar Christina <tamar.christina@arm.com>
103
104 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
105 arguments.
106
a8cc8a54
AM		 1072017-04-22 Alexander Fedotov <alfedotov@gmail.com>
108 Alan Modra <amodra@gmail.com>
109
110 * ppc-opc.c (ELEV): Define.
111 (vle_opcodes): Add se_rfgi and e_sc.
112 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
113 for E200Z4.
114
3ab87b68
JM		 1152017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
116
117 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
118
792f174f
NC		 1192017-04-21 Nick Clifton <nickc@redhat.com>
120
121 PR binutils/21380
122 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
123 LD3R and LD4R.
124
42742084
AM		 1252017-04-13 Alan Modra <amodra@gmail.com>
126
127 * epiphany-desc.c: Regenerate.
128 * fr30-desc.c: Regenerate.
129 * frv-desc.c: Regenerate.
130 * ip2k-desc.c: Regenerate.
131 * iq2000-desc.c: Regenerate.
132 * lm32-desc.c: Regenerate.
133 * m32c-desc.c: Regenerate.
134 * m32r-desc.c: Regenerate.
135 * mep-desc.c: Regenerate.
136 * mt-desc.c: Regenerate.
137 * or1k-desc.c: Regenerate.
138 * xc16x-desc.c: Regenerate.
139 * xstormy16-desc.c: Regenerate.
140
9a85b496
AM		 1412017-04-11 Alan Modra <amodra@gmail.com>
142
ef85eab0 143 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 144 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
145 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 146 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
147 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 148 (PPCVSX2): Define as PPC_OPCODE_POWER8.
149 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 150 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 151 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 152
62adc510
AM		 1532017-04-10 Alan Modra <amodra@gmail.com>
154
155 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
156 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
157 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
158 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
159
aa808707
PC		 1602017-04-09 Pip Cet <pipcet@gmail.com>
161
162 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
163 appropriate floating-point precision directly.
164
ac8f0f72
AM		 1652017-04-07 Alan Modra <amodra@gmail.com>
166
167 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
168 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
169 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
170 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
171 vector instructions with E6500 not PPCVEC2.
172
62ecb94c
PC		 1732017-04-06 Pip Cet <pipcet@gmail.com>
174
175 * Makefile.am: Add wasm32-dis.c.
176 * configure.ac: Add wasm32-dis.c to wasm32 target.
177 * disassemble.c: Add wasm32 disassembler code.
178 * wasm32-dis.c: New file.
179 * Makefile.in: Regenerate.
180 * configure: Regenerate.
181 * po/POTFILES.in: Regenerate.
182 * po/opcodes.pot: Regenerate.
183
f995bbe8
PA		 1842017-04-05 Pedro Alves <palves@redhat.com>
185
186 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
187 * arm-dis.c (parse_arm_disassembler_options): Constify.
188 * ppc-dis.c (powerpc_init_dialect): Constify local.
189 * vax-dis.c (parse_disassembler_options): Constify.
190
b5292032
PD		 1912017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
192
193 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
194 RISCV_GP_SYMBOL.
195
f96bd6c2
PC		 1962017-03-30 Pip Cet <pipcet@gmail.com>
197
198 * configure.ac: Add (empty) bfd_wasm32_arch target.
199 * configure: Regenerate
200 * po/opcodes.pot: Regenerate.
201
f7c514a3
JM		 2022017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
203
204 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
205 OSA2015.
206 * opcodes/sparc-opc.c (asi_table): New ASIs.
207
52be03fd
AM		 2082017-03-29 Alan Modra <amodra@gmail.com>
209
210 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
211 "raw" option.
212 (lookup_powerpc): Don't special case -1 dialect. Handle
213 PPC_OPCODE_RAW.
214 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
215 lookup_powerpc call, pass it on second.
216
9b753937
AM		 2172017-03-27 Alan Modra <amodra@gmail.com>
218
219 PR 21303
220 * ppc-dis.c (struct ppc_mopt): Comment.
221 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
222
c0c31e91
RZ		 2232017-03-27 Rinat Zelig <rinat@mellanox.com>
224
225 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
226 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
227 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
228 (insert_nps_misc_imm_offset): New function.
229 (extract_nps_misc imm_offset): New function.
230 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
231 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
232
2253c8f0
AK		 2332017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
234
235 * s390-mkopc.c (main): Remove vx2 check.
236 * s390-opc.txt: Remove vx2 instruction flags.
237
645d3342
RZ		 2382017-03-21 Rinat Zelig <rinat@mellanox.com>
239
240 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
241 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
242 (insert_nps_imm_offset): New function.
243 (extract_nps_imm_offset): New function.
244 (insert_nps_imm_entry): New function.
245 (extract_nps_imm_entry): New function.
246
4b94dd2d
AM		 2472017-03-17 Alan Modra <amodra@gmail.com>
248
249 PR 21248
250 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
251 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
252 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
253
b416fe87
KC		 2542017-03-14 Kito Cheng <kito.cheng@gmail.com>
255
256 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
257 <c.andi>: Likewise.
258 <c.addiw> Likewise.
259
03b039a5
KC		 2602017-03-14 Kito Cheng <kito.cheng@gmail.com>
261
262 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
263
2c232b83
AW		 2642017-03-13 Andrew Waterman <andrew@sifive.com>
265
266 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
267 <srl> Likewise.
268 <srai> Likewise.
269 <sra> Likewise.
270
86fa6981
L		 2712017-03-09 H.J. Lu <hongjiu.lu@intel.com>
272
273 * i386-gen.c (opcode_modifiers): Replace S with Load.
274 * i386-opc.h (S): Removed.
275 (Load): New.
276 (i386_opcode_modifier): Replace s with load.
277 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
278 and {evex}. Replace S with Load.
279 * i386-tbl.h: Regenerated.
280
c1fe188b
L		 2812017-03-09 H.J. Lu <hongjiu.lu@intel.com>
282
283 * i386-opc.tbl: Use CpuCET on rdsspq.
284 * i386-tbl.h: Regenerated.
285
4b8b687e
PB		 2862017-03-08 Peter Bergner <bergner@vnet.ibm.com>
287
288 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
289 <vsx>: Do not use PPC_OPCODE_VSX3;
290
1437d063
PB		 2912017-03-08 Peter Bergner <bergner@vnet.ibm.com>
292
293 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
294
603555e5
L		 2952017-03-06 H.J. Lu <hongjiu.lu@intel.com>
296
297 * i386-dis.c (REG_0F1E_MOD_3): New enum.
298 (MOD_0F1E_PREFIX_1): Likewise.
299 (MOD_0F38F5_PREFIX_2): Likewise.
300 (MOD_0F38F6_PREFIX_0): Likewise.
301 (RM_0F1E_MOD_3_REG_7): Likewise.
302 (PREFIX_MOD_0_0F01_REG_5): Likewise.
303 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
304 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
305 (PREFIX_0F1E): Likewise.
306 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
307 (PREFIX_0F38F5): Likewise.
308 (dis386_twobyte): Use PREFIX_0F1E.
309 (reg_table): Add REG_0F1E_MOD_3.
310 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
311 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
312 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
313 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
314 (three_byte_table): Use PREFIX_0F38F5.
315 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
316 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
317 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
318 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
319 PREFIX_MOD_3_0F01_REG_5_RM_2.
320 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
321 (cpu_flags): Add CpuCET.
322 * i386-opc.h (CpuCET): New enum.
323 (CpuUnused): Commented out.
324 (i386_cpu_flags): Add cpucet.
325 * i386-opc.tbl: Add Intel CET instructions.
326 * i386-init.h: Regenerated.
327 * i386-tbl.h: Likewise.
328
73f07bff
AM		 3292017-03-06 Alan Modra <amodra@gmail.com>
330
331 PR 21124
332 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
333 (extract_raq, extract_ras, extract_rbx): New functions.
334 (powerpc_operands): Use opposite corresponding insert function.
335 (Q_MASK): Define.
336 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
337 register restriction.
338
65b48a81
PB		 3392017-02-28 Peter Bergner <bergner@vnet.ibm.com>
340
341 * disassemble.c Include "safe-ctype.h".
342 (disassemble_init_for_target): Handle s390 init.
343 (remove_whitespace_and_extra_commas): New function.
344 (disassembler_options_cmp): Likewise.
345 * arm-dis.c: Include "libiberty.h".
346 (NUM_ELEM): Delete.
347 (regnames): Use long disassembler style names.
348 Add force-thumb and no-force-thumb options.
349 (NUM_ARM_REGNAMES): Rename from this...
350 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
351 (get_arm_regname_num_options): Delete.
352 (set_arm_regname_option): Likewise.
353 (get_arm_regnames): Likewise.
354 (parse_disassembler_options): Likewise.
355 (parse_arm_disassembler_option): Rename from this...
356 (parse_arm_disassembler_options): ...to this. Make static.
357 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
358 (print_insn): Use parse_arm_disassembler_options.
359 (disassembler_options_arm): New function.
360 (print_arm_disassembler_options): Handle updated regnames.
361 * ppc-dis.c: Include "libiberty.h".
362 (ppc_opts): Add "32" and "64" entries.
363 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
364 (powerpc_init_dialect): Add break to switch statement.
365 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
366 (disassembler_options_powerpc): New function.
367 (print_ppc_disassembler_options): Use ARRAY_SIZE.
368 Remove printing of "32" and "64".
369 * s390-dis.c: Include "libiberty.h".
370 (init_flag): Remove unneeded variable.
371 (struct s390_options_t): New structure type.
372 (options): New structure.
373 (init_disasm): Rename from this...
374 (disassemble_init_s390): ...to this. Add initializations for
375 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
376 (print_insn_s390): Delete call to init_disasm.
377 (disassembler_options_s390): New function.
378 (print_s390_disassembler_options): Print using information from
379 struct 'options'.
380 * po/opcodes.pot: Regenerate.
381
15c7c1d8
JB		 3822017-02-28 Jan Beulich <jbeulich@suse.com>
383
384 * i386-dis.c (PCMPESTR_Fixup): New.
385 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
386 (prefix_table): Use PCMPESTR_Fixup.
387 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
388 PCMPESTR_Fixup.
389 (vex_w_table): Delete VPCMPESTR{I,M} entries.
390 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
391 Split 64-bit and non-64-bit variants.
392 * opcodes/i386-tbl.h: Re-generate.
393
582e12bf
RS		 3942017-02-24 Richard Sandiford <richard.sandiford@arm.com>
395
396 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
397 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
398 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
399 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
400 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
401 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
402 (OP_SVE_V_HSD): New macros.
403 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
404 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
405 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
406 (aarch64_opcode_table): Add new SVE instructions.
407 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
408 for rotation operands. Add new SVE operands.
409 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
410 (ins_sve_quad_index): Likewise.
411 (ins_imm_rotate): Split into...
412 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
413 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
414 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
415 functions.
416 (aarch64_ins_sve_addr_ri_s4): New function.
417 (aarch64_ins_sve_quad_index): Likewise.
418 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
419 * aarch64-asm-2.c: Regenerate.
420 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
421 (ext_sve_quad_index): Likewise.
422 (ext_imm_rotate): Split into...
423 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
424 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
425 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
426 functions.
427 (aarch64_ext_sve_addr_ri_s4): New function.
428 (aarch64_ext_sve_quad_index): Likewise.
429 (aarch64_ext_sve_index): Allow quad indices.
430 (do_misc_decoding): Likewise.
431 * aarch64-dis-2.c: Regenerate.
432 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
433 aarch64_field_kinds.
434 (OPD_F_OD_MASK): Widen by one bit.
435 (OPD_F_NO_ZR): Bump accordingly.
436 (get_operand_field_width): New function.
437 * aarch64-opc.c (fields): Add new SVE fields.
438 (operand_general_constraint_met_p): Handle new SVE operands.
439 (aarch64_print_operand): Likewise.
440 * aarch64-opc-2.c: Regenerate.
441
f482d304
RS		 4422017-02-24 Richard Sandiford <richard.sandiford@arm.com>
443
444 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
445 (aarch64_feature_compnum): ...this.
446 (SIMD_V8_3): Replace with...
447 (COMPNUM): ...this.
448 (CNUM_INSN): New macro.
449 (aarch64_opcode_table): Use it for the complex number instructions.
450
7db2c588
JB		 4512017-02-24 Jan Beulich <jbeulich@suse.com>
452
453 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
454
1e9d41d4
SL		 4552017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
456
457 Add support for associating SPARC ASIs with an architecture level.
458 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
459 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
460 decoding of SPARC ASIs.
461
53c4d625
JB		 4622017-02-23 Jan Beulich <jbeulich@suse.com>
463
464 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
465 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
466
11648de5
JB		 4672017-02-21 Jan Beulich <jbeulich@suse.com>
468
469 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
470 1 (instead of to itself). Correct typo.
471
f98d33be
AW		 4722017-02-14 Andrew Waterman <andrew@sifive.com>
473
474 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
475 pseudoinstructions.
476
773fb663
RS		 4772017-02-15 Richard Sandiford <richard.sandiford@arm.com>
478
479 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
480 (aarch64_sys_reg_supported_p): Handle them.
481
cc07cda6
CZ		 4822017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
483
484 * arc-opc.c (UIMM6_20R): Define.
485 (SIMM12_20): Use above.
486 (SIMM12_20R): Define.
487 (SIMM3_5_S): Use above.
488 (UIMM7_A32_11R_S): Define.
489 (UIMM7_9_S): Use above.
490 (UIMM3_13R_S): Define.
491 (SIMM11_A32_7_S): Use above.
492 (SIMM9_8R): Define.
493 (UIMM10_A32_8_S): Use above.
494 (UIMM8_8R_S): Define.
495 (W6): Use above.
496 (arc_relax_opcodes): Use all above defines.
497
66a5a740
VG		 4982017-02-15 Vineet Gupta <vgupta@synopsys.com>
499
500 * arc-regs.h: Distinguish some of the registers different on
501 ARC700 and HS38 cpus.
502
7e0de605
AM		 5032017-02-14 Alan Modra <amodra@gmail.com>
504
505 PR 21118
506 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
507 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
508
54064fdb
AM		 5092017-02-11 Stafford Horne <shorne@gmail.com>
510 Alan Modra <amodra@gmail.com>
511
512 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
513 Use insn_bytes_value and insn_int_value directly instead. Don't
514 free allocated memory until function exit.
515
dce75bf9
NP		 5162017-02-10 Nicholas Piggin <npiggin@gmail.com>
517
518 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
519
1b7e3d2f
NC		 5202017-02-03 Nick Clifton <nickc@redhat.com>
521
522 PR 21096
523 * aarch64-opc.c (print_register_list): Ensure that the register
524 list index will fir into the tb buffer.
525 (print_register_offset_address): Likewise.
526 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
527
8ec5cf65
AD		 5282017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
529
530 PR 21056
531 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
532 instructions when the previous fetch packet ends with a 32-bit
533 instruction.
534
a1aa5e81
DD		 5352017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
536
537 * pru-opc.c: Remove vague reference to a future GDB port.
538
add3afb2
NC		 5392017-01-20 Nick Clifton <nickc@redhat.com>
540
541 * po/ga.po: Updated Irish translation.
542
c13a63b0
SN		 5432017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
544
545 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
546
9608051a
YQ		 5472017-01-13 Yao Qi <yao.qi@linaro.org>
548
549 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
550 if FETCH_DATA returns 0.
551 (m68k_scan_mask): Likewise.
552 (print_insn_m68k): Update code to handle -1 return value.
553
f622ea96
YQ		 5542017-01-13 Yao Qi <yao.qi@linaro.org>
555
556 * m68k-dis.c (enum print_insn_arg_error): New.
557 (NEXTBYTE): Replace -3 with
558 PRINT_INSN_ARG_MEMORY_ERROR.
559 (NEXTULONG): Likewise.
560 (NEXTSINGLE): Likewise.
561 (NEXTDOUBLE): Likewise.
562 (NEXTDOUBLE): Likewise.
563 (NEXTPACKED): Likewise.
564 (FETCH_ARG): Likewise.
565 (FETCH_DATA): Update comments.
566 (print_insn_arg): Update comments. Replace magic numbers with
567 enum.
568 (match_insn_m68k): Likewise.
569
620214f7
IT		 5702017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
571
572 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
573 * i386-dis-evex.h (evex_table): Updated.
574 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
575 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
576 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
577 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
578 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
579 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
580 * i386-init.h: Regenerate.
581 * i386-tbl.h: Ditto.
582
d95014a2
YQ		 5832017-01-12 Yao Qi <yao.qi@linaro.org>
584
585 * msp430-dis.c (msp430_singleoperand): Return -1 if
586 msp430dis_opcode_signed returns false.
587 (msp430_doubleoperand): Likewise.
588 (msp430_branchinstr): Return -1 if
589 msp430dis_opcode_unsigned returns false.
590 (msp430x_calla_instr): Likewise.
591 (print_insn_msp430): Likewise.
592
0ae60c3e
NC		 5932017-01-05 Nick Clifton <nickc@redhat.com>
594
595 PR 20946
596 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
597 could not be matched.
598 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
599 NULL.
600
d74d4880
SN		 6012017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
602
603 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
604 (aarch64_opcode_table): Use RCPC_INSN.
605
cc917fd9
KC		 6062017-01-03 Kito Cheng <kito.cheng@gmail.com>
607
608 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
609 extension.
610 * riscv-opcodes/all-opcodes: Likewise.
611
b52d3cfc
DP		 6122017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
613
614 * riscv-dis.c (print_insn_args): Add fall through comment.
615
f90c58d5
NC		 6162017-01-03 Nick Clifton <nickc@redhat.com>
617
618 * po/sr.po: New Serbian translation.
619 * configure.ac (ALL_LINGUAS): Add sr.
620 * configure: Regenerate.
621
f47b0d4a
AM		 6222017-01-02 Alan Modra <amodra@gmail.com>
623
624 * epiphany-desc.h: Regenerate.
625 * epiphany-opc.h: Regenerate.
626 * fr30-desc.h: Regenerate.
627 * fr30-opc.h: Regenerate.
628 * frv-desc.h: Regenerate.
629 * frv-opc.h: Regenerate.
630 * ip2k-desc.h: Regenerate.
631 * ip2k-opc.h: Regenerate.
632 * iq2000-desc.h: Regenerate.
633 * iq2000-opc.h: Regenerate.
634 * lm32-desc.h: Regenerate.
635 * lm32-opc.h: Regenerate.
636 * m32c-desc.h: Regenerate.
637 * m32c-opc.h: Regenerate.
638 * m32r-desc.h: Regenerate.
639 * m32r-opc.h: Regenerate.
640 * mep-desc.h: Regenerate.
641 * mep-opc.h: Regenerate.
642 * mt-desc.h: Regenerate.
643 * mt-opc.h: Regenerate.
644 * or1k-desc.h: Regenerate.
645 * or1k-opc.h: Regenerate.
646 * xc16x-desc.h: Regenerate.
647 * xc16x-opc.h: Regenerate.
648 * xstormy16-desc.h: Regenerate.
649 * xstormy16-opc.h: Regenerate.
650
2571583a
AM		 6512017-01-02 Alan Modra <amodra@gmail.com>
652
653 Update year range in copyright notice of all files.
654
5c1ad6b5 655For older changes see ChangeLog-2016
3499769a 656\f
5c1ad6b5 657Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 658
659Copying and distribution of this file, with or without modification,
660are permitted in any medium without royalty provided the copyright
661notice and this notice are preserved.
662
663Local Variables:
664mode: change-log
665left-margin: 8
666fill-column: 74
667version-control: never
668End:
GDB Binutils - Deliverables
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