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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
cfc08d49
L		 12010-10-14 H.J. Lu <hongjiu.lu@intel.com>
2
3 * i386-opc.tbl: Remove CheckRegSize from instructions with
4 0, 1 or fixed operands.
5 * i386-tbl.h: Regenerated.
6
56ffb741
L		 72010-10-14 H.J. Lu <hongjiu.lu@intel.com>
8
9 * i386-gen.c (opcode_modifiers): Add CheckRegSize.
10
11 * i386-opc.h (CheckRegSize): New.
12 (i386_opcode_modifier): Add checkregsize.
13
14 * i386-opc.tbl: Add CheckRegSize to instructions which
15 require register size check.
16 * i386-tbl.h: Regenerated.
17
1a2dab1f
AS		 182010-10-12 Andreas Schwab <schwab@linux-m68k.org>
19
20 * m68k-opc.c (m68k_opcodes): Move fnop before fbf.
21
a3ec2691
AK		 222010-10-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
23
24 * s390-opc.c: Make the instruction masks for the load/store on
25 condition instructions to cover the condition code mask as well.
26 * s390-opc.txt: lgoc -> locg and stgoc -> stocg.
27
d92fa646
JK		 282010-10-11 Jan Kratochvil <jan.kratochvil@redhat.com>
29 Jiang Jilin <freephp@gmail.com>
30
31 * Makefile.am (libopcodes_a_SOURCES): New as empty.
32 * Makefile.in: Regenerate.
33
4469d2be
AM		 342010-10-09 Matt Rice <ratmice@gmail.com>
35
36 * fr30-desc.h: Regenerate.
37 * frv-desc.h: Regenerate.
38 * ip2k-desc.h: Regenerate.
39 * iq2000-desc.h: Regenerate.
40 * lm32-desc.h: Regenerate.
41 * m32c-desc.h: Regenerate.
42 * m32r-desc.h: Regenerate.
43 * mep-desc.h: Regenerate.
44 * mep-opc.c: Regenerate.
45 * mt-desc.h: Regenerate.
46 * openrisc-desc.h: Regenerate.
47 * xc16x-desc.h: Regenerate.
48 * xstormy16-desc.h: Regenerate.
49
9ccb8af9
AM		 502010-10-08 Pierre Muller <muller@ics.u-strasbg.fr>
51
52 Fix build with -DDEBUG=7
53 * frv-opc.c: Regenerate.
54 * or32-dis.c (DEBUG): Don't redefine.
55 (find_bytes_big, or32_extract, or32_opcode_match, or32_print_register):
56 Adapt DEBUG code to some type changes throughout.
57 * or32-opc.c (or32_extract): Likewise.
58
5d4c71e1
BS		 592010-10-07 Bernd Schmidt <bernds@codesourcery.com>
60
61 * tic6x-dis.c (print_insn_tic6x): Correct decoding of fstg field
62 in SPKERNEL instructions.
63
9ce00134
L		 642010-10-02 H.J. Lu <hongjiu.lu@intel.com>
65
66 PR binutils/12076
67 * i386-dis.c (RMAL): Remove duplicate.
68
e7390eec
PM		 692010-09-30 Pierre Muller <muller@ics.u-strasbg.fr>
70
71 * s390-mkopc.c (main): Exit with error 1 if sscanf fails
72 to parse all 6 parameters.
73
d2ae9c84
PM		 742010-09-28 Pierre Muller <muller@ics.u-strasbg.fr>
75
76 * s390-mkopc.c (main): Change description array size to 80.
77 Add maximum length of 79 to description parsing.
78
3cac54d2
RW		 792010-09-27 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
80
81 * configure: Regenerate.
82
d9aee5d7
AK		 832010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
84
85 * s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196.
86 (main): Recognize the new CPU string.
87 * s390-opc.c: Add new instruction formats and masks.
88 * s390-opc.txt: Add new z196 instructions.
89
02cbf767
AK		 902010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
91
92 * s390-dis.c (print_insn_s390): Pick instruction with most
93 specific mask.
94 * s390-opc.c: Add unused bits to the insn mask.
95 * s390-opc.txt: Reorder some instructions to prefer more recent
96 versions.
97
6844b2c2
MGD		 982010-09-27 Tejas Belagod <tejas.belagod@arm.com>
99
100 * arm_dis.c (print_insn_coprocessor): Apply off-by-alignment
101 correction to unaligned PCs while printing comment.
102
90ec0d68
MGD		 1032010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
104
105 * arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
106 (thumb32_opcodes): Likewise.
107 (banked_regname): New function.
108 (print_insn_arm): Add Virtualization Extensions support.
109 (print_insn_thumb32): Likewise.
110
eea54501
MGD		 1112010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
112
113 * arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
114 ARM state.
115
f4c65163
MGD		 1162010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
117
118 * arm-dis.c (arm_opcodes): SMC implies Security Extensions.
119 (thumb32_opcodes): Likewise.
120
60e5ef9f
MGD		 1212010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
122
123 * arm-dis.c (arm_opcodes): Add support for pldw.
124 (thumb32_opcodes): Likewise.
125
7a360e83
MF		 1262010-09-22 Robin Getz <robin.getz@analog.com>
127
128 * bfin-dis.c (fmtconst): Cast address to 32bits.
129
35fc57f3
MF		 1302010-09-22 Mike Frysinger <vapier@gentoo.org>
131
132 * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks.
133
219b747a
MF		 1342010-09-22 Robin Getz <robin.getz@analog.com>
135
136 * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns.
137 Reject P6/P7 to TESTSET.
138 (decode_PushPopReg_0): Check for parallel insns. Reject pushing
139 SP onto the stack.
140 (decode_PushPopMultiple_0): Check for parallel insns. Make sure
141 P/D fields match all the time.
142 (decode_CCflag_0): Check for parallel insns. Verify x/y fields
143 are 0 for accumulator compares.
144 (decode_CC2stat_0): Check for parallel insns. Reject CC<op>CC.
145 (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0,
146 decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0,
147 decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
148 decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
149 decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel
150 insns.
151 (decode_dagMODim_0): Verify br field for IREG ops.
152 (decode_LDST_0): Reject preg load into same preg.
153 (_print_insn_bfin): Handle returns for ILLEGAL decodes.
154 (print_insn_bfin): Likewise.
155
775f1cf0
MF		 1562010-09-22 Mike Frysinger <vapier@gentoo.org>
157
158 * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5.
159
0b7691fd
MF		 1602010-09-22 Robin Getz <robin.getz@analog.com>
161
162 * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.
163
b2459327
MF		 1642010-09-22 Mike Frysinger <vapier@gentoo.org>
165
166 * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
167
50e2162a
MF		 1682010-09-22 Robin Getz <robin.getz@analog.com>
169
170 * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
171 register values greater than 8.
172 (IS_RESERVEDREG, allreg, mostreg): New helpers.
173 (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
174 (decode_PushPopReg_0): Call mostreg/allreg as appropriate.
175 (decode_CC2dreg_0): Check valid CC register number.
176
a01eda85
MF		 1772010-09-22 Robin Getz <robin.getz@analog.com>
178
179 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
180
22215ae0
MF		 1812010-09-22 Robin Getz <robin.getz@analog.com>
182
183 * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
184 (reg_names): Likewise.
185 (decode_statbits): Likewise; while reformatting to make manageable.
186
73a63ccf
MF		 1872010-09-22 Mike Frysinger <vapier@gentoo.org>
188
189 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
190 (decode_pseudoOChar_0): New function.
191 (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
192
59a82d23
MF		 1932010-09-22 Robin Getz <robin.getz@analog.com>
194
195 * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
196 LSHIFT instead of SHIFT.
197
528c6277
MF		 1982010-09-22 Mike Frysinger <vapier@gentoo.org>
199
200 * bfin-dis.c (constant_formats): Constify the whole structure.
201 (fmtconst): Add const to return value.
202 (reg_names): Mark const.
203 (decode_multfunc): Mark s0/s1 as const.
204 (decode_macfunc): Mark a/sop as const.
205
db472d6f
MGD		 2062010-09-17 Tejas Belagod <tejas.belagod@arm.com>
207
208 * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
209
f6690563
MR		 2102010-09-14 Maciej W. Rozycki <macro@codesourcery.com>
211
212 * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
213 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
214
8901a3cd
PM		 2152010-09-10 Pierre Muller <muller@ics.u-strasbg.fr>
216
217 * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
218 dlx_insn_type array.
219
d9e3625e
L		 2202010-08-31 H.J. Lu <hongjiu.lu@intel.com>
221
222 PR binutils/11960
223 * i386-dis.c (sIv): New.
224 (dis386): Replace Iq with sIv on "pushT".
225 (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
4469d2be 226 (x86_64_table): Replace {T|}/{P|} with P.
d9e3625e
L		 227 (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
228 (OP_sI): Update v_mode. Remove w_mode.
229
f383de66
NF		 2302010-08-27 Nathan Froyd <froydnj@codesourcery.com>
231
232 * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
233 on E500 and E500MC.
234
1ab03f4b
L		 2352010-08-17 H.J. Lu <hongjiu.lu@intel.com>
236
237 * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
238 prefetchw.
239
22109423
L		 2402010-08-06 Quentin Neill <quentin.neill@amd.com>
241
242 * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
243 to processor flags for PENTIUMPRO processors and later.
244 * i386-opc.h (enum): Add CpuNop.
245 (i386_cpu_flags): Add cpunop bit.
246 * i386-opc.tbl: Change nop cpu_flags.
247 * i386-init.h: Regenerated.
248 * i386-tbl.h: Likewise.
249
b49dfb4a
L		 2502010-08-06 Quentin Neill <quentin.neill@amd.com>
251
252 * i386-opc.h (enum): Fix typos in comments.
253
6ca4eb77
AM		 2542010-08-06 Alan Modra <amodra@gmail.com>
255
256 * disassemble.c: Formatting.
257 (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
258
92d4d42e
L		 2592010-08-05 H.J. Lu <hongjiu.lu@intel.com>
260
261 * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
262 * i386-tbl.h: Regenerated.
263
b414985b
L		 2642010-08-05 H.J. Lu <hongjiu.lu@intel.com>
265
266 * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
267
268 * i386-opc.tbl: Add ud1. Remove Cpu686 from ud2/ud2a/ud2b.
269 * i386-tbl.h: Regenerated.
270
f9c7014e
DD		 2712010-07-29 DJ Delorie <dj@redhat.com>
272
273 * rx-decode.opc (SRR): New.
274 (rx_decode_opcode): Use it for movbi and movbir. Decode NOP2 (mov
275 r0,r0) and NOP3 (max r0,r0) special cases.
276 * rx-decode.c: Regenerate.
6ca4eb77 277
592a252b
L		 2782010-07-28 H.J. Lu <hongjiu.lu@intel.com>
279
280 * i386-dis.c: Add 0F to VEX opcode enums.
281
3cf79a01
DD		 2822010-07-27 DJ Delorie <dj@redhat.com>
283
284 * rx-decode.opc (store_flags): Remove, replace with F_* macros.
285 (rx_decode_opcode): Likewise.
286 * rx-decode.c: Regenerate.
287
1cd986c5
NC		 2882010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
289 Ina Pandit <ina.pandit@kpitcummins.com>
290
291 * v850-dis.c (v850_sreg_names): Updated structure for system
292 registers.
293 (float_cc_names): new structure for condition codes.
294 (print_value): Update the function that prints value.
295 (get_operand_value): New function to get the operand value.
296 (disassemble): Updated to handle the disassembly of instructions.
297 (print_insn_v850): Updated function to print instruction for different
298 families.
299 * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
300 extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
301 extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
302 insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
303 extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
304 extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
305 extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
306 insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
307 (insert_d8_7, insert_d5_4, insert_i5div): Remove.
308 (v850_operands): Update with the relocation name. Also update
309 the instructions with specific set of processors.
310
52e7f43d
RE		 3112010-07-08 Tejas Belagod <tejas.belagod@arm.com>
312
313 * arm-dis.c (print_insn_arm): Add cases for printing more
314 symbolic operands.
315 (print_insn_thumb32): Likewise.
316
c680e7f6
MR		 3172010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
318
319 * mips-dis.c (print_insn_mips): Correct branch instruction type
320 determination.
321
9a2c7088
MR		 3222010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
323
324 * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
325 type and delay slot determination.
326 (print_insn_mips16): Extend branch instruction type and delay
327 slot determination to cover all instructions.
328 * mips16-opc.c (BR): Remove macro.
329 (UBR, CBR): New macros.
330 (mips16_opcodes): Update branch annotation for "b", "beqz",
331 "bnez", "bteqz" and "btnez". Add branch annotation for "jalrc"
332 and "jrc".
333
d7d9a9f8
L		 3342010-07-05 H.J. Lu <hongjiu.lu@intel.com>
335
336 AVX Programming Reference (June, 2010)
337 * i386-dis.c (mod_table): Replace rdrnd with rdrand.
338 * i386-opc.tbl: Likewise.
339 * i386-tbl.h: Regenerated.
340
77321f53
L		 3412010-07-05 H.J. Lu <hongjiu.lu@intel.com>
342
343 * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
344
7102e95e
AS		 3452010-07-03 Andreas Schwab <schwab@linux-m68k.org>
346
347 * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
348 ppc_cpu_t before inverting.
3a5530ea
AS		 349 (ppc_parse_cpu): Likewise.
350 (print_insn_powerpc): Likewise.
7102e95e 351
bdc70b4a
AM		 3522010-07-03 Alan Modra <amodra@gmail.com>
353
354 * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
355 * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
356 (PPC64, MFDEC2): Update.
357 (NON32, NO371): Define.
358 (powerpc_opcode): Update to not use old opcode flags, and avoid
359 -m601 duplicates.
360
21375995
DD		 3612010-07-03 DJ Delorie <dj@delorie.com>
362
363 * m32c-ibld.c: Regenerate.
364
81a0b7e2
AM		 3652010-07-03 Alan Modra <amodra@gmail.com>
366
367 * ppc-opc.c (PWR2COM): Define.
368 (PPCPWR2): Add PPC_OPCODE_COMMON.
369 (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
370 "fcirz", "fcirz." to -mcom opcodes. Remove "mfsri", "dclst",
371 "rac" from -mcom.
372
c7b8aa3a
L		 3732010-07-01 H.J. Lu <hongjiu.lu@intel.com>
374
375 AVX Programming Reference (June, 2010)
376 * i386-dis.c (PREFIX_0FAE_REG_0): New.
377 (PREFIX_0FAE_REG_1): Likewise.
378 (PREFIX_0FAE_REG_2): Likewise.
379 (PREFIX_0FAE_REG_3): Likewise.
380 (PREFIX_VEX_3813): Likewise.
381 (PREFIX_VEX_3A1D): Likewise.
382 (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
383 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
384 PREFIX_VEX_3A1D.
385 (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
386 (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
387 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
388
389 * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
390 CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
391 (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
392
393 * i386-opc.h (CpuXsaveopt): New.
77321f53 394 (CpuFSGSBase): Likewise.
c7b8aa3a
L		 395 (CpuRdRnd): Likewise.
396 (CpuF16C): Likewise.
397 (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
398 cpuf16c.
399
400 * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
401 wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
a00eb5e8
L		 402 * i386-init.h: Regenerated.
403 * i386-tbl.h: Likewise.
c7b8aa3a 404
09a8ad8d
AM		 4052010-07-01 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
406
407 * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
408 and mtocrf on EFS.
409
360cfc9c
AM		 4102010-06-29 Alan Modra <amodra@gmail.com>
411
412 * maxq-dis.c: Delete file.
413 * Makefile.am: Remove references to maxq.
414 * configure.in: Likewise.
415 * disassemble.c: Likewise.
416 * Makefile.in: Regenerate.
417 * configure: Regenerate.
418 * po/POTFILES.in: Regenerate.
419
dc898d5e
AM		 4202010-06-29 Alan Modra <amodra@gmail.com>
421
422 * mep-dis.c: Regenerate.
423
8e560766
MGD		 4242010-06-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
425
426 * arm-disc.c (parse_insn_neon): Fix Neon alignment syntax.
427
c7e2358a
AM		 4282010-06-27 Alan Modra <amodra@gmail.com>
429
430 * arc-dis.c (arc_sprintf): Delete set but unused variables.
431 (decodeInstr): Likewise.
432 * dlx-dis.c (print_insn_dlx): Likewise.
433 * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
434 * maxq-dis.c (check_move, print_insn): Likewise.
435 * mep-dis.c (mep_examine_ivc2_insns): Likewise.
436 * msp430-dis.c (msp430_branchinstr): Likewise.
437 * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
438 * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
439 * sparc-dis.c (print_insn_sparc): Likewise.
440 * fr30-asm.c: Regenerate.
441 * frv-asm.c: Regenerate.
442 * ip2k-asm.c: Regenerate.
443 * iq2000-asm.c: Regenerate.
444 * lm32-asm.c: Regenerate.
445 * m32c-asm.c: Regenerate.
446 * m32r-asm.c: Regenerate.
447 * mep-asm.c: Regenerate.
448 * mt-asm.c: Regenerate.
449 * openrisc-asm.c: Regenerate.
450 * xc16x-asm.c: Regenerate.
451 * xstormy16-asm.c: Regenerate.
452
6ffe3d99
NC		 4532010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
454
455 PR gas/11673
456 * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
457
09ec0d17
NC		 4582010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
459
460 PR binutils/11676
461 * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
462
e01d869a
AM		 4632010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
464
465 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_E500MC from e500 and
466 e500x2. Add PPC_OPCODE_E500 to e500 and e500x2
467 * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
468 touch floating point regs and are enabled by COM, PPC or PPCCOM.
469 Treat sync as msync on e500. Treat eieio as mbar 1 on e500.
470 Treat lwsync as msync on e500.
471
1f4e4950
MGD		 4722010-06-07 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
473
474 * arm-dis.c (thumb-opcodes): Add disassembly for movs.
475
9d82ec38
MGD		 4762010-05-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
477
e01d869a 478 * arm-dis.c (print_insn_neon): Ensure disassembly of Neon
9d82ec38
MGD		 479 constants is the same on 32-bit and 64-bit hosts.
480
c3a6ea62 4812010-05-27 Jason Duerstock <jason.duerstock+binutils@gmail.com>
d8b24b95
NC		 482
483 * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
484 .short directives so that they can be reassembled.
485
9db8dccb
CM		 4862010-05-26 Catherine Moore <clm@codesourcery.com>
487 David Ung <davidu@mips.com>
488
489 * mips-opc.c: Change membership to I1 for instructions ssnop and
490 ehb.
491
dfc8cf43
L		 4922010-05-26 H.J. Lu <hongjiu.lu@intel.com>
493
494 * i386-dis.c (sib): New.
495 (get_sib): Likewise.
496 (print_insn): Call get_sib.
497 OP_E_memory): Use sib.
498
f79e2745
CM		 4992010-05-26 Catherine Moore <clm@codesoourcery.com>
500
501 * mips-dis.c (mips_arch): Remove INSN_MIPS16.
502 * mips-opc.c (I16): Remove.
503 (mips_builtin_op): Reclassify jalx.
504
51b5d4a8
AM		 5052010-05-19 Alan Modra <amodra@gmail.com>
506
507 * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
508 divwe, divdeuo, divweuo, divdeo, divweo for A2. Add icswepx.
509
85d4ac0b
AM		 5102010-05-13 Alan Modra <amodra@gmail.com>
511
512 * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
513
4547cb56
NC		 5142010-05-11 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
515
516 * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
517 format.
518 (print_insn_thumb16): Add support for new %W format.
519
6540b386
TG		 5202010-05-07 Tristan Gingold <gingold@adacore.com>
521
522 * Makefile.in: Regenerate with automake 1.11.1.
523 * aclocal.m4: Ditto.
524
3e01a7fd
NC		 5252010-05-05 Nick Clifton <nickc@redhat.com>
526
527 * po/es.po: Updated Spanish translation.
528
9c9c98a5
NC		 5292010-04-22 Nick Clifton <nickc@redhat.com>
530
531 * po/opcodes.pot: Updated by the Translation project.
532 * po/vi.po: Updated Vietnamese translation.
533
f07af43e
L		 5342010-04-16 H.J. Lu <hongjiu.lu@intel.com>
535
536 * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
537 bits in opcode.
538
3d540e93
NC		 5392010-04-09 Nick Clifton <nickc@redhat.com>
540
541 * i386-dis.c (print_insn): Remove unused variable op.
542 (OP_sI): Remove unused variable mask.
543
397841b5
AM		 5442010-04-07 Alan Modra <amodra@gmail.com>
545
546 * configure: Regenerate.
547
cee62821
PB		 5482010-04-06 Peter Bergner <bergner@vnet.ibm.com>
549
550 * ppc-opc.c (RBOPT): New define.
551 ("dccci"): Enable for PPCA2. Make operands optional.
552 ("iccci"): Likewise. Do not deprecate for PPC476.
553
accf4463
NC		 5542010-04-02 Masaki Muranaka <monaka@monami-software.com>
555
556 * cr16-opc.c (cr16_instruction): Fix typo in comment.
557
40b36596
JM		 5582010-03-25 Joseph Myers <joseph@codesourcery.com>
559
560 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
561 * Makefile.in: Regenerate.
562 * configure.in (bfd_tic6x_arch): New.
563 * configure: Regenerate.
564 * disassemble.c (ARCH_tic6x): Define if ARCH_all.
565 (disassembler): Handle TI C6X.
566 * tic6x-dis.c: New.
567
1985c81c
MF		 5682010-03-24 Mike Frysinger <vapier@gentoo.org>
569
570 * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
571
f66187fd
JM		 5722010-03-23 Joseph Myers <joseph@codesourcery.com>
573
574 * dis-buf.c (buffer_read_memory): Give error for reading just
575 before the start of memory.
576
ce7d077e
SP		 5772010-03-22 Sebastian Pop <sebastian.pop@amd.com>
578 Quentin Neill <quentin.neill@amd.com>
579
580 * i386-dis.c (OP_LWP_I): Removed.
581 (reg_table): Do not use OP_LWP_I, use Iq.
582 (OP_LWPCB_E): Remove use of names16.
583 (OP_LWP_E): Same.
584 * i386-opc.tbl: Removed 16bit LWP insns. 32bit LWP insns
585 should not set the Vex.length bit.
586 * i386-tbl.h: Regenerated.
587
63d0fa4e
AM		 5882010-02-25 Edmar Wienskoski <edmar@freescale.com>
589
590 * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
591
c060226a
NC		 5922010-02-24 Nick Clifton <nickc@redhat.com>
593
594 PR binutils/6773
595 * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
596 <prefix>asx. Replace <prefix>subaddx with <prefix>sax.
597 (thumb32_opcodes): Likewise.
598
ab7875de
NC		 5992010-02-15 Nick Clifton <nickc@redhat.com>
600
601 * po/vi.po: Updated Vietnamese translation.
602
fee1d3e8
DE		 6032010-02-12 Doug Evans <dje@sebabeach.org>
604
605 * lm32-opinst.c: Regenerate.
606
37ec9240
DE		 6072010-02-11 Doug Evans <dje@sebabeach.org>
608
9468ae89
DE		 609 * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
610 (print_address): Delete CGEN_PRINT_ADDRESS.
611 * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
612 * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
613 * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
614 * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
615
37ec9240
DE		 616 * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
617 * frv-desc.c, * frv-desc.h, * frv-opc.c,
618 * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
619 * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
620 * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
621 * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
622 * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
623 * mep-desc.c, * mep-desc.h, * mep-opc.c,
624 * mt-desc.c, * mt-desc.h, * mt-opc.c,
625 * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
626 * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
627 * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
628
c75ef631
L		 6292010-02-11 H.J. Lu <hongjiu.lu@intel.com>
630
631 * i386-dis.c: Update copyright.
632 * i386-gen.c: Likewise.
633 * i386-opc.h: Likewise.
634 * i386-opc.tbl: Likewise.
635
a683cc34
SP		 6362010-02-10 Quentin Neill <quentin.neill@amd.com>
637 Sebastian Pop <sebastian.pop@amd.com>
638
639 * i386-dis.c (OP_EX_VexImmW): Reintroduced
640 function to handle 5th imm8 operand.
641 (PREFIX_VEX_3A48): Added.
642 (PREFIX_VEX_3A49): Added.
643 (VEX_W_3A48_P_2): Added.
644 (VEX_W_3A49_P_2): Added.
645 (prefix table): Added entries for PREFIX_VEX_3A48
646 and PREFIX_VEX_3A49.
647 (vex table): Added entries for VEX_W_3A48_P_2 and
648 and VEX_W_3A49_P_2.
649 * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
650 for Vec_Imm4 operands.
651 * i386-opc.h (enum): Added Vec_Imm4.
652 (i386_operand_type): Added vec_imm4.
653 * i386-opc.tbl: Add entries for vpermilp[ds].
654 * i386-init.h: Regenerated.
655 * i386-tbl.h: Regenerated.
656
cdc51b07
RS		 6572010-02-10 Richard Sandiford <r.sandiford@uk.ibm.com>
658
659 * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
660 and "pwr7". Move "a2" into alphabetical order.
661
ce3d2015
AM		 6622010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
663
664 * ppc-dis.c (ppc_opts): Add titan entry.
665 * ppc-opc.c (TITAN, MULHW): Define.
666 (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
667
68339fdf
SP		 6682010-02-03 Quentin Neill <quentin.neill@amd.com>
669
670 * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
671 to CPU_BDVER1_FLAGS
672 * i386-init.h: Regenerated.
673
f3d55a94
AG		 6742010-02-03 Anthony Green <green@moxielogic.com>
675
676 * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
677 0x0f, and make 0x00 an illegal instruction.
678
b0e28b39
DJ		 6792010-01-29 Daniel Jacobowitz <dan@codesourcery.com>
680
681 * opcodes/arm-dis.c (struct arm_private_data): New.
682 (print_insn_coprocessor, print_insn_arm): Update to use struct
683 arm_private_data.
684 (is_mapping_symbol, get_map_sym_type): New functions.
685 (get_sym_code_type): Check the symbol's section. Do not check
686 mapping symbols.
687 (print_insn): Default to disassembling ARM mode code. Check
688 for mapping symbols separately from other symbols. Use
689 struct arm_private_data.
690
1c480963
L		 6912010-01-28 H.J. Lu <hongjiu.lu@intel.com>
692
693 * i386-dis.c (EXVexWdqScalar): New.
694 (vex_scalar_w_dq_mode): Likewise.
695 (prefix_table): Update entries for PREFIX_VEX_3899,
696 PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
697 PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
698 PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
699 PREFIX_VEX_38BD and PREFIX_VEX_38BF.
700 (intel_operand_size): Handle vex_scalar_w_dq_mode.
701 (OP_EX): Likewise.
702
539f890d
L		 7032010-01-27 H.J. Lu <hongjiu.lu@intel.com>
704
705 * i386-dis.c (XMScalar): New.
706 (EXdScalar): Likewise.
707 (EXqScalar): Likewise.
708 (EXqScalarS): Likewise.
709 (VexScalar): Likewise.
710 (EXdVexScalarS): Likewise.
711 (EXqVexScalarS): Likewise.
712 (XMVexScalar): Likewise.
713 (scalar_mode): Likewise.
714 (d_scalar_mode): Likewise.
715 (d_scalar_swap_mode): Likewise.
716 (q_scalar_mode): Likewise.
717 (q_scalar_swap_mode): Likewise.
718 (vex_scalar_mode): Likewise.
719 (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
720 VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
721 VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
722 VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
723 VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
724 VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
725 VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
726 VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
727 VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
728 VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
729 (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
730 VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
731 VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
732 VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
733 VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
734 VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
735 VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
736 VEX_W_7E_P_1, VEX_W_D6_P_2 VEX_W_C2_P_1, VEX_W_C2_P_3,
737 VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
738 (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
739 q_scalar_mode, q_scalar_swap_mode.
740 (OP_XMM): Handle scalar_mode.
741 (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
742 and q_scalar_swap_mode.
743 (OP_VEX): Handle vex_scalar_mode.
744
208b4d78
L		 7452010-01-24 H.J. Lu <hongjiu.lu@intel.com>
746
747 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
748
448b213a
L		 7492010-01-24 H.J. Lu <hongjiu.lu@intel.com>
750
751 * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
752
47cf8fa0
L		 7532010-01-24 H.J. Lu <hongjiu.lu@intel.com>
754
755 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
756
592d1631
L		 7572010-01-24 H.J. Lu <hongjiu.lu@intel.com>
758
759 * i386-dis.c (Bad_Opcode): New.
760 (bad_opcode): Likewise.
761 (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
762 (dis386_twobyte): Likewise.
763 (reg_table): Likewise.
764 (prefix_table): Likewise.
765 (x86_64_table): Likewise.
766 (vex_len_table): Likewise.
767 (vex_w_table): Likewise.
768 (mod_table): Likewise.
769 (rm_table): Likewise.
770 (float_reg): Likewise.
771 (reg_table): Remove trailing "(bad)" entries.
772 (prefix_table): Likewise.
773 (x86_64_table): Likewise.
774 (vex_len_table): Likewise.
775 (vex_w_table): Likewise.
776 (mod_table): Likewise.
777 (rm_table): Likewise.
778 (get_valid_dis386): Handle bytemode 0.
779
712366da
L		 7802010-01-23 H.J. Lu <hongjiu.lu@intel.com>
781
782 * i386-opc.h (VEXScalar): New.
783
784 * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
785 instructions.
786 * i386-tbl.h: Regenerated.
787
706e8205 7882010-01-21 H.J. Lu <hongjiu.lu@intel.com>
73bb6729
L		 789
790 * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
791
792 * i386-opc.tbl: Add xsave64 and xrstor64.
793 * i386-tbl.h: Regenerated.
794
99ea83aa
NC		 7952010-01-20 Nick Clifton <nickc@redhat.com>
796
797 PR 11170
798 * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
799 based post-indexed addressing.
800
a6461c02
SP		 8012010-01-15 Sebastian Pop <sebastian.pop@amd.com>
802
803 * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
804 * i386-tbl.h: Regenerated.
805
a2a7d12c
L		 8062010-01-14 H.J. Lu <hongjiu.lu@intel.com>
807
808 * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
809 comments.
810
b9733481
L		 8112010-01-14 H.J. Lu <hongjiu.lu@intel.com>
812
813 * i386-dis.c (names_mm): New.
814 (intel_names_mm): Likewise.
815 (att_names_mm): Likewise.
816 (names_xmm): Likewise.
817 (intel_names_xmm): Likewise.
818 (att_names_xmm): Likewise.
819 (names_ymm): Likewise.
820 (intel_names_ymm): Likewise.
821 (att_names_ymm): Likewise.
822 (print_insn): Set names_mm, names_xmm and names_ymm.
823 (OP_MMX): Use names_mm, names_xmm and names_ymm.
824 (OP_XMM): Likewise.
825 (OP_EM): Likewise.
826 (OP_EMC): Likewise.
827 (OP_MXC): Likewise.
828 (OP_EX): Likewise.
829 (XMM_Fixup): Likewise.
830 (OP_VEX): Likewise.
831 (OP_EX_VexReg): Likewise.
832 (OP_Vex_2src): Likewise.
833 (OP_Vex_2src_1): Likewise.
834 (OP_Vex_2src_2): Likewise.
835 (OP_REG_VexI4): Likewise.
836
5e6718e4
L		 8372010-01-13 H.J. Lu <hongjiu.lu@intel.com>
838
839 * i386-dis.c (print_insn): Update comments.
840
d869730d
L		 8412010-01-12 H.J. Lu <hongjiu.lu@intel.com>
842
843 * i386-dis.c (rex_original): Removed.
844 (ckprefix): Remove rex_original.
845 (print_insn): Update comments.
846
3725885a
RW		 8472010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
848
849 * Makefile.in: Regenerate.
850 * configure: Regenerate.
851
b7cd1872
DE		 8522010-01-07 Doug Evans <dje@sebabeach.org>
853
854 * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
855 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
856 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
857 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
858 * xstormy16-ibld.c: Regenerate.
859
69dd9865
SP		 8602010-01-06 Quentin Neill <quentin.neill@amd.com>
861
862 * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
863 * i386-init.h: Regenerated.
864
e3e535bc
NC		 8652010-01-06 Daniel Gutson <dgutson@codesourcery.com>
866
867 * arm-dis.c (print_insn): Fixed search for next symbol and data
868 dumping condition, and the initial mapping symbol state.
869
fe8afbc4
DE		 8702010-01-05 Doug Evans <dje@sebabeach.org>
871
872 * cgen-ibld.in: #include "cgen/basic-modes.h".
873 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
874 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
875 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
876 * xstormy16-ibld.c: Regenerate.
877
2edcd244
NC		 8782010-01-04 Nick Clifton <nickc@redhat.com>
879
880 PR 11123
881 * arm-dis.c (print_insn_coprocessor): Initialise value.
882
0dc93057
AM		 8832010-01-04 Edmar Wienskoski <edmar@freescale.com>
884
885 * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
886
05994f45
DE		 8872010-01-02 Doug Evans <dje@sebabeach.org>
888
889 * cgen-asm.in: Update copyright year.
890 * cgen-dis.in: Update copyright year.
891 * cgen-ibld.in: Update copyright year.
892 * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
893 * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
894 * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
895 * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
896 * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
897 * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
898 * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
899 * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
900 * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
901 * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
902 * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
903 * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
904 * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
905 * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
906 * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
907 * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
908 * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
909 * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
910 * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
911 * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
912 * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
2426c15f 913
43ecc30f 914For older changes see ChangeLog-2009
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RH		 915\f
916Local Variables:
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NC		 917mode: change-log
918left-margin: 8
919fill-column: 74
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RH		 920version-control: never
921End:
GDB Binutils - Deliverables
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