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Constify command_line_input
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
f74a6307
JB		 12019-11-08 Jan Beulich <jbeulich@suse.com>
2
3 * i386-gen.c (operand_type_init): Add Class= to
4 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
5 OPERAND_TYPE_REGBND entry.
6 (operand_classes): Add RegMask and RegBND entries.
7 (operand_types): Drop RegMask and RegBND entry.
8 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
9 (RegMask, RegBND): Delete.
10 (union i386_operand_type): Remove regmask and regbnd fields.
11 * i386-opc.tbl (RegMask, RegBND): Define.
12 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
13 Class=RegBND.
14 * i386-init.h, i386-tbl.h: Re-generate.
15
3528c362
JB		 162019-11-08 Jan Beulich <jbeulich@suse.com>
17
18 * i386-gen.c (operand_type_init): Add Class= to
19 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
20 OPERAND_TYPE_REGZMM entries.
21 (operand_classes): Add RegMMX and RegSIMD entries.
22 (operand_types): Drop RegMMX and RegSIMD entries.
23 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
24 (RegMMX, RegSIMD): Delete.
25 (union i386_operand_type): Remove regmmx and regsimd fields.
26 * i386-opc.tbl (RegMMX): Define.
27 (RegXMM, RegYMM, RegZMM): Add Class=.
28 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
29 Class=RegSIMD.
30 * i386-init.h, i386-tbl.h: Re-generate.
31
4a5c67ed
JB		 322019-11-08 Jan Beulich <jbeulich@suse.com>
33
34 * i386-gen.c (operand_type_init): Add Class= to
35 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
36 entries.
37 (operand_classes): Add RegCR, RegDR, and RegTR entries.
38 (operand_types): Drop Control, Debug, and Test entries.
39 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
40 (Control, Debug, Test): Delete.
41 (union i386_operand_type): Remove control, debug, and test
42 fields.
43 * i386-opc.tbl (Control, Debug, Test): Define.
44 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
45 Class=RegDR, and Test by Class=RegTR.
46 * i386-init.h, i386-tbl.h: Re-generate.
47
00cee14f
JB		 482019-11-08 Jan Beulich <jbeulich@suse.com>
49
50 * i386-gen.c (operand_type_init): Add Class= to
51 OPERAND_TYPE_SREG entry.
52 (operand_classes): Add SReg entry.
53 (operand_types): Drop SReg entry.
54 * i386-opc.h (enum operand_class): Add SReg.
55 (SReg): Delete.
56 (union i386_operand_type): Remove sreg field.
57 * i386-opc.tbl (SReg): Define.
58 * i386-reg.tbl: Replace SReg by Class=SReg.
59 * i386-init.h, i386-tbl.h: Re-generate.
60
bab6aec1
JB		 612019-11-08 Jan Beulich <jbeulich@suse.com>
62
63 * i386-gen.c (operand_type_init): Add Class=. New
64 OPERAND_TYPE_ANYIMM entry.
65 (operand_classes): New.
66 (operand_types): Drop Reg entry.
67 (output_operand_type): New parameter "class". Process it.
68 (process_i386_operand_type): New local variable "class".
69 (main): Adjust static assertions.
70 * i386-opc.h (CLASS_WIDTH): Define.
71 (enum operand_class): New.
72 (Reg): Replace by Class. Adjust comment.
73 (union i386_operand_type): Replace reg by class.
74 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
75 Class=.
76 * i386-reg.tbl: Replace Reg by Class=Reg.
77 * i386-init.h: Re-generate.
78
1f4cd317
MM		 792019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
80
81 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
82 (aarch64_opcode_table): Add data gathering hint mnemonic.
83 * opcodes/aarch64-dis-2.c: Account for new instruction.
84
616ce08e
MM		 852019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
86
87 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
88
89
8382113f
MM		 902019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
91
92 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
93 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
94 aarch64_feature_f64mm): New feature sets.
95 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
96 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
97 instructions.
98 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
99 macros.
100 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
101 (OP_SVE_QQQ): New qualifier.
102 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
103 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
104 the movprfx constraint.
105 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
106 (aarch64_opcode_table): Define new instructions smmla,
107 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
108 uzip{1/2}, trn{1/2}.
109 * aarch64-opc.c (operand_general_constraint_met_p): Handle
110 AARCH64_OPND_SVE_ADDR_RI_S4x32.
111 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
112 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
113 Account for new instructions.
114 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
115 S4x32 operand.
116 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
117
aab2c27d
MM		 1182019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
1192019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
120
121 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
122 Armv8.6-A.
123 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
124 (neon_opcodes): Add bfloat SIMD instructions.
125 (print_insn_coprocessor): Add new control character %b to print
126 condition code without checking cp_num.
127 (print_insn_neon): Account for BFloat16 instructions that have no
128 special top-byte handling.
129
33593eaf
MM		 1302019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
1312019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
132
133 * arm-dis.c (print_insn_coprocessor,
134 print_insn_generic_coprocessor): Create wrapper functions around
135 the implementation of the print_insn_coprocessor control codes.
136 (print_insn_coprocessor_1): Original print_insn_coprocessor
137 function that now takes which array to look at as an argument.
138 (print_insn_arm): Use both print_insn_coprocessor and
139 print_insn_generic_coprocessor.
140 (print_insn_thumb32): As above.
141
df678013
MM		 1422019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
1432019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
144
145 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
146 in reglane special case.
147 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
148 aarch64_find_next_opcode): Account for new instructions.
149 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
150 in reglane special case.
151 * aarch64-opc.c (struct operand_qualifier_data): Add data for
152 new AARCH64_OPND_QLF_S_2H qualifier.
153 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
154 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
155 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
156 sets.
157 (BFLOAT_SVE, BFLOAT): New feature set macros.
158 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
159 instructions.
160 (aarch64_opcode_table): Define new instructions bfdot,
161 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
162 bfcvtn2, bfcvt.
163
8ae2d3d9
MM		 1642019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
1652019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
166
167 * aarch64-tbl.h (ARMV8_6): New macro.
168
142861df
JB		 1692019-11-07 Jan Beulich <jbeulich@suse.com>
170
171 * i386-dis.c (prefix_table): Add mcommit.
172 (rm_table): Add rdpru.
173 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
174 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
175 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
176 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
177 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
178 * i386-opc.tbl (mcommit, rdpru): New.
179 * i386-init.h, i386-tbl.h: Re-generate.
180
081e283f
JB		 1812019-11-07 Jan Beulich <jbeulich@suse.com>
182
183 * i386-dis.c (OP_Mwait): Drop local variable "names", use
184 "names32" instead.
185 (OP_Monitor): Drop local variable "op1_names", re-purpose
186 "names" for it instead, and replace former "names" uses by
187 "names32" ones.
188
c050c89a
JB		 1892019-11-07 Jan Beulich <jbeulich@suse.com>
190
191 PR/gas 25167
192 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
193 operand-less forms.
194 * opcodes/i386-tbl.h: Re-generate.
195
7abb8d81
JB		 1962019-11-05 Jan Beulich <jbeulich@suse.com>
197
198 * i386-dis.c (OP_Mwaitx): Delete.
199 (prefix_table): Use OP_Mwait for mwaitx entry.
200 (OP_Mwait): Also handle mwaitx.
201
267b8516
JB		 2022019-11-05 Jan Beulich <jbeulich@suse.com>
203
204 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
205 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
206 (prefix_table): Add respective entries.
207 (rm_table): Link to those entries.
208
f8687e93
JB		 2092019-11-05 Jan Beulich <jbeulich@suse.com>
210
211 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
212 (REG_0F1C_P_0_MOD_0): ... this.
213 (REG_0F1E_MOD_3): Rename to ...
214 (REG_0F1E_P_1_MOD_3): ... this.
215 (RM_0F01_REG_5): Rename to ...
216 (RM_0F01_REG_5_MOD_3): ... this.
217 (RM_0F01_REG_7): Rename to ...
218 (RM_0F01_REG_7_MOD_3): ... this.
219 (RM_0F1E_MOD_3_REG_7): Rename to ...
220 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
221 (RM_0FAE_REG_6): Rename to ...
222 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
223 (RM_0FAE_REG_7): Rename to ...
224 (RM_0FAE_REG_7_MOD_3): ... this.
225 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
226 (PREFIX_0F01_REG_5_MOD_0): ... this.
227 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
228 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
229 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
230 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
231 (PREFIX_0FAE_REG_0): Rename to ...
232 (PREFIX_0FAE_REG_0_MOD_3): ... this.
233 (PREFIX_0FAE_REG_1): Rename to ...
234 (PREFIX_0FAE_REG_1_MOD_3): ... this.
235 (PREFIX_0FAE_REG_2): Rename to ...
236 (PREFIX_0FAE_REG_2_MOD_3): ... this.
237 (PREFIX_0FAE_REG_3): Rename to ...
238 (PREFIX_0FAE_REG_3_MOD_3): ... this.
239 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
240 (PREFIX_0FAE_REG_4_MOD_0): ... this.
241 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
242 (PREFIX_0FAE_REG_4_MOD_3): ... this.
243 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
244 (PREFIX_0FAE_REG_5_MOD_0): ... this.
245 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
246 (PREFIX_0FAE_REG_5_MOD_3): ... this.
247 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
248 (PREFIX_0FAE_REG_6_MOD_0): ... this.
249 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
250 (PREFIX_0FAE_REG_6_MOD_3): ... this.
251 (PREFIX_0FAE_REG_7): Rename to ...
252 (PREFIX_0FAE_REG_7_MOD_0): ... this.
253 (PREFIX_MOD_0_0FC3): Rename to ...
254 (PREFIX_0FC3_MOD_0): ... this.
255 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
256 (PREFIX_0FC7_REG_6_MOD_0): ... this.
257 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
258 (PREFIX_0FC7_REG_6_MOD_3): ... this.
259 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
260 (PREFIX_0FC7_REG_7_MOD_3): ... this.
261 (reg_table, prefix_table, mod_table, rm_table): Adjust
262 accordingly.
263
5103274f
NC		 2642019-11-04 Nick Clifton <nickc@redhat.com>
265
266 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
267 of a v850 system register. Move the v850_sreg_names array into
268 this function.
269 (get_v850_reg_name): Likewise for ordinary register names.
270 (get_v850_vreg_name): Likewise for vector register names.
271 (get_v850_cc_name): Likewise for condition codes.
272 * get_v850_float_cc_name): Likewise for floating point condition
273 codes.
274 (get_v850_cacheop_name): Likewise for cache-ops.
275 (get_v850_prefop_name): Likewise for pref-ops.
276 (disassemble): Use the new accessor functions.
277
1820262b
DB		 2782019-10-30 Delia Burduv <delia.burduv@arm.com>
279
280 * aarch64-opc.c (print_immediate_offset_address): Don't print the
281 immediate for the writeback form of ldraa/ldrab if it is 0.
282 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
283 * aarch64-opc-2.c: Regenerated.
284
3cc17af5
JB		 2852019-10-30 Jan Beulich <jbeulich@suse.com>
286
287 * i386-gen.c (operand_type_shorthands): Delete.
288 (operand_type_init): Expand previous shorthands.
289 (set_bitfield_from_shorthand): Rename back to ...
290 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
291 of operand_type_init[].
292 (set_bitfield): Adjust call to the above function.
293 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
294 RegXMM, RegYMM, RegZMM): Define.
295 * i386-reg.tbl: Expand prior shorthands.
296
a2cebd03
JB		 2972019-10-30 Jan Beulich <jbeulich@suse.com>
298
299 * i386-gen.c (output_i386_opcode): Change order of fields
300 emitted to output.
301 * i386-opc.h (struct insn_template): Move operands field.
302 Convert extension_opcode field to unsigned short.
303 * i386-tbl.h: Re-generate.
304
507916b8
JB		 3052019-10-30 Jan Beulich <jbeulich@suse.com>
306
307 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
308 of W.
309 * i386-opc.h (W): Extend comment.
310 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
311 general purpose variants not allowing for byte operands.
312 * i386-tbl.h: Re-generate.
313
efea62b4
NC		 3142019-10-29 Nick Clifton <nickc@redhat.com>
315
316 * tic30-dis.c (print_branch): Correct size of operand array.
317
9adb2591
NC		 3182019-10-29 Nick Clifton <nickc@redhat.com>
319
320 * d30v-dis.c (print_insn): Check that operand index is valid
321 before attempting to access the operands array.
322
993a00a9
NC		 3232019-10-29 Nick Clifton <nickc@redhat.com>
324
325 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
326 locating the bit to be tested.
327
66a66a17
NC		 3282019-10-29 Nick Clifton <nickc@redhat.com>
329
330 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
331 values.
332 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
333 (print_insn_s12z): Check for illegal size values.
334
1ee3542c
NC		 3352019-10-28 Nick Clifton <nickc@redhat.com>
336
337 * csky-dis.c (csky_chars_to_number): Check for a negative
338 count. Use an unsigned integer to construct the return value.
339
bbf9a0b5
NC		 3402019-10-28 Nick Clifton <nickc@redhat.com>
341
342 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
343 operand buffer. Set value to 15 not 13.
344 (get_register_operand): Use OPERAND_BUFFER_LEN.
345 (get_indirect_operand): Likewise.
346 (print_two_operand): Likewise.
347 (print_three_operand): Likewise.
348 (print_oar_insn): Likewise.
349
d1e304bc
NC		 3502019-10-28 Nick Clifton <nickc@redhat.com>
351
352 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
353 (bit_extract_simple): Likewise.
354 (bit_copy): Likewise.
355 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
356 index_offset array are not accessed.
357
dee33451
NC		 3582019-10-28 Nick Clifton <nickc@redhat.com>
359
360 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
361 operand.
362
27cee81d
NC		 3632019-10-25 Nick Clifton <nickc@redhat.com>
364
365 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
366 access to opcodes.op array element.
367
de6d8dc2
NC		 3682019-10-23 Nick Clifton <nickc@redhat.com>
369
370 * rx-dis.c (get_register_name): Fix spelling typo in error
371 message.
372 (get_condition_name, get_flag_name, get_double_register_name)
373 (get_double_register_high_name, get_double_register_low_name)
374 (get_double_control_register_name, get_double_condition_name)
375 (get_opsize_name, get_size_name): Likewise.
376
6207ed28
NC		 3772019-10-22 Nick Clifton <nickc@redhat.com>
378
379 * rx-dis.c (get_size_name): New function. Provides safe
380 access to name array.
381 (get_opsize_name): Likewise.
382 (print_insn_rx): Use the accessor functions.
383
12234dfd
NC		 3842019-10-16 Nick Clifton <nickc@redhat.com>
385
386 * rx-dis.c (get_register_name): New function. Provides safe
387 access to name array.
388 (get_condition_name, get_flag_name, get_double_register_name)
389 (get_double_register_high_name, get_double_register_low_name)
390 (get_double_control_register_name, get_double_condition_name):
391 Likewise.
392 (print_insn_rx): Use the accessor functions.
393
1d378749
NC		 3942019-10-09 Nick Clifton <nickc@redhat.com>
395
396 PR 25041
397 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
398 instructions.
399
d241b910
JB		 4002019-10-07 Jan Beulich <jbeulich@suse.com>
401
402 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
403 (cmpsd): Likewise. Move EsSeg to other operand.
404 * opcodes/i386-tbl.h: Re-generate.
405
f5c5b7c1
AM		 4062019-09-23 Alan Modra <amodra@gmail.com>
407
408 * m68k-dis.c: Include cpu-m68k.h
409
7beeaeb8
AM		 4102019-09-23 Alan Modra <amodra@gmail.com>
411
412 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
413 "elf/mips.h" earlier.
414
3f9aad11
JB		 4152018-09-20 Jan Beulich <jbeulich@suse.com>
416
417 PR gas/25012
418 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
419 with SReg operand.
420 * i386-tbl.h: Re-generate.
421
fd361982
AM		 4222019-09-18 Alan Modra <amodra@gmail.com>
423
424 * arc-ext.c: Update throughout for bfd section macro changes.
425
e0b2a78c
SM		 4262019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
427
428 * Makefile.in: Re-generate.
429 * configure: Re-generate.
430
7e9ad3a3
JW		 4312019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
432
433 * riscv-opc.c (riscv_opcodes): Change subset field
434 to insn_class field for all instructions.
435 (riscv_insn_types): Likewise.
436
bb695960
PB		 4372019-09-16 Phil Blundell <pb@pbcl.net>
438
439 * configure: Regenerated.
440
8063ab7e
MV		 4412019-09-10 Miod Vallat <miod@online.fr>
442
443 PR 24982
444 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
445
60391a25
PB		 4462019-09-09 Phil Blundell <pb@pbcl.net>
447
448 binutils 2.33 branch created.
449
f44b758d
NC		 4502019-09-03 Nick Clifton <nickc@redhat.com>
451
452 PR 24961
453 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
454 greater than zero before indexing via (bufcnt -1).
455
1e4b5e7d
NC		 4562019-09-03 Nick Clifton <nickc@redhat.com>
457
458 PR 24958
459 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
460 (MAX_SPEC_REG_NAME_LEN): Define.
461 (struct mmix_dis_info): Use defined constants for array lengths.
462 (get_reg_name): New function.
463 (get_sprec_reg_name): New function.
464 (print_insn_mmix): Use new functions.
465
c4a23bf8
SP		 4662019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
467
468 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
469 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
470 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
471
a051e2f3
KT		 4722019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
473
474 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
475 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
476 (aarch64_sys_reg_supported_p): Update checks for the above.
477
08132bdd
SP		 4782019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
479
480 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
481 cases MVE_SQRSHRL and MVE_UQRSHLL.
482 (print_insn_mve): Add case for specifier 'k' to check
483 specific bit of the instruction.
484
d88bdcb4
PA		 4852019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
486
487 PR 24854
488 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
489 encountering an unknown machine type.
490 (print_insn_arc): Handle arc_insn_length returning 0. In error
491 cases return -1 rather than calling abort.
492
bc750500
JB		 4932019-08-07 Jan Beulich <jbeulich@suse.com>
494
495 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
496 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
497 IgnoreSize.
498 * i386-tbl.h: Re-generate.
499
23d188c7
BW		 5002019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
501
502 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
503 instructions.
504
c0d6f62f
JW		 5052019-07-30 Mel Chen <mel.chen@sifive.com>
506
507 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
508 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
509
510 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
511 fscsr.
512
0f3f7167
CZ		 5132019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
514
515 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
516 and MPY class instructions.
517 (parse_option): Add nps400 option.
518 (print_arc_disassembler_options): Add nps400 info.
519
7e126ba3
CZ		 5202019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
521
522 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
523 (bspop): Likewise.
524 (modapp): Likewise.
525 * arc-opc.c (RAD_CHK): Add.
526 * arc-tbl.h: Regenerate.
527
a028026d
KT		 5282019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
529
530 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
531 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
532
ac79ff9e
NC		 5332019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
534
535 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
536 instructions as UNPREDICTABLE.
537
231097b0
JM		 5382019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
539
540 * bpf-desc.c: Regenerated.
541
1d942ae9
JB		 5422019-07-17 Jan Beulich <jbeulich@suse.com>
543
544 * i386-gen.c (static_assert): Define.
545 (main): Use it.
546 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
547 (Opcode_Modifier_Num): ... this.
548 (Mem): Delete.
549
dfd69174
JB		 5502019-07-16 Jan Beulich <jbeulich@suse.com>
551
552 * i386-gen.c (operand_types): Move RegMem ...
553 (opcode_modifiers): ... here.
554 * i386-opc.h (RegMem): Move to opcode modifer enum.
555 (union i386_operand_type): Move regmem field ...
556 (struct i386_opcode_modifier): ... here.
557 * i386-opc.tbl (RegMem): Define.
558 (mov, movq): Move RegMem on segment, control, debug, and test
559 register flavors.
560 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
561 to non-SSE2AVX flavor.
562 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
563 Move RegMem on register only flavors. Drop IgnoreSize from
564 legacy encoding flavors.
565 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
566 flavors.
567 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
568 register only flavors.
569 (vmovd): Move RegMem and drop IgnoreSize on register only
570 flavor. Change opcode and operand order to store form.
571 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
572
21df382b
JB		 5732019-07-16 Jan Beulich <jbeulich@suse.com>
574
575 * i386-gen.c (operand_type_init, operand_types): Replace SReg
576 entries.
577 * i386-opc.h (SReg2, SReg3): Replace by ...
578 (SReg): ... this.
579 (union i386_operand_type): Replace sreg fields.
580 * i386-opc.tbl (mov, ): Use SReg.
581 (push, pop): Likewies. Drop i386 and x86-64 specific segment
582 register flavors.
583 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
584 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
585
3719fd55
JM		 5862019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
587
588 * bpf-desc.c: Regenerate.
589 * bpf-opc.c: Likewise.
590 * bpf-opc.h: Likewise.
591
92434a14
JM		 5922019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
593
594 * bpf-desc.c: Regenerate.
595 * bpf-opc.c: Likewise.
596
43dd7626
HPN		 5972019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
598
599 * arm-dis.c (print_insn_coprocessor): Rename index to
600 index_operand.
601
98602811
JW		 6022019-07-05 Kito Cheng <kito.cheng@sifive.com>
603
604 * riscv-opc.c (riscv_insn_types): Add r4 type.
605
606 * riscv-opc.c (riscv_insn_types): Add b and j type.
607
608 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
609 format for sb type and correct s type.
610
01c1ee4a
RS		 6112019-07-02 Richard Sandiford <richard.sandiford@arm.com>
612
613 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
614 SVE FMOV alias of FCPY.
615
83adff69
RS		 6162019-07-02 Richard Sandiford <richard.sandiford@arm.com>
617
618 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
619 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
620
89418844
RS		 6212019-07-02 Richard Sandiford <richard.sandiford@arm.com>
622
623 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
624 registers in an instruction prefixed by MOVPRFX.
625
41be57ca
MM		 6262019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
627
628 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
629 sve_size_13 icode to account for variant behaviour of
630 pmull{t,b}.
631 * aarch64-dis-2.c: Regenerate.
632 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
633 sve_size_13 icode to account for variant behaviour of
634 pmull{t,b}.
635 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
636 (OP_SVE_VVV_Q_D): Add new qualifier.
637 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
638 (struct aarch64_opcode): Split pmull{t,b} into those requiring
639 AES and those not.
640
9d3bf266
JB		 6412019-07-01 Jan Beulich <jbeulich@suse.com>
642
643 * opcodes/i386-gen.c (operand_type_init): Remove
644 OPERAND_TYPE_VEC_IMM4 entry.
645 (operand_types): Remove Vec_Imm4.
646 * opcodes/i386-opc.h (Vec_Imm4): Delete.
647 (union i386_operand_type): Remove vec_imm4.
648 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
649 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
650
c3949f43
JB		 6512019-07-01 Jan Beulich <jbeulich@suse.com>
652
653 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
654 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
655 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
656 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
657 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
658 monitorx, mwaitx): Drop ImmExt from operand-less forms.
659 * i386-tbl.h: Re-generate.
660
5641ec01
JB		 6612019-07-01 Jan Beulich <jbeulich@suse.com>
662
663 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
664 register operands.
665 * i386-tbl.h: Re-generate.
666
79dec6b7
JB		 6672019-07-01 Jan Beulich <jbeulich@suse.com>
668
669 * i386-opc.tbl (C): New.
670 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
671 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
672 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
673 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
674 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
675 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
676 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
677 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
678 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
679 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
680 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
681 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
682 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
683 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
684 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
685 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
686 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
687 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
688 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
689 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
690 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
691 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
692 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
693 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
694 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
695 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
696 flavors.
697 * i386-tbl.h: Re-generate.
698
a0a1771e
JB		 6992019-07-01 Jan Beulich <jbeulich@suse.com>
700
701 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
702 register operands.
703 * i386-tbl.h: Re-generate.
704
cd546e7b
JB		 7052019-07-01 Jan Beulich <jbeulich@suse.com>
706
707 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
708 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
709 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
710 * i386-tbl.h: Re-generate.
711
e3bba3fc
JB		 7122019-07-01 Jan Beulich <jbeulich@suse.com>
713
714 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
715 Disp8MemShift from register only templates.
716 * i386-tbl.h: Re-generate.
717
36cc073e
JB		 7182019-07-01 Jan Beulich <jbeulich@suse.com>
719
720 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
721 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
722 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
723 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
724 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
725 EVEX_W_0F11_P_3_M_1): Delete.
726 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
727 EVEX_W_0F11_P_3): New.
728 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
729 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
730 MOD_EVEX_0F11_PREFIX_3 table entries.
731 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
732 PREFIX_EVEX_0F11 table entries.
733 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
734 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
735 EVEX_W_0F11_P_3_M_{0,1} table entries.
736
219920a7
JB		 7372019-07-01 Jan Beulich <jbeulich@suse.com>
738
739 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
740 Delete.
741
e395f487
L		 7422019-06-27 H.J. Lu <hongjiu.lu@intel.com>
743
744 PR binutils/24719
745 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
746 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
747 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
748 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
749 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
750 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
751 EVEX_LEN_0F38C7_R_6_P_2_W_1.
752 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
753 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
754 PREFIX_EVEX_0F38C6_REG_6 entries.
755 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
756 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
757 EVEX_W_0F38C7_R_6_P_2 entries.
758 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
759 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
760 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
761 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
762 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
763 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
764 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
765
2b7bcc87
JB		 7662019-06-27 Jan Beulich <jbeulich@suse.com>
767
768 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
769 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
770 VEX_LEN_0F2D_P_3): Delete.
771 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
772 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
773 (prefix_table): ... here.
774
c1dc7af5
JB		 7752019-06-27 Jan Beulich <jbeulich@suse.com>
776
777 * i386-dis.c (Iq): Delete.
778 (Id): New.
779 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
780 TBM insns.
781 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
782 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
783 (OP_E_memory): Also honor needindex when deciding whether an
784 address size prefix needs printing.
785 (OP_I): Remove handling of q_mode. Add handling of d_mode.
786
d7560e2d
JW		 7872019-06-26 Jim Wilson <jimw@sifive.com>
788
789 PR binutils/24739
790 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
791 Set info->display_endian to info->endian_code.
792
2c703856
JB		 7932019-06-25 Jan Beulich <jbeulich@suse.com>
794
795 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
796 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
797 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
798 OPERAND_TYPE_ACC64 entries.
799 * i386-init.h: Re-generate.
800
54fbadc0
JB		 8012019-06-25 Jan Beulich <jbeulich@suse.com>
802
803 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
804 Delete.
805 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
806 of dqa_mode.
807 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
808 entries here.
809 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
810 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
811
a280ab8e
JB		 8122019-06-25 Jan Beulich <jbeulich@suse.com>
813
814 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
815 variables.
816
e1a1babd
JB		 8172019-06-25 Jan Beulich <jbeulich@suse.com>
818
819 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
820 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
821 movnti.
d7560e2d 822 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 823 * i386-tbl.h: Re-generate.
824
b8364fa7
JB		 8252019-06-25 Jan Beulich <jbeulich@suse.com>
826
827 * i386-opc.tbl (and): Mark Imm8S form for optimization.
828 * i386-tbl.h: Re-generate.
829
ad692897
L		 8302019-06-21 H.J. Lu <hongjiu.lu@intel.com>
831
832 * i386-dis-evex.h: Break into ...
833 * i386-dis-evex-len.h: New file.
834 * i386-dis-evex-mod.h: Likewise.
835 * i386-dis-evex-prefix.h: Likewise.
836 * i386-dis-evex-reg.h: Likewise.
837 * i386-dis-evex-w.h: Likewise.
838 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
839 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
840 i386-dis-evex-mod.h.
841
f0a6222e
L		 8422019-06-19 H.J. Lu <hongjiu.lu@intel.com>
843
844 PR binutils/24700
845 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
846 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
847 EVEX_W_0F385B_P_2.
848 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
849 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
850 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
851 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
852 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
853 EVEX_LEN_0F385B_P_2_W_1.
854 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
855 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
856 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
857 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
858 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
859 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
860 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
861 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
862 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
863 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
864
6e1c90b7
L		 8652019-06-17 H.J. Lu <hongjiu.lu@intel.com>
866
867 PR binutils/24691
868 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
869 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
870 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
871 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
872 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
873 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
874 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
875 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
876 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
877 EVEX_LEN_0F3A43_P_2_W_1.
878 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
879 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
880 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
881 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
882 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
883 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
884 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
885 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
886 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
887 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
888 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
889 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
890
bcc5a6eb
NC		 8912019-06-14 Nick Clifton <nickc@redhat.com>
892
893 * po/fr.po; Updated French translation.
894
e4c4ac46
SH		 8952019-06-13 Stafford Horne <shorne@gmail.com>
896
897 * or1k-asm.c: Regenerated.
898 * or1k-desc.c: Regenerated.
899 * or1k-desc.h: Regenerated.
900 * or1k-dis.c: Regenerated.
901 * or1k-ibld.c: Regenerated.
902 * or1k-opc.c: Regenerated.
903 * or1k-opc.h: Regenerated.
904 * or1k-opinst.c: Regenerated.
905
a0e44ef5
PB		 9062019-06-12 Peter Bergner <bergner@linux.ibm.com>
907
908 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
909
12efd68d
L		 9102019-06-05 H.J. Lu <hongjiu.lu@intel.com>
911
912 PR binutils/24633
913 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
914 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
915 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
916 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
917 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
918 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
919 EVEX_LEN_0F3A1B_P_2_W_1.
920 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
921 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
922 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
923 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
924 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
925 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
926 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
927 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
928
63c6fc6c
L		 9292019-06-04 H.J. Lu <hongjiu.lu@intel.com>
930
931 PR binutils/24626
932 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
933 EVEX.vvvv when disassembling VEX and EVEX instructions.
934 (OP_VEX): Set vex.register_specifier to 0 after readding
935 vex.register_specifier.
936 (OP_Vex_2src_1): Likewise.
937 (OP_Vex_2src_2): Likewise.
938 (OP_LWP_E): Likewise.
939 (OP_EX_Vex): Don't check vex.register_specifier.
940 (OP_XMM_Vex): Likewise.
941
9186c494
L		 9422019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
943 Lili Cui <lili.cui@intel.com>
944
945 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
946 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
947 instructions.
948 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
949 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
950 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
951 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
952 (i386_cpu_flags): Add cpuavx512_vp2intersect.
953 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
954 * i386-init.h: Regenerated.
955 * i386-tbl.h: Likewise.
956
5d79adc4
L		 9572019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
958 Lili Cui <lili.cui@intel.com>
959
960 * doc/c-i386.texi: Document enqcmd.
961 * testsuite/gas/i386/enqcmd-intel.d: New file.
962 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
963 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
964 * testsuite/gas/i386/enqcmd.d: Likewise.
965 * testsuite/gas/i386/enqcmd.s: Likewise.
966 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
967 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
968 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
969 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
970 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
971 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
972 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
973 and x86-64-enqcmd.
974
a9d96ab9
AH		 9752019-06-04 Alan Hayward <alan.hayward@arm.com>
976
977 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
978
4f6d070a
AM		 9792019-06-03 Alan Modra <amodra@gmail.com>
980
981 * ppc-dis.c (prefix_opcd_indices): Correct size.
982
a2f4b66c
L		 9832019-05-28 H.J. Lu <hongjiu.lu@intel.com>
984
985 PR gas/24625
986 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
987 Disp8ShiftVL.
988 * i386-tbl.h: Regenerated.
989
405b5bd8
AM		 9902019-05-24 Alan Modra <amodra@gmail.com>
991
992 * po/POTFILES.in: Regenerate.
993
8acf1435
PB		 9942019-05-24 Peter Bergner <bergner@linux.ibm.com>
995 Alan Modra <amodra@gmail.com>
996
997 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
998 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
999 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1000 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1001 XTOP>): Define and add entries.
1002 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1003 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1004 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1005 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1006
dd7efa79
PB		 10072019-05-24 Peter Bergner <bergner@linux.ibm.com>
1008 Alan Modra <amodra@gmail.com>
1009
1010 * ppc-dis.c (ppc_opts): Add "future" entry.
1011 (PREFIX_OPCD_SEGS): Define.
1012 (prefix_opcd_indices): New array.
1013 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1014 (lookup_prefix): New function.
1015 (print_insn_powerpc): Handle 64-bit prefix instructions.
1016 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1017 (PMRR, POWERXX): Define.
1018 (prefix_opcodes): New instruction table.
1019 (prefix_num_opcodes): New constant.
1020
79472b45
JM		 10212019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1022
1023 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1024 * configure: Regenerated.
1025 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1026 and cpu/bpf.opc.
1027 (HFILES): Add bpf-desc.h and bpf-opc.h.
1028 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1029 bpf-ibld.c and bpf-opc.c.
1030 (BPF_DEPS): Define.
1031 * Makefile.in: Regenerated.
1032 * disassemble.c (ARCH_bpf): Define.
1033 (disassembler): Add case for bfd_arch_bpf.
1034 (disassemble_init_for_target): Likewise.
1035 (enum epbf_isa_attr): Define.
1036 * disassemble.h: extern print_insn_bpf.
1037 * bpf-asm.c: Generated.
1038 * bpf-opc.h: Likewise.
1039 * bpf-opc.c: Likewise.
1040 * bpf-ibld.c: Likewise.
1041 * bpf-dis.c: Likewise.
1042 * bpf-desc.h: Likewise.
1043 * bpf-desc.c: Likewise.
1044
ba6cd17f
SD		 10452019-05-21 Sudakshina Das <sudi.das@arm.com>
1046
1047 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1048 and VMSR with the new operands.
1049
e39c1607
SD		 10502019-05-21 Sudakshina Das <sudi.das@arm.com>
1051
1052 * arm-dis.c (enum mve_instructions): New enum
1053 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1054 and cneg.
1055 (mve_opcodes): New instructions as above.
1056 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1057 csneg and csel.
1058 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1059
23d00a41
SD		 10602019-05-21 Sudakshina Das <sudi.das@arm.com>
1061
1062 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1063 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1064 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1065 uqshl, urshrl and urshr.
1066 (is_mve_okay_in_it): Add new instructions to TRUE list.
1067 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1068 (print_insn_mve): Updated to accept new %j,
1069 %<bitfield>m and %<bitfield>n patterns.
1070
cd4797ee
FS		 10712019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1072
1073 * mips-opc.c (mips_builtin_opcodes): Change source register
1074 constraint for DAUI.
1075
999b073b
NC		 10762019-05-20 Nick Clifton <nickc@redhat.com>
1077
1078 * po/fr.po: Updated French translation.
1079
14b456f2
AV		 10802019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1081 Michael Collison <michael.collison@arm.com>
1082
1083 * arm-dis.c (thumb32_opcodes): Add new instructions.
1084 (enum mve_instructions): Likewise.
1085 (enum mve_undefined): Add new reasons.
1086 (is_mve_encoding_conflict): Handle new instructions.
1087 (is_mve_undefined): Likewise.
1088 (is_mve_unpredictable): Likewise.
1089 (print_mve_undefined): Likewise.
1090 (print_mve_size): Likewise.
1091
f49bb598
AV		 10922019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1093 Michael Collison <michael.collison@arm.com>
1094
1095 * arm-dis.c (thumb32_opcodes): Add new instructions.
1096 (enum mve_instructions): Likewise.
1097 (is_mve_encoding_conflict): Handle new instructions.
1098 (is_mve_undefined): Likewise.
1099 (is_mve_unpredictable): Likewise.
1100 (print_mve_size): Likewise.
1101
56858bea
AV		 11022019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1103 Michael Collison <michael.collison@arm.com>
1104
1105 * arm-dis.c (thumb32_opcodes): Add new instructions.
1106 (enum mve_instructions): Likewise.
1107 (is_mve_encoding_conflict): Likewise.
1108 (is_mve_unpredictable): Likewise.
1109 (print_mve_size): Likewise.
1110
e523f101
AV		 11112019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1112 Michael Collison <michael.collison@arm.com>
1113
1114 * arm-dis.c (thumb32_opcodes): Add new instructions.
1115 (enum mve_instructions): Likewise.
1116 (is_mve_encoding_conflict): Handle new instructions.
1117 (is_mve_undefined): Likewise.
1118 (is_mve_unpredictable): Likewise.
1119 (print_mve_size): Likewise.
1120
66dcaa5d
AV		 11212019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1122 Michael Collison <michael.collison@arm.com>
1123
1124 * arm-dis.c (thumb32_opcodes): Add new instructions.
1125 (enum mve_instructions): Likewise.
1126 (is_mve_encoding_conflict): Handle new instructions.
1127 (is_mve_undefined): Likewise.
1128 (is_mve_unpredictable): Likewise.
1129 (print_mve_size): Likewise.
1130 (print_insn_mve): Likewise.
1131
d052b9b7
AV		 11322019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1133 Michael Collison <michael.collison@arm.com>
1134
1135 * arm-dis.c (thumb32_opcodes): Add new instructions.
1136 (print_insn_thumb32): Handle new instructions.
1137
ed63aa17
AV		 11382019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1139 Michael Collison <michael.collison@arm.com>
1140
1141 * arm-dis.c (enum mve_instructions): Add new instructions.
1142 (enum mve_undefined): Add new reasons.
1143 (is_mve_encoding_conflict): Handle new instructions.
1144 (is_mve_undefined): Likewise.
1145 (is_mve_unpredictable): Likewise.
1146 (print_mve_undefined): Likewise.
1147 (print_mve_size): Likewise.
1148 (print_mve_shift_n): Likewise.
1149 (print_insn_mve): Likewise.
1150
897b9bbc
AV		 11512019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1152 Michael Collison <michael.collison@arm.com>
1153
1154 * arm-dis.c (enum mve_instructions): Add new instructions.
1155 (is_mve_encoding_conflict): Handle new instructions.
1156 (is_mve_unpredictable): Likewise.
1157 (print_mve_rotate): Likewise.
1158 (print_mve_size): Likewise.
1159 (print_insn_mve): Likewise.
1160
1c8f2df8
AV		 11612019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1162 Michael Collison <michael.collison@arm.com>
1163
1164 * arm-dis.c (enum mve_instructions): Add new instructions.
1165 (is_mve_encoding_conflict): Handle new instructions.
1166 (is_mve_unpredictable): Likewise.
1167 (print_mve_size): Likewise.
1168 (print_insn_mve): Likewise.
1169
d3b63143
AV		 11702019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1171 Michael Collison <michael.collison@arm.com>
1172
1173 * arm-dis.c (enum mve_instructions): Add new instructions.
1174 (enum mve_undefined): Add new reasons.
1175 (is_mve_encoding_conflict): Handle new instructions.
1176 (is_mve_undefined): Likewise.
1177 (is_mve_unpredictable): Likewise.
1178 (print_mve_undefined): Likewise.
1179 (print_mve_size): Likewise.
1180 (print_insn_mve): Likewise.
1181
14925797
AV		 11822019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1183 Michael Collison <michael.collison@arm.com>
1184
1185 * arm-dis.c (enum mve_instructions): Add new instructions.
1186 (is_mve_encoding_conflict): Handle new instructions.
1187 (is_mve_undefined): Likewise.
1188 (is_mve_unpredictable): Likewise.
1189 (print_mve_size): Likewise.
1190 (print_insn_mve): Likewise.
1191
c507f10b
AV		 11922019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1193 Michael Collison <michael.collison@arm.com>
1194
1195 * arm-dis.c (enum mve_instructions): Add new instructions.
1196 (enum mve_unpredictable): Add new reasons.
1197 (enum mve_undefined): Likewise.
1198 (is_mve_okay_in_it): Handle new isntructions.
1199 (is_mve_encoding_conflict): Likewise.
1200 (is_mve_undefined): Likewise.
1201 (is_mve_unpredictable): Likewise.
1202 (print_mve_vmov_index): Likewise.
1203 (print_simd_imm8): Likewise.
1204 (print_mve_undefined): Likewise.
1205 (print_mve_unpredictable): Likewise.
1206 (print_mve_size): Likewise.
1207 (print_insn_mve): Likewise.
1208
bf0b396d
AV		 12092019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1210 Michael Collison <michael.collison@arm.com>
1211
1212 * arm-dis.c (enum mve_instructions): Add new instructions.
1213 (enum mve_unpredictable): Add new reasons.
1214 (enum mve_undefined): Likewise.
1215 (is_mve_encoding_conflict): Handle new instructions.
1216 (is_mve_undefined): Likewise.
1217 (is_mve_unpredictable): Likewise.
1218 (print_mve_undefined): Likewise.
1219 (print_mve_unpredictable): Likewise.
1220 (print_mve_rounding_mode): Likewise.
1221 (print_mve_vcvt_size): Likewise.
1222 (print_mve_size): Likewise.
1223 (print_insn_mve): Likewise.
1224
ef1576a1
AV		 12252019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1226 Michael Collison <michael.collison@arm.com>
1227
1228 * arm-dis.c (enum mve_instructions): Add new instructions.
1229 (enum mve_unpredictable): Add new reasons.
1230 (enum mve_undefined): Likewise.
1231 (is_mve_undefined): Handle new instructions.
1232 (is_mve_unpredictable): Likewise.
1233 (print_mve_undefined): Likewise.
1234 (print_mve_unpredictable): Likewise.
1235 (print_mve_size): Likewise.
1236 (print_insn_mve): Likewise.
1237
aef6d006
AV		 12382019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1239 Michael Collison <michael.collison@arm.com>
1240
1241 * arm-dis.c (enum mve_instructions): Add new instructions.
1242 (enum mve_undefined): Add new reasons.
1243 (insns): Add new instructions.
1244 (is_mve_encoding_conflict):
1245 (print_mve_vld_str_addr): New print function.
1246 (is_mve_undefined): Handle new instructions.
1247 (is_mve_unpredictable): Likewise.
1248 (print_mve_undefined): Likewise.
1249 (print_mve_size): Likewise.
1250 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1251 (print_insn_mve): Handle new operands.
1252
04d54ace
AV		 12532019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1254 Michael Collison <michael.collison@arm.com>
1255
1256 * arm-dis.c (enum mve_instructions): Add new instructions.
1257 (enum mve_unpredictable): Add new reasons.
1258 (is_mve_encoding_conflict): Handle new instructions.
1259 (is_mve_unpredictable): Likewise.
1260 (mve_opcodes): Add new instructions.
1261 (print_mve_unpredictable): Handle new reasons.
1262 (print_mve_register_blocks): New print function.
1263 (print_mve_size): Handle new instructions.
1264 (print_insn_mve): Likewise.
1265
9743db03
AV		 12662019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1267 Michael Collison <michael.collison@arm.com>
1268
1269 * arm-dis.c (enum mve_instructions): Add new instructions.
1270 (enum mve_unpredictable): Add new reasons.
1271 (enum mve_undefined): Likewise.
1272 (is_mve_encoding_conflict): Handle new instructions.
1273 (is_mve_undefined): Likewise.
1274 (is_mve_unpredictable): Likewise.
1275 (coprocessor_opcodes): Move NEON VDUP from here...
1276 (neon_opcodes): ... to here.
1277 (mve_opcodes): Add new instructions.
1278 (print_mve_undefined): Handle new reasons.
1279 (print_mve_unpredictable): Likewise.
1280 (print_mve_size): Handle new instructions.
1281 (print_insn_neon): Handle vdup.
1282 (print_insn_mve): Handle new operands.
1283
143275ea
AV		 12842019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1285 Michael Collison <michael.collison@arm.com>
1286
1287 * arm-dis.c (enum mve_instructions): Add new instructions.
1288 (enum mve_unpredictable): Add new values.
1289 (mve_opcodes): Add new instructions.
1290 (vec_condnames): New array with vector conditions.
1291 (mve_predicatenames): New array with predicate suffixes.
1292 (mve_vec_sizename): New array with vector sizes.
1293 (enum vpt_pred_state): New enum with vector predication states.
1294 (struct vpt_block): New struct type for vpt blocks.
1295 (vpt_block_state): Global struct to keep track of state.
1296 (mve_extract_pred_mask): New helper function.
1297 (num_instructions_vpt_block): Likewise.
1298 (mark_outside_vpt_block): Likewise.
1299 (mark_inside_vpt_block): Likewise.
1300 (invert_next_predicate_state): Likewise.
1301 (update_next_predicate_state): Likewise.
1302 (update_vpt_block_state): Likewise.
1303 (is_vpt_instruction): Likewise.
1304 (is_mve_encoding_conflict): Add entries for new instructions.
1305 (is_mve_unpredictable): Likewise.
1306 (print_mve_unpredictable): Handle new cases.
1307 (print_instruction_predicate): Likewise.
1308 (print_mve_size): New function.
1309 (print_vec_condition): New function.
1310 (print_insn_mve): Handle vpt blocks and new print operands.
1311
f08d8ce3
AV		 13122019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1313
1314 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1315 8, 14 and 15 for Armv8.1-M Mainline.
1316
73cd51e5
AV		 13172019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1318 Michael Collison <michael.collison@arm.com>
1319
1320 * arm-dis.c (enum mve_instructions): New enum.
1321 (enum mve_unpredictable): Likewise.
1322 (enum mve_undefined): Likewise.
1323 (struct mopcode32): New struct.
1324 (is_mve_okay_in_it): New function.
1325 (is_mve_architecture): Likewise.
1326 (arm_decode_field): Likewise.
1327 (arm_decode_field_multiple): Likewise.
1328 (is_mve_encoding_conflict): Likewise.
1329 (is_mve_undefined): Likewise.
1330 (is_mve_unpredictable): Likewise.
1331 (print_mve_undefined): Likewise.
1332 (print_mve_unpredictable): Likewise.
1333 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1334 (print_insn_mve): New function.
1335 (print_insn_thumb32): Handle MVE architecture.
1336 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1337
3076e594
NC		 13382019-05-10 Nick Clifton <nickc@redhat.com>
1339
1340 PR 24538
1341 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1342 end of the table prematurely.
1343
387e7624
FS		 13442019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1345
1346 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1347 macros for R6.
1348
0067be51
AM		 13492019-05-11 Alan Modra <amodra@gmail.com>
1350
1351 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1352 when -Mraw is in effect.
1353
42e6288f
MM		 13542019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1355
1356 * aarch64-dis-2.c: Regenerate.
1357 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1358 (OP_SVE_BBB): New variant set.
1359 (OP_SVE_DDDD): New variant set.
1360 (OP_SVE_HHH): New variant set.
1361 (OP_SVE_HHHU): New variant set.
1362 (OP_SVE_SSS): New variant set.
1363 (OP_SVE_SSSU): New variant set.
1364 (OP_SVE_SHH): New variant set.
1365 (OP_SVE_SBBU): New variant set.
1366 (OP_SVE_DSS): New variant set.
1367 (OP_SVE_DHHU): New variant set.
1368 (OP_SVE_VMV_HSD_BHS): New variant set.
1369 (OP_SVE_VVU_HSD_BHS): New variant set.
1370 (OP_SVE_VVVU_SD_BH): New variant set.
1371 (OP_SVE_VVVU_BHSD): New variant set.
1372 (OP_SVE_VVV_QHD_DBS): New variant set.
1373 (OP_SVE_VVV_HSD_BHS): New variant set.
1374 (OP_SVE_VVV_HSD_BHS2): New variant set.
1375 (OP_SVE_VVV_BHS_HSD): New variant set.
1376 (OP_SVE_VV_BHS_HSD): New variant set.
1377 (OP_SVE_VVV_SD): New variant set.
1378 (OP_SVE_VVU_BHS_HSD): New variant set.
1379 (OP_SVE_VZVV_SD): New variant set.
1380 (OP_SVE_VZVV_BH): New variant set.
1381 (OP_SVE_VZV_SD): New variant set.
1382 (aarch64_opcode_table): Add sve2 instructions.
1383
28ed815a
MM		 13842019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1385
1386 * aarch64-asm-2.c: Regenerated.
1387 * aarch64-dis-2.c: Regenerated.
1388 * aarch64-opc-2.c: Regenerated.
1389 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1390 for SVE_SHLIMM_UNPRED_22.
1391 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1392 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1393 operand.
1394
fd1dc4a0
MM		 13952019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1396
1397 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1398 sve_size_tsz_bhs iclass encode.
1399 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1400 sve_size_tsz_bhs iclass decode.
1401
31e36ab3
MM		 14022019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1403
1404 * aarch64-asm-2.c: Regenerated.
1405 * aarch64-dis-2.c: Regenerated.
1406 * aarch64-opc-2.c: Regenerated.
1407 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1408 for SVE_Zm4_11_INDEX.
1409 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1410 (fields): Handle SVE_i2h field.
1411 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1412 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1413
1be5f94f
MM		 14142019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1415
1416 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1417 sve_shift_tsz_bhsd iclass encode.
1418 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1419 sve_shift_tsz_bhsd iclass decode.
1420
3c17238b
MM		 14212019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1422
1423 * aarch64-asm-2.c: Regenerated.
1424 * aarch64-dis-2.c: Regenerated.
1425 * aarch64-opc-2.c: Regenerated.
1426 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1427 (aarch64_encode_variant_using_iclass): Handle
1428 sve_shift_tsz_hsd iclass encode.
1429 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1430 sve_shift_tsz_hsd iclass decode.
1431 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1432 for SVE_SHRIMM_UNPRED_22.
1433 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1434 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1435 operand.
1436
cd50a87a
MM		 14372019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1438
1439 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1440 sve_size_013 iclass encode.
1441 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1442 sve_size_013 iclass decode.
1443
3c705960
MM		 14442019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1445
1446 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1447 sve_size_bh iclass encode.
1448 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1449 sve_size_bh iclass decode.
1450
0a57e14f
MM		 14512019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1452
1453 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1454 sve_size_sd2 iclass encode.
1455 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1456 sve_size_sd2 iclass decode.
1457 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1458 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1459
c469c864
MM		 14602019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1461
1462 * aarch64-asm-2.c: Regenerated.
1463 * aarch64-dis-2.c: Regenerated.
1464 * aarch64-opc-2.c: Regenerated.
1465 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1466 for SVE_ADDR_ZX.
1467 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1468 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1469
116adc27
MM		 14702019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1471
1472 * aarch64-asm-2.c: Regenerated.
1473 * aarch64-dis-2.c: Regenerated.
1474 * aarch64-opc-2.c: Regenerated.
1475 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1476 for SVE_Zm3_11_INDEX.
1477 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1478 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1479 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1480 fields.
1481 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1482
3bd82c86
MM		 14832019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1484
1485 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1486 sve_size_hsd2 iclass encode.
1487 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1488 sve_size_hsd2 iclass decode.
1489 * aarch64-opc.c (fields): Handle SVE_size field.
1490 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1491
adccc507
MM		 14922019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1493
1494 * aarch64-asm-2.c: Regenerated.
1495 * aarch64-dis-2.c: Regenerated.
1496 * aarch64-opc-2.c: Regenerated.
1497 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1498 for SVE_IMM_ROT3.
1499 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1500 (fields): Handle SVE_rot3 field.
1501 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1502 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1503
5cd99750
MM		 15042019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1505
1506 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1507 instructions.
1508
7ce2460a
MM		 15092019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1510
1511 * aarch64-tbl.h
1512 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1513 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1514 aarch64_feature_sve2bitperm): New feature sets.
1515 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1516 for feature set addresses.
1517 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1518 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1519
41cee089
FS		 15202019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1521 Faraz Shahbazker <fshahbazker@wavecomp.com>
1522
1523 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1524 argument and set ASE_EVA_R6 appropriately.
1525 (set_default_mips_dis_options): Pass ISA to above.
1526 (parse_mips_dis_option): Likewise.
1527 * mips-opc.c (EVAR6): New macro.
1528 (mips_builtin_opcodes): Add llwpe, scwpe.
1529
b83b4b13
SD		 15302019-05-01 Sudakshina Das <sudi.das@arm.com>
1531
1532 * aarch64-asm-2.c: Regenerated.
1533 * aarch64-dis-2.c: Regenerated.
1534 * aarch64-opc-2.c: Regenerated.
1535 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1536 AARCH64_OPND_TME_UIMM16.
1537 (aarch64_print_operand): Likewise.
1538 * aarch64-tbl.h (QL_IMM_NIL): New.
1539 (TME): New.
1540 (_TME_INSN): New.
1541 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1542
4a90ce95
JD		 15432019-04-29 John Darrington <john@darrington.wattle.id.au>
1544
1545 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1546
a45328b9
AB		 15472019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1548 Faraz Shahbazker <fshahbazker@wavecomp.com>
1549
1550 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1551
d10be0cb
JD		 15522019-04-24 John Darrington <john@darrington.wattle.id.au>
1553
1554 * s12z-opc.h: Add extern "C" bracketing to help
1555 users who wish to use this interface in c++ code.
1556
a679f24e
JD		 15572019-04-24 John Darrington <john@darrington.wattle.id.au>
1558
1559 * s12z-opc.c (bm_decode): Handle bit map operations with the
1560 "reserved0" mode.
1561
32c36c3c
AV		 15622019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1563
1564 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1565 specifier. Add entries for VLDR and VSTR of system registers.
1566 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1567 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1568 of %J and %K format specifier.
1569
efd6b359
AV		 15702019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1571
1572 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1573 Add new entries for VSCCLRM instruction.
1574 (print_insn_coprocessor): Handle new %C format control code.
1575
6b0dd094
AV		 15762019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1577
1578 * arm-dis.c (enum isa): New enum.
1579 (struct sopcode32): New structure.
1580 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1581 set isa field of all current entries to ANY.
1582 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1583 Only match an entry if its isa field allows the current mode.
1584
4b5a202f
AV		 15852019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1586
1587 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1588 CLRM.
1589 (print_insn_thumb32): Add logic to print %n CLRM register list.
1590
60f993ce
AV		 15912019-04-15 Sudakshina Das <sudi.das@arm.com>
1592
1593 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1594 and %Q patterns.
1595
f6b2b12d
AV		 15962019-04-15 Sudakshina Das <sudi.das@arm.com>
1597
1598 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1599 (print_insn_thumb32): Edit the switch case for %Z.
1600
1889da70
AV		 16012019-04-15 Sudakshina Das <sudi.das@arm.com>
1602
1603 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1604
65d1bc05
AV		 16052019-04-15 Sudakshina Das <sudi.das@arm.com>
1606
1607 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1608
1caf72a5
AV		 16092019-04-15 Sudakshina Das <sudi.das@arm.com>
1610
1611 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1612
f1c7f421
AV		 16132019-04-15 Sudakshina Das <sudi.das@arm.com>
1614
1615 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1616 Arm register with r13 and r15 unpredictable.
1617 (thumb32_opcodes): New instructions for bfx and bflx.
1618
4389b29a
AV		 16192019-04-15 Sudakshina Das <sudi.das@arm.com>
1620
1621 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1622
e5d6e09e
AV		 16232019-04-15 Sudakshina Das <sudi.das@arm.com>
1624
1625 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1626
e12437dc
AV		 16272019-04-15 Sudakshina Das <sudi.das@arm.com>
1628
1629 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1630
031254f2
AV		 16312019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1632
1633 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1634
e5a557ac
JD		 16352019-04-12 John Darrington <john@darrington.wattle.id.au>
1636
1637 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1638 "optr". ("operator" is a reserved word in c++).
1639
bd7ceb8d
SD		 16402019-04-11 Sudakshina Das <sudi.das@arm.com>
1641
1642 * aarch64-opc.c (aarch64_print_operand): Add case for
1643 AARCH64_OPND_Rt_SP.
1644 (verify_constraints): Likewise.
1645 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1646 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1647 to accept Rt|SP as first operand.
1648 (AARCH64_OPERANDS): Add new Rt_SP.
1649 * aarch64-asm-2.c: Regenerated.
1650 * aarch64-dis-2.c: Regenerated.
1651 * aarch64-opc-2.c: Regenerated.
1652
e54010f1
SD		 16532019-04-11 Sudakshina Das <sudi.das@arm.com>
1654
1655 * aarch64-asm-2.c: Regenerated.
1656 * aarch64-dis-2.c: Likewise.
1657 * aarch64-opc-2.c: Likewise.
1658 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1659
7e96e219
RS		 16602019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1661
1662 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1663
6f2791d5
L		 16642019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1665
1666 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1667 * i386-init.h: Regenerated.
1668
e392bad3
AM		 16692019-04-07 Alan Modra <amodra@gmail.com>
1670
1671 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1672 op_separator to control printing of spaces, comma and parens
1673 rather than need_comma, need_paren and spaces vars.
1674
dffaa15c
AM		 16752019-04-07 Alan Modra <amodra@gmail.com>
1676
1677 PR 24421
1678 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1679 (print_insn_neon, print_insn_arm): Likewise.
1680
d6aab7a1
XG		 16812019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1682
1683 * i386-dis-evex.h (evex_table): Updated to support BF16
1684 instructions.
1685 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1686 and EVEX_W_0F3872_P_3.
1687 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1688 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1689 * i386-opc.h (enum): Add CpuAVX512_BF16.
1690 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1691 * i386-opc.tbl: Add AVX512 BF16 instructions.
1692 * i386-init.h: Regenerated.
1693 * i386-tbl.h: Likewise.
1694
66e85460
AM		 16952019-04-05 Alan Modra <amodra@gmail.com>
1696
1697 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1698 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1699 to favour printing of "-" branch hint when using the "y" bit.
1700 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1701
c2b1c275
AM		 17022019-04-05 Alan Modra <amodra@gmail.com>
1703
1704 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1705 opcode until first operand is output.
1706
aae9718e
PB		 17072019-04-04 Peter Bergner <bergner@linux.ibm.com>
1708
1709 PR gas/24349
1710 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1711 (valid_bo_post_v2): Add support for 'at' branch hints.
1712 (insert_bo): Only error on branch on ctr.
1713 (get_bo_hint_mask): New function.
1714 (insert_boe): Add new 'branch_taken' formal argument. Add support
1715 for inserting 'at' branch hints.
1716 (extract_boe): Add new 'branch_taken' formal argument. Add support
1717 for extracting 'at' branch hints.
1718 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1719 (BOE): Delete operand.
1720 (BOM, BOP): New operands.
1721 (RM): Update value.
1722 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1723 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1724 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1725 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1726 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1727 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1728 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1729 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1730 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1731 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1732 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1733 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1734 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1735 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1736 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1737 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1738 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1739 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1740 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1741 bttarl+>: New extended mnemonics.
1742
96a86c01
AM		 17432019-03-28 Alan Modra <amodra@gmail.com>
1744
1745 PR 24390
1746 * ppc-opc.c (BTF): Define.
1747 (powerpc_opcodes): Use for mtfsb*.
1748 * ppc-dis.c (print_insn_powerpc): Print fields with both
1749 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1750
796d6298
TC		 17512019-03-25 Tamar Christina <tamar.christina@arm.com>
1752
1753 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1754 (mapping_symbol_for_insn): Implement new algorithm.
1755 (print_insn): Remove duplicate code.
1756
60df3720
TC		 17572019-03-25 Tamar Christina <tamar.christina@arm.com>
1758
1759 * aarch64-dis.c (print_insn_aarch64):
1760 Implement override.
1761
51457761
TC		 17622019-03-25 Tamar Christina <tamar.christina@arm.com>
1763
1764 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1765 order.
1766
53b2f36b
TC		 17672019-03-25 Tamar Christina <tamar.christina@arm.com>
1768
1769 * aarch64-dis.c (last_stop_offset): New.
1770 (print_insn_aarch64): Use stop_offset.
1771
89199bb5
L		 17722019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1773
1774 PR gas/24359
1775 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1776 CPU_ANY_AVX2_FLAGS.
1777 * i386-init.h: Regenerated.
1778
97ed31ae
L		 17792019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1780
1781 PR gas/24348
1782 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1783 vmovdqu16, vmovdqu32 and vmovdqu64.
1784 * i386-tbl.h: Regenerated.
1785
0919bfe9
AK		 17862019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1787
1788 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1789 from vstrszb, vstrszh, and vstrszf.
1790
17912019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1792
1793 * s390-opc.txt: Add instruction descriptions.
1794
21820ebe
JW		 17952019-02-08 Jim Wilson <jimw@sifive.com>
1796
1797 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1798 <bne>: Likewise.
1799
f7dd2fb2
TC		 18002019-02-07 Tamar Christina <tamar.christina@arm.com>
1801
1802 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1803
6456d318
TC		 18042019-02-07 Tamar Christina <tamar.christina@arm.com>
1805
1806 PR binutils/23212
1807 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1808 * aarch64-opc.c (verify_elem_sd): New.
1809 (fields): Add FLD_sz entr.
1810 * aarch64-tbl.h (_SIMD_INSN): New.
1811 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1812 fmulx scalar and vector by element isns.
1813
4a83b610
NC		 18142019-02-07 Nick Clifton <nickc@redhat.com>
1815
1816 * po/sv.po: Updated Swedish translation.
1817
fc60b8c8
AK		 18182019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1819
1820 * s390-mkopc.c (main): Accept arch13 as cpu string.
1821 * s390-opc.c: Add new instruction formats and instruction opcode
1822 masks.
1823 * s390-opc.txt: Add new arch13 instructions.
1824
e10620d3
TC		 18252019-01-25 Sudakshina Das <sudi.das@arm.com>
1826
1827 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1828 (aarch64_opcode): Change encoding for stg, stzg
1829 st2g and st2zg.
1830 * aarch64-asm-2.c: Regenerated.
1831 * aarch64-dis-2.c: Regenerated.
1832 * aarch64-opc-2.c: Regenerated.
1833
20a4ca55
SD		 18342019-01-25 Sudakshina Das <sudi.das@arm.com>
1835
1836 * aarch64-asm-2.c: Regenerated.
1837 * aarch64-dis-2.c: Likewise.
1838 * aarch64-opc-2.c: Likewise.
1839 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1840
550fd7bf
SD		 18412019-01-25 Sudakshina Das <sudi.das@arm.com>
1842 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1843
1844 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1845 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1846 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1847 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1848 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1849 case for ldstgv_indexed.
1850 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1851 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1852 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1853 * aarch64-asm-2.c: Regenerated.
1854 * aarch64-dis-2.c: Regenerated.
1855 * aarch64-opc-2.c: Regenerated.
1856
d9938630
NC		 18572019-01-23 Nick Clifton <nickc@redhat.com>
1858
1859 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1860
375cd423
NC		 18612019-01-21 Nick Clifton <nickc@redhat.com>
1862
1863 * po/de.po: Updated German translation.
1864 * po/uk.po: Updated Ukranian translation.
1865
57299f48
CX		 18662019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1867 * mips-dis.c (mips_arch_choices): Fix typo in
1868 gs464, gs464e and gs264e descriptors.
1869
f48dfe41
NC		 18702019-01-19 Nick Clifton <nickc@redhat.com>
1871
1872 * configure: Regenerate.
1873 * po/opcodes.pot: Regenerate.
1874
f974f26c
NC		 18752018-06-24 Nick Clifton <nickc@redhat.com>
1876
1877 2.32 branch created.
1878
39f286cd
JD		 18792019-01-09 John Darrington <john@darrington.wattle.id.au>
1880
448b8ca8
JD		 1881 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1882 if it is null.
1883 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 1884 zero.
1885
3107326d
AP		 18862019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1887
1888 * configure: Regenerate.
1889
7e9ca91e
AM		 18902019-01-07 Alan Modra <amodra@gmail.com>
1891
1892 * configure: Regenerate.
1893 * po/POTFILES.in: Regenerate.
1894
ef1ad42b
JD		 18952019-01-03 John Darrington <john@darrington.wattle.id.au>
1896
1897 * s12z-opc.c: New file.
1898 * s12z-opc.h: New file.
1899 * s12z-dis.c: Removed all code not directly related to display
1900 of instructions. Used the interface provided by the new files
1901 instead.
1902 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 1903 * Makefile.in: Regenerate.
ef1ad42b 1904 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 1905 * configure: Regenerate.
ef1ad42b 1906
82704155
AM		 19072019-01-01 Alan Modra <amodra@gmail.com>
1908
1909 Update year range in copyright notice of all files.
1910
d5c04e1b 1911For older changes see ChangeLog-2018
3499769a 1912\f
d5c04e1b 1913Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 1914
1915Copying and distribution of this file, with or without modification,
1916are permitted in any medium without royalty provided the copyright
1917notice and this notice are preserved.
1918
1919Local Variables:
1920mode: change-log
1921left-margin: 8
1922fill-column: 74
1923version-control: never
1924End:
GDB Binutils - Deliverables
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