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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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9bdfdbf9
AW		 12017-06-23 Andrew Waterman <andrew@sifive.com>
2
3 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
4 alias; do not mark SLTI instruction as an alias.
5
2234eee6
L		 62017-06-21 H.J. Lu <hongjiu.lu@intel.com>
7
8 * i386-dis.c (RM_0FAE_REG_5): Removed.
9 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
10 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
11 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
12 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
13 PREFIX_MOD_3_0F01_REG_5_RM_0.
14 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
15 PREFIX_MOD_3_0FAE_REG_5.
16 (mod_table): Update MOD_0FAE_REG_5.
17 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
18 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
19 * i386-tbl.h: Regenerated.
20
c2f76402
L		 212017-06-21 H.J. Lu <hongjiu.lu@intel.com>
22
23 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
24 * i386-opc.tbl: Likewise.
25 * i386-tbl.h: Regenerated.
26
9fef80d6
L		 272017-06-21 H.J. Lu <hongjiu.lu@intel.com>
28
29 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
30 and "jmp{&|}".
31 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
32 prefix.
33
0f6d864d
NC		 342017-06-19 Nick Clifton <nickc@redhat.com>
35
36 PR binutils/21614
37 * score-dis.c (score_opcodes): Add sentinel.
38
e197589b
AM		 392017-06-16 Alan Modra <amodra@gmail.com>
40
41 * rx-decode.c: Regenerate.
42
0d96e4df
L		 432017-06-15 H.J. Lu <hongjiu.lu@intel.com>
44
45 PR binutils/21594
46 * i386-dis.c (OP_E_register): Check valid bnd register.
47 (OP_G): Likewise.
48
cd3ea7c6
NC		 492017-06-15 Nick Clifton <nickc@redhat.com>
50
51 PR binutils/21595
52 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
53 range value.
54
63323b5b
NC		 552017-06-15 Nick Clifton <nickc@redhat.com>
56
57 PR binutils/21588
58 * rl78-decode.opc (OP_BUF_LEN): Define.
59 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
60 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
61 array.
62 * rl78-decode.c: Regenerate.
63
08c7881b
NC		 642017-06-15 Nick Clifton <nickc@redhat.com>
65
66 PR binutils/21586
67 * bfin-dis.c (gregs): Clip index to prevent overflow.
68 (regs): Likewise.
69 (regs_lo): Likewise.
70 (regs_hi): Likewise.
71
e64519d1
NC		 722017-06-14 Nick Clifton <nickc@redhat.com>
73
74 PR binutils/21576
75 * score7-dis.c (score_opcodes): Add sentinel.
76
6394c606
YQ		 772017-06-14 Yao Qi <yao.qi@linaro.org>
78
79 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
80 * arm-dis.c: Likewise.
81 * ia64-dis.c: Likewise.
82 * mips-dis.c: Likewise.
83 * spu-dis.c: Likewise.
84 * disassemble.h (print_insn_aarch64): New declaration, moved from
85 include/dis-asm.h.
86 (print_insn_big_arm, print_insn_big_mips): Likewise.
87 (print_insn_i386, print_insn_ia64): Likewise.
88 (print_insn_little_arm, print_insn_little_mips): Likewise.
89
db5fa770
NC		 902017-06-14 Nick Clifton <nickc@redhat.com>
91
92 PR binutils/21587
93 * rx-decode.opc: Include libiberty.h
94 (GET_SCALE): New macro - validates access to SCALE array.
95 (GET_PSCALE): New macro - validates access to PSCALE array.
96 (DIs, SIs, S2Is, rx_disp): Use new macros.
97 * rx-decode.c: Regenerate.
98
05c966f3
AV		 992017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
100
101 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
102
10045478
AK		 1032017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
104
105 * arc-dis.c (enforced_isa_mask): Declare.
106 (cpu_types): Likewise.
107 (parse_cpu_option): New function.
108 (parse_disassembler_options): Use it.
109 (print_insn_arc): Use enforced_isa_mask.
110 (print_arc_disassembler_options): Document new options.
111
88c1242d
YQ		 1122017-05-24 Yao Qi <yao.qi@linaro.org>
113
114 * alpha-dis.c: Include disassemble.h, don't include
115 dis-asm.h.
116 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
117 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
118 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
119 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
120 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
121 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
122 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
123 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
124 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
125 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
126 * moxie-dis.c, msp430-dis.c, mt-dis.c:
127 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
128 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
129 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
130 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
131 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
132 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
133 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
134 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
135 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
136 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
137 * z80-dis.c, z8k-dis.c: Likewise.
138 * disassemble.h: New file.
139
ab20fa4a
YQ		 1402017-05-24 Yao Qi <yao.qi@linaro.org>
141
142 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
143 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
144
003ca0fd
YQ		 1452017-05-24 Yao Qi <yao.qi@linaro.org>
146
147 * disassemble.c (disassembler): Add arguments a, big and mach.
148 Use them.
149
04ef582a
L		 1502017-05-22 H.J. Lu <hongjiu.lu@intel.com>
151
152 * i386-dis.c (NOTRACK_Fixup): New.
153 (NOTRACK): Likewise.
154 (NOTRACK_PREFIX): Likewise.
155 (last_active_prefix): Likewise.
156 (reg_table): Use NOTRACK on indirect call and jmp.
157 (ckprefix): Set last_active_prefix.
158 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
159 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
160 * i386-opc.h (NoTrackPrefixOk): New.
161 (i386_opcode_modifier): Add notrackprefixok.
162 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
163 Add notrack.
164 * i386-tbl.h: Regenerated.
165
64517994
JM		 1662017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
167
168 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
169 (X_IMM2): Define.
170 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
171 bfd_mach_sparc_v9m8.
172 (print_insn_sparc): Handle new operand types.
173 * sparc-opc.c (MASK_M8): Define.
174 (v6): Add MASK_M8.
175 (v6notlet): Likewise.
176 (v7): Likewise.
177 (v8): Likewise.
178 (v9): Likewise.
179 (v9a): Likewise.
180 (v9b): Likewise.
181 (v9c): Likewise.
182 (v9d): Likewise.
183 (v9e): Likewise.
184 (v9v): Likewise.
185 (v9m): Likewise.
186 (v9andleon): Likewise.
187 (m8): Define.
188 (HWS_VM8): Define.
189 (HWS2_VM8): Likewise.
190 (sparc_opcode_archs): Add entry for "m8".
191 (sparc_opcodes): Add OSA2017 and M8 instructions
192 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
193 fpx{ll,ra,rl}64x,
194 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
195 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
196 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
197 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
198 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
199 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
200 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
201 ASI_CORE_SELECT_COMMIT_NHT.
202
535b785f
AM		 2032017-05-18 Alan Modra <amodra@gmail.com>
204
205 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
206 * aarch64-dis.c: Likewise.
207 * aarch64-gen.c: Likewise.
208 * aarch64-opc.c: Likewise.
209
25499ac7
MR		 2102017-05-15 Maciej W. Rozycki <macro@imgtec.com>
211 Matthew Fortune <matthew.fortune@imgtec.com>
212
213 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
214 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
215 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
216 (print_insn_arg) <OP_REG28>: Add handler.
217 (validate_insn_args) <OP_REG28>: Handle.
218 (print_mips16_insn_arg): Handle MIPS16 instructions that require
219 32-bit encoding and 9-bit immediates.
220 (print_insn_mips16): Handle MIPS16 instructions that require
221 32-bit encoding and MFC0/MTC0 operand decoding.
222 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
223 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
224 (RD_C0, WR_C0, E2, E2MT): New macros.
225 (mips16_opcodes): Add entries for MIPS16e2 instructions:
226 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
227 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
228 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
229 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
230 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
231 instructions, "swl", "swr", "sync" and its "sync_acquire",
232 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
233 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
234 regular/extended entries for original MIPS16 ISA revision
235 instructions whose extended forms are subdecoded in the MIPS16e2
236 ISA revision: "li", "sll" and "srl".
237
fdfb4752
MR		 2382017-05-15 Maciej W. Rozycki <macro@imgtec.com>
239
240 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
241 reference in CP0 move operand decoding.
242
a4f89915
MR		 2432017-05-12 Maciej W. Rozycki <macro@imgtec.com>
244
245 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
246 type to hexadecimal.
247 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
248
99e2d67a
MR		 2492017-05-11 Maciej W. Rozycki <macro@imgtec.com>
250
251 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
252 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
253 "sync_rmb" and "sync_wmb" as aliases.
254 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
255 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
256
53a346d8
CZ		 2572017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
258
259 * arc-dis.c (parse_option): Update quarkse_em option..
260 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
261 QUARKSE1.
262 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
263
f91d48de
KC		 2642017-05-03 Kito Cheng <kito.cheng@gmail.com>
265
266 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
267
43e379d7
MC		 2682017-05-01 Michael Clark <michaeljclark@mac.com>
269
270 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
271 register.
272
a4ddc54e
MR		 2732017-05-02 Maciej W. Rozycki <macro@imgtec.com>
274
275 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
276 and branches and not synthetic data instructions.
277
fe50e98c
BE		 2782017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
279
280 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
281
126124cc
CZ		 2822017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
283
284 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
285 * arc-opc.c (insert_r13el): New function.
286 (R13_EL): Define.
287 * arc-tbl.h: Add new enter/leave variants.
288
be6a24d8
CZ		 2892017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
290
291 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
292
0348fd79
MR		 2932017-04-25 Maciej W. Rozycki <macro@imgtec.com>
294
295 * mips-dis.c (print_mips_disassembler_options): Add
296 `no-aliases'.
297
6e3d1f07
MR		 2982017-04-25 Maciej W. Rozycki <macro@imgtec.com>
299
300 * mips16-opc.c (AL): New macro.
301 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
302 of "ld" and "lw" as aliases.
303
957f6b39
TC		 3042017-04-24 Tamar Christina <tamar.christina@arm.com>
305
306 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
307 arguments.
308
a8cc8a54
AM		 3092017-04-22 Alexander Fedotov <alfedotov@gmail.com>
310 Alan Modra <amodra@gmail.com>
311
312 * ppc-opc.c (ELEV): Define.
313 (vle_opcodes): Add se_rfgi and e_sc.
314 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
315 for E200Z4.
316
3ab87b68
JM		 3172017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
318
319 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
320
792f174f
NC		 3212017-04-21 Nick Clifton <nickc@redhat.com>
322
323 PR binutils/21380
324 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
325 LD3R and LD4R.
326
42742084
AM		 3272017-04-13 Alan Modra <amodra@gmail.com>
328
329 * epiphany-desc.c: Regenerate.
330 * fr30-desc.c: Regenerate.
331 * frv-desc.c: Regenerate.
332 * ip2k-desc.c: Regenerate.
333 * iq2000-desc.c: Regenerate.
334 * lm32-desc.c: Regenerate.
335 * m32c-desc.c: Regenerate.
336 * m32r-desc.c: Regenerate.
337 * mep-desc.c: Regenerate.
338 * mt-desc.c: Regenerate.
339 * or1k-desc.c: Regenerate.
340 * xc16x-desc.c: Regenerate.
341 * xstormy16-desc.c: Regenerate.
342
9a85b496
AM		 3432017-04-11 Alan Modra <amodra@gmail.com>
344
ef85eab0 345 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 346 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
347 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 348 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
349 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 350 (PPCVSX2): Define as PPC_OPCODE_POWER8.
351 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 352 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 353 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 354
62adc510
AM		 3552017-04-10 Alan Modra <amodra@gmail.com>
356
357 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
358 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
359 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
360 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
361
aa808707
PC		 3622017-04-09 Pip Cet <pipcet@gmail.com>
363
364 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
365 appropriate floating-point precision directly.
366
ac8f0f72
AM		 3672017-04-07 Alan Modra <amodra@gmail.com>
368
369 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
370 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
371 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
372 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
373 vector instructions with E6500 not PPCVEC2.
374
62ecb94c
PC		 3752017-04-06 Pip Cet <pipcet@gmail.com>
376
377 * Makefile.am: Add wasm32-dis.c.
378 * configure.ac: Add wasm32-dis.c to wasm32 target.
379 * disassemble.c: Add wasm32 disassembler code.
380 * wasm32-dis.c: New file.
381 * Makefile.in: Regenerate.
382 * configure: Regenerate.
383 * po/POTFILES.in: Regenerate.
384 * po/opcodes.pot: Regenerate.
385
f995bbe8
PA		 3862017-04-05 Pedro Alves <palves@redhat.com>
387
388 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
389 * arm-dis.c (parse_arm_disassembler_options): Constify.
390 * ppc-dis.c (powerpc_init_dialect): Constify local.
391 * vax-dis.c (parse_disassembler_options): Constify.
392
b5292032
PD		 3932017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
394
395 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
396 RISCV_GP_SYMBOL.
397
f96bd6c2
PC		 3982017-03-30 Pip Cet <pipcet@gmail.com>
399
400 * configure.ac: Add (empty) bfd_wasm32_arch target.
401 * configure: Regenerate
402 * po/opcodes.pot: Regenerate.
403
f7c514a3
JM		 4042017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
405
406 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
407 OSA2015.
408 * opcodes/sparc-opc.c (asi_table): New ASIs.
409
52be03fd
AM		 4102017-03-29 Alan Modra <amodra@gmail.com>
411
412 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
413 "raw" option.
414 (lookup_powerpc): Don't special case -1 dialect. Handle
415 PPC_OPCODE_RAW.
416 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
417 lookup_powerpc call, pass it on second.
418
9b753937
AM		 4192017-03-27 Alan Modra <amodra@gmail.com>
420
421 PR 21303
422 * ppc-dis.c (struct ppc_mopt): Comment.
423 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
424
c0c31e91
RZ		 4252017-03-27 Rinat Zelig <rinat@mellanox.com>
426
427 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
428 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
429 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
430 (insert_nps_misc_imm_offset): New function.
431 (extract_nps_misc imm_offset): New function.
432 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
433 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
434
2253c8f0
AK		 4352017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
436
437 * s390-mkopc.c (main): Remove vx2 check.
438 * s390-opc.txt: Remove vx2 instruction flags.
439
645d3342
RZ		 4402017-03-21 Rinat Zelig <rinat@mellanox.com>
441
442 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
443 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
444 (insert_nps_imm_offset): New function.
445 (extract_nps_imm_offset): New function.
446 (insert_nps_imm_entry): New function.
447 (extract_nps_imm_entry): New function.
448
4b94dd2d
AM		 4492017-03-17 Alan Modra <amodra@gmail.com>
450
451 PR 21248
452 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
453 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
454 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
455
b416fe87
KC		 4562017-03-14 Kito Cheng <kito.cheng@gmail.com>
457
458 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
459 <c.andi>: Likewise.
460 <c.addiw> Likewise.
461
03b039a5
KC		 4622017-03-14 Kito Cheng <kito.cheng@gmail.com>
463
464 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
465
2c232b83
AW		 4662017-03-13 Andrew Waterman <andrew@sifive.com>
467
468 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
469 <srl> Likewise.
470 <srai> Likewise.
471 <sra> Likewise.
472
86fa6981
L		 4732017-03-09 H.J. Lu <hongjiu.lu@intel.com>
474
475 * i386-gen.c (opcode_modifiers): Replace S with Load.
476 * i386-opc.h (S): Removed.
477 (Load): New.
478 (i386_opcode_modifier): Replace s with load.
479 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
480 and {evex}. Replace S with Load.
481 * i386-tbl.h: Regenerated.
482
c1fe188b
L		 4832017-03-09 H.J. Lu <hongjiu.lu@intel.com>
484
485 * i386-opc.tbl: Use CpuCET on rdsspq.
486 * i386-tbl.h: Regenerated.
487
4b8b687e
PB		 4882017-03-08 Peter Bergner <bergner@vnet.ibm.com>
489
490 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
491 <vsx>: Do not use PPC_OPCODE_VSX3;
492
1437d063
PB		 4932017-03-08 Peter Bergner <bergner@vnet.ibm.com>
494
495 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
496
603555e5
L		 4972017-03-06 H.J. Lu <hongjiu.lu@intel.com>
498
499 * i386-dis.c (REG_0F1E_MOD_3): New enum.
500 (MOD_0F1E_PREFIX_1): Likewise.
501 (MOD_0F38F5_PREFIX_2): Likewise.
502 (MOD_0F38F6_PREFIX_0): Likewise.
503 (RM_0F1E_MOD_3_REG_7): Likewise.
504 (PREFIX_MOD_0_0F01_REG_5): Likewise.
505 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
506 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
507 (PREFIX_0F1E): Likewise.
508 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
509 (PREFIX_0F38F5): Likewise.
510 (dis386_twobyte): Use PREFIX_0F1E.
511 (reg_table): Add REG_0F1E_MOD_3.
512 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
513 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
514 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
515 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
516 (three_byte_table): Use PREFIX_0F38F5.
517 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
518 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
519 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
520 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
521 PREFIX_MOD_3_0F01_REG_5_RM_2.
522 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
523 (cpu_flags): Add CpuCET.
524 * i386-opc.h (CpuCET): New enum.
525 (CpuUnused): Commented out.
526 (i386_cpu_flags): Add cpucet.
527 * i386-opc.tbl: Add Intel CET instructions.
528 * i386-init.h: Regenerated.
529 * i386-tbl.h: Likewise.
530
73f07bff
AM		 5312017-03-06 Alan Modra <amodra@gmail.com>
532
533 PR 21124
534 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
535 (extract_raq, extract_ras, extract_rbx): New functions.
536 (powerpc_operands): Use opposite corresponding insert function.
537 (Q_MASK): Define.
538 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
539 register restriction.
540
65b48a81
PB		 5412017-02-28 Peter Bergner <bergner@vnet.ibm.com>
542
543 * disassemble.c Include "safe-ctype.h".
544 (disassemble_init_for_target): Handle s390 init.
545 (remove_whitespace_and_extra_commas): New function.
546 (disassembler_options_cmp): Likewise.
547 * arm-dis.c: Include "libiberty.h".
548 (NUM_ELEM): Delete.
549 (regnames): Use long disassembler style names.
550 Add force-thumb and no-force-thumb options.
551 (NUM_ARM_REGNAMES): Rename from this...
552 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
553 (get_arm_regname_num_options): Delete.
554 (set_arm_regname_option): Likewise.
555 (get_arm_regnames): Likewise.
556 (parse_disassembler_options): Likewise.
557 (parse_arm_disassembler_option): Rename from this...
558 (parse_arm_disassembler_options): ...to this. Make static.
559 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
560 (print_insn): Use parse_arm_disassembler_options.
561 (disassembler_options_arm): New function.
562 (print_arm_disassembler_options): Handle updated regnames.
563 * ppc-dis.c: Include "libiberty.h".
564 (ppc_opts): Add "32" and "64" entries.
565 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
566 (powerpc_init_dialect): Add break to switch statement.
567 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
568 (disassembler_options_powerpc): New function.
569 (print_ppc_disassembler_options): Use ARRAY_SIZE.
570 Remove printing of "32" and "64".
571 * s390-dis.c: Include "libiberty.h".
572 (init_flag): Remove unneeded variable.
573 (struct s390_options_t): New structure type.
574 (options): New structure.
575 (init_disasm): Rename from this...
576 (disassemble_init_s390): ...to this. Add initializations for
577 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
578 (print_insn_s390): Delete call to init_disasm.
579 (disassembler_options_s390): New function.
580 (print_s390_disassembler_options): Print using information from
581 struct 'options'.
582 * po/opcodes.pot: Regenerate.
583
15c7c1d8
JB		 5842017-02-28 Jan Beulich <jbeulich@suse.com>
585
586 * i386-dis.c (PCMPESTR_Fixup): New.
587 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
588 (prefix_table): Use PCMPESTR_Fixup.
589 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
590 PCMPESTR_Fixup.
591 (vex_w_table): Delete VPCMPESTR{I,M} entries.
592 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
593 Split 64-bit and non-64-bit variants.
594 * opcodes/i386-tbl.h: Re-generate.
595
582e12bf
RS		 5962017-02-24 Richard Sandiford <richard.sandiford@arm.com>
597
598 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
599 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
600 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
601 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
602 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
603 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
604 (OP_SVE_V_HSD): New macros.
605 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
606 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
607 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
608 (aarch64_opcode_table): Add new SVE instructions.
609 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
610 for rotation operands. Add new SVE operands.
611 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
612 (ins_sve_quad_index): Likewise.
613 (ins_imm_rotate): Split into...
614 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
615 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
616 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
617 functions.
618 (aarch64_ins_sve_addr_ri_s4): New function.
619 (aarch64_ins_sve_quad_index): Likewise.
620 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
621 * aarch64-asm-2.c: Regenerate.
622 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
623 (ext_sve_quad_index): Likewise.
624 (ext_imm_rotate): Split into...
625 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
626 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
627 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
628 functions.
629 (aarch64_ext_sve_addr_ri_s4): New function.
630 (aarch64_ext_sve_quad_index): Likewise.
631 (aarch64_ext_sve_index): Allow quad indices.
632 (do_misc_decoding): Likewise.
633 * aarch64-dis-2.c: Regenerate.
634 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
635 aarch64_field_kinds.
636 (OPD_F_OD_MASK): Widen by one bit.
637 (OPD_F_NO_ZR): Bump accordingly.
638 (get_operand_field_width): New function.
639 * aarch64-opc.c (fields): Add new SVE fields.
640 (operand_general_constraint_met_p): Handle new SVE operands.
641 (aarch64_print_operand): Likewise.
642 * aarch64-opc-2.c: Regenerate.
643
f482d304
RS		 6442017-02-24 Richard Sandiford <richard.sandiford@arm.com>
645
646 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
647 (aarch64_feature_compnum): ...this.
648 (SIMD_V8_3): Replace with...
649 (COMPNUM): ...this.
650 (CNUM_INSN): New macro.
651 (aarch64_opcode_table): Use it for the complex number instructions.
652
7db2c588
JB		 6532017-02-24 Jan Beulich <jbeulich@suse.com>
654
655 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
656
1e9d41d4
SL		 6572017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
658
659 Add support for associating SPARC ASIs with an architecture level.
660 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
661 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
662 decoding of SPARC ASIs.
663
53c4d625
JB		 6642017-02-23 Jan Beulich <jbeulich@suse.com>
665
666 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
667 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
668
11648de5
JB		 6692017-02-21 Jan Beulich <jbeulich@suse.com>
670
671 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
672 1 (instead of to itself). Correct typo.
673
f98d33be
AW		 6742017-02-14 Andrew Waterman <andrew@sifive.com>
675
676 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
677 pseudoinstructions.
678
773fb663
RS		 6792017-02-15 Richard Sandiford <richard.sandiford@arm.com>
680
681 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
682 (aarch64_sys_reg_supported_p): Handle them.
683
cc07cda6
CZ		 6842017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
685
686 * arc-opc.c (UIMM6_20R): Define.
687 (SIMM12_20): Use above.
688 (SIMM12_20R): Define.
689 (SIMM3_5_S): Use above.
690 (UIMM7_A32_11R_S): Define.
691 (UIMM7_9_S): Use above.
692 (UIMM3_13R_S): Define.
693 (SIMM11_A32_7_S): Use above.
694 (SIMM9_8R): Define.
695 (UIMM10_A32_8_S): Use above.
696 (UIMM8_8R_S): Define.
697 (W6): Use above.
698 (arc_relax_opcodes): Use all above defines.
699
66a5a740
VG		 7002017-02-15 Vineet Gupta <vgupta@synopsys.com>
701
702 * arc-regs.h: Distinguish some of the registers different on
703 ARC700 and HS38 cpus.
704
7e0de605
AM		 7052017-02-14 Alan Modra <amodra@gmail.com>
706
707 PR 21118
708 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
709 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
710
54064fdb
AM		 7112017-02-11 Stafford Horne <shorne@gmail.com>
712 Alan Modra <amodra@gmail.com>
713
714 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
715 Use insn_bytes_value and insn_int_value directly instead. Don't
716 free allocated memory until function exit.
717
dce75bf9
NP		 7182017-02-10 Nicholas Piggin <npiggin@gmail.com>
719
720 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
721
1b7e3d2f
NC		 7222017-02-03 Nick Clifton <nickc@redhat.com>
723
724 PR 21096
725 * aarch64-opc.c (print_register_list): Ensure that the register
726 list index will fir into the tb buffer.
727 (print_register_offset_address): Likewise.
728 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
729
8ec5cf65
AD		 7302017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
731
732 PR 21056
733 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
734 instructions when the previous fetch packet ends with a 32-bit
735 instruction.
736
a1aa5e81
DD		 7372017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
738
739 * pru-opc.c: Remove vague reference to a future GDB port.
740
add3afb2
NC		 7412017-01-20 Nick Clifton <nickc@redhat.com>
742
743 * po/ga.po: Updated Irish translation.
744
c13a63b0
SN		 7452017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
746
747 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
748
9608051a
YQ		 7492017-01-13 Yao Qi <yao.qi@linaro.org>
750
751 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
752 if FETCH_DATA returns 0.
753 (m68k_scan_mask): Likewise.
754 (print_insn_m68k): Update code to handle -1 return value.
755
f622ea96
YQ		 7562017-01-13 Yao Qi <yao.qi@linaro.org>
757
758 * m68k-dis.c (enum print_insn_arg_error): New.
759 (NEXTBYTE): Replace -3 with
760 PRINT_INSN_ARG_MEMORY_ERROR.
761 (NEXTULONG): Likewise.
762 (NEXTSINGLE): Likewise.
763 (NEXTDOUBLE): Likewise.
764 (NEXTDOUBLE): Likewise.
765 (NEXTPACKED): Likewise.
766 (FETCH_ARG): Likewise.
767 (FETCH_DATA): Update comments.
768 (print_insn_arg): Update comments. Replace magic numbers with
769 enum.
770 (match_insn_m68k): Likewise.
771
620214f7
IT		 7722017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
773
774 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
775 * i386-dis-evex.h (evex_table): Updated.
776 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
777 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
778 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
779 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
780 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
781 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
782 * i386-init.h: Regenerate.
783 * i386-tbl.h: Ditto.
784
d95014a2
YQ		 7852017-01-12 Yao Qi <yao.qi@linaro.org>
786
787 * msp430-dis.c (msp430_singleoperand): Return -1 if
788 msp430dis_opcode_signed returns false.
789 (msp430_doubleoperand): Likewise.
790 (msp430_branchinstr): Return -1 if
791 msp430dis_opcode_unsigned returns false.
792 (msp430x_calla_instr): Likewise.
793 (print_insn_msp430): Likewise.
794
0ae60c3e
NC		 7952017-01-05 Nick Clifton <nickc@redhat.com>
796
797 PR 20946
798 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
799 could not be matched.
800 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
801 NULL.
802
d74d4880
SN		 8032017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
804
805 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
806 (aarch64_opcode_table): Use RCPC_INSN.
807
cc917fd9
KC		 8082017-01-03 Kito Cheng <kito.cheng@gmail.com>
809
810 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
811 extension.
812 * riscv-opcodes/all-opcodes: Likewise.
813
b52d3cfc
DP		 8142017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
815
816 * riscv-dis.c (print_insn_args): Add fall through comment.
817
f90c58d5
NC		 8182017-01-03 Nick Clifton <nickc@redhat.com>
819
820 * po/sr.po: New Serbian translation.
821 * configure.ac (ALL_LINGUAS): Add sr.
822 * configure: Regenerate.
823
f47b0d4a
AM		 8242017-01-02 Alan Modra <amodra@gmail.com>
825
826 * epiphany-desc.h: Regenerate.
827 * epiphany-opc.h: Regenerate.
828 * fr30-desc.h: Regenerate.
829 * fr30-opc.h: Regenerate.
830 * frv-desc.h: Regenerate.
831 * frv-opc.h: Regenerate.
832 * ip2k-desc.h: Regenerate.
833 * ip2k-opc.h: Regenerate.
834 * iq2000-desc.h: Regenerate.
835 * iq2000-opc.h: Regenerate.
836 * lm32-desc.h: Regenerate.
837 * lm32-opc.h: Regenerate.
838 * m32c-desc.h: Regenerate.
839 * m32c-opc.h: Regenerate.
840 * m32r-desc.h: Regenerate.
841 * m32r-opc.h: Regenerate.
842 * mep-desc.h: Regenerate.
843 * mep-opc.h: Regenerate.
844 * mt-desc.h: Regenerate.
845 * mt-opc.h: Regenerate.
846 * or1k-desc.h: Regenerate.
847 * or1k-opc.h: Regenerate.
848 * xc16x-desc.h: Regenerate.
849 * xc16x-opc.h: Regenerate.
850 * xstormy16-desc.h: Regenerate.
851 * xstormy16-opc.h: Regenerate.
852
2571583a
AM		 8532017-01-02 Alan Modra <amodra@gmail.com>
854
855 Update year range in copyright notice of all files.
856
5c1ad6b5 857For older changes see ChangeLog-2016
3499769a 858\f
5c1ad6b5 859Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 860
861Copying and distribution of this file, with or without modification,
862are permitted in any medium without royalty provided the copyright
863notice and this notice are preserved.
864
865Local Variables:
866mode: change-log
867left-margin: 8
868fill-column: 74
869version-control: never
870End:
GDB Binutils - Deliverables
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