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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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99c513f6
DD		 12011-11-01 DJ Delorie <dj@redhat.com>
2
3 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add rl78-decode.c and
4 rl78-dis.c.
5 (MAINTAINERCLEANFILES): Add rl78-decode.c.
6 (rl78-decode.c): New rule, built from rl78-decode.opc and opc2c.
7 * Makefile.in: Regenerate.
8 * configure.in: Add bfd_rl78_arch case.
9 * configure: Regenerate.
10 * disassemble.c: Define ARCH_rl78.
11 (disassembler): Add ARCH_rl78 case.
12 * rl78-decode.c: New file.
13 * rl78-decode.opc: New file.
14 * rl78-dis.c: New file.
15
a08fc942
PB		 162011-10-27 Peter Bergner <bergner@vnet.ibm.com>
17
18 * ppc-opc.c (powerpc_opcodes) <drrndq, drrndq., dtstexq, dctqpq,
19 dctqpq., dctfixq, dctfixq., dxexq, dxexq., dtstsfq, dcffixq, dcffixq.,
20 diexq, diexq.>: Use FRT, FRA, FRB and FRBp repsectively on DFP quad
21 instructions.
22
f6dd4781
NC		 232011-10-26 Nick Clifton <nickc@redhat.com>
24
25 PR binutils/13348
26 * i386-dis.c (print_insn): Fix testing of array subscript.
27
56b13185
JR		 282011-10-26 Joern Rennecke <joern.rennecke@embecosm.com>
29
30 * disassemble.c (ARCH_epiphany): Move into alphasorted spot.
fd936b4c
JR		 31 * epiphany-asm.c, epiphany-opc.h: Regenerate.
32
cfb8c092
NC		 332011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
34
35 * Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h .
36 (TARGET_LIBOPCODES_CFILES): Add epiphany-asm.c, epiphany-desc.c,
37 epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c .
38 (CLEANFILES): Add stamp-epiphany.
39 (EPIPHANY_DEPS): Set. Make CGEN-generated Epiphany files depend on it.
40 (stamp-epiphany): New rule.
41 * configure.in: Handle bfd_epiphany_arch.
42 * disassemble.c (ARCH_epiphany): Define.
43 (disassembler): Handle bfd_arch_epiphany.
44 * epiphany-asm.c: New file.
45 * epiphany-desc.c: New file.
46 * epiphany-desc.h: New file.
47 * epiphany-dis.c: New file.
48 * epiphany-ibld.c: New file.
49 * epiphany-opc.c: New file.
50 * epiphany-opc.h: New file.
51 * Makefile.in: Regenerate.
52 * configure: Regenerate.
53 * po/POTFILES.in: Regenerate.
54 * po/opcodes.pot: Regenerate.
55
c3732716
JB		 562011-10-24 Julian Brown <julian@codesourcery.com>
57
58 * m68k-opc.c (m68k_opcodes): Fix entries for ColdFire moveml.
59
9cae27dc
AK		 602011-10-21 Jan Glauber <jang@linux.vnet.ibm.com>
61
62 * s390-opc.txt: Add CPUMF instructions.
63
a415b1cd
JB		 642011-10-18 Jie Zhang <jie@codesourcery.com>
65 Julian Brown <julian@codesourcery.com>
66
67 * arm-dis.c (print_insn_arm): Explicitly specify rotation if needed.
68
d5698657
NC		 692011-10-10 Nick Clifton <nickc@redhat.com>
70
71 * po/es.po: Updated Spanish translation.
72 * po/fi.po: Updated Finnish translation.
73
989993d8
JB		 742011-09-28 Jan Beulich <jbeulich@suse.com>
75
76 * ppc-opc.c (insert_nbi, insert_rbx, FRAp, FRBp, FRSp, FRTp, NBI, RAX,
77 RBX): New.
78 (insert_bo, insert_boe): Reject bcctr with bit 2 in bo unset.
79 (powerpc_opcodes): Use RAX for second and RBXC for third operand of
80 lswx. Use NBI for third operand of lswi. Use FRTp for first operand of
81 lfdp and lfdpx. Use FRSp for first operand of stfdp and stfdpx, and
82 mark them as invalid on POWER7. Use FRTp, FRAp, and FRBp repsectively
83 on DFP quad instructions.
84
92a7795b
DM		 852011-09-27 David S. Miller <davem@davemloft.net>
86
87 * sparc-opc.c (sparc_opcodes): Fix random instruction to write
88 to a float instead of an integer register.
89
e91d1076
DM		 902011-09-26 David S. Miller <davem@davemloft.net>
91
92 * sparc-opc.c (sparc_opcodes): Add integer multiply-add
93 instructions.
94
9e8c70f9
DM		 952011-09-21 David S. Miller <davem@davemloft.net>
96
97 * sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag
98 bits. Fix "fchksm16" mnemonic.
99
9bf29d72
DM		 1002011-09-08 Mark Fortescue <mark@mtfhpc.demon.co.uk>
101
102 The changes below bring 'mov' and 'ticc' instructions into line
103 with the V8 SPARC Architecture Manual.
104 * sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'.
105 * sparc-opc.c (sparc_opcodes): Add alias entries for
106 'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs';
107 'mov regrs2,%wim' and 'mov regrs2,%tbr'.
108 * sparc-opc.c (sparc_opcodes): Move/Change entries for
109 'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim'
110 and 'mov imm,%tbr'.
111 * sparc-opc.c (sparc_opcodes): Add wr alias entries to match above
112 mov aliases.
113
8dbb9eb3
DM		 114 * sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd'
115 This has been reported as being accepted by the Sun assmebler.
116
cdf49201
DM		 1172011-09-08 David S. Miller <davem@davemloft.net>
118
119 * sparc-opc.c (pdistn): Destination is integer not float register.
120
96e67898
AS		 1212011-09-07 Andreas Schwab <schwab@linux-m68k.org>
122
b2ea1829 123 PR gas/13145
96e67898
AS		 124 * m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.
125
7cf80422
NC		 1262011-08-26 Nick Clifton <nickc@redhat.com>
127
128 * po/es.po: Updated Spanish translation.
129
dc15e575
NC		 1302011-08-22 Nick Clifton <nickc@redhat.com>
131
132 * Makefile.am (CPUDIR): Redfine to point to top level cpu
133 directory.
134 (stamp-frv): Use CPUDIR.
135 (stamp-iq2000): Likewise.
136 (stamp-lm32): Likewise.
137 (stamp-m32c): Likewise.
138 (stamp-mt): Likewise.
139 (stamp-xc16x): Likewise.
140 * Makefile.in: Regenerate.
141
dec0624d
MR		 1422011-08-09 Chao-ying Fu <fu@mips.com>
143 Maciej W. Rozycki <macro@codesourcery.com>
144
145 * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
146 and "mips64r2".
147 (print_insn_args, print_insn_micromips): Handle MCU.
148 * micromips-opc.c (MC): New macro.
149 (micromips_opcodes): Add "aclr", "aset" and "iret".
150 * mips-opc.c (MC): New macro.
151 (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
152
2b0c8b40
MR		 1532011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
154
155 * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
156 (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
157 (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
158 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
159 (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
160 (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
161 (WR_s): Update macro.
162 (micromips_opcodes): Update register use flags of: "addiu",
163 "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
164 "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
165 "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
166 "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
167 "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
168 "swm" and "xor" instructions.
169
ea783ef3
DM		 1702011-08-05 David S. Miller <davem@davemloft.net>
171
172 * sparc-dis.c (v9a_ast_reg_names): Add "cps".
173 (X_RS3): New macro.
174 (print_insn_sparc): Handle '4', '5', and '(' format codes.
175 Accept %asr numbers below 28.
176 * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
177 instructions.
178
3929df09
QN		 1792011-08-02 Quentin Neill <quentin.neill@amd.com>
180
181 * i386-dis.c (xop_table): Remove spurious bextr insn.
182
d7921315
L		 1832011-08-01 H.J. Lu <hongjiu.lu@intel.com>
184
185 PR ld/13048
186 * i386-dis.c (print_insn): Optimize info->mach check.
187
00f51a41
L		 1882011-08-01 H.J. Lu <hongjiu.lu@intel.com>
189
190 PR gas/13046
191 * i386-opc.tbl: Add Disp32S to 64bit call.
192 * i386-tbl.h: Regenerated.
193
df58fc94
RS		 1942011-07-24 Chao-ying Fu <fu@mips.com>
195 Maciej W. Rozycki <macro@codesourcery.com>
196
197 * micromips-opc.c: New file.
198 * mips-dis.c (micromips_to_32_reg_b_map): New array.
199 (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
200 (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
201 (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
202 (micromips_to_32_reg_q_map): Likewise.
203 (micromips_imm_b_map, micromips_imm_c_map): Likewise.
204 (micromips_ase): New variable.
205 (is_micromips): New function.
206 (set_default_mips_dis_options): Handle microMIPS ASE.
207 (print_insn_micromips): New function.
208 (is_compressed_mode_p): Likewise.
209 (_print_insn_mips): Handle microMIPS instructions.
210 * Makefile.am (CFILES): Add micromips-opc.c.
211 * configure.in (bfd_mips_arch): Add micromips-opc.lo.
212 * Makefile.in: Regenerate.
213 * configure: Regenerate.
214
215 * mips-dis.c (micromips_to_32_reg_h_map): New variable.
216 (micromips_to_32_reg_i_map): Likewise.
217 (micromips_to_32_reg_m_map): Likewise.
218 (micromips_to_32_reg_n_map): New macro.
219
bcd530a7
RS		 2202011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
221
222 * mips-opc.c (NODS): New macro.
223 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
224 (DSP_VOLA): Likewise.
225 (mips_builtin_opcodes): Add NODS annotation to "deret" and
226 "eret". Replace INSN_SYNC with NODS throughout. Use NODS in
227 place of TRAP for "wait", "waiti" and "yield".
228 * mips16-opc.c (NODS): New macro.
229 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
230 (mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc",
231 "restore" and "save".
232
7a9068fe
L		 2332011-07-22 H.J. Lu <hongjiu.lu@intel.com>
234
235 * configure.in: Handle bfd_k1om_arch.
236 * configure: Regenerated.
237
238 * disassemble.c (disassembler): Handle bfd_k1om_arch.
239
240 * i386-dis.c (print_insn): Handle bfd_mach_k1om and
241 bfd_mach_k1om_intel_syntax.
242
243 * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
244 ~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS.
245 (cpu_flags): Add CpuK1OM.
246
247 * i386-opc.h (CpuK1OM): New.
248 (i386_cpu_flags): Add cpuk1om.
249
250 * i386-init.h: Regenerated.
251 * i386-tbl.h: Likewise.
252
1b93226d
NC		 2532011-07-12 Nick Clifton <nickc@redhat.com>
254
255 * arm-dis.c (print_insn_arm): Revert previous, undocumented,
256 accidental change.
257
5d73b1f1
NC		 2582011-07-01 Nick Clifton <nickc@redhat.com>
259
260 PR binutils/12329
261 * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
262 insns using post-increment addressing.
263
182ae480
L		 2642011-06-30 H.J. Lu <hongjiu.lu@intel.com>
265
266 * i386-dis.c (vex_len_table): Update rorxS.
267
4cb0953d
L		 2682011-06-30 H.J. Lu <hongjiu.lu@intel.com>
269
270 AVX Programming Reference (June, 2011)
271 * i386-dis.c (vex_len_table): Correct rorxS.
272
273 * i386-opc.tbl: Correct rorx.
274 * i386-tbl.h: Regenerated.
275
906efcbc
L		 2762011-06-29 H.J. Lu <hongjiu.lu@intel.com>
277
278 * tilegx-opc.c (find_opcode): Replace "index" with "i".
279 * tilepro-opc.c (find_opcode): Likewise.
280
ceb94aa5
RS		 2812011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
282
283 * mips16-opc.c (jalrc, jrc): Move earlier in file.
284
f7002f42
L		 2852011-06-21 H.J. Lu <hongjiu.lu@intel.com>
286
287 * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
288 PREFIX_VEX_0F388E.
289
56300268
AS		 2902011-06-17 Andreas Schwab <schwab@redhat.com>
291
292 * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
293 (MOSTLYCLEANFILES): ... here.
294 * Makefile.in: Regenerate.
295
bcf2cf9f
AM		 2962011-06-14 Alan Modra <amodra@gmail.com>
297
298 * Makefile.in: Regenerate.
299
aa137e4d
NC		 3002011-06-13 Walter Lee <walt@tilera.com>
301
302 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
303 tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
304 * Makefile.in: Regenerate.
305 * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
306 * configure: Regenerate.
307 * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
308 * po/POTFILES.in: Regenerate.
309 * tilegx-dis.c: New file.
310 * tilegx-opc.c: New file.
311 * tilepro-dis.c: New file.
312 * tilepro-opc.c: New file.
313
6c30d220
L		 3142011-06-10 H.J. Lu <hongjiu.lu@intel.com>
315
316 AVX Programming Reference (June, 2011)
317 * i386-dis.c (XMGatherQ): New.
318 * i386-dis.c (EXxmm_mb): New.
319 (EXxmm_mb): Likewise.
320 (EXxmm_mw): Likewise.
321 (EXxmm_md): Likewise.
322 (EXxmm_mq): Likewise.
323 (EXxmmdw): Likewise.
324 (EXxmmqd): Likewise.
325 (VexGatherQ): Likewise.
326 (MVexVSIBDWpX): Likewise.
327 (MVexVSIBQWpX): Likewise.
328 (xmm_mb_mode): Likewise.
329 (xmm_mw_mode): Likewise.
330 (xmm_md_mode): Likewise.
331 (xmm_mq_mode): Likewise.
332 (xmmdw_mode): Likewise.
333 (xmmqd_mode): Likewise.
334 (ymmxmm_mode): Likewise.
335 (vex_vsib_d_w_dq_mode): Likewise.
336 (vex_vsib_q_w_dq_mode): Likewise.
337 (MOD_VEX_0F385A_PREFIX_2): Likewise.
338 (MOD_VEX_0F388C_PREFIX_2): Likewise.
339 (MOD_VEX_0F388E_PREFIX_2): Likewise.
340 (PREFIX_0F3882): Likewise.
341 (PREFIX_VEX_0F3816): Likewise.
342 (PREFIX_VEX_0F3836): Likewise.
343 (PREFIX_VEX_0F3845): Likewise.
344 (PREFIX_VEX_0F3846): Likewise.
345 (PREFIX_VEX_0F3847): Likewise.
346 (PREFIX_VEX_0F3858): Likewise.
347 (PREFIX_VEX_0F3859): Likewise.
348 (PREFIX_VEX_0F385A): Likewise.
349 (PREFIX_VEX_0F3878): Likewise.
350 (PREFIX_VEX_0F3879): Likewise.
351 (PREFIX_VEX_0F388C): Likewise.
352 (PREFIX_VEX_0F388E): Likewise.
353 (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
354 (PREFIX_VEX_0F38F5): Likewise.
355 (PREFIX_VEX_0F38F6): Likewise.
356 (PREFIX_VEX_0F3A00): Likewise.
357 (PREFIX_VEX_0F3A01): Likewise.
358 (PREFIX_VEX_0F3A02): Likewise.
359 (PREFIX_VEX_0F3A38): Likewise.
360 (PREFIX_VEX_0F3A39): Likewise.
361 (PREFIX_VEX_0F3A46): Likewise.
362 (PREFIX_VEX_0F3AF0): Likewise.
363 (VEX_LEN_0F3816_P_2): Likewise.
364 (VEX_LEN_0F3819_P_2): Likewise.
365 (VEX_LEN_0F3836_P_2): Likewise.
366 (VEX_LEN_0F385A_P_2_M_0): Likewise.
367 (VEX_LEN_0F38F5_P_0): Likewise.
368 (VEX_LEN_0F38F5_P_1): Likewise.
369 (VEX_LEN_0F38F5_P_3): Likewise.
370 (VEX_LEN_0F38F6_P_3): Likewise.
371 (VEX_LEN_0F38F7_P_1): Likewise.
372 (VEX_LEN_0F38F7_P_2): Likewise.
373 (VEX_LEN_0F38F7_P_3): Likewise.
374 (VEX_LEN_0F3A00_P_2): Likewise.
375 (VEX_LEN_0F3A01_P_2): Likewise.
376 (VEX_LEN_0F3A38_P_2): Likewise.
377 (VEX_LEN_0F3A39_P_2): Likewise.
378 (VEX_LEN_0F3A46_P_2): Likewise.
379 (VEX_LEN_0F3AF0_P_3): Likewise.
380 (VEX_W_0F3816_P_2): Likewise.
381 (VEX_W_0F3818_P_2): Likewise.
382 (VEX_W_0F3819_P_2): Likewise.
383 (VEX_W_0F3836_P_2): Likewise.
384 (VEX_W_0F3846_P_2): Likewise.
385 (VEX_W_0F3858_P_2): Likewise.
386 (VEX_W_0F3859_P_2): Likewise.
387 (VEX_W_0F385A_P_2_M_0): Likewise.
388 (VEX_W_0F3878_P_2): Likewise.
389 (VEX_W_0F3879_P_2): Likewise.
390 (VEX_W_0F3A00_P_2): Likewise.
391 (VEX_W_0F3A01_P_2): Likewise.
392 (VEX_W_0F3A02_P_2): Likewise.
393 (VEX_W_0F3A38_P_2): Likewise.
394 (VEX_W_0F3A39_P_2): Likewise.
395 (VEX_W_0F3A46_P_2): Likewise.
396 (MOD_VEX_0F3818_PREFIX_2): Removed.
397 (MOD_VEX_0F3819_PREFIX_2): Likewise.
398 (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
399 (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
400 (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
401 (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
402 (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
403 (VEX_LEN_0F3A0E_P_2): Likewise.
404 (VEX_LEN_0F3A0F_P_2): Likewise.
405 (VEX_LEN_0F3A42_P_2): Likewise.
406 (VEX_LEN_0F3A4C_P_2): Likewise.
407 (VEX_W_0F3818_P_2_M_0): Likewise.
408 (VEX_W_0F3819_P_2_M_0): Likewise.
409 (prefix_table): Updated.
410 (three_byte_table): Likewise.
411 (vex_table): Likewise.
412 (vex_len_table): Likewise.
413 (vex_w_table): Likewise.
414 (mod_table): Likewise.
415 (putop): Handle "LW".
416 (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
417 xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
418 vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
419 (OP_EX): Likewise.
420 (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
421 vex_vsib_q_w_dq_mode.
422 (OP_XMM): Handle vex_vsib_q_w_dq_mode.
423 (OP_VEX): Likewise.
424
425 * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
426 and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
427 CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
428 (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
429 (opcode_modifiers): Add VecSIB.
430
431 * i386-opc.h (CpuAVX2): New.
432 (CpuBMI2): Likewise.
433 (CpuLZCNT): Likewise.
434 (CpuINVPCID): Likewise.
435 (VecSIB128): Likewise.
436 (VecSIB256): Likewise.
437 (VecSIB): Likewise.
438 (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
439 (i386_opcode_modifier): Add vecsib.
440
441 * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
442 * i386-init.h: Regenerated.
443 * i386-tbl.h: Likewise.
444
d535accd
QN		 4452011-06-03 Quentin Neill <quentin.neill@amd.com>
446
447 * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
448 * i386-init.h: Regenerated.
449
f8b960bc
NC		 4502011-06-03 Nick Clifton <nickc@redhat.com>
451
452 PR binutils/12752
453 * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
454 computing address offsets.
455 (print_arm_address): Likewise.
456 (print_insn_arm): Likewise.
457 (print_insn_thumb16): Likewise.
458 (print_insn_thumb32): Likewise.
459
26d97720
NS		 4602011-06-02 Jie Zhang <jie@codesourcery.com>
461 Nathan Sidwell <nathan@codesourcery.com>
462 Maciej Rozycki <macro@codesourcery.com>
463
464 * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
465 as address offset.
466 (print_arm_address): Likewise. Elide positive #0 appropriately.
467 (print_insn_arm): Likewise.
468
f8b960bc
NC		 4692011-06-02 Nick Clifton <nickc@redhat.com>
470
471 PR gas/12752
472 * arm-dis.c (print_insn_thumb32): Do not sign extend addresses
473 passed to print_address_func.
474
cc643b88
NC		 4752011-06-02 Nick Clifton <nickc@redhat.com>
476
477 * arm-dis.c: Fix spelling mistakes.
478 * op/opcodes.pot: Regenerate.
479
c8fa16ed
AK		 4802011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
481
482 * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
483 S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
484 * s390-opc.txt: Fix cxr instruction type.
485
5e4b319c
AK		 4862011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
487
488 * s390-opc.c: Add new instruction types marking register pair
489 operands.
490 * s390-opc.txt: Match instructions having register pair operands
491 to the new instruction types.
492
fda544a2
NC		 4932011-05-19 Nick Clifton <nickc@redhat.com>
494
495 * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
496 operands.
497
4cab4add
QN		 4982011-05-10 Quentin Neill <quentin.neill@amd.com>
499
500 * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
501 * i386-init.h: Regenerated.
502
b4e7b885
NC		 5032011-04-27 Nick Clifton <nickc@redhat.com>
504
505 * po/da.po: Updated Danish translation.
506
2f7f7710
AM		 5072011-04-26 Anton Blanchard <anton@samba.org>
508
509 * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
510
9887672f
DD		 5112011-04-21 DJ Delorie <dj@redhat.com>
512
513 * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
514 * rx-decode.c: Regenerate.
515
3251b375
L		 5162011-04-20 H.J. Lu <hongjiu.lu@intel.com>
517
518 * i386-init.h: Regenerated.
519
b13a3ca6
QN		 5202011-04-19 Quentin Neill <quentin.neill@amd.com>
521
522 * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
523 from bdver1 flags.
524
7d063384
NC		 5252011-04-13 Nick Clifton <nickc@redhat.com>
526
527 * v850-dis.c (disassemble): Always print a closing square brace if
528 an opening square brace was printed.
529
32a94698
NC		 5302011-04-12 Nick Clifton <nickc@redhat.com>
531
532 PR binutils/12534
533 * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
534 patterns.
535 (print_insn_thumb32): Handle %L.
536
d2cd1205
JB		 5372011-04-11 Julian Brown <julian@codesourcery.com>
538
539 * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
540 (print_insn_thumb32): Add APSR bitmask support.
541
1fbaefec
PB		 5422011-04-07 Paul Carroll<pcarroll@codesourcery.com>
543
544 * arm-dis.c (print_insn): init vars moved into private_data structure.
545
67171547
MF		 5462011-03-24 Mike Frysinger <vapier@gentoo.org>
547
548 * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
549
8cc66334
EW		 5502011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
551
552 * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
553 post-increment to support LPM Z+ instruction. Add support for 'E'
554 constraint for DES instruction.
555 (print_insn_avr): Adjust calls to avr_operand. Rename variable.
556
34e77a92
RS		 5572011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
558
559 * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
560
35fc36a8
RS		 5612011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
562
563 * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
564 Use branch types instead.
565 (print_insn): Likewise.
566
0067d8fc
MR		 5672011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
568
569 * mips-opc.c (mips_builtin_opcodes): Correct register use
570 annotation of "alnv.ps".
571
3eebd5eb
MR		 5722011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
573
574 * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
575
500cccad
MF		 5762011-02-22 Mike Frysinger <vapier@gentoo.org>
577
578 * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
579
f5caf9f4
MF		 5802011-02-22 Mike Frysinger <vapier@gentoo.org>
581
582 * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
583
e5bc4265
MF		 5842011-02-19 Mike Frysinger <vapier@gentoo.org>
585
586 * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
587 a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
588 av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
589 exception, end_of_registers, msize, memory, bfd_mach.
590 (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
591 LB0REG, LC1REG, LT1REG, LB1REG): Delete
592 (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
593 (get_allreg): Change to new defines. Fallback to abort().
594
602427c4
MF		 5952011-02-14 Mike Frysinger <vapier@gentoo.org>
596
597 * bfin-dis.c: Add whitespace/parenthesis where needed.
598
298c1ec2
MF		 5992011-02-14 Mike Frysinger <vapier@gentoo.org>
600
601 * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
602 than 7.
603
822ce8ee
RW		 6042011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
605
606 * configure: Regenerate.
607
13c02f06
MF		 6082011-02-13 Mike Frysinger <vapier@gentoo.org>
609
610 * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
611
4db66394
MF		 6122011-02-13 Mike Frysinger <vapier@gentoo.org>
613
614 * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
615 dregs only when P is set, and dregs_lo otherwise.
616
36f44611
MF		 6172011-02-13 Mike Frysinger <vapier@gentoo.org>
618
619 * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
620
9805c0a5
MF		 6212011-02-12 Mike Frysinger <vapier@gentoo.org>
622
623 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
624
43a6aa65
MF		 6252011-02-12 Mike Frysinger <vapier@gentoo.org>
626
627 * bfin-dis.c (machine_registers): Delete REG_GP.
628 (reg_names): Delete "GP".
629 (decode_allregs): Change REG_GP to REG_LASTREG.
630
26bb3ddd
MF		 6312011-02-12 Mike Frysinger <vapier@gentoo.org>
632
89c0d58c
MR		 633 * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
634 M_IH, M_IU): Delete.
26bb3ddd 635
69b8ea4a
MF		 6362011-02-11 Mike Frysinger <vapier@gentoo.org>
637
638 * bfin-dis.c (reg_names): Add const.
639 (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
640 decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
641 decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
642 decode_counters, decode_allregs): Likewise.
643
42d5f9c6
MS		 6442011-02-09 Michael Snyder <msnyder@vmware.com>
645
56300268 646 * i386-dis.c (OP_J): Parenthesize expression to prevent
42d5f9c6
MS		 647 truncated addresses.
648 (print_insn): Fix indentation off-by-one.
649
4be0c941
NC		 6502011-02-01 Nick Clifton <nickc@redhat.com>
651
652 * po/da.po: Updated Danish translation.
653
6b069ee7
AM		 6542011-01-21 Dave Murphy <davem@devkitpro.org>
655
656 * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
657
e3949f17
L		 6582011-01-18 H.J. Lu <hongjiu.lu@intel.com>
659
660 * i386-dis.c (sIbT): New.
661 (b_T_mode): Likewise.
662 (dis386): Replace sIb with sIbT on "pushT".
663 (x86_64_table): Replace sIb with Ib on "aam" and "aad".
664 (OP_sI): Handle b_T_mode. Properly sign-extend byte.
665
752573b2
JK		 6662011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
667
668 * i386-init.h: Regenerated.
669 * i386-tbl.h: Regenerated
670
2a2a0f38
QN		 6712011-01-17 Quentin Neill <quentin.neill@amd.com>
672
673 * i386-dis.c (REG_XOP_TBM_01): New.
674 (REG_XOP_TBM_02): New.
675 (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
676 (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
677 entries, and add bextr instruction.
678
679 * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
680 (cpu_flags): Add CpuTBM.
681
682 * i386-opc.h (CpuTBM) New.
683 (i386_cpu_flags): Add bit cputbm.
684
685 * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
686 blcs, blsfill, blsic, t1mskc, and tzmsk.
687
90d6ff62
DD		 6882011-01-12 DJ Delorie <dj@redhat.com>
689
690 * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
691
c95354ed
MX		 6922011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
693
694 * mips-dis.c (print_insn_args): Adjust the value to print the real
695 offset for "+c" argument.
696
f7465604
NC		 6972011-01-10 Nick Clifton <nickc@redhat.com>
698
699 * po/da.po: Updated Danish translation.
700
639e30d2
NS		 7012011-01-05 Nathan Sidwell <nathan@codesourcery.com>
702
703 * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
704
f12dc422
L		 7052011-01-04 H.J. Lu <hongjiu.lu@intel.com>
706
707 * i386-dis.c (REG_VEX_38F3): New.
708 (PREFIX_0FBC): Likewise.
709 (PREFIX_VEX_38F2): Likewise.
710 (PREFIX_VEX_38F3_REG_1): Likewise.
711 (PREFIX_VEX_38F3_REG_2): Likewise.
712 (PREFIX_VEX_38F3_REG_3): Likewise.
713 (PREFIX_VEX_38F7): Likewise.
714 (VEX_LEN_38F2_P_0): Likewise.
715 (VEX_LEN_38F3_R_1_P_0): Likewise.
716 (VEX_LEN_38F3_R_2_P_0): Likewise.
717 (VEX_LEN_38F3_R_3_P_0): Likewise.
718 (VEX_LEN_38F7_P_0): Likewise.
719 (dis386_twobyte): Use PREFIX_0FBC.
720 (reg_table): Add REG_VEX_38F3.
721 (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
722 PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
723 PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
724 (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
725 PREFIX_VEX_38F7.
726 (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
727 VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
728 VEX_LEN_38F7_P_0.
729
730 * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
731 (cpu_flags): Add CpuBMI.
732
733 * i386-opc.h (CpuBMI): New.
734 (i386_cpu_flags): Add cpubmi.
735
736 * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
737 * i386-init.h: Regenerated.
738 * i386-tbl.h: Likewise.
739
cb21baef
L		 7402011-01-04 H.J. Lu <hongjiu.lu@intel.com>
741
742 * i386-dis.c (VexGdq): New.
743 (OP_VEX): Handle dq_mode.
744
0db46eb4
L		 7452011-01-01 H.J. Lu <hongjiu.lu@intel.com>
746
747 * i386-gen.c (process_copyright): Update copyright to 2011.
748
9e9e0820 749For older changes see ChangeLog-2010
252b5132
RH		 750\f
751Local Variables:
2f6d2f85
NC		 752mode: change-log
753left-margin: 8
754fill-column: 74
252b5132
RH		 755version-control: never
756End:
GDB Binutils - Deliverables
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