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x86: optimize EVEX packed integer logical instructions
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
a0a1771e
JB		 12019-07-01 Jan Beulich <jbeulich@suse.com>
2
3 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
4 register operands.
5 * i386-tbl.h: Re-generate.
6
cd546e7b
JB		 72019-07-01 Jan Beulich <jbeulich@suse.com>
8
9 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
10 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
11 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
12 * i386-tbl.h: Re-generate.
13
e3bba3fc
JB		 142019-07-01 Jan Beulich <jbeulich@suse.com>
15
16 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
17 Disp8MemShift from register only templates.
18 * i386-tbl.h: Re-generate.
19
36cc073e
JB		 202019-07-01 Jan Beulich <jbeulich@suse.com>
21
22 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
23 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
24 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
25 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
26 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
27 EVEX_W_0F11_P_3_M_1): Delete.
28 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
29 EVEX_W_0F11_P_3): New.
30 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
31 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
32 MOD_EVEX_0F11_PREFIX_3 table entries.
33 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
34 PREFIX_EVEX_0F11 table entries.
35 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
36 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
37 EVEX_W_0F11_P_3_M_{0,1} table entries.
38
219920a7
JB		 392019-07-01 Jan Beulich <jbeulich@suse.com>
40
41 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
42 Delete.
43
e395f487
L		 442019-06-27 H.J. Lu <hongjiu.lu@intel.com>
45
46 PR binutils/24719
47 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
48 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
49 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
50 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
51 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
52 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
53 EVEX_LEN_0F38C7_R_6_P_2_W_1.
54 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
55 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
56 PREFIX_EVEX_0F38C6_REG_6 entries.
57 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
58 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
59 EVEX_W_0F38C7_R_6_P_2 entries.
60 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
61 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
62 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
63 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
64 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
65 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
66 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
67
2b7bcc87
JB		 682019-06-27 Jan Beulich <jbeulich@suse.com>
69
70 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
71 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
72 VEX_LEN_0F2D_P_3): Delete.
73 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
74 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
75 (prefix_table): ... here.
76
c1dc7af5
JB		 772019-06-27 Jan Beulich <jbeulich@suse.com>
78
79 * i386-dis.c (Iq): Delete.
80 (Id): New.
81 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
82 TBM insns.
83 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
84 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
85 (OP_E_memory): Also honor needindex when deciding whether an
86 address size prefix needs printing.
87 (OP_I): Remove handling of q_mode. Add handling of d_mode.
88
d7560e2d
JW		 892019-06-26 Jim Wilson <jimw@sifive.com>
90
91 PR binutils/24739
92 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
93 Set info->display_endian to info->endian_code.
94
2c703856
JB		 952019-06-25 Jan Beulich <jbeulich@suse.com>
96
97 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
98 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
99 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
100 OPERAND_TYPE_ACC64 entries.
101 * i386-init.h: Re-generate.
102
54fbadc0
JB		 1032019-06-25 Jan Beulich <jbeulich@suse.com>
104
105 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
106 Delete.
107 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
108 of dqa_mode.
109 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
110 entries here.
111 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
112 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
113
a280ab8e
JB		 1142019-06-25 Jan Beulich <jbeulich@suse.com>
115
116 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
117 variables.
118
e1a1babd
JB		 1192019-06-25 Jan Beulich <jbeulich@suse.com>
120
121 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
122 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
123 movnti.
d7560e2d 124 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 125 * i386-tbl.h: Re-generate.
126
b8364fa7
JB		 1272019-06-25 Jan Beulich <jbeulich@suse.com>
128
129 * i386-opc.tbl (and): Mark Imm8S form for optimization.
130 * i386-tbl.h: Re-generate.
131
ad692897
L		 1322019-06-21 H.J. Lu <hongjiu.lu@intel.com>
133
134 * i386-dis-evex.h: Break into ...
135 * i386-dis-evex-len.h: New file.
136 * i386-dis-evex-mod.h: Likewise.
137 * i386-dis-evex-prefix.h: Likewise.
138 * i386-dis-evex-reg.h: Likewise.
139 * i386-dis-evex-w.h: Likewise.
140 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
141 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
142 i386-dis-evex-mod.h.
143
f0a6222e
L		 1442019-06-19 H.J. Lu <hongjiu.lu@intel.com>
145
146 PR binutils/24700
147 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
148 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
149 EVEX_W_0F385B_P_2.
150 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
151 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
152 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
153 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
154 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
155 EVEX_LEN_0F385B_P_2_W_1.
156 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
157 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
158 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
159 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
160 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
161 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
162 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
163 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
164 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
165 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
166
6e1c90b7
L		 1672019-06-17 H.J. Lu <hongjiu.lu@intel.com>
168
169 PR binutils/24691
170 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
171 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
172 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
173 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
174 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
175 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
176 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
177 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
178 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
179 EVEX_LEN_0F3A43_P_2_W_1.
180 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
181 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
182 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
183 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
184 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
185 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
186 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
187 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
188 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
189 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
190 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
191 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
192
bcc5a6eb
NC		 1932019-06-14 Nick Clifton <nickc@redhat.com>
194
195 * po/fr.po; Updated French translation.
196
e4c4ac46
SH		 1972019-06-13 Stafford Horne <shorne@gmail.com>
198
199 * or1k-asm.c: Regenerated.
200 * or1k-desc.c: Regenerated.
201 * or1k-desc.h: Regenerated.
202 * or1k-dis.c: Regenerated.
203 * or1k-ibld.c: Regenerated.
204 * or1k-opc.c: Regenerated.
205 * or1k-opc.h: Regenerated.
206 * or1k-opinst.c: Regenerated.
207
a0e44ef5
PB		 2082019-06-12 Peter Bergner <bergner@linux.ibm.com>
209
210 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
211
12efd68d
L		 2122019-06-05 H.J. Lu <hongjiu.lu@intel.com>
213
214 PR binutils/24633
215 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
216 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
217 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
218 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
219 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
220 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
221 EVEX_LEN_0F3A1B_P_2_W_1.
222 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
223 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
224 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
225 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
226 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
227 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
228 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
229 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
230
63c6fc6c
L		 2312019-06-04 H.J. Lu <hongjiu.lu@intel.com>
232
233 PR binutils/24626
234 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
235 EVEX.vvvv when disassembling VEX and EVEX instructions.
236 (OP_VEX): Set vex.register_specifier to 0 after readding
237 vex.register_specifier.
238 (OP_Vex_2src_1): Likewise.
239 (OP_Vex_2src_2): Likewise.
240 (OP_LWP_E): Likewise.
241 (OP_EX_Vex): Don't check vex.register_specifier.
242 (OP_XMM_Vex): Likewise.
243
9186c494
L		 2442019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
245 Lili Cui <lili.cui@intel.com>
246
247 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
248 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
249 instructions.
250 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
251 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
252 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
253 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
254 (i386_cpu_flags): Add cpuavx512_vp2intersect.
255 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
256 * i386-init.h: Regenerated.
257 * i386-tbl.h: Likewise.
258
5d79adc4
L		 2592019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
260 Lili Cui <lili.cui@intel.com>
261
262 * doc/c-i386.texi: Document enqcmd.
263 * testsuite/gas/i386/enqcmd-intel.d: New file.
264 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
265 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
266 * testsuite/gas/i386/enqcmd.d: Likewise.
267 * testsuite/gas/i386/enqcmd.s: Likewise.
268 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
269 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
270 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
271 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
272 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
273 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
274 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
275 and x86-64-enqcmd.
276
a9d96ab9
AH		 2772019-06-04 Alan Hayward <alan.hayward@arm.com>
278
279 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
280
4f6d070a
AM		 2812019-06-03 Alan Modra <amodra@gmail.com>
282
283 * ppc-dis.c (prefix_opcd_indices): Correct size.
284
a2f4b66c
L		 2852019-05-28 H.J. Lu <hongjiu.lu@intel.com>
286
287 PR gas/24625
288 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
289 Disp8ShiftVL.
290 * i386-tbl.h: Regenerated.
291
405b5bd8
AM		 2922019-05-24 Alan Modra <amodra@gmail.com>
293
294 * po/POTFILES.in: Regenerate.
295
8acf1435
PB		 2962019-05-24 Peter Bergner <bergner@linux.ibm.com>
297 Alan Modra <amodra@gmail.com>
298
299 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
300 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
301 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
302 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
303 XTOP>): Define and add entries.
304 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
305 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
306 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
307 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
308
dd7efa79
PB		 3092019-05-24 Peter Bergner <bergner@linux.ibm.com>
310 Alan Modra <amodra@gmail.com>
311
312 * ppc-dis.c (ppc_opts): Add "future" entry.
313 (PREFIX_OPCD_SEGS): Define.
314 (prefix_opcd_indices): New array.
315 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
316 (lookup_prefix): New function.
317 (print_insn_powerpc): Handle 64-bit prefix instructions.
318 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
319 (PMRR, POWERXX): Define.
320 (prefix_opcodes): New instruction table.
321 (prefix_num_opcodes): New constant.
322
79472b45
JM		 3232019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
324
325 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
326 * configure: Regenerated.
327 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
328 and cpu/bpf.opc.
329 (HFILES): Add bpf-desc.h and bpf-opc.h.
330 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
331 bpf-ibld.c and bpf-opc.c.
332 (BPF_DEPS): Define.
333 * Makefile.in: Regenerated.
334 * disassemble.c (ARCH_bpf): Define.
335 (disassembler): Add case for bfd_arch_bpf.
336 (disassemble_init_for_target): Likewise.
337 (enum epbf_isa_attr): Define.
338 * disassemble.h: extern print_insn_bpf.
339 * bpf-asm.c: Generated.
340 * bpf-opc.h: Likewise.
341 * bpf-opc.c: Likewise.
342 * bpf-ibld.c: Likewise.
343 * bpf-dis.c: Likewise.
344 * bpf-desc.h: Likewise.
345 * bpf-desc.c: Likewise.
346
ba6cd17f
SD		 3472019-05-21 Sudakshina Das <sudi.das@arm.com>
348
349 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
350 and VMSR with the new operands.
351
e39c1607
SD		 3522019-05-21 Sudakshina Das <sudi.das@arm.com>
353
354 * arm-dis.c (enum mve_instructions): New enum
355 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
356 and cneg.
357 (mve_opcodes): New instructions as above.
358 (is_mve_encoding_conflict): Add cases for csinc, csinv,
359 csneg and csel.
360 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
361
23d00a41
SD		 3622019-05-21 Sudakshina Das <sudi.das@arm.com>
363
364 * arm-dis.c (emun mve_instructions): Updated for new instructions.
365 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
366 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
367 uqshl, urshrl and urshr.
368 (is_mve_okay_in_it): Add new instructions to TRUE list.
369 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
370 (print_insn_mve): Updated to accept new %j,
371 %<bitfield>m and %<bitfield>n patterns.
372
cd4797ee
FS		 3732019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
374
375 * mips-opc.c (mips_builtin_opcodes): Change source register
376 constraint for DAUI.
377
999b073b
NC		 3782019-05-20 Nick Clifton <nickc@redhat.com>
379
380 * po/fr.po: Updated French translation.
381
14b456f2
AV		 3822019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
383 Michael Collison <michael.collison@arm.com>
384
385 * arm-dis.c (thumb32_opcodes): Add new instructions.
386 (enum mve_instructions): Likewise.
387 (enum mve_undefined): Add new reasons.
388 (is_mve_encoding_conflict): Handle new instructions.
389 (is_mve_undefined): Likewise.
390 (is_mve_unpredictable): Likewise.
391 (print_mve_undefined): Likewise.
392 (print_mve_size): Likewise.
393
f49bb598
AV		 3942019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
395 Michael Collison <michael.collison@arm.com>
396
397 * arm-dis.c (thumb32_opcodes): Add new instructions.
398 (enum mve_instructions): Likewise.
399 (is_mve_encoding_conflict): Handle new instructions.
400 (is_mve_undefined): Likewise.
401 (is_mve_unpredictable): Likewise.
402 (print_mve_size): Likewise.
403
56858bea
AV		 4042019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
405 Michael Collison <michael.collison@arm.com>
406
407 * arm-dis.c (thumb32_opcodes): Add new instructions.
408 (enum mve_instructions): Likewise.
409 (is_mve_encoding_conflict): Likewise.
410 (is_mve_unpredictable): Likewise.
411 (print_mve_size): Likewise.
412
e523f101
AV		 4132019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
414 Michael Collison <michael.collison@arm.com>
415
416 * arm-dis.c (thumb32_opcodes): Add new instructions.
417 (enum mve_instructions): Likewise.
418 (is_mve_encoding_conflict): Handle new instructions.
419 (is_mve_undefined): Likewise.
420 (is_mve_unpredictable): Likewise.
421 (print_mve_size): Likewise.
422
66dcaa5d
AV		 4232019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
424 Michael Collison <michael.collison@arm.com>
425
426 * arm-dis.c (thumb32_opcodes): Add new instructions.
427 (enum mve_instructions): Likewise.
428 (is_mve_encoding_conflict): Handle new instructions.
429 (is_mve_undefined): Likewise.
430 (is_mve_unpredictable): Likewise.
431 (print_mve_size): Likewise.
432 (print_insn_mve): Likewise.
433
d052b9b7
AV		 4342019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
435 Michael Collison <michael.collison@arm.com>
436
437 * arm-dis.c (thumb32_opcodes): Add new instructions.
438 (print_insn_thumb32): Handle new instructions.
439
ed63aa17
AV		 4402019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
441 Michael Collison <michael.collison@arm.com>
442
443 * arm-dis.c (enum mve_instructions): Add new instructions.
444 (enum mve_undefined): Add new reasons.
445 (is_mve_encoding_conflict): Handle new instructions.
446 (is_mve_undefined): Likewise.
447 (is_mve_unpredictable): Likewise.
448 (print_mve_undefined): Likewise.
449 (print_mve_size): Likewise.
450 (print_mve_shift_n): Likewise.
451 (print_insn_mve): Likewise.
452
897b9bbc
AV		 4532019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
454 Michael Collison <michael.collison@arm.com>
455
456 * arm-dis.c (enum mve_instructions): Add new instructions.
457 (is_mve_encoding_conflict): Handle new instructions.
458 (is_mve_unpredictable): Likewise.
459 (print_mve_rotate): Likewise.
460 (print_mve_size): Likewise.
461 (print_insn_mve): Likewise.
462
1c8f2df8
AV		 4632019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
464 Michael Collison <michael.collison@arm.com>
465
466 * arm-dis.c (enum mve_instructions): Add new instructions.
467 (is_mve_encoding_conflict): Handle new instructions.
468 (is_mve_unpredictable): Likewise.
469 (print_mve_size): Likewise.
470 (print_insn_mve): Likewise.
471
d3b63143
AV		 4722019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
473 Michael Collison <michael.collison@arm.com>
474
475 * arm-dis.c (enum mve_instructions): Add new instructions.
476 (enum mve_undefined): Add new reasons.
477 (is_mve_encoding_conflict): Handle new instructions.
478 (is_mve_undefined): Likewise.
479 (is_mve_unpredictable): Likewise.
480 (print_mve_undefined): Likewise.
481 (print_mve_size): Likewise.
482 (print_insn_mve): Likewise.
483
14925797
AV		 4842019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
485 Michael Collison <michael.collison@arm.com>
486
487 * arm-dis.c (enum mve_instructions): Add new instructions.
488 (is_mve_encoding_conflict): Handle new instructions.
489 (is_mve_undefined): Likewise.
490 (is_mve_unpredictable): Likewise.
491 (print_mve_size): Likewise.
492 (print_insn_mve): Likewise.
493
c507f10b
AV		 4942019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
495 Michael Collison <michael.collison@arm.com>
496
497 * arm-dis.c (enum mve_instructions): Add new instructions.
498 (enum mve_unpredictable): Add new reasons.
499 (enum mve_undefined): Likewise.
500 (is_mve_okay_in_it): Handle new isntructions.
501 (is_mve_encoding_conflict): Likewise.
502 (is_mve_undefined): Likewise.
503 (is_mve_unpredictable): Likewise.
504 (print_mve_vmov_index): Likewise.
505 (print_simd_imm8): Likewise.
506 (print_mve_undefined): Likewise.
507 (print_mve_unpredictable): Likewise.
508 (print_mve_size): Likewise.
509 (print_insn_mve): Likewise.
510
bf0b396d
AV		 5112019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
512 Michael Collison <michael.collison@arm.com>
513
514 * arm-dis.c (enum mve_instructions): Add new instructions.
515 (enum mve_unpredictable): Add new reasons.
516 (enum mve_undefined): Likewise.
517 (is_mve_encoding_conflict): Handle new instructions.
518 (is_mve_undefined): Likewise.
519 (is_mve_unpredictable): Likewise.
520 (print_mve_undefined): Likewise.
521 (print_mve_unpredictable): Likewise.
522 (print_mve_rounding_mode): Likewise.
523 (print_mve_vcvt_size): Likewise.
524 (print_mve_size): Likewise.
525 (print_insn_mve): Likewise.
526
ef1576a1
AV		 5272019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
528 Michael Collison <michael.collison@arm.com>
529
530 * arm-dis.c (enum mve_instructions): Add new instructions.
531 (enum mve_unpredictable): Add new reasons.
532 (enum mve_undefined): Likewise.
533 (is_mve_undefined): Handle new instructions.
534 (is_mve_unpredictable): Likewise.
535 (print_mve_undefined): Likewise.
536 (print_mve_unpredictable): Likewise.
537 (print_mve_size): Likewise.
538 (print_insn_mve): Likewise.
539
aef6d006
AV		 5402019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
541 Michael Collison <michael.collison@arm.com>
542
543 * arm-dis.c (enum mve_instructions): Add new instructions.
544 (enum mve_undefined): Add new reasons.
545 (insns): Add new instructions.
546 (is_mve_encoding_conflict):
547 (print_mve_vld_str_addr): New print function.
548 (is_mve_undefined): Handle new instructions.
549 (is_mve_unpredictable): Likewise.
550 (print_mve_undefined): Likewise.
551 (print_mve_size): Likewise.
552 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
553 (print_insn_mve): Handle new operands.
554
04d54ace
AV		 5552019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
556 Michael Collison <michael.collison@arm.com>
557
558 * arm-dis.c (enum mve_instructions): Add new instructions.
559 (enum mve_unpredictable): Add new reasons.
560 (is_mve_encoding_conflict): Handle new instructions.
561 (is_mve_unpredictable): Likewise.
562 (mve_opcodes): Add new instructions.
563 (print_mve_unpredictable): Handle new reasons.
564 (print_mve_register_blocks): New print function.
565 (print_mve_size): Handle new instructions.
566 (print_insn_mve): Likewise.
567
9743db03
AV		 5682019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
569 Michael Collison <michael.collison@arm.com>
570
571 * arm-dis.c (enum mve_instructions): Add new instructions.
572 (enum mve_unpredictable): Add new reasons.
573 (enum mve_undefined): Likewise.
574 (is_mve_encoding_conflict): Handle new instructions.
575 (is_mve_undefined): Likewise.
576 (is_mve_unpredictable): Likewise.
577 (coprocessor_opcodes): Move NEON VDUP from here...
578 (neon_opcodes): ... to here.
579 (mve_opcodes): Add new instructions.
580 (print_mve_undefined): Handle new reasons.
581 (print_mve_unpredictable): Likewise.
582 (print_mve_size): Handle new instructions.
583 (print_insn_neon): Handle vdup.
584 (print_insn_mve): Handle new operands.
585
143275ea
AV		 5862019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
587 Michael Collison <michael.collison@arm.com>
588
589 * arm-dis.c (enum mve_instructions): Add new instructions.
590 (enum mve_unpredictable): Add new values.
591 (mve_opcodes): Add new instructions.
592 (vec_condnames): New array with vector conditions.
593 (mve_predicatenames): New array with predicate suffixes.
594 (mve_vec_sizename): New array with vector sizes.
595 (enum vpt_pred_state): New enum with vector predication states.
596 (struct vpt_block): New struct type for vpt blocks.
597 (vpt_block_state): Global struct to keep track of state.
598 (mve_extract_pred_mask): New helper function.
599 (num_instructions_vpt_block): Likewise.
600 (mark_outside_vpt_block): Likewise.
601 (mark_inside_vpt_block): Likewise.
602 (invert_next_predicate_state): Likewise.
603 (update_next_predicate_state): Likewise.
604 (update_vpt_block_state): Likewise.
605 (is_vpt_instruction): Likewise.
606 (is_mve_encoding_conflict): Add entries for new instructions.
607 (is_mve_unpredictable): Likewise.
608 (print_mve_unpredictable): Handle new cases.
609 (print_instruction_predicate): Likewise.
610 (print_mve_size): New function.
611 (print_vec_condition): New function.
612 (print_insn_mve): Handle vpt blocks and new print operands.
613
f08d8ce3
AV		 6142019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
615
616 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
617 8, 14 and 15 for Armv8.1-M Mainline.
618
73cd51e5
AV		 6192019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
620 Michael Collison <michael.collison@arm.com>
621
622 * arm-dis.c (enum mve_instructions): New enum.
623 (enum mve_unpredictable): Likewise.
624 (enum mve_undefined): Likewise.
625 (struct mopcode32): New struct.
626 (is_mve_okay_in_it): New function.
627 (is_mve_architecture): Likewise.
628 (arm_decode_field): Likewise.
629 (arm_decode_field_multiple): Likewise.
630 (is_mve_encoding_conflict): Likewise.
631 (is_mve_undefined): Likewise.
632 (is_mve_unpredictable): Likewise.
633 (print_mve_undefined): Likewise.
634 (print_mve_unpredictable): Likewise.
635 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
636 (print_insn_mve): New function.
637 (print_insn_thumb32): Handle MVE architecture.
638 (select_arm_features): Force thumb for Armv8.1-m Mainline.
639
3076e594
NC		 6402019-05-10 Nick Clifton <nickc@redhat.com>
641
642 PR 24538
643 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
644 end of the table prematurely.
645
387e7624
FS		 6462019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
647
648 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
649 macros for R6.
650
0067be51
AM		 6512019-05-11 Alan Modra <amodra@gmail.com>
652
653 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
654 when -Mraw is in effect.
655
42e6288f
MM		 6562019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
657
658 * aarch64-dis-2.c: Regenerate.
659 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
660 (OP_SVE_BBB): New variant set.
661 (OP_SVE_DDDD): New variant set.
662 (OP_SVE_HHH): New variant set.
663 (OP_SVE_HHHU): New variant set.
664 (OP_SVE_SSS): New variant set.
665 (OP_SVE_SSSU): New variant set.
666 (OP_SVE_SHH): New variant set.
667 (OP_SVE_SBBU): New variant set.
668 (OP_SVE_DSS): New variant set.
669 (OP_SVE_DHHU): New variant set.
670 (OP_SVE_VMV_HSD_BHS): New variant set.
671 (OP_SVE_VVU_HSD_BHS): New variant set.
672 (OP_SVE_VVVU_SD_BH): New variant set.
673 (OP_SVE_VVVU_BHSD): New variant set.
674 (OP_SVE_VVV_QHD_DBS): New variant set.
675 (OP_SVE_VVV_HSD_BHS): New variant set.
676 (OP_SVE_VVV_HSD_BHS2): New variant set.
677 (OP_SVE_VVV_BHS_HSD): New variant set.
678 (OP_SVE_VV_BHS_HSD): New variant set.
679 (OP_SVE_VVV_SD): New variant set.
680 (OP_SVE_VVU_BHS_HSD): New variant set.
681 (OP_SVE_VZVV_SD): New variant set.
682 (OP_SVE_VZVV_BH): New variant set.
683 (OP_SVE_VZV_SD): New variant set.
684 (aarch64_opcode_table): Add sve2 instructions.
685
28ed815a
MM		 6862019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
687
688 * aarch64-asm-2.c: Regenerated.
689 * aarch64-dis-2.c: Regenerated.
690 * aarch64-opc-2.c: Regenerated.
691 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
692 for SVE_SHLIMM_UNPRED_22.
693 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
694 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
695 operand.
696
fd1dc4a0
MM		 6972019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
698
699 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
700 sve_size_tsz_bhs iclass encode.
701 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
702 sve_size_tsz_bhs iclass decode.
703
31e36ab3
MM		 7042019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
705
706 * aarch64-asm-2.c: Regenerated.
707 * aarch64-dis-2.c: Regenerated.
708 * aarch64-opc-2.c: Regenerated.
709 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
710 for SVE_Zm4_11_INDEX.
711 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
712 (fields): Handle SVE_i2h field.
713 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
714 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
715
1be5f94f
MM		 7162019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
717
718 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
719 sve_shift_tsz_bhsd iclass encode.
720 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
721 sve_shift_tsz_bhsd iclass decode.
722
3c17238b
MM		 7232019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
724
725 * aarch64-asm-2.c: Regenerated.
726 * aarch64-dis-2.c: Regenerated.
727 * aarch64-opc-2.c: Regenerated.
728 * aarch64-asm.c (aarch64_ins_sve_shrimm):
729 (aarch64_encode_variant_using_iclass): Handle
730 sve_shift_tsz_hsd iclass encode.
731 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
732 sve_shift_tsz_hsd iclass decode.
733 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
734 for SVE_SHRIMM_UNPRED_22.
735 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
736 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
737 operand.
738
cd50a87a
MM		 7392019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
740
741 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
742 sve_size_013 iclass encode.
743 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
744 sve_size_013 iclass decode.
745
3c705960
MM		 7462019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
747
748 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
749 sve_size_bh iclass encode.
750 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
751 sve_size_bh iclass decode.
752
0a57e14f
MM		 7532019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
754
755 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
756 sve_size_sd2 iclass encode.
757 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
758 sve_size_sd2 iclass decode.
759 * aarch64-opc.c (fields): Handle SVE_sz2 field.
760 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
761
c469c864
MM		 7622019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
763
764 * aarch64-asm-2.c: Regenerated.
765 * aarch64-dis-2.c: Regenerated.
766 * aarch64-opc-2.c: Regenerated.
767 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
768 for SVE_ADDR_ZX.
769 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
770 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
771
116adc27
MM		 7722019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
773
774 * aarch64-asm-2.c: Regenerated.
775 * aarch64-dis-2.c: Regenerated.
776 * aarch64-opc-2.c: Regenerated.
777 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
778 for SVE_Zm3_11_INDEX.
779 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
780 (fields): Handle SVE_i3l and SVE_i3h2 fields.
781 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
782 fields.
783 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
784
3bd82c86
MM		 7852019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
786
787 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
788 sve_size_hsd2 iclass encode.
789 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
790 sve_size_hsd2 iclass decode.
791 * aarch64-opc.c (fields): Handle SVE_size field.
792 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
793
adccc507
MM		 7942019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
795
796 * aarch64-asm-2.c: Regenerated.
797 * aarch64-dis-2.c: Regenerated.
798 * aarch64-opc-2.c: Regenerated.
799 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
800 for SVE_IMM_ROT3.
801 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
802 (fields): Handle SVE_rot3 field.
803 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
804 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
805
5cd99750
MM		 8062019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
807
808 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
809 instructions.
810
7ce2460a
MM		 8112019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
812
813 * aarch64-tbl.h
814 (aarch64_feature_sve2, aarch64_feature_sve2aes,
815 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
816 aarch64_feature_sve2bitperm): New feature sets.
817 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
818 for feature set addresses.
819 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
820 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
821
41cee089
FS		 8222019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
823 Faraz Shahbazker <fshahbazker@wavecomp.com>
824
825 * mips-dis.c (mips_calculate_combination_ases): Add ISA
826 argument and set ASE_EVA_R6 appropriately.
827 (set_default_mips_dis_options): Pass ISA to above.
828 (parse_mips_dis_option): Likewise.
829 * mips-opc.c (EVAR6): New macro.
830 (mips_builtin_opcodes): Add llwpe, scwpe.
831
b83b4b13
SD		 8322019-05-01 Sudakshina Das <sudi.das@arm.com>
833
834 * aarch64-asm-2.c: Regenerated.
835 * aarch64-dis-2.c: Regenerated.
836 * aarch64-opc-2.c: Regenerated.
837 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
838 AARCH64_OPND_TME_UIMM16.
839 (aarch64_print_operand): Likewise.
840 * aarch64-tbl.h (QL_IMM_NIL): New.
841 (TME): New.
842 (_TME_INSN): New.
843 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
844
4a90ce95
JD		 8452019-04-29 John Darrington <john@darrington.wattle.id.au>
846
847 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
848
a45328b9
AB		 8492019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
850 Faraz Shahbazker <fshahbazker@wavecomp.com>
851
852 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
853
d10be0cb
JD		 8542019-04-24 John Darrington <john@darrington.wattle.id.au>
855
856 * s12z-opc.h: Add extern "C" bracketing to help
857 users who wish to use this interface in c++ code.
858
a679f24e
JD		 8592019-04-24 John Darrington <john@darrington.wattle.id.au>
860
861 * s12z-opc.c (bm_decode): Handle bit map operations with the
862 "reserved0" mode.
863
32c36c3c
AV		 8642019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
865
866 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
867 specifier. Add entries for VLDR and VSTR of system registers.
868 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
869 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
870 of %J and %K format specifier.
871
efd6b359
AV		 8722019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
873
874 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
875 Add new entries for VSCCLRM instruction.
876 (print_insn_coprocessor): Handle new %C format control code.
877
6b0dd094
AV		 8782019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
879
880 * arm-dis.c (enum isa): New enum.
881 (struct sopcode32): New structure.
882 (coprocessor_opcodes): change type of entries to struct sopcode32 and
883 set isa field of all current entries to ANY.
884 (print_insn_coprocessor): Change type of insn to struct sopcode32.
885 Only match an entry if its isa field allows the current mode.
886
4b5a202f
AV		 8872019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
888
889 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
890 CLRM.
891 (print_insn_thumb32): Add logic to print %n CLRM register list.
892
60f993ce
AV		 8932019-04-15 Sudakshina Das <sudi.das@arm.com>
894
895 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
896 and %Q patterns.
897
f6b2b12d
AV		 8982019-04-15 Sudakshina Das <sudi.das@arm.com>
899
900 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
901 (print_insn_thumb32): Edit the switch case for %Z.
902
1889da70
AV		 9032019-04-15 Sudakshina Das <sudi.das@arm.com>
904
905 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
906
65d1bc05
AV		 9072019-04-15 Sudakshina Das <sudi.das@arm.com>
908
909 * arm-dis.c (thumb32_opcodes): New instruction bfl.
910
1caf72a5
AV		 9112019-04-15 Sudakshina Das <sudi.das@arm.com>
912
913 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
914
f1c7f421
AV		 9152019-04-15 Sudakshina Das <sudi.das@arm.com>
916
917 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
918 Arm register with r13 and r15 unpredictable.
919 (thumb32_opcodes): New instructions for bfx and bflx.
920
4389b29a
AV		 9212019-04-15 Sudakshina Das <sudi.das@arm.com>
922
923 * arm-dis.c (thumb32_opcodes): New instructions for bf.
924
e5d6e09e
AV		 9252019-04-15 Sudakshina Das <sudi.das@arm.com>
926
927 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
928
e12437dc
AV		 9292019-04-15 Sudakshina Das <sudi.das@arm.com>
930
931 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
932
031254f2
AV		 9332019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
934
935 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
936
e5a557ac
JD		 9372019-04-12 John Darrington <john@darrington.wattle.id.au>
938
939 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
940 "optr". ("operator" is a reserved word in c++).
941
bd7ceb8d
SD		 9422019-04-11 Sudakshina Das <sudi.das@arm.com>
943
944 * aarch64-opc.c (aarch64_print_operand): Add case for
945 AARCH64_OPND_Rt_SP.
946 (verify_constraints): Likewise.
947 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
948 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
949 to accept Rt|SP as first operand.
950 (AARCH64_OPERANDS): Add new Rt_SP.
951 * aarch64-asm-2.c: Regenerated.
952 * aarch64-dis-2.c: Regenerated.
953 * aarch64-opc-2.c: Regenerated.
954
e54010f1
SD		 9552019-04-11 Sudakshina Das <sudi.das@arm.com>
956
957 * aarch64-asm-2.c: Regenerated.
958 * aarch64-dis-2.c: Likewise.
959 * aarch64-opc-2.c: Likewise.
960 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
961
7e96e219
RS		 9622019-04-09 Robert Suchanek <robert.suchanek@mips.com>
963
964 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
965
6f2791d5
L		 9662019-04-08 H.J. Lu <hongjiu.lu@intel.com>
967
968 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
969 * i386-init.h: Regenerated.
970
e392bad3
AM		 9712019-04-07 Alan Modra <amodra@gmail.com>
972
973 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
974 op_separator to control printing of spaces, comma and parens
975 rather than need_comma, need_paren and spaces vars.
976
dffaa15c
AM		 9772019-04-07 Alan Modra <amodra@gmail.com>
978
979 PR 24421
980 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
981 (print_insn_neon, print_insn_arm): Likewise.
982
d6aab7a1
XG		 9832019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
984
985 * i386-dis-evex.h (evex_table): Updated to support BF16
986 instructions.
987 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
988 and EVEX_W_0F3872_P_3.
989 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
990 (cpu_flags): Add bitfield for CpuAVX512_BF16.
991 * i386-opc.h (enum): Add CpuAVX512_BF16.
992 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
993 * i386-opc.tbl: Add AVX512 BF16 instructions.
994 * i386-init.h: Regenerated.
995 * i386-tbl.h: Likewise.
996
66e85460
AM		 9972019-04-05 Alan Modra <amodra@gmail.com>
998
999 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1000 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1001 to favour printing of "-" branch hint when using the "y" bit.
1002 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1003
c2b1c275
AM		 10042019-04-05 Alan Modra <amodra@gmail.com>
1005
1006 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1007 opcode until first operand is output.
1008
aae9718e
PB		 10092019-04-04 Peter Bergner <bergner@linux.ibm.com>
1010
1011 PR gas/24349
1012 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1013 (valid_bo_post_v2): Add support for 'at' branch hints.
1014 (insert_bo): Only error on branch on ctr.
1015 (get_bo_hint_mask): New function.
1016 (insert_boe): Add new 'branch_taken' formal argument. Add support
1017 for inserting 'at' branch hints.
1018 (extract_boe): Add new 'branch_taken' formal argument. Add support
1019 for extracting 'at' branch hints.
1020 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1021 (BOE): Delete operand.
1022 (BOM, BOP): New operands.
1023 (RM): Update value.
1024 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1025 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1026 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1027 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1028 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1029 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1030 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1031 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1032 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1033 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1034 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1035 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1036 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1037 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1038 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1039 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1040 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1041 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1042 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1043 bttarl+>: New extended mnemonics.
1044
96a86c01
AM		 10452019-03-28 Alan Modra <amodra@gmail.com>
1046
1047 PR 24390
1048 * ppc-opc.c (BTF): Define.
1049 (powerpc_opcodes): Use for mtfsb*.
1050 * ppc-dis.c (print_insn_powerpc): Print fields with both
1051 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1052
796d6298
TC		 10532019-03-25 Tamar Christina <tamar.christina@arm.com>
1054
1055 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1056 (mapping_symbol_for_insn): Implement new algorithm.
1057 (print_insn): Remove duplicate code.
1058
60df3720
TC		 10592019-03-25 Tamar Christina <tamar.christina@arm.com>
1060
1061 * aarch64-dis.c (print_insn_aarch64):
1062 Implement override.
1063
51457761
TC		 10642019-03-25 Tamar Christina <tamar.christina@arm.com>
1065
1066 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1067 order.
1068
53b2f36b
TC		 10692019-03-25 Tamar Christina <tamar.christina@arm.com>
1070
1071 * aarch64-dis.c (last_stop_offset): New.
1072 (print_insn_aarch64): Use stop_offset.
1073
89199bb5
L		 10742019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1075
1076 PR gas/24359
1077 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1078 CPU_ANY_AVX2_FLAGS.
1079 * i386-init.h: Regenerated.
1080
97ed31ae
L		 10812019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1082
1083 PR gas/24348
1084 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1085 vmovdqu16, vmovdqu32 and vmovdqu64.
1086 * i386-tbl.h: Regenerated.
1087
0919bfe9
AK		 10882019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1089
1090 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1091 from vstrszb, vstrszh, and vstrszf.
1092
10932019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1094
1095 * s390-opc.txt: Add instruction descriptions.
1096
21820ebe
JW		 10972019-02-08 Jim Wilson <jimw@sifive.com>
1098
1099 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1100 <bne>: Likewise.
1101
f7dd2fb2
TC		 11022019-02-07 Tamar Christina <tamar.christina@arm.com>
1103
1104 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1105
6456d318
TC		 11062019-02-07 Tamar Christina <tamar.christina@arm.com>
1107
1108 PR binutils/23212
1109 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1110 * aarch64-opc.c (verify_elem_sd): New.
1111 (fields): Add FLD_sz entr.
1112 * aarch64-tbl.h (_SIMD_INSN): New.
1113 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1114 fmulx scalar and vector by element isns.
1115
4a83b610
NC		 11162019-02-07 Nick Clifton <nickc@redhat.com>
1117
1118 * po/sv.po: Updated Swedish translation.
1119
fc60b8c8
AK		 11202019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1121
1122 * s390-mkopc.c (main): Accept arch13 as cpu string.
1123 * s390-opc.c: Add new instruction formats and instruction opcode
1124 masks.
1125 * s390-opc.txt: Add new arch13 instructions.
1126
e10620d3
TC		 11272019-01-25 Sudakshina Das <sudi.das@arm.com>
1128
1129 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1130 (aarch64_opcode): Change encoding for stg, stzg
1131 st2g and st2zg.
1132 * aarch64-asm-2.c: Regenerated.
1133 * aarch64-dis-2.c: Regenerated.
1134 * aarch64-opc-2.c: Regenerated.
1135
20a4ca55
SD		 11362019-01-25 Sudakshina Das <sudi.das@arm.com>
1137
1138 * aarch64-asm-2.c: Regenerated.
1139 * aarch64-dis-2.c: Likewise.
1140 * aarch64-opc-2.c: Likewise.
1141 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1142
550fd7bf
SD		 11432019-01-25 Sudakshina Das <sudi.das@arm.com>
1144 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1145
1146 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1147 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1148 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1149 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1150 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1151 case for ldstgv_indexed.
1152 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1153 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1154 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1155 * aarch64-asm-2.c: Regenerated.
1156 * aarch64-dis-2.c: Regenerated.
1157 * aarch64-opc-2.c: Regenerated.
1158
d9938630
NC		 11592019-01-23 Nick Clifton <nickc@redhat.com>
1160
1161 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1162
375cd423
NC		 11632019-01-21 Nick Clifton <nickc@redhat.com>
1164
1165 * po/de.po: Updated German translation.
1166 * po/uk.po: Updated Ukranian translation.
1167
57299f48
CX		 11682019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1169 * mips-dis.c (mips_arch_choices): Fix typo in
1170 gs464, gs464e and gs264e descriptors.
1171
f48dfe41
NC		 11722019-01-19 Nick Clifton <nickc@redhat.com>
1173
1174 * configure: Regenerate.
1175 * po/opcodes.pot: Regenerate.
1176
f974f26c
NC		 11772018-06-24 Nick Clifton <nickc@redhat.com>
1178
1179 2.32 branch created.
1180
39f286cd
JD		 11812019-01-09 John Darrington <john@darrington.wattle.id.au>
1182
448b8ca8
JD		 1183 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1184 if it is null.
1185 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 1186 zero.
1187
3107326d
AP		 11882019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1189
1190 * configure: Regenerate.
1191
7e9ca91e
AM		 11922019-01-07 Alan Modra <amodra@gmail.com>
1193
1194 * configure: Regenerate.
1195 * po/POTFILES.in: Regenerate.
1196
ef1ad42b
JD		 11972019-01-03 John Darrington <john@darrington.wattle.id.au>
1198
1199 * s12z-opc.c: New file.
1200 * s12z-opc.h: New file.
1201 * s12z-dis.c: Removed all code not directly related to display
1202 of instructions. Used the interface provided by the new files
1203 instead.
1204 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 1205 * Makefile.in: Regenerate.
ef1ad42b 1206 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 1207 * configure: Regenerate.
ef1ad42b 1208
82704155
AM		 12092019-01-01 Alan Modra <amodra@gmail.com>
1210
1211 Update year range in copyright notice of all files.
1212
d5c04e1b 1213For older changes see ChangeLog-2018
3499769a 1214\f
d5c04e1b 1215Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 1216
1217Copying and distribution of this file, with or without modification,
1218are permitted in any medium without royalty provided the copyright
1219notice and this notice are preserved.
1220
1221Local Variables:
1222mode: change-log
1223left-margin: 8
1224fill-column: 74
1225version-control: never
1226End:
GDB Binutils - Deliverables
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