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x86: slightly rearrange struct insn_template
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
a2cebd03
JB		 12019-10-30 Jan Beulich <jbeulich@suse.com>
2
3 * i386-gen.c (output_i386_opcode): Change order of fields
4 emitted to output.
5 * i386-opc.h (struct insn_template): Move operands field.
6 Convert extension_opcode field to unsigned short.
7 * i386-tbl.h: Re-generate.
8
507916b8
JB		 92019-10-30 Jan Beulich <jbeulich@suse.com>
10
11 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
12 of W.
13 * i386-opc.h (W): Extend comment.
14 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
15 general purpose variants not allowing for byte operands.
16 * i386-tbl.h: Re-generate.
17
efea62b4
NC		 182019-10-29 Nick Clifton <nickc@redhat.com>
19
20 * tic30-dis.c (print_branch): Correct size of operand array.
21
9adb2591
NC		 222019-10-29 Nick Clifton <nickc@redhat.com>
23
24 * d30v-dis.c (print_insn): Check that operand index is valid
25 before attempting to access the operands array.
26
993a00a9
NC		 272019-10-29 Nick Clifton <nickc@redhat.com>
28
29 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
30 locating the bit to be tested.
31
66a66a17
NC		 322019-10-29 Nick Clifton <nickc@redhat.com>
33
34 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
35 values.
36 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
37 (print_insn_s12z): Check for illegal size values.
38
1ee3542c
NC		 392019-10-28 Nick Clifton <nickc@redhat.com>
40
41 * csky-dis.c (csky_chars_to_number): Check for a negative
42 count. Use an unsigned integer to construct the return value.
43
bbf9a0b5
NC		 442019-10-28 Nick Clifton <nickc@redhat.com>
45
46 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
47 operand buffer. Set value to 15 not 13.
48 (get_register_operand): Use OPERAND_BUFFER_LEN.
49 (get_indirect_operand): Likewise.
50 (print_two_operand): Likewise.
51 (print_three_operand): Likewise.
52 (print_oar_insn): Likewise.
53
d1e304bc
NC		 542019-10-28 Nick Clifton <nickc@redhat.com>
55
56 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
57 (bit_extract_simple): Likewise.
58 (bit_copy): Likewise.
59 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
60 index_offset array are not accessed.
61
dee33451
NC		 622019-10-28 Nick Clifton <nickc@redhat.com>
63
64 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
65 operand.
66
27cee81d
NC		 672019-10-25 Nick Clifton <nickc@redhat.com>
68
69 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
70 access to opcodes.op array element.
71
de6d8dc2
NC		 722019-10-23 Nick Clifton <nickc@redhat.com>
73
74 * rx-dis.c (get_register_name): Fix spelling typo in error
75 message.
76 (get_condition_name, get_flag_name, get_double_register_name)
77 (get_double_register_high_name, get_double_register_low_name)
78 (get_double_control_register_name, get_double_condition_name)
79 (get_opsize_name, get_size_name): Likewise.
80
6207ed28
NC		 812019-10-22 Nick Clifton <nickc@redhat.com>
82
83 * rx-dis.c (get_size_name): New function. Provides safe
84 access to name array.
85 (get_opsize_name): Likewise.
86 (print_insn_rx): Use the accessor functions.
87
12234dfd
NC		 882019-10-16 Nick Clifton <nickc@redhat.com>
89
90 * rx-dis.c (get_register_name): New function. Provides safe
91 access to name array.
92 (get_condition_name, get_flag_name, get_double_register_name)
93 (get_double_register_high_name, get_double_register_low_name)
94 (get_double_control_register_name, get_double_condition_name):
95 Likewise.
96 (print_insn_rx): Use the accessor functions.
97
1d378749
NC		 982019-10-09 Nick Clifton <nickc@redhat.com>
99
100 PR 25041
101 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
102 instructions.
103
d241b910
JB		 1042019-10-07 Jan Beulich <jbeulich@suse.com>
105
106 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
107 (cmpsd): Likewise. Move EsSeg to other operand.
108 * opcodes/i386-tbl.h: Re-generate.
109
f5c5b7c1
AM		 1102019-09-23 Alan Modra <amodra@gmail.com>
111
112 * m68k-dis.c: Include cpu-m68k.h
113
7beeaeb8
AM		 1142019-09-23 Alan Modra <amodra@gmail.com>
115
116 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
117 "elf/mips.h" earlier.
118
3f9aad11
JB		 1192018-09-20 Jan Beulich <jbeulich@suse.com>
120
121 PR gas/25012
122 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
123 with SReg operand.
124 * i386-tbl.h: Re-generate.
125
fd361982
AM		 1262019-09-18 Alan Modra <amodra@gmail.com>
127
128 * arc-ext.c: Update throughout for bfd section macro changes.
129
e0b2a78c
SM		 1302019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
131
132 * Makefile.in: Re-generate.
133 * configure: Re-generate.
134
7e9ad3a3
JW		 1352019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
136
137 * riscv-opc.c (riscv_opcodes): Change subset field
138 to insn_class field for all instructions.
139 (riscv_insn_types): Likewise.
140
bb695960
PB		 1412019-09-16 Phil Blundell <pb@pbcl.net>
142
143 * configure: Regenerated.
144
8063ab7e
MV		 1452019-09-10 Miod Vallat <miod@online.fr>
146
147 PR 24982
148 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
149
60391a25
PB		 1502019-09-09 Phil Blundell <pb@pbcl.net>
151
152 binutils 2.33 branch created.
153
f44b758d
NC		 1542019-09-03 Nick Clifton <nickc@redhat.com>
155
156 PR 24961
157 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
158 greater than zero before indexing via (bufcnt -1).
159
1e4b5e7d
NC		 1602019-09-03 Nick Clifton <nickc@redhat.com>
161
162 PR 24958
163 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
164 (MAX_SPEC_REG_NAME_LEN): Define.
165 (struct mmix_dis_info): Use defined constants for array lengths.
166 (get_reg_name): New function.
167 (get_sprec_reg_name): New function.
168 (print_insn_mmix): Use new functions.
169
c4a23bf8
SP		 1702019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
171
172 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
173 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
174 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
175
a051e2f3
KT		 1762019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
177
178 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
179 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
180 (aarch64_sys_reg_supported_p): Update checks for the above.
181
08132bdd
SP		 1822019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
183
184 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
185 cases MVE_SQRSHRL and MVE_UQRSHLL.
186 (print_insn_mve): Add case for specifier 'k' to check
187 specific bit of the instruction.
188
d88bdcb4
PA		 1892019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
190
191 PR 24854
192 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
193 encountering an unknown machine type.
194 (print_insn_arc): Handle arc_insn_length returning 0. In error
195 cases return -1 rather than calling abort.
196
bc750500
JB		 1972019-08-07 Jan Beulich <jbeulich@suse.com>
198
199 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
200 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
201 IgnoreSize.
202 * i386-tbl.h: Re-generate.
203
23d188c7
BW		 2042019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
205
206 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
207 instructions.
208
c0d6f62f
JW		 2092019-07-30 Mel Chen <mel.chen@sifive.com>
210
211 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
212 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
213
214 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
215 fscsr.
216
0f3f7167
CZ		 2172019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
218
219 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
220 and MPY class instructions.
221 (parse_option): Add nps400 option.
222 (print_arc_disassembler_options): Add nps400 info.
223
7e126ba3
CZ		 2242019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
225
226 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
227 (bspop): Likewise.
228 (modapp): Likewise.
229 * arc-opc.c (RAD_CHK): Add.
230 * arc-tbl.h: Regenerate.
231
a028026d
KT		 2322019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
233
234 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
235 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
236
ac79ff9e
NC		 2372019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
238
239 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
240 instructions as UNPREDICTABLE.
241
231097b0
JM		 2422019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
243
244 * bpf-desc.c: Regenerated.
245
1d942ae9
JB		 2462019-07-17 Jan Beulich <jbeulich@suse.com>
247
248 * i386-gen.c (static_assert): Define.
249 (main): Use it.
250 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
251 (Opcode_Modifier_Num): ... this.
252 (Mem): Delete.
253
dfd69174
JB		 2542019-07-16 Jan Beulich <jbeulich@suse.com>
255
256 * i386-gen.c (operand_types): Move RegMem ...
257 (opcode_modifiers): ... here.
258 * i386-opc.h (RegMem): Move to opcode modifer enum.
259 (union i386_operand_type): Move regmem field ...
260 (struct i386_opcode_modifier): ... here.
261 * i386-opc.tbl (RegMem): Define.
262 (mov, movq): Move RegMem on segment, control, debug, and test
263 register flavors.
264 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
265 to non-SSE2AVX flavor.
266 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
267 Move RegMem on register only flavors. Drop IgnoreSize from
268 legacy encoding flavors.
269 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
270 flavors.
271 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
272 register only flavors.
273 (vmovd): Move RegMem and drop IgnoreSize on register only
274 flavor. Change opcode and operand order to store form.
275 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
276
21df382b
JB		 2772019-07-16 Jan Beulich <jbeulich@suse.com>
278
279 * i386-gen.c (operand_type_init, operand_types): Replace SReg
280 entries.
281 * i386-opc.h (SReg2, SReg3): Replace by ...
282 (SReg): ... this.
283 (union i386_operand_type): Replace sreg fields.
284 * i386-opc.tbl (mov, ): Use SReg.
285 (push, pop): Likewies. Drop i386 and x86-64 specific segment
286 register flavors.
287 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
288 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
289
3719fd55
JM		 2902019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
291
292 * bpf-desc.c: Regenerate.
293 * bpf-opc.c: Likewise.
294 * bpf-opc.h: Likewise.
295
92434a14
JM		 2962019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
297
298 * bpf-desc.c: Regenerate.
299 * bpf-opc.c: Likewise.
300
43dd7626
HPN		 3012019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
302
303 * arm-dis.c (print_insn_coprocessor): Rename index to
304 index_operand.
305
98602811
JW		 3062019-07-05 Kito Cheng <kito.cheng@sifive.com>
307
308 * riscv-opc.c (riscv_insn_types): Add r4 type.
309
310 * riscv-opc.c (riscv_insn_types): Add b and j type.
311
312 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
313 format for sb type and correct s type.
314
01c1ee4a
RS		 3152019-07-02 Richard Sandiford <richard.sandiford@arm.com>
316
317 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
318 SVE FMOV alias of FCPY.
319
83adff69
RS		 3202019-07-02 Richard Sandiford <richard.sandiford@arm.com>
321
322 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
323 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
324
89418844
RS		 3252019-07-02 Richard Sandiford <richard.sandiford@arm.com>
326
327 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
328 registers in an instruction prefixed by MOVPRFX.
329
41be57ca
MM		 3302019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
331
332 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
333 sve_size_13 icode to account for variant behaviour of
334 pmull{t,b}.
335 * aarch64-dis-2.c: Regenerate.
336 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
337 sve_size_13 icode to account for variant behaviour of
338 pmull{t,b}.
339 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
340 (OP_SVE_VVV_Q_D): Add new qualifier.
341 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
342 (struct aarch64_opcode): Split pmull{t,b} into those requiring
343 AES and those not.
344
9d3bf266
JB		 3452019-07-01 Jan Beulich <jbeulich@suse.com>
346
347 * opcodes/i386-gen.c (operand_type_init): Remove
348 OPERAND_TYPE_VEC_IMM4 entry.
349 (operand_types): Remove Vec_Imm4.
350 * opcodes/i386-opc.h (Vec_Imm4): Delete.
351 (union i386_operand_type): Remove vec_imm4.
352 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
353 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
354
c3949f43
JB		 3552019-07-01 Jan Beulich <jbeulich@suse.com>
356
357 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
358 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
359 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
360 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
361 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
362 monitorx, mwaitx): Drop ImmExt from operand-less forms.
363 * i386-tbl.h: Re-generate.
364
5641ec01
JB		 3652019-07-01 Jan Beulich <jbeulich@suse.com>
366
367 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
368 register operands.
369 * i386-tbl.h: Re-generate.
370
79dec6b7
JB		 3712019-07-01 Jan Beulich <jbeulich@suse.com>
372
373 * i386-opc.tbl (C): New.
374 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
375 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
376 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
377 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
378 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
379 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
380 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
381 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
382 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
383 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
384 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
385 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
386 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
387 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
388 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
389 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
390 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
391 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
392 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
393 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
394 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
395 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
396 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
397 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
398 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
399 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
400 flavors.
401 * i386-tbl.h: Re-generate.
402
a0a1771e
JB		 4032019-07-01 Jan Beulich <jbeulich@suse.com>
404
405 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
406 register operands.
407 * i386-tbl.h: Re-generate.
408
cd546e7b
JB		 4092019-07-01 Jan Beulich <jbeulich@suse.com>
410
411 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
412 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
413 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
414 * i386-tbl.h: Re-generate.
415
e3bba3fc
JB		 4162019-07-01 Jan Beulich <jbeulich@suse.com>
417
418 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
419 Disp8MemShift from register only templates.
420 * i386-tbl.h: Re-generate.
421
36cc073e
JB		 4222019-07-01 Jan Beulich <jbeulich@suse.com>
423
424 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
425 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
426 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
427 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
428 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
429 EVEX_W_0F11_P_3_M_1): Delete.
430 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
431 EVEX_W_0F11_P_3): New.
432 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
433 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
434 MOD_EVEX_0F11_PREFIX_3 table entries.
435 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
436 PREFIX_EVEX_0F11 table entries.
437 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
438 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
439 EVEX_W_0F11_P_3_M_{0,1} table entries.
440
219920a7
JB		 4412019-07-01 Jan Beulich <jbeulich@suse.com>
442
443 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
444 Delete.
445
e395f487
L		 4462019-06-27 H.J. Lu <hongjiu.lu@intel.com>
447
448 PR binutils/24719
449 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
450 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
451 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
452 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
453 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
454 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
455 EVEX_LEN_0F38C7_R_6_P_2_W_1.
456 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
457 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
458 PREFIX_EVEX_0F38C6_REG_6 entries.
459 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
460 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
461 EVEX_W_0F38C7_R_6_P_2 entries.
462 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
463 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
464 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
465 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
466 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
467 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
468 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
469
2b7bcc87
JB		 4702019-06-27 Jan Beulich <jbeulich@suse.com>
471
472 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
473 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
474 VEX_LEN_0F2D_P_3): Delete.
475 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
476 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
477 (prefix_table): ... here.
478
c1dc7af5
JB		 4792019-06-27 Jan Beulich <jbeulich@suse.com>
480
481 * i386-dis.c (Iq): Delete.
482 (Id): New.
483 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
484 TBM insns.
485 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
486 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
487 (OP_E_memory): Also honor needindex when deciding whether an
488 address size prefix needs printing.
489 (OP_I): Remove handling of q_mode. Add handling of d_mode.
490
d7560e2d
JW		 4912019-06-26 Jim Wilson <jimw@sifive.com>
492
493 PR binutils/24739
494 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
495 Set info->display_endian to info->endian_code.
496
2c703856
JB		 4972019-06-25 Jan Beulich <jbeulich@suse.com>
498
499 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
500 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
501 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
502 OPERAND_TYPE_ACC64 entries.
503 * i386-init.h: Re-generate.
504
54fbadc0
JB		 5052019-06-25 Jan Beulich <jbeulich@suse.com>
506
507 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
508 Delete.
509 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
510 of dqa_mode.
511 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
512 entries here.
513 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
514 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
515
a280ab8e
JB		 5162019-06-25 Jan Beulich <jbeulich@suse.com>
517
518 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
519 variables.
520
e1a1babd
JB		 5212019-06-25 Jan Beulich <jbeulich@suse.com>
522
523 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
524 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
525 movnti.
d7560e2d 526 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 527 * i386-tbl.h: Re-generate.
528
b8364fa7
JB		 5292019-06-25 Jan Beulich <jbeulich@suse.com>
530
531 * i386-opc.tbl (and): Mark Imm8S form for optimization.
532 * i386-tbl.h: Re-generate.
533
ad692897
L		 5342019-06-21 H.J. Lu <hongjiu.lu@intel.com>
535
536 * i386-dis-evex.h: Break into ...
537 * i386-dis-evex-len.h: New file.
538 * i386-dis-evex-mod.h: Likewise.
539 * i386-dis-evex-prefix.h: Likewise.
540 * i386-dis-evex-reg.h: Likewise.
541 * i386-dis-evex-w.h: Likewise.
542 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
543 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
544 i386-dis-evex-mod.h.
545
f0a6222e
L		 5462019-06-19 H.J. Lu <hongjiu.lu@intel.com>
547
548 PR binutils/24700
549 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
550 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
551 EVEX_W_0F385B_P_2.
552 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
553 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
554 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
555 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
556 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
557 EVEX_LEN_0F385B_P_2_W_1.
558 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
559 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
560 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
561 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
562 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
563 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
564 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
565 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
566 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
567 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
568
6e1c90b7
L		 5692019-06-17 H.J. Lu <hongjiu.lu@intel.com>
570
571 PR binutils/24691
572 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
573 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
574 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
575 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
576 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
577 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
578 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
579 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
580 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
581 EVEX_LEN_0F3A43_P_2_W_1.
582 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
583 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
584 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
585 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
586 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
587 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
588 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
589 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
590 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
591 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
592 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
593 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
594
bcc5a6eb
NC		 5952019-06-14 Nick Clifton <nickc@redhat.com>
596
597 * po/fr.po; Updated French translation.
598
e4c4ac46
SH		 5992019-06-13 Stafford Horne <shorne@gmail.com>
600
601 * or1k-asm.c: Regenerated.
602 * or1k-desc.c: Regenerated.
603 * or1k-desc.h: Regenerated.
604 * or1k-dis.c: Regenerated.
605 * or1k-ibld.c: Regenerated.
606 * or1k-opc.c: Regenerated.
607 * or1k-opc.h: Regenerated.
608 * or1k-opinst.c: Regenerated.
609
a0e44ef5
PB		 6102019-06-12 Peter Bergner <bergner@linux.ibm.com>
611
612 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
613
12efd68d
L		 6142019-06-05 H.J. Lu <hongjiu.lu@intel.com>
615
616 PR binutils/24633
617 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
618 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
619 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
620 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
621 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
622 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
623 EVEX_LEN_0F3A1B_P_2_W_1.
624 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
625 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
626 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
627 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
628 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
629 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
630 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
631 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
632
63c6fc6c
L		 6332019-06-04 H.J. Lu <hongjiu.lu@intel.com>
634
635 PR binutils/24626
636 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
637 EVEX.vvvv when disassembling VEX and EVEX instructions.
638 (OP_VEX): Set vex.register_specifier to 0 after readding
639 vex.register_specifier.
640 (OP_Vex_2src_1): Likewise.
641 (OP_Vex_2src_2): Likewise.
642 (OP_LWP_E): Likewise.
643 (OP_EX_Vex): Don't check vex.register_specifier.
644 (OP_XMM_Vex): Likewise.
645
9186c494
L		 6462019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
647 Lili Cui <lili.cui@intel.com>
648
649 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
650 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
651 instructions.
652 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
653 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
654 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
655 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
656 (i386_cpu_flags): Add cpuavx512_vp2intersect.
657 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
658 * i386-init.h: Regenerated.
659 * i386-tbl.h: Likewise.
660
5d79adc4
L		 6612019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
662 Lili Cui <lili.cui@intel.com>
663
664 * doc/c-i386.texi: Document enqcmd.
665 * testsuite/gas/i386/enqcmd-intel.d: New file.
666 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
667 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
668 * testsuite/gas/i386/enqcmd.d: Likewise.
669 * testsuite/gas/i386/enqcmd.s: Likewise.
670 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
671 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
672 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
673 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
674 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
675 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
676 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
677 and x86-64-enqcmd.
678
a9d96ab9
AH		 6792019-06-04 Alan Hayward <alan.hayward@arm.com>
680
681 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
682
4f6d070a
AM		 6832019-06-03 Alan Modra <amodra@gmail.com>
684
685 * ppc-dis.c (prefix_opcd_indices): Correct size.
686
a2f4b66c
L		 6872019-05-28 H.J. Lu <hongjiu.lu@intel.com>
688
689 PR gas/24625
690 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
691 Disp8ShiftVL.
692 * i386-tbl.h: Regenerated.
693
405b5bd8
AM		 6942019-05-24 Alan Modra <amodra@gmail.com>
695
696 * po/POTFILES.in: Regenerate.
697
8acf1435
PB		 6982019-05-24 Peter Bergner <bergner@linux.ibm.com>
699 Alan Modra <amodra@gmail.com>
700
701 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
702 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
703 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
704 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
705 XTOP>): Define and add entries.
706 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
707 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
708 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
709 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
710
dd7efa79
PB		 7112019-05-24 Peter Bergner <bergner@linux.ibm.com>
712 Alan Modra <amodra@gmail.com>
713
714 * ppc-dis.c (ppc_opts): Add "future" entry.
715 (PREFIX_OPCD_SEGS): Define.
716 (prefix_opcd_indices): New array.
717 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
718 (lookup_prefix): New function.
719 (print_insn_powerpc): Handle 64-bit prefix instructions.
720 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
721 (PMRR, POWERXX): Define.
722 (prefix_opcodes): New instruction table.
723 (prefix_num_opcodes): New constant.
724
79472b45
JM		 7252019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
726
727 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
728 * configure: Regenerated.
729 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
730 and cpu/bpf.opc.
731 (HFILES): Add bpf-desc.h and bpf-opc.h.
732 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
733 bpf-ibld.c and bpf-opc.c.
734 (BPF_DEPS): Define.
735 * Makefile.in: Regenerated.
736 * disassemble.c (ARCH_bpf): Define.
737 (disassembler): Add case for bfd_arch_bpf.
738 (disassemble_init_for_target): Likewise.
739 (enum epbf_isa_attr): Define.
740 * disassemble.h: extern print_insn_bpf.
741 * bpf-asm.c: Generated.
742 * bpf-opc.h: Likewise.
743 * bpf-opc.c: Likewise.
744 * bpf-ibld.c: Likewise.
745 * bpf-dis.c: Likewise.
746 * bpf-desc.h: Likewise.
747 * bpf-desc.c: Likewise.
748
ba6cd17f
SD		 7492019-05-21 Sudakshina Das <sudi.das@arm.com>
750
751 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
752 and VMSR with the new operands.
753
e39c1607
SD		 7542019-05-21 Sudakshina Das <sudi.das@arm.com>
755
756 * arm-dis.c (enum mve_instructions): New enum
757 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
758 and cneg.
759 (mve_opcodes): New instructions as above.
760 (is_mve_encoding_conflict): Add cases for csinc, csinv,
761 csneg and csel.
762 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
763
23d00a41
SD		 7642019-05-21 Sudakshina Das <sudi.das@arm.com>
765
766 * arm-dis.c (emun mve_instructions): Updated for new instructions.
767 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
768 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
769 uqshl, urshrl and urshr.
770 (is_mve_okay_in_it): Add new instructions to TRUE list.
771 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
772 (print_insn_mve): Updated to accept new %j,
773 %<bitfield>m and %<bitfield>n patterns.
774
cd4797ee
FS		 7752019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
776
777 * mips-opc.c (mips_builtin_opcodes): Change source register
778 constraint for DAUI.
779
999b073b
NC		 7802019-05-20 Nick Clifton <nickc@redhat.com>
781
782 * po/fr.po: Updated French translation.
783
14b456f2
AV		 7842019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
785 Michael Collison <michael.collison@arm.com>
786
787 * arm-dis.c (thumb32_opcodes): Add new instructions.
788 (enum mve_instructions): Likewise.
789 (enum mve_undefined): Add new reasons.
790 (is_mve_encoding_conflict): Handle new instructions.
791 (is_mve_undefined): Likewise.
792 (is_mve_unpredictable): Likewise.
793 (print_mve_undefined): Likewise.
794 (print_mve_size): Likewise.
795
f49bb598
AV		 7962019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
797 Michael Collison <michael.collison@arm.com>
798
799 * arm-dis.c (thumb32_opcodes): Add new instructions.
800 (enum mve_instructions): Likewise.
801 (is_mve_encoding_conflict): Handle new instructions.
802 (is_mve_undefined): Likewise.
803 (is_mve_unpredictable): Likewise.
804 (print_mve_size): Likewise.
805
56858bea
AV		 8062019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
807 Michael Collison <michael.collison@arm.com>
808
809 * arm-dis.c (thumb32_opcodes): Add new instructions.
810 (enum mve_instructions): Likewise.
811 (is_mve_encoding_conflict): Likewise.
812 (is_mve_unpredictable): Likewise.
813 (print_mve_size): Likewise.
814
e523f101
AV		 8152019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
816 Michael Collison <michael.collison@arm.com>
817
818 * arm-dis.c (thumb32_opcodes): Add new instructions.
819 (enum mve_instructions): Likewise.
820 (is_mve_encoding_conflict): Handle new instructions.
821 (is_mve_undefined): Likewise.
822 (is_mve_unpredictable): Likewise.
823 (print_mve_size): Likewise.
824
66dcaa5d
AV		 8252019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
826 Michael Collison <michael.collison@arm.com>
827
828 * arm-dis.c (thumb32_opcodes): Add new instructions.
829 (enum mve_instructions): Likewise.
830 (is_mve_encoding_conflict): Handle new instructions.
831 (is_mve_undefined): Likewise.
832 (is_mve_unpredictable): Likewise.
833 (print_mve_size): Likewise.
834 (print_insn_mve): Likewise.
835
d052b9b7
AV		 8362019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
837 Michael Collison <michael.collison@arm.com>
838
839 * arm-dis.c (thumb32_opcodes): Add new instructions.
840 (print_insn_thumb32): Handle new instructions.
841
ed63aa17
AV		 8422019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
843 Michael Collison <michael.collison@arm.com>
844
845 * arm-dis.c (enum mve_instructions): Add new instructions.
846 (enum mve_undefined): Add new reasons.
847 (is_mve_encoding_conflict): Handle new instructions.
848 (is_mve_undefined): Likewise.
849 (is_mve_unpredictable): Likewise.
850 (print_mve_undefined): Likewise.
851 (print_mve_size): Likewise.
852 (print_mve_shift_n): Likewise.
853 (print_insn_mve): Likewise.
854
897b9bbc
AV		 8552019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
856 Michael Collison <michael.collison@arm.com>
857
858 * arm-dis.c (enum mve_instructions): Add new instructions.
859 (is_mve_encoding_conflict): Handle new instructions.
860 (is_mve_unpredictable): Likewise.
861 (print_mve_rotate): Likewise.
862 (print_mve_size): Likewise.
863 (print_insn_mve): Likewise.
864
1c8f2df8
AV		 8652019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
866 Michael Collison <michael.collison@arm.com>
867
868 * arm-dis.c (enum mve_instructions): Add new instructions.
869 (is_mve_encoding_conflict): Handle new instructions.
870 (is_mve_unpredictable): Likewise.
871 (print_mve_size): Likewise.
872 (print_insn_mve): Likewise.
873
d3b63143
AV		 8742019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
875 Michael Collison <michael.collison@arm.com>
876
877 * arm-dis.c (enum mve_instructions): Add new instructions.
878 (enum mve_undefined): Add new reasons.
879 (is_mve_encoding_conflict): Handle new instructions.
880 (is_mve_undefined): Likewise.
881 (is_mve_unpredictable): Likewise.
882 (print_mve_undefined): Likewise.
883 (print_mve_size): Likewise.
884 (print_insn_mve): Likewise.
885
14925797
AV		 8862019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
887 Michael Collison <michael.collison@arm.com>
888
889 * arm-dis.c (enum mve_instructions): Add new instructions.
890 (is_mve_encoding_conflict): Handle new instructions.
891 (is_mve_undefined): Likewise.
892 (is_mve_unpredictable): Likewise.
893 (print_mve_size): Likewise.
894 (print_insn_mve): Likewise.
895
c507f10b
AV		 8962019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
897 Michael Collison <michael.collison@arm.com>
898
899 * arm-dis.c (enum mve_instructions): Add new instructions.
900 (enum mve_unpredictable): Add new reasons.
901 (enum mve_undefined): Likewise.
902 (is_mve_okay_in_it): Handle new isntructions.
903 (is_mve_encoding_conflict): Likewise.
904 (is_mve_undefined): Likewise.
905 (is_mve_unpredictable): Likewise.
906 (print_mve_vmov_index): Likewise.
907 (print_simd_imm8): Likewise.
908 (print_mve_undefined): Likewise.
909 (print_mve_unpredictable): Likewise.
910 (print_mve_size): Likewise.
911 (print_insn_mve): Likewise.
912
bf0b396d
AV		 9132019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
914 Michael Collison <michael.collison@arm.com>
915
916 * arm-dis.c (enum mve_instructions): Add new instructions.
917 (enum mve_unpredictable): Add new reasons.
918 (enum mve_undefined): Likewise.
919 (is_mve_encoding_conflict): Handle new instructions.
920 (is_mve_undefined): Likewise.
921 (is_mve_unpredictable): Likewise.
922 (print_mve_undefined): Likewise.
923 (print_mve_unpredictable): Likewise.
924 (print_mve_rounding_mode): Likewise.
925 (print_mve_vcvt_size): Likewise.
926 (print_mve_size): Likewise.
927 (print_insn_mve): Likewise.
928
ef1576a1
AV		 9292019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
930 Michael Collison <michael.collison@arm.com>
931
932 * arm-dis.c (enum mve_instructions): Add new instructions.
933 (enum mve_unpredictable): Add new reasons.
934 (enum mve_undefined): Likewise.
935 (is_mve_undefined): Handle new instructions.
936 (is_mve_unpredictable): Likewise.
937 (print_mve_undefined): Likewise.
938 (print_mve_unpredictable): Likewise.
939 (print_mve_size): Likewise.
940 (print_insn_mve): Likewise.
941
aef6d006
AV		 9422019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
943 Michael Collison <michael.collison@arm.com>
944
945 * arm-dis.c (enum mve_instructions): Add new instructions.
946 (enum mve_undefined): Add new reasons.
947 (insns): Add new instructions.
948 (is_mve_encoding_conflict):
949 (print_mve_vld_str_addr): New print function.
950 (is_mve_undefined): Handle new instructions.
951 (is_mve_unpredictable): Likewise.
952 (print_mve_undefined): Likewise.
953 (print_mve_size): Likewise.
954 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
955 (print_insn_mve): Handle new operands.
956
04d54ace
AV		 9572019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
958 Michael Collison <michael.collison@arm.com>
959
960 * arm-dis.c (enum mve_instructions): Add new instructions.
961 (enum mve_unpredictable): Add new reasons.
962 (is_mve_encoding_conflict): Handle new instructions.
963 (is_mve_unpredictable): Likewise.
964 (mve_opcodes): Add new instructions.
965 (print_mve_unpredictable): Handle new reasons.
966 (print_mve_register_blocks): New print function.
967 (print_mve_size): Handle new instructions.
968 (print_insn_mve): Likewise.
969
9743db03
AV		 9702019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
971 Michael Collison <michael.collison@arm.com>
972
973 * arm-dis.c (enum mve_instructions): Add new instructions.
974 (enum mve_unpredictable): Add new reasons.
975 (enum mve_undefined): Likewise.
976 (is_mve_encoding_conflict): Handle new instructions.
977 (is_mve_undefined): Likewise.
978 (is_mve_unpredictable): Likewise.
979 (coprocessor_opcodes): Move NEON VDUP from here...
980 (neon_opcodes): ... to here.
981 (mve_opcodes): Add new instructions.
982 (print_mve_undefined): Handle new reasons.
983 (print_mve_unpredictable): Likewise.
984 (print_mve_size): Handle new instructions.
985 (print_insn_neon): Handle vdup.
986 (print_insn_mve): Handle new operands.
987
143275ea
AV		 9882019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
989 Michael Collison <michael.collison@arm.com>
990
991 * arm-dis.c (enum mve_instructions): Add new instructions.
992 (enum mve_unpredictable): Add new values.
993 (mve_opcodes): Add new instructions.
994 (vec_condnames): New array with vector conditions.
995 (mve_predicatenames): New array with predicate suffixes.
996 (mve_vec_sizename): New array with vector sizes.
997 (enum vpt_pred_state): New enum with vector predication states.
998 (struct vpt_block): New struct type for vpt blocks.
999 (vpt_block_state): Global struct to keep track of state.
1000 (mve_extract_pred_mask): New helper function.
1001 (num_instructions_vpt_block): Likewise.
1002 (mark_outside_vpt_block): Likewise.
1003 (mark_inside_vpt_block): Likewise.
1004 (invert_next_predicate_state): Likewise.
1005 (update_next_predicate_state): Likewise.
1006 (update_vpt_block_state): Likewise.
1007 (is_vpt_instruction): Likewise.
1008 (is_mve_encoding_conflict): Add entries for new instructions.
1009 (is_mve_unpredictable): Likewise.
1010 (print_mve_unpredictable): Handle new cases.
1011 (print_instruction_predicate): Likewise.
1012 (print_mve_size): New function.
1013 (print_vec_condition): New function.
1014 (print_insn_mve): Handle vpt blocks and new print operands.
1015
f08d8ce3
AV		 10162019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1017
1018 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1019 8, 14 and 15 for Armv8.1-M Mainline.
1020
73cd51e5
AV		 10212019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1022 Michael Collison <michael.collison@arm.com>
1023
1024 * arm-dis.c (enum mve_instructions): New enum.
1025 (enum mve_unpredictable): Likewise.
1026 (enum mve_undefined): Likewise.
1027 (struct mopcode32): New struct.
1028 (is_mve_okay_in_it): New function.
1029 (is_mve_architecture): Likewise.
1030 (arm_decode_field): Likewise.
1031 (arm_decode_field_multiple): Likewise.
1032 (is_mve_encoding_conflict): Likewise.
1033 (is_mve_undefined): Likewise.
1034 (is_mve_unpredictable): Likewise.
1035 (print_mve_undefined): Likewise.
1036 (print_mve_unpredictable): Likewise.
1037 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1038 (print_insn_mve): New function.
1039 (print_insn_thumb32): Handle MVE architecture.
1040 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1041
3076e594
NC		 10422019-05-10 Nick Clifton <nickc@redhat.com>
1043
1044 PR 24538
1045 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1046 end of the table prematurely.
1047
387e7624
FS		 10482019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1049
1050 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1051 macros for R6.
1052
0067be51
AM		 10532019-05-11 Alan Modra <amodra@gmail.com>
1054
1055 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1056 when -Mraw is in effect.
1057
42e6288f
MM		 10582019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1059
1060 * aarch64-dis-2.c: Regenerate.
1061 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1062 (OP_SVE_BBB): New variant set.
1063 (OP_SVE_DDDD): New variant set.
1064 (OP_SVE_HHH): New variant set.
1065 (OP_SVE_HHHU): New variant set.
1066 (OP_SVE_SSS): New variant set.
1067 (OP_SVE_SSSU): New variant set.
1068 (OP_SVE_SHH): New variant set.
1069 (OP_SVE_SBBU): New variant set.
1070 (OP_SVE_DSS): New variant set.
1071 (OP_SVE_DHHU): New variant set.
1072 (OP_SVE_VMV_HSD_BHS): New variant set.
1073 (OP_SVE_VVU_HSD_BHS): New variant set.
1074 (OP_SVE_VVVU_SD_BH): New variant set.
1075 (OP_SVE_VVVU_BHSD): New variant set.
1076 (OP_SVE_VVV_QHD_DBS): New variant set.
1077 (OP_SVE_VVV_HSD_BHS): New variant set.
1078 (OP_SVE_VVV_HSD_BHS2): New variant set.
1079 (OP_SVE_VVV_BHS_HSD): New variant set.
1080 (OP_SVE_VV_BHS_HSD): New variant set.
1081 (OP_SVE_VVV_SD): New variant set.
1082 (OP_SVE_VVU_BHS_HSD): New variant set.
1083 (OP_SVE_VZVV_SD): New variant set.
1084 (OP_SVE_VZVV_BH): New variant set.
1085 (OP_SVE_VZV_SD): New variant set.
1086 (aarch64_opcode_table): Add sve2 instructions.
1087
28ed815a
MM		 10882019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1089
1090 * aarch64-asm-2.c: Regenerated.
1091 * aarch64-dis-2.c: Regenerated.
1092 * aarch64-opc-2.c: Regenerated.
1093 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1094 for SVE_SHLIMM_UNPRED_22.
1095 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1096 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1097 operand.
1098
fd1dc4a0
MM		 10992019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1100
1101 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1102 sve_size_tsz_bhs iclass encode.
1103 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1104 sve_size_tsz_bhs iclass decode.
1105
31e36ab3
MM		 11062019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1107
1108 * aarch64-asm-2.c: Regenerated.
1109 * aarch64-dis-2.c: Regenerated.
1110 * aarch64-opc-2.c: Regenerated.
1111 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1112 for SVE_Zm4_11_INDEX.
1113 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1114 (fields): Handle SVE_i2h field.
1115 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1116 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1117
1be5f94f
MM		 11182019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1119
1120 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1121 sve_shift_tsz_bhsd iclass encode.
1122 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1123 sve_shift_tsz_bhsd iclass decode.
1124
3c17238b
MM		 11252019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1126
1127 * aarch64-asm-2.c: Regenerated.
1128 * aarch64-dis-2.c: Regenerated.
1129 * aarch64-opc-2.c: Regenerated.
1130 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1131 (aarch64_encode_variant_using_iclass): Handle
1132 sve_shift_tsz_hsd iclass encode.
1133 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1134 sve_shift_tsz_hsd iclass decode.
1135 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1136 for SVE_SHRIMM_UNPRED_22.
1137 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1138 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1139 operand.
1140
cd50a87a
MM		 11412019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1142
1143 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1144 sve_size_013 iclass encode.
1145 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1146 sve_size_013 iclass decode.
1147
3c705960
MM		 11482019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1149
1150 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1151 sve_size_bh iclass encode.
1152 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1153 sve_size_bh iclass decode.
1154
0a57e14f
MM		 11552019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1156
1157 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1158 sve_size_sd2 iclass encode.
1159 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1160 sve_size_sd2 iclass decode.
1161 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1162 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1163
c469c864
MM		 11642019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1165
1166 * aarch64-asm-2.c: Regenerated.
1167 * aarch64-dis-2.c: Regenerated.
1168 * aarch64-opc-2.c: Regenerated.
1169 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1170 for SVE_ADDR_ZX.
1171 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1172 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1173
116adc27
MM		 11742019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1175
1176 * aarch64-asm-2.c: Regenerated.
1177 * aarch64-dis-2.c: Regenerated.
1178 * aarch64-opc-2.c: Regenerated.
1179 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1180 for SVE_Zm3_11_INDEX.
1181 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1182 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1183 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1184 fields.
1185 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1186
3bd82c86
MM		 11872019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1188
1189 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1190 sve_size_hsd2 iclass encode.
1191 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1192 sve_size_hsd2 iclass decode.
1193 * aarch64-opc.c (fields): Handle SVE_size field.
1194 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1195
adccc507
MM		 11962019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1197
1198 * aarch64-asm-2.c: Regenerated.
1199 * aarch64-dis-2.c: Regenerated.
1200 * aarch64-opc-2.c: Regenerated.
1201 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1202 for SVE_IMM_ROT3.
1203 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1204 (fields): Handle SVE_rot3 field.
1205 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1206 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1207
5cd99750
MM		 12082019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1209
1210 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1211 instructions.
1212
7ce2460a
MM		 12132019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1214
1215 * aarch64-tbl.h
1216 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1217 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1218 aarch64_feature_sve2bitperm): New feature sets.
1219 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1220 for feature set addresses.
1221 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1222 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1223
41cee089
FS		 12242019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1225 Faraz Shahbazker <fshahbazker@wavecomp.com>
1226
1227 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1228 argument and set ASE_EVA_R6 appropriately.
1229 (set_default_mips_dis_options): Pass ISA to above.
1230 (parse_mips_dis_option): Likewise.
1231 * mips-opc.c (EVAR6): New macro.
1232 (mips_builtin_opcodes): Add llwpe, scwpe.
1233
b83b4b13
SD		 12342019-05-01 Sudakshina Das <sudi.das@arm.com>
1235
1236 * aarch64-asm-2.c: Regenerated.
1237 * aarch64-dis-2.c: Regenerated.
1238 * aarch64-opc-2.c: Regenerated.
1239 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1240 AARCH64_OPND_TME_UIMM16.
1241 (aarch64_print_operand): Likewise.
1242 * aarch64-tbl.h (QL_IMM_NIL): New.
1243 (TME): New.
1244 (_TME_INSN): New.
1245 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1246
4a90ce95
JD		 12472019-04-29 John Darrington <john@darrington.wattle.id.au>
1248
1249 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1250
a45328b9
AB		 12512019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1252 Faraz Shahbazker <fshahbazker@wavecomp.com>
1253
1254 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1255
d10be0cb
JD		 12562019-04-24 John Darrington <john@darrington.wattle.id.au>
1257
1258 * s12z-opc.h: Add extern "C" bracketing to help
1259 users who wish to use this interface in c++ code.
1260
a679f24e
JD		 12612019-04-24 John Darrington <john@darrington.wattle.id.au>
1262
1263 * s12z-opc.c (bm_decode): Handle bit map operations with the
1264 "reserved0" mode.
1265
32c36c3c
AV		 12662019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1267
1268 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1269 specifier. Add entries for VLDR and VSTR of system registers.
1270 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1271 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1272 of %J and %K format specifier.
1273
efd6b359
AV		 12742019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1275
1276 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1277 Add new entries for VSCCLRM instruction.
1278 (print_insn_coprocessor): Handle new %C format control code.
1279
6b0dd094
AV		 12802019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1281
1282 * arm-dis.c (enum isa): New enum.
1283 (struct sopcode32): New structure.
1284 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1285 set isa field of all current entries to ANY.
1286 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1287 Only match an entry if its isa field allows the current mode.
1288
4b5a202f
AV		 12892019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1290
1291 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1292 CLRM.
1293 (print_insn_thumb32): Add logic to print %n CLRM register list.
1294
60f993ce
AV		 12952019-04-15 Sudakshina Das <sudi.das@arm.com>
1296
1297 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1298 and %Q patterns.
1299
f6b2b12d
AV		 13002019-04-15 Sudakshina Das <sudi.das@arm.com>
1301
1302 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1303 (print_insn_thumb32): Edit the switch case for %Z.
1304
1889da70
AV		 13052019-04-15 Sudakshina Das <sudi.das@arm.com>
1306
1307 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1308
65d1bc05
AV		 13092019-04-15 Sudakshina Das <sudi.das@arm.com>
1310
1311 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1312
1caf72a5
AV		 13132019-04-15 Sudakshina Das <sudi.das@arm.com>
1314
1315 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1316
f1c7f421
AV		 13172019-04-15 Sudakshina Das <sudi.das@arm.com>
1318
1319 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1320 Arm register with r13 and r15 unpredictable.
1321 (thumb32_opcodes): New instructions for bfx and bflx.
1322
4389b29a
AV		 13232019-04-15 Sudakshina Das <sudi.das@arm.com>
1324
1325 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1326
e5d6e09e
AV		 13272019-04-15 Sudakshina Das <sudi.das@arm.com>
1328
1329 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1330
e12437dc
AV		 13312019-04-15 Sudakshina Das <sudi.das@arm.com>
1332
1333 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1334
031254f2
AV		 13352019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1336
1337 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1338
e5a557ac
JD		 13392019-04-12 John Darrington <john@darrington.wattle.id.au>
1340
1341 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1342 "optr". ("operator" is a reserved word in c++).
1343
bd7ceb8d
SD		 13442019-04-11 Sudakshina Das <sudi.das@arm.com>
1345
1346 * aarch64-opc.c (aarch64_print_operand): Add case for
1347 AARCH64_OPND_Rt_SP.
1348 (verify_constraints): Likewise.
1349 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1350 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1351 to accept Rt|SP as first operand.
1352 (AARCH64_OPERANDS): Add new Rt_SP.
1353 * aarch64-asm-2.c: Regenerated.
1354 * aarch64-dis-2.c: Regenerated.
1355 * aarch64-opc-2.c: Regenerated.
1356
e54010f1
SD		 13572019-04-11 Sudakshina Das <sudi.das@arm.com>
1358
1359 * aarch64-asm-2.c: Regenerated.
1360 * aarch64-dis-2.c: Likewise.
1361 * aarch64-opc-2.c: Likewise.
1362 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1363
7e96e219
RS		 13642019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1365
1366 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1367
6f2791d5
L		 13682019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1369
1370 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1371 * i386-init.h: Regenerated.
1372
e392bad3
AM		 13732019-04-07 Alan Modra <amodra@gmail.com>
1374
1375 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1376 op_separator to control printing of spaces, comma and parens
1377 rather than need_comma, need_paren and spaces vars.
1378
dffaa15c
AM		 13792019-04-07 Alan Modra <amodra@gmail.com>
1380
1381 PR 24421
1382 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1383 (print_insn_neon, print_insn_arm): Likewise.
1384
d6aab7a1
XG		 13852019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1386
1387 * i386-dis-evex.h (evex_table): Updated to support BF16
1388 instructions.
1389 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1390 and EVEX_W_0F3872_P_3.
1391 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1392 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1393 * i386-opc.h (enum): Add CpuAVX512_BF16.
1394 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1395 * i386-opc.tbl: Add AVX512 BF16 instructions.
1396 * i386-init.h: Regenerated.
1397 * i386-tbl.h: Likewise.
1398
66e85460
AM		 13992019-04-05 Alan Modra <amodra@gmail.com>
1400
1401 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1402 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1403 to favour printing of "-" branch hint when using the "y" bit.
1404 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1405
c2b1c275
AM		 14062019-04-05 Alan Modra <amodra@gmail.com>
1407
1408 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1409 opcode until first operand is output.
1410
aae9718e
PB		 14112019-04-04 Peter Bergner <bergner@linux.ibm.com>
1412
1413 PR gas/24349
1414 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1415 (valid_bo_post_v2): Add support for 'at' branch hints.
1416 (insert_bo): Only error on branch on ctr.
1417 (get_bo_hint_mask): New function.
1418 (insert_boe): Add new 'branch_taken' formal argument. Add support
1419 for inserting 'at' branch hints.
1420 (extract_boe): Add new 'branch_taken' formal argument. Add support
1421 for extracting 'at' branch hints.
1422 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1423 (BOE): Delete operand.
1424 (BOM, BOP): New operands.
1425 (RM): Update value.
1426 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1427 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1428 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1429 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1430 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1431 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1432 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1433 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1434 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1435 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1436 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1437 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1438 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1439 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1440 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1441 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1442 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1443 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1444 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1445 bttarl+>: New extended mnemonics.
1446
96a86c01
AM		 14472019-03-28 Alan Modra <amodra@gmail.com>
1448
1449 PR 24390
1450 * ppc-opc.c (BTF): Define.
1451 (powerpc_opcodes): Use for mtfsb*.
1452 * ppc-dis.c (print_insn_powerpc): Print fields with both
1453 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1454
796d6298
TC		 14552019-03-25 Tamar Christina <tamar.christina@arm.com>
1456
1457 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1458 (mapping_symbol_for_insn): Implement new algorithm.
1459 (print_insn): Remove duplicate code.
1460
60df3720
TC		 14612019-03-25 Tamar Christina <tamar.christina@arm.com>
1462
1463 * aarch64-dis.c (print_insn_aarch64):
1464 Implement override.
1465
51457761
TC		 14662019-03-25 Tamar Christina <tamar.christina@arm.com>
1467
1468 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1469 order.
1470
53b2f36b
TC		 14712019-03-25 Tamar Christina <tamar.christina@arm.com>
1472
1473 * aarch64-dis.c (last_stop_offset): New.
1474 (print_insn_aarch64): Use stop_offset.
1475
89199bb5
L		 14762019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1477
1478 PR gas/24359
1479 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1480 CPU_ANY_AVX2_FLAGS.
1481 * i386-init.h: Regenerated.
1482
97ed31ae
L		 14832019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1484
1485 PR gas/24348
1486 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1487 vmovdqu16, vmovdqu32 and vmovdqu64.
1488 * i386-tbl.h: Regenerated.
1489
0919bfe9
AK		 14902019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1491
1492 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1493 from vstrszb, vstrszh, and vstrszf.
1494
14952019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1496
1497 * s390-opc.txt: Add instruction descriptions.
1498
21820ebe
JW		 14992019-02-08 Jim Wilson <jimw@sifive.com>
1500
1501 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1502 <bne>: Likewise.
1503
f7dd2fb2
TC		 15042019-02-07 Tamar Christina <tamar.christina@arm.com>
1505
1506 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1507
6456d318
TC		 15082019-02-07 Tamar Christina <tamar.christina@arm.com>
1509
1510 PR binutils/23212
1511 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1512 * aarch64-opc.c (verify_elem_sd): New.
1513 (fields): Add FLD_sz entr.
1514 * aarch64-tbl.h (_SIMD_INSN): New.
1515 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1516 fmulx scalar and vector by element isns.
1517
4a83b610
NC		 15182019-02-07 Nick Clifton <nickc@redhat.com>
1519
1520 * po/sv.po: Updated Swedish translation.
1521
fc60b8c8
AK		 15222019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1523
1524 * s390-mkopc.c (main): Accept arch13 as cpu string.
1525 * s390-opc.c: Add new instruction formats and instruction opcode
1526 masks.
1527 * s390-opc.txt: Add new arch13 instructions.
1528
e10620d3
TC		 15292019-01-25 Sudakshina Das <sudi.das@arm.com>
1530
1531 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1532 (aarch64_opcode): Change encoding for stg, stzg
1533 st2g and st2zg.
1534 * aarch64-asm-2.c: Regenerated.
1535 * aarch64-dis-2.c: Regenerated.
1536 * aarch64-opc-2.c: Regenerated.
1537
20a4ca55
SD		 15382019-01-25 Sudakshina Das <sudi.das@arm.com>
1539
1540 * aarch64-asm-2.c: Regenerated.
1541 * aarch64-dis-2.c: Likewise.
1542 * aarch64-opc-2.c: Likewise.
1543 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1544
550fd7bf
SD		 15452019-01-25 Sudakshina Das <sudi.das@arm.com>
1546 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1547
1548 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1549 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1550 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1551 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1552 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1553 case for ldstgv_indexed.
1554 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1555 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1556 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1557 * aarch64-asm-2.c: Regenerated.
1558 * aarch64-dis-2.c: Regenerated.
1559 * aarch64-opc-2.c: Regenerated.
1560
d9938630
NC		 15612019-01-23 Nick Clifton <nickc@redhat.com>
1562
1563 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1564
375cd423
NC		 15652019-01-21 Nick Clifton <nickc@redhat.com>
1566
1567 * po/de.po: Updated German translation.
1568 * po/uk.po: Updated Ukranian translation.
1569
57299f48
CX		 15702019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1571 * mips-dis.c (mips_arch_choices): Fix typo in
1572 gs464, gs464e and gs264e descriptors.
1573
f48dfe41
NC		 15742019-01-19 Nick Clifton <nickc@redhat.com>
1575
1576 * configure: Regenerate.
1577 * po/opcodes.pot: Regenerate.
1578
f974f26c
NC		 15792018-06-24 Nick Clifton <nickc@redhat.com>
1580
1581 2.32 branch created.
1582
39f286cd
JD		 15832019-01-09 John Darrington <john@darrington.wattle.id.au>
1584
448b8ca8
JD		 1585 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1586 if it is null.
1587 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 1588 zero.
1589
3107326d
AP		 15902019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1591
1592 * configure: Regenerate.
1593
7e9ca91e
AM		 15942019-01-07 Alan Modra <amodra@gmail.com>
1595
1596 * configure: Regenerate.
1597 * po/POTFILES.in: Regenerate.
1598
ef1ad42b
JD		 15992019-01-03 John Darrington <john@darrington.wattle.id.au>
1600
1601 * s12z-opc.c: New file.
1602 * s12z-opc.h: New file.
1603 * s12z-dis.c: Removed all code not directly related to display
1604 of instructions. Used the interface provided by the new files
1605 instead.
1606 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 1607 * Makefile.in: Regenerate.
ef1ad42b 1608 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 1609 * configure: Regenerate.
ef1ad42b 1610
82704155
AM		 16112019-01-01 Alan Modra <amodra@gmail.com>
1612
1613 Update year range in copyright notice of all files.
1614
d5c04e1b 1615For older changes see ChangeLog-2018
3499769a 1616\f
d5c04e1b 1617Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 1618
1619Copying and distribution of this file, with or without modification,
1620are permitted in any medium without royalty provided the copyright
1621notice and this notice are preserved.
1622
1623Local Variables:
1624mode: change-log
1625left-margin: 8
1626fill-column: 74
1627version-control: never
1628End:
GDB Binutils - Deliverables
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