projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Fix the RX assembler's section alignment parameter to use multiples of N rather than...
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
43cdf5ae
YQ		 12015-10-28 Yao Qi <yao.qi@linaro.org>
2
3 * aarch64-dis.c (aarch64_decode_insn): Add one argument
4 noaliases_p. Update comments. Pass noaliases_p rather than
5 no_aliases to aarch64_opcode_decode.
6 (print_insn_aarch64_word): Pass no_aliases to
7 aarch64_decode_insn.
8
c2f28758
VK		 92015-10-27 Vinay <Vinay.G@kpit.com>
10
11 PR binutils/19159
12 * rl78-decode.opc (MOV): Added offset to DE register in index
13 addressing mode.
14 * rl78-decode.c: Regenerate.
15
46662804
VK		 162015-10-27 Vinay Kumar <vinay.g@kpit.com>
17
18 PR binutils/19158
19 * rl78-decode.opc: Add 's' print operator to instructions that
20 access system registers.
21 * rl78-decode.c: Regenerate.
22 * rl78-dis.c (print_insn_rl78_common): Decode all system
23 registers.
24
02f12cd4
VK		 252015-10-27 Vinay Kumar <vinay.g@kpit.com>
26
27 PR binutils/19157
28 * rl78-decode.opc: Add 'a' print operator to mov instructions
29 using stack pointer plus index addressing.
30 * rl78-decode.c: Regenerate.
31
485f23cf
AK		 322015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
33
34 * s390-opc.c: Fix comment.
35 * s390-opc.txt: Change instruction type for troo, trot, trto, and
36 trtt to RRF_U0RER since the second parameter does not need to be a
37 register pair.
38
3f94e60d
NC		 392015-10-08 Nick Clifton <nickc@redhat.com>
40
41 * arc-dis.c (print_insn_arc): Initiallise insn array.
42
875880c6
YQ		 432015-10-07 Yao Qi <yao.qi@linaro.org>
44
45 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
46 'name' rather than 'template'.
47 * aarch64-opc.c (aarch64_print_operand): Likewise.
48
886a2506
NC		 492015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
50
51 * arc-dis.c: Revamped file for ARC support
52 * arc-dis.h: Likewise.
53 * arc-ext.c: Likewise.
54 * arc-ext.h: Likewise.
55 * arc-opc.c: Likewise.
56 * arc-fxi.h: New file.
57 * arc-regs.h: Likewise.
58 * arc-tbl.h: Likewise.
59
36f4aab1
YQ		 602015-10-02 Yao Qi <yao.qi@linaro.org>
61
62 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
63 argument insn type to aarch64_insn. Rename to ...
64 (aarch64_decode_insn): ... it.
65 (print_insn_aarch64_word): Caller updated.
66
7232d389
YQ		 672015-10-02 Yao Qi <yao.qi@linaro.org>
68
69 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
70 (print_insn_aarch64_word): Caller updated.
71
7ecc513a
DV		 722015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
73
74 * s390-mkopc.c (main): Parse htm and vx flag.
75 * s390-opc.txt: Mark instructions from the hardware transactional
76 memory and vector facilities with the "htm"/"vx" flag.
77
b08b78e7
NC		 782015-09-28 Nick Clifton <nickc@redhat.com>
79
80 * po/de.po: Updated German translation.
81
36f7a941
TR		 822015-09-28 Tom Rix <tom@bumblecow.com>
83
84 * ppc-opc.c (PPC500): Mark some opcodes as invalid
85
b6518b38
NC		 862015-09-23 Nick Clifton <nickc@redhat.com>
87
88 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
89 function.
90 * tic30-dis.c (print_branch): Likewise.
91 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
92 value before left shifting.
93 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
94 * hppa-dis.c (print_insn_hppa): Likewise.
95 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
96 array.
97 * msp430-dis.c (msp430_singleoperand): Likewise.
98 (msp430_doubleoperand): Likewise.
99 (print_insn_msp430): Likewise.
100 * nds32-asm.c (parse_operand): Likewise.
101 * sh-opc.h (MASK): Likewise.
102 * v850-dis.c (get_operand_value): Likewise.
103
f04265ec
NC		 1042015-09-22 Nick Clifton <nickc@redhat.com>
105
106 * rx-decode.opc (bwl): Use RX_Bad_Size.
107 (sbwl): Likewise.
108 (ubwl): Likewise. Rename to ubw.
109 (uBWL): Rename to uBW.
110 Replace all references to uBWL with uBW.
111 * rx-decode.c: Regenerate.
112 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
113 (opsize_names): Likewise.
114 (print_insn_rx): Detect and report RX_Bad_Size.
115
6dca4fd1
AB		 1162015-09-22 Anton Blanchard <anton@samba.org>
117
118 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
119
38074311
JM		 1202015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
121
122 * sparc-dis.c (print_insn_sparc): Handle the privileged register
123 %pmcdper.
124
5f40e14d
JS		 1252015-08-24 Jan Stancek <jstancek@redhat.com>
126
127 * i386-dis.c (print_insn): Fix decoding of three byte operands.
128
ab4e4ed5
AF		 1292015-08-21 Alexander Fomin <alexander.fomin@intel.com>
130
131 PR binutils/18257
132 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
133 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
134 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
135 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
136 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
137 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
138 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
139 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
140 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
141 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
142 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
143 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
144 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
145 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
146 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
147 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
148 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
149 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
150 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
151 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
152 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
153 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
154 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
155 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
156 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
157 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
158 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
159 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
160 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
161 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
162 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
163 (vex_w_table): Replace terminals with MOD_TABLE entries for
164 most of mask instructions.
165
919b75f7
AM		 1662015-08-17 Alan Modra <amodra@gmail.com>
167
168 * cgen.sh: Trim trailing space from cgen output.
169 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
170 (print_dis_table): Likewise.
171 * opc2c.c (dump_lines): Likewise.
172 (orig_filename): Warning fix.
173 * ia64-asmtab.c: Regenerate.
174
4ab90a7a
AV		 1752015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
176
177 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
178 and higher with ARM instruction set will now mark the 26-bit
179 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
180 (arm_opcodes): Fix for unpredictable nop being recognized as a
181 teq.
182
40fc1451
SD		 1832015-08-12 Simon Dardis <simon.dardis@imgtec.com>
184
185 * micromips-opc.c (micromips_opcodes): Re-order table so that move
186 based on 'or' is first.
187 * mips-opc.c (mips_builtin_opcodes): Ditto.
188
922c5db5
NC		 1892015-08-11 Nick Clifton <nickc@redhat.com>
190
191 PR 18800
192 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
193 instruction.
194
75fb7498
RS		 1952015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
196
197 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
198
36aed29d
AP		 1992015-08-07 Amit Pawar <Amit.Pawar@amd.com>
200
201 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
202 * i386-init.h: Regenerated.
203
a8484f96
L		 2042015-07-30 H.J. Lu <hongjiu.lu@intel.com>
205
206 PR binutils/13571
207 * i386-dis.c (MOD_0FC3): New.
208 (PREFIX_0FC3): Renamed to ...
209 (PREFIX_MOD_0_0FC3): This.
210 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
211 (prefix_table): Replace Ma with Ev on movntiS.
212 (mod_table): Add MOD_0FC3.
213
37a42ee9
L		 2142015-07-27 H.J. Lu <hongjiu.lu@intel.com>
215
216 * configure: Regenerated.
217
070fe95d
AM		 2182015-07-23 Alan Modra <amodra@gmail.com>
219
220 PR 18708
221 * i386-dis.c (get64): Avoid signed integer overflow.
222
20c2a615
L		 2232015-07-22 Alexander Fomin <alexander.fomin@intel.com>
224
225 PR binutils/18631
226 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
227 "EXEvexHalfBcstXmmq" for the second operand.
228 (EVEX_W_0F79_P_2): Likewise.
229 (EVEX_W_0F7A_P_2): Likewise.
230 (EVEX_W_0F7B_P_2): Likewise.
231
6f1c2142
AM		 2322015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
233
234 * arm-dis.c (print_insn_coprocessor): Added support for quarter
235 float bitfield format.
236 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
237 quarter float bitfield format.
238
8a643cc3
L		 2392015-07-14 H.J. Lu <hongjiu.lu@intel.com>
240
241 * configure: Regenerated.
242
ef5a96d5
AM		 2432015-07-03 Alan Modra <amodra@gmail.com>
244
245 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
246 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
247 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
248
c8c8175b
SL		 2492015-07-01 Sandra Loosemore <sandra@codesourcery.com>
250 Cesar Philippidis <cesar@codesourcery.com>
251
252 * nios2-dis.c (nios2_extract_opcode): New.
253 (nios2_disassembler_state): New.
254 (nios2_find_opcode_hash): Use mach parameter to select correct
255 disassembler state.
256 (nios2_print_insn_arg): Extend to support new R2 argument letters
257 and formats.
258 (print_insn_nios2): Check for 16-bit instruction at end of memory.
259 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
260 (NIOS2_NUM_OPCODES): Rename to...
261 (NIOS2_NUM_R1_OPCODES): This.
262 (nios2_r2_opcodes): New.
263 (NIOS2_NUM_R2_OPCODES): New.
264 (nios2_num_r2_opcodes): New.
265 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
266 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
267 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
268 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
269 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
270
9916071f
AP		 2712015-06-30 Amit Pawar <Amit.Pawar@amd.com>
272
273 * i386-dis.c (OP_Mwaitx): New.
274 (rm_table): Add monitorx/mwaitx.
275 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
276 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
277 (operand_type_init): Add CpuMWAITX.
278 * i386-opc.h (CpuMWAITX): New.
279 (i386_cpu_flags): Add cpumwaitx.
280 * i386-opc.tbl: Add monitorx and mwaitx.
281 * i386-init.h: Regenerated.
282 * i386-tbl.h: Likewise.
283
7b934113
PB		 2842015-06-22 Peter Bergner <bergner@vnet.ibm.com>
285
286 * ppc-opc.c (insert_ls): Test for invalid LS operands.
287 (insert_esync): New function.
288 (LS, WC): Use insert_ls.
289 (ESYNC): Use insert_esync.
290
bdc4de1b
NC		 2912015-06-22 Nick Clifton <nickc@redhat.com>
292
293 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
294 requested region lies beyond it.
295 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
296 looking for 32-bit insns.
297 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
298 data.
299 * sh-dis.c (print_insn_sh): Likewise.
300 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
301 blocks of instructions.
302 * vax-dis.c (print_insn_vax): Check that the requested address
303 does not clash with the stop_vma.
304
11a0cf2e
PB		 3052015-06-19 Peter Bergner <bergner@vnet.ibm.com>
306
070fe95d 307 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 308 * ppc-opc.c (FXM4): Add non-zero optional value.
309 (TBR): Likewise.
310 (SXL): Likewise.
311 (insert_fxm): Handle new default operand value.
312 (extract_fxm): Likewise.
313 (insert_tbr): Likewise.
314 (extract_tbr): Likewise.
315
bdfa8b95
MW		 3162015-06-16 Matthew Wahab <matthew.wahab@arm.com>
317
318 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
319
24b4cf66
SN		 3202015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
321
322 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
323
99a2c561
PB		 3242015-06-12 Peter Bergner <bergner@vnet.ibm.com>
325
326 * ppc-opc.c: Add comment accidentally removed by old commit.
327 (MTMSRD_L): Delete.
328
40f77f82
AM		 3292015-06-04 Peter Bergner <bergner@vnet.ibm.com>
330
331 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
332
13be46a2
NC		 3332015-06-04 Nick Clifton <nickc@redhat.com>
334
335 PR 18474
336 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
337
ddfded2f
MW		 3382015-06-02 Matthew Wahab <matthew.wahab@arm.com>
339
340 * arm-dis.c (arm_opcodes): Add "setpan".
341 (thumb_opcodes): Add "setpan".
342
1af1dd51
MW		 3432015-06-02 Matthew Wahab <matthew.wahab@arm.com>
344
345 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
346 macros.
347
9e1f0fa7
MW		 3482015-06-02 Matthew Wahab <matthew.wahab@arm.com>
349
350 * aarch64-tbl.h (aarch64_feature_rdma): New.
351 (RDMA): New.
352 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
353 * aarch64-asm-2.c: Regenerate.
354 * aarch64-dis-2.c: Regenerate.
355 * aarch64-opc-2.c: Regenerate.
356
290806fd
MW		 3572015-06-02 Matthew Wahab <matthew.wahab@arm.com>
358
359 * aarch64-tbl.h (aarch64_feature_lor): New.
360 (LOR): New.
361 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
362 "stllrb", "stllrh".
363 * aarch64-asm-2.c: Regenerate.
364 * aarch64-dis-2.c: Regenerate.
365 * aarch64-opc-2.c: Regenerate.
366
f21cce2c
MW		 3672015-06-01 Matthew Wahab <matthew.wahab@arm.com>
368
369 * aarch64-opc.c (F_ARCHEXT): New.
370 (aarch64_sys_regs): Add "pan".
371 (aarch64_sys_reg_supported_p): New.
372 (aarch64_pstatefields): Add "pan".
373 (aarch64_pstatefield_supported_p): New.
374
d194d186
JB		 3752015-06-01 Jan Beulich <jbeulich@suse.com>
376
377 * i386-tbl.h: Regenerate.
378
3a8547d2
JB		 3792015-06-01 Jan Beulich <jbeulich@suse.com>
380
381 * i386-dis.c (print_insn): Swap rounding mode specifier and
382 general purpose register in Intel mode.
383
015c54d5
JB		 3842015-06-01 Jan Beulich <jbeulich@suse.com>
385
386 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
387 * i386-tbl.h: Regenerate.
388
071f0063
L		 3892015-05-18 H.J. Lu <hongjiu.lu@intel.com>
390
391 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
392 * i386-init.h: Regenerated.
393
5db04b09
L		 3942015-05-15 H.J. Lu <hongjiu.lu@intel.com>
395
396 PR binutis/18386
397 * i386-dis.c: Add comments for '@'.
398 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
399 (enum x86_64_isa): New.
400 (isa64): Likewise.
401 (print_i386_disassembler_options): Add amd64 and intel64.
402 (print_insn): Handle amd64 and intel64.
403 (putop): Handle '@'.
404 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
405 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
406 * i386-opc.h (AMD64): New.
407 (CpuIntel64): Likewise.
408 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
409 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
410 Mark direct call/jmp without Disp16|Disp32 as Intel64.
411 * i386-init.h: Regenerated.
412 * i386-tbl.h: Likewise.
413
4bc0608a
PB		 4142015-05-14 Peter Bergner <bergner@vnet.ibm.com>
415
416 * ppc-opc.c (IH) New define.
417 (powerpc_opcodes) <wait>: Do not enable for POWER7.
418 <tlbie>: Add RS operand for POWER7.
419 <slbia>: Add IH operand for POWER6.
420
70cead07
L		 4212015-05-11 H.J. Lu <hongjiu.lu@intel.com>
422
423 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
424 direct branch.
425 (jmp): Likewise.
426 * i386-tbl.h: Regenerated.
427
7b6d09fb
L		 4282015-05-11 H.J. Lu <hongjiu.lu@intel.com>
429
430 * configure.ac: Support bfd_iamcu_arch.
431 * disassemble.c (disassembler): Support bfd_iamcu_arch.
432 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
433 CPU_IAMCU_COMPAT_FLAGS.
434 (cpu_flags): Add CpuIAMCU.
435 * i386-opc.h (CpuIAMCU): New.
436 (i386_cpu_flags): Add cpuiamcu.
437 * configure: Regenerated.
438 * i386-init.h: Likewise.
439 * i386-tbl.h: Likewise.
440
31955f99
L		 4412015-05-08 H.J. Lu <hongjiu.lu@intel.com>
442
443 PR binutis/18386
444 * i386-dis.c (X86_64_E8): New.
445 (X86_64_E9): Likewise.
446 Update comments on 'T', 'U', 'V'. Add comments for '^'.
447 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
448 (x86_64_table): Add X86_64_E8 and X86_64_E9.
449 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
450 (putop): Handle '^'.
451 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
452 REX_W.
453
0952813b
DD		 4542015-04-30 DJ Delorie <dj@redhat.com>
455
456 * disassemble.c (disassembler): Choose suitable disassembler based
457 on E_ABI.
458 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
459 it to decode mul/div insns.
460 * rl78-decode.c: Regenerate.
461 * rl78-dis.c (print_insn_rl78): Rename to...
462 (print_insn_rl78_common): ...this, take ISA parameter.
463 (print_insn_rl78): New.
464 (print_insn_rl78_g10): New.
465 (print_insn_rl78_g13): New.
466 (print_insn_rl78_g14): New.
467 (rl78_get_disassembler): New.
468
f9d3ecaa
NC		 4692015-04-29 Nick Clifton <nickc@redhat.com>
470
471 * po/fr.po: Updated French translation.
472
4fff86c5
PB		 4732015-04-27 Peter Bergner <bergner@vnet.ibm.com>
474
475 * ppc-opc.c (DCBT_EO): New define.
476 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
477 <lharx>: Likewise.
478 <stbcx.>: Likewise.
479 <sthcx.>: Likewise.
480 <waitrsv>: Do not enable for POWER7 and later.
481 <waitimpl>: Likewise.
482 <dcbt>: Default to the two operand form of the instruction for all
483 "old" cpus. For "new" cpus, use the operand ordering that matches
484 whether the cpu is server or embedded.
485 <dcbtst>: Likewise.
486
3b78cfe1
AK		 4872015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
488
489 * s390-opc.c: New instruction type VV0UU2.
490 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
491 and WFC.
492
04d824a4
JB		 4932015-04-23 Jan Beulich <jbeulich@suse.com>
494
495 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
496 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
497 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
498 (vfpclasspd, vfpclassps): Add %XZ.
499
09708981
L		 5002015-04-15 H.J. Lu <hongjiu.lu@intel.com>
501
502 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
503 (PREFIX_UD_REPZ): Likewise.
504 (PREFIX_UD_REPNZ): Likewise.
505 (PREFIX_UD_DATA): Likewise.
506 (PREFIX_UD_ADDR): Likewise.
507 (PREFIX_UD_LOCK): Likewise.
508
3888916d
L		 5092015-04-15 H.J. Lu <hongjiu.lu@intel.com>
510
511 * i386-dis.c (prefix_requirement): Removed.
512 (print_insn): Don't set prefix_requirement. Check
513 dp->prefix_requirement instead of prefix_requirement.
514
f24bcbaa
L		 5152015-04-15 H.J. Lu <hongjiu.lu@intel.com>
516
517 PR binutils/17898
518 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
519 (PREFIX_MOD_0_0FC7_REG_6): This.
520 (PREFIX_MOD_3_0FC7_REG_6): New.
521 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
522 (prefix_table): Replace PREFIX_0FC7_REG_6 with
523 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
524 PREFIX_MOD_3_0FC7_REG_7.
525 (mod_table): Replace PREFIX_0FC7_REG_6 with
526 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
527 PREFIX_MOD_3_0FC7_REG_7.
528
507bd325
L		 5292015-04-15 H.J. Lu <hongjiu.lu@intel.com>
530
531 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
532 (PREFIX_MANDATORY_REPNZ): Likewise.
533 (PREFIX_MANDATORY_DATA): Likewise.
534 (PREFIX_MANDATORY_ADDR): Likewise.
535 (PREFIX_MANDATORY_LOCK): Likewise.
536 (PREFIX_MANDATORY): Likewise.
537 (PREFIX_UD_SHIFT): Set to 8
538 (PREFIX_UD_REPZ): Updated.
539 (PREFIX_UD_REPNZ): Likewise.
540 (PREFIX_UD_DATA): Likewise.
541 (PREFIX_UD_ADDR): Likewise.
542 (PREFIX_UD_LOCK): Likewise.
543 (PREFIX_IGNORED_SHIFT): New.
544 (PREFIX_IGNORED_REPZ): Likewise.
545 (PREFIX_IGNORED_REPNZ): Likewise.
546 (PREFIX_IGNORED_DATA): Likewise.
547 (PREFIX_IGNORED_ADDR): Likewise.
548 (PREFIX_IGNORED_LOCK): Likewise.
549 (PREFIX_OPCODE): Likewise.
550 (PREFIX_IGNORED): Likewise.
551 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
552 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
553 (three_byte_table): Likewise.
554 (mod_table): Likewise.
555 (mandatory_prefix): Renamed to ...
556 (prefix_requirement): This.
557 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
558 Update PREFIX_90 entry.
559 (get_valid_dis386): Check prefix_requirement to see if a prefix
560 should be ignored.
561 (print_insn): Replace mandatory_prefix with prefix_requirement.
562
f0fba320
RL		 5632015-04-15 Renlin Li <renlin.li@arm.com>
564
565 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
566 use it for ssat and ssat16.
567 (print_insn_thumb32): Add handle case for 'D' control code.
568
bf890a93
IT		 5692015-04-06 Ilya Tocar <ilya.tocar@intel.com>
570 H.J. Lu <hongjiu.lu@intel.com>
571
572 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
573 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
574 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
575 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
576 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
577 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
578 Fill prefix_requirement field.
579 (struct dis386): Add prefix_requirement field.
580 (dis386): Fill prefix_requirement field.
581 (dis386_twobyte): Ditto.
582 (twobyte_has_mandatory_prefix_: Remove.
583 (reg_table): Fill prefix_requirement field.
584 (prefix_table): Ditto.
585 (x86_64_table): Ditto.
586 (three_byte_table): Ditto.
587 (xop_table): Ditto.
588 (vex_table): Ditto.
589 (vex_len_table): Ditto.
590 (vex_w_table): Ditto.
591 (mod_table): Ditto.
592 (bad_opcode): Ditto.
593 (print_insn): Use prefix_requirement.
594 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
595 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
596 (float_reg): Ditto.
597
2f783c1f
MF		 5982015-03-30 Mike Frysinger <vapier@gentoo.org>
599
600 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
601
b9d94d62
L		 6022015-03-29 H.J. Lu <hongjiu.lu@intel.com>
603
604 * Makefile.in: Regenerated.
605
27c49e9a
AB		 6062015-03-25 Anton Blanchard <anton@samba.org>
607
608 * ppc-dis.c (disassemble_init_powerpc): Only initialise
609 powerpc_opcd_indices and vle_opcd_indices once.
610
c4e676f1
AB		 6112015-03-25 Anton Blanchard <anton@samba.org>
612
613 * ppc-opc.c (powerpc_opcodes): Add slbfee.
614
823d2571
TG		 6152015-03-24 Terry Guo <terry.guo@arm.com>
616
617 * arm-dis.c (opcode32): Updated to use new arm feature struct.
618 (opcode16): Likewise.
619 (coprocessor_opcodes): Replace bit with feature struct.
620 (neon_opcodes): Likewise.
621 (arm_opcodes): Likewise.
622 (thumb_opcodes): Likewise.
623 (thumb32_opcodes): Likewise.
624 (print_insn_coprocessor): Likewise.
625 (print_insn_arm): Likewise.
626 (select_arm_features): Follow new feature struct.
627
029f3522
GG		 6282015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
629
630 * i386-dis.c (rm_table): Add clzero.
631 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
632 Add CPU_CLZERO_FLAGS.
633 (cpu_flags): Add CpuCLZERO.
634 * i386-opc.h: Add CpuCLZERO.
635 * i386-opc.tbl: Add clzero.
636 * i386-init.h: Re-generated.
637 * i386-tbl.h: Re-generated.
638
6914869a
AB		 6392015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
640
641 * mips-opc.c (decode_mips_operand): Fix constraint issues
642 with u and y operands.
643
21e20815
AB		 6442015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
645
646 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
647
6b1d7593
AK		 6482015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
649
650 * s390-opc.c: Add new IBM z13 instructions.
651 * s390-opc.txt: Likewise.
652
c8f89a34
JW		 6532015-03-10 Renlin Li <renlin.li@arm.com>
654
655 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
656 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
657 related alias.
658 * aarch64-asm-2.c: Regenerate.
659 * aarch64-dis-2.c: Likewise.
660 * aarch64-opc-2.c: Likewise.
661
d8282f0e
JW		 6622015-03-03 Jiong Wang <jiong.wang@arm.com>
663
664 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
665
ac994365
OE		 6662015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
667
668 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
669 arch_sh_up.
670 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
671 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
672
fd63f640
V		 6732015-02-23 Vinay <Vinay.G@kpit.com>
674
675 * rl78-decode.opc (MOV): Added space between two operands for
676 'mov' instruction in index addressing mode.
677 * rl78-decode.c: Regenerate.
678
f63c1776
PA		 6792015-02-19 Pedro Alves <palves@redhat.com>
680
681 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
682
07774fcc
PA		 6832015-02-10 Pedro Alves <palves@redhat.com>
684 Tom Tromey <tromey@redhat.com>
685
686 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
687 microblaze_and, microblaze_xor.
688 * microblaze-opc.h (opcodes): Adjust.
689
3f8107ab
AM		 6902015-01-28 James Bowman <james.bowman@ftdichip.com>
691
692 * Makefile.am: Add FT32 files.
693 * configure.ac: Handle FT32.
694 * disassemble.c (disassembler): Call print_insn_ft32.
695 * ft32-dis.c: New file.
696 * ft32-opc.c: New file.
697 * Makefile.in: Regenerate.
698 * configure: Regenerate.
699 * po/POTFILES.in: Regenerate.
700
e5fe4957
KLC		 7012015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
702
703 * nds32-asm.c (keyword_sr): Add new system registers.
704
1e2e8c52
AK		 7052015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
706
707 * s390-dis.c (s390_extract_operand): Support vector register
708 operands.
709 (s390_print_insn_with_opcode): Support new operands types and add
710 new handling of optional operands.
711 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
712 and include opcode/s390.h instead.
713 (struct op_struct): New field `flags'.
714 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
715 (dumpTable): Dump flags.
716 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
717 string.
718 * s390-opc.c: Add new operands types, instruction formats, and
719 instruction masks.
720 (s390_opformats): Add new formats for .insn.
721 * s390-opc.txt: Add new instructions.
722
b90efa5b 7232015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 724
b90efa5b 725 Update year range in copyright notice of all files.
bffb6004 726
b90efa5b 727For older changes see ChangeLog-2014
252b5132 728\f
b90efa5b 729Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 730
731Copying and distribution of this file, with or without modification,
732are permitted in any medium without royalty provided the copyright
733notice and this notice are preserved.
734
252b5132 735Local Variables:
2f6d2f85
NC		 736mode: change-log
737left-margin: 8
738fill-column: 74
252b5132
RH		 739version-control: never
740End:
GDB Binutils - Deliverables
This page took 0.766506 seconds and 4 git commands to generate.