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Remove type_name_no_tag and rename type_name_no_tag_or_error
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
733bd0ab
JB		 12018-06-01 Jan Beulich <jbeulich@suse.com>
2
3 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
4 * i386-tbl.h: Re-generate.
5
dfd27d41
JB		 62018-06-01 Jan Beulich <jbeulich@suse.com>
7
8 * i386-opc.tbl (sldt, str): Add NoRex64.
9 * i386-tbl.h: Re-generate.
10
64795710
JB		 112018-06-01 Jan Beulich <jbeulich@suse.com>
12
13 * i386-opc.tbl (invpcid): Add Oword.
14 * i386-tbl.h: Re-generate.
15
030157d8
AM		 162018-06-01 Alan Modra <amodra@gmail.com>
17
18 * sysdep.h (_bfd_error_handler): Don't declare.
19 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
20 * rl78-decode.opc: Likewise.
21 * msp430-decode.c: Regenerate.
22 * rl78-decode.c: Regenerate.
23
a9660a6f
AP		 242018-05-30 Amit Pawar <Amit.Pawar@amd.com>
25
26 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
27 * i386-init.h : Regenerated.
28
277eb7f6
AM		 292018-05-25 Alan Modra <amodra@gmail.com>
30
31 * Makefile.in: Regenerate.
32 * po/POTFILES.in: Regenerate.
33
98553ad3
PB		 342018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
35
36 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
37 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
38 (insert_bab, extract_bab, insert_btab, extract_btab,
39 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
40 (BAT, BBA VBA RBS XB6S): Delete macros.
41 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
42 (BB, BD, RBX, XC6): Update for new macros.
43 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
44 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
45 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
46 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
47
7b4ae824
JD		 482018-05-18 John Darrington <john@darrington.wattle.id.au>
49
50 * Makefile.am: Add support for s12z architecture.
51 * configure.ac: Likewise.
52 * disassemble.c: Likewise.
53 * disassemble.h: Likewise.
54 * Makefile.in: Regenerate.
55 * configure: Regenerate.
56 * s12z-dis.c: New file.
57 * s12z.h: New file.
58
29e0f0a1
AM		 592018-05-18 Alan Modra <amodra@gmail.com>
60
61 * nfp-dis.c: Don't #include libbfd.h.
62 (init_nfp3200_priv): Use bfd_get_section_contents.
63 (nit_nfp6000_mecsr_sec): Likewise.
64
809276d2
NC		 652018-05-17 Nick Clifton <nickc@redhat.com>
66
67 * po/zh_CN.po: Updated simplified Chinese translation.
68
ff329288
TC		 692018-05-16 Tamar Christina <tamar.christina@arm.com>
70
71 PR binutils/23109
72 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
73 * aarch64-dis-2.c: Regenerate.
74
f9830ec1
TC		 752018-05-15 Tamar Christina <tamar.christina@arm.com>
76
77 PR binutils/21446
78 * aarch64-asm.c (opintl.h): Include.
79 (aarch64_ins_sysreg): Enforce read/write constraints.
80 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
81 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
82 (F_REG_READ, F_REG_WRITE): New.
83 * aarch64-opc.c (aarch64_print_operand): Generate notes for
84 AARCH64_OPND_SYSREG.
85 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
86 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
87 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
88 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
89 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
90 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
91 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
92 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
93 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
94 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
95 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
96 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
97 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
98 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
99 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
100 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
101 msr (F_SYS_WRITE), mrs (F_SYS_READ).
102
7d02540a
TC		 1032018-05-15 Tamar Christina <tamar.christina@arm.com>
104
105 PR binutils/21446
106 * aarch64-dis.c (no_notes: New.
107 (parse_aarch64_dis_option): Support notes.
108 (aarch64_decode_insn, print_operands): Likewise.
109 (print_aarch64_disassembler_options): Document notes.
110 * aarch64-opc.c (aarch64_print_operand): Support notes.
111
561a72d4
TC		 1122018-05-15 Tamar Christina <tamar.christina@arm.com>
113
114 PR binutils/21446
115 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
116 and take error struct.
117 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
118 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
119 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
120 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
121 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
122 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
123 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
124 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
125 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
126 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
127 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
128 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
129 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
130 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
131 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
132 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
133 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
134 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
135 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
136 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
137 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
138 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
139 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
140 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
141 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
142 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
143 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
144 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
145 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
146 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
147 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
148 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
149 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
150 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
151 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
152 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
153 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
154 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
155 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
156 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
157 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
158 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
159 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
160 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
161 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
162 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
163 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
164 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
165 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
166 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
167 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
168 (determine_disassembling_preference, aarch64_decode_insn,
169 print_insn_aarch64_word, print_insn_data): Take errors struct.
170 (print_insn_aarch64): Use errors.
171 * aarch64-asm-2.c: Regenerate.
172 * aarch64-dis-2.c: Regenerate.
173 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
174 boolean in aarch64_insert_operan.
175 (print_operand_extractor): Likewise.
176 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
177
1678bd35
FT		 1782018-05-15 Francois H. Theron <francois.theron@netronome.com>
179
180 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
181
06cfb1c8
L		 1822018-05-09 H.J. Lu <hongjiu.lu@intel.com>
183
184 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
185
84f9f8c3
AM		 1862018-05-09 Sebastian Rasmussen <sebras@gmail.com>
187
188 * cr16-opc.c (cr16_instruction): Comment typo fix.
189 * hppa-dis.c (print_insn_hppa): Likewise.
190
e6f372ba
JW		 1912018-05-08 Jim Wilson <jimw@sifive.com>
192
193 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
194 (match_c_slli64, match_srxi_as_c_srxi): New.
195 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
196 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
197 <c.slli, c.srli, c.srai>: Use match_s_slli.
198 <c.slli64, c.srli64, c.srai64>: New.
199
f413a913
AM		 2002018-05-08 Alan Modra <amodra@gmail.com>
201
202 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
203 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
204 partition opcode space for index lookup.
205
a87a6478
PB		 2062018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
207
208 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
209 <insn_length>: ...with this. Update usage.
210 Remove duplicate call to *info->memory_error_func.
211
c0a30a9f
L		 2122018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
213 H.J. Lu <hongjiu.lu@intel.com>
214
215 * i386-dis.c (Gva): New.
216 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
217 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
218 (prefix_table): New instructions (see prefix above).
219 (mod_table): New instructions (see prefix above).
220 (OP_G): Handle va_mode.
221 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
222 CPU_MOVDIR64B_FLAGS.
223 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
224 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
225 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
226 * i386-opc.tbl: Add movidir{i,64b}.
227 * i386-init.h: Regenerated.
228 * i386-tbl.h: Likewise.
229
75c0a438
L		 2302018-05-07 H.J. Lu <hongjiu.lu@intel.com>
231
232 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
233 AddrPrefixOpReg.
234 * i386-opc.h (AddrPrefixOp0): Renamed to ...
235 (AddrPrefixOpReg): This.
236 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
237 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
238
2ceb7719
PB		 2392018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
240
241 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
242 (vle_num_opcodes): Likewise.
243 (spe2_num_opcodes): Likewise.
244 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
245 initialization loop.
246 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
247 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
248 only once.
249
b3ac5c6c
TC		 2502018-05-01 Tamar Christina <tamar.christina@arm.com>
251
252 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
253
fe944acf
FT		 2542018-04-30 Francois H. Theron <francois.theron@netronome.com>
255
256 Makefile.am: Added nfp-dis.c.
257 configure.ac: Added bfd_nfp_arch.
258 disassemble.h: Added print_insn_nfp prototype.
259 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
260 nfp-dis.c: New, for NFP support.
261 po/POTFILES.in: Added nfp-dis.c to the list.
262 Makefile.in: Regenerate.
263 configure: Regenerate.
264
e2195274
JB		 2652018-04-26 Jan Beulich <jbeulich@suse.com>
266
267 * i386-opc.tbl: Fold various non-memory operand AVX512VL
268 templates into their base ones.
269 * i386-tlb.h: Re-generate.
270
59ef5df4
JB		 2712018-04-26 Jan Beulich <jbeulich@suse.com>
272
273 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
274 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
275 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
276 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
277 * i386-init.h: Re-generate.
278
6e041cf4
JB		 2792018-04-26 Jan Beulich <jbeulich@suse.com>
280
281 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
282 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
283 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
284 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
285 comment.
286 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
287 and CpuRegMask.
288 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
289 CpuRegMask: Delete.
290 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
291 cpuregzmm, and cpuregmask.
292 * i386-init.h: Re-generate.
293 * i386-tbl.h: Re-generate.
294
0e0eea78
JB		 2952018-04-26 Jan Beulich <jbeulich@suse.com>
296
297 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
298 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
299 * i386-init.h: Re-generate.
300
2f1bada2
JB		 3012018-04-26 Jan Beulich <jbeulich@suse.com>
302
303 * i386-gen.c (VexImmExt): Delete.
304 * i386-opc.h (VexImmExt, veximmext): Delete.
305 * i386-opc.tbl: Drop all VexImmExt uses.
306 * i386-tlb.h: Re-generate.
307
bacd1457
JB		 3082018-04-25 Jan Beulich <jbeulich@suse.com>
309
310 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
311 register-only forms.
312 * i386-tlb.h: Re-generate.
313
10bba94b
TC		 3142018-04-25 Tamar Christina <tamar.christina@arm.com>
315
316 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
317
c48935d7
IT		 3182018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
319
320 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
321 PREFIX_0F1C.
322 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
323 (cpu_flags): Add CpuCLDEMOTE.
324 * i386-init.h: Regenerate.
325 * i386-opc.h (enum): Add CpuCLDEMOTE,
326 (i386_cpu_flags): Add cpucldemote.
327 * i386-opc.tbl: Add cldemote.
328 * i386-tbl.h: Regenerate.
329
211dc24b
AM		 3302018-04-16 Alan Modra <amodra@gmail.com>
331
332 * Makefile.am: Remove sh5 and sh64 support.
333 * configure.ac: Likewise.
334 * disassemble.c: Likewise.
335 * disassemble.h: Likewise.
336 * sh-dis.c: Likewise.
337 * sh64-dis.c: Delete.
338 * sh64-opc.c: Delete.
339 * sh64-opc.h: Delete.
340 * Makefile.in: Regenerate.
341 * configure: Regenerate.
342 * po/POTFILES.in: Regenerate.
343
a9a4b302
AM		 3442018-04-16 Alan Modra <amodra@gmail.com>
345
346 * Makefile.am: Remove w65 support.
347 * configure.ac: Likewise.
348 * disassemble.c: Likewise.
349 * disassemble.h: Likewise.
350 * w65-dis.c: Delete.
351 * w65-opc.h: Delete.
352 * Makefile.in: Regenerate.
353 * configure: Regenerate.
354 * po/POTFILES.in: Regenerate.
355
04cb01fd
AM		 3562018-04-16 Alan Modra <amodra@gmail.com>
357
358 * configure.ac: Remove we32k support.
359 * configure: Regenerate.
360
c2bf1eec
AM		 3612018-04-16 Alan Modra <amodra@gmail.com>
362
363 * Makefile.am: Remove m88k support.
364 * configure.ac: Likewise.
365 * disassemble.c: Likewise.
366 * disassemble.h: Likewise.
367 * m88k-dis.c: Delete.
368 * Makefile.in: Regenerate.
369 * configure: Regenerate.
370 * po/POTFILES.in: Regenerate.
371
6793974d
AM		 3722018-04-16 Alan Modra <amodra@gmail.com>
373
374 * Makefile.am: Remove i370 support.
375 * configure.ac: Likewise.
376 * disassemble.c: Likewise.
377 * disassemble.h: Likewise.
378 * i370-dis.c: Delete.
379 * i370-opc.c: Delete.
380 * Makefile.in: Regenerate.
381 * configure: Regenerate.
382 * po/POTFILES.in: Regenerate.
383
e82aa794
AM		 3842018-04-16 Alan Modra <amodra@gmail.com>
385
386 * Makefile.am: Remove h8500 support.
387 * configure.ac: Likewise.
388 * disassemble.c: Likewise.
389 * disassemble.h: Likewise.
390 * h8500-dis.c: Delete.
391 * h8500-opc.h: Delete.
392 * Makefile.in: Regenerate.
393 * configure: Regenerate.
394 * po/POTFILES.in: Regenerate.
395
fceadf09
AM		 3962018-04-16 Alan Modra <amodra@gmail.com>
397
398 * configure.ac: Remove tahoe support.
399 * configure: Regenerate.
400
ae1d3843
L		 4012018-04-15 H.J. Lu <hongjiu.lu@intel.com>
402
403 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
404 umwait.
405 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
406 64-bit mode.
407 * i386-tbl.h: Regenerated.
408
de89d0a3
IT		 4092018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
410
411 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
412 PREFIX_MOD_1_0FAE_REG_6.
413 (va_mode): New.
414 (OP_E_register): Use va_mode.
415 * i386-dis-evex.h (prefix_table):
416 New instructions (see prefixes above).
417 * i386-gen.c (cpu_flag_init): Add WAITPKG.
418 (cpu_flags): Likewise.
419 * i386-opc.h (enum): Likewise.
420 (i386_cpu_flags): Likewise.
421 * i386-opc.tbl: Add umonitor, umwait, tpause.
422 * i386-init.h: Regenerate.
423 * i386-tbl.h: Likewise.
424
a8eb42a8
AM		 4252018-04-11 Alan Modra <amodra@gmail.com>
426
427 * opcodes/i860-dis.c: Delete.
428 * opcodes/i960-dis.c: Delete.
429 * Makefile.am: Remove i860 and i960 support.
430 * configure.ac: Likewise.
431 * disassemble.c: Likewise.
432 * disassemble.h: Likewise.
433 * Makefile.in: Regenerate.
434 * configure: Regenerate.
435 * po/POTFILES.in: Regenerate.
436
caf0678c
L		 4372018-04-04 H.J. Lu <hongjiu.lu@intel.com>
438
439 PR binutils/23025
440 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
441 to 0.
442 (print_insn): Clear vex instead of vex.evex.
443
4fb0d2b9
NC		 4442018-04-04 Nick Clifton <nickc@redhat.com>
445
446 * po/es.po: Updated Spanish translation.
447
c39e5b26
JB		 4482018-03-28 Jan Beulich <jbeulich@suse.com>
449
450 * i386-gen.c (opcode_modifiers): Delete VecESize.
451 * i386-opc.h (VecESize): Delete.
452 (struct i386_opcode_modifier): Delete vecesize.
453 * i386-opc.tbl: Drop VecESize.
454 * i386-tlb.h: Re-generate.
455
8e6e0792
JB		 4562018-03-28 Jan Beulich <jbeulich@suse.com>
457
458 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
459 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
460 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
461 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
462 * i386-tlb.h: Re-generate.
463
9f123b91
JB		 4642018-03-28 Jan Beulich <jbeulich@suse.com>
465
466 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
467 Fold AVX512 forms
468 * i386-tlb.h: Re-generate.
469
9646c87b
JB		 4702018-03-28 Jan Beulich <jbeulich@suse.com>
471
472 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
473 (vex_len_table): Drop Y for vcvt*2si.
474 (putop): Replace plain 'Y' handling by abort().
475
c8d59609
NC		 4762018-03-28 Nick Clifton <nickc@redhat.com>
477
478 PR 22988
479 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
480 instructions with only a base address register.
481 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
482 handle AARHC64_OPND_SVE_ADDR_R.
483 (aarch64_print_operand): Likewise.
484 * aarch64-asm-2.c: Regenerate.
485 * aarch64_dis-2.c: Regenerate.
486 * aarch64-opc-2.c: Regenerate.
487
b8c169f3
JB		 4882018-03-22 Jan Beulich <jbeulich@suse.com>
489
490 * i386-opc.tbl: Drop VecESize from register only insn forms and
491 memory forms not allowing broadcast.
492 * i386-tlb.h: Re-generate.
493
96bc132a
JB		 4942018-03-22 Jan Beulich <jbeulich@suse.com>
495
496 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
497 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
498 sha256*): Drop Disp<N>.
499
9f79e886
JB		 5002018-03-22 Jan Beulich <jbeulich@suse.com>
501
502 * i386-dis.c (EbndS, bnd_swap_mode): New.
503 (prefix_table): Use EbndS.
504 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
505 * i386-opc.tbl (bndmov): Move misplaced Load.
506 * i386-tlb.h: Re-generate.
507
d6793fa1
JB		 5082018-03-22 Jan Beulich <jbeulich@suse.com>
509
510 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
511 templates allowing memory operands and folded ones for register
512 only flavors.
513 * i386-tlb.h: Re-generate.
514
f7768225
JB		 5152018-03-22 Jan Beulich <jbeulich@suse.com>
516
517 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
518 256-bit templates. Drop redundant leftover Disp<N>.
519 * i386-tlb.h: Re-generate.
520
0e35537d
JW		 5212018-03-14 Kito Cheng <kito.cheng@gmail.com>
522
523 * riscv-opc.c (riscv_insn_types): New.
524
b4a3689a
NC		 5252018-03-13 Nick Clifton <nickc@redhat.com>
526
527 * po/pt_BR.po: Updated Brazilian Portuguese translation.
528
d3d50934
L		 5292018-03-08 H.J. Lu <hongjiu.lu@intel.com>
530
531 * i386-opc.tbl: Add Optimize to clr.
532 * i386-tbl.h: Regenerated.
533
bd5dea88
L		 5342018-03-08 H.J. Lu <hongjiu.lu@intel.com>
535
536 * i386-gen.c (opcode_modifiers): Remove OldGcc.
537 * i386-opc.h (OldGcc): Removed.
538 (i386_opcode_modifier): Remove oldgcc.
539 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
540 instructions for old (<= 2.8.1) versions of gcc.
541 * i386-tbl.h: Regenerated.
542
e771e7c9
JB		 5432018-03-08 Jan Beulich <jbeulich@suse.com>
544
545 * i386-opc.h (EVEXDYN): New.
546 * i386-opc.tbl: Fold various AVX512VL templates.
547 * i386-tlb.h: Re-generate.
548
ed438a93
JB		 5492018-03-08 Jan Beulich <jbeulich@suse.com>
550
551 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
552 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
553 vpexpandd, vpexpandq): Fold AFX512VF templates.
554 * i386-tlb.h: Re-generate.
555
454172a9
JB		 5562018-03-08 Jan Beulich <jbeulich@suse.com>
557
558 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
559 Fold 128- and 256-bit VEX-encoded templates.
560 * i386-tlb.h: Re-generate.
561
36824150
JB		 5622018-03-08 Jan Beulich <jbeulich@suse.com>
563
564 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
565 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
566 vpexpandd, vpexpandq): Fold AVX512F templates.
567 * i386-tlb.h: Re-generate.
568
e7f5c0a9
JB		 5692018-03-08 Jan Beulich <jbeulich@suse.com>
570
571 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
572 64-bit templates. Drop Disp<N>.
573 * i386-tlb.h: Re-generate.
574
25a4277f
JB		 5752018-03-08 Jan Beulich <jbeulich@suse.com>
576
577 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
578 and 256-bit templates.
579 * i386-tlb.h: Re-generate.
580
d2224064
JB		 5812018-03-08 Jan Beulich <jbeulich@suse.com>
582
583 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
584 * i386-tlb.h: Re-generate.
585
1b193f0b
JB		 5862018-03-08 Jan Beulich <jbeulich@suse.com>
587
588 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
589 Drop NoAVX.
590 * i386-tlb.h: Re-generate.
591
f2f6a710
JB		 5922018-03-08 Jan Beulich <jbeulich@suse.com>
593
594 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
595 * i386-tlb.h: Re-generate.
596
38e314eb
JB		 5972018-03-08 Jan Beulich <jbeulich@suse.com>
598
599 * i386-gen.c (opcode_modifiers): Delete FloatD.
600 * i386-opc.h (FloatD): Delete.
601 (struct i386_opcode_modifier): Delete floatd.
602 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
603 FloatD by D.
604 * i386-tlb.h: Re-generate.
605
d53e6b98
JB		 6062018-03-08 Jan Beulich <jbeulich@suse.com>
607
608 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
609
2907c2f5
JB		 6102018-03-08 Jan Beulich <jbeulich@suse.com>
611
612 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
613 * i386-tlb.h: Re-generate.
614
73053c1f
JB		 6152018-03-08 Jan Beulich <jbeulich@suse.com>
616
617 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
618 forms.
619 * i386-tlb.h: Re-generate.
620
52fe4420
AM		 6212018-03-07 Alan Modra <amodra@gmail.com>
622
623 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
624 bfd_arch_rs6000.
625 * disassemble.h (print_insn_rs6000): Delete.
626 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
627 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
628 (print_insn_rs6000): Delete.
629
a6743a54
AM		 6302018-03-03 Alan Modra <amodra@gmail.com>
631
632 * sysdep.h (opcodes_error_handler): Define.
633 (_bfd_error_handler): Declare.
634 * Makefile.am: Remove stray #.
635 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
636 EDIT" comment.
637 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
638 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
639 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
640 opcodes_error_handler to print errors. Standardize error messages.
641 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
642 and include opintl.h.
643 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
644 * i386-gen.c: Standardize error messages.
645 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
646 * Makefile.in: Regenerate.
647 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
648 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
649 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
650 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
651 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
652 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
653 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
654 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
655 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
656 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
657 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
658 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
659 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
660
8305403a
L		 6612018-03-01 H.J. Lu <hongjiu.lu@intel.com>
662
663 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
664 vpsub[bwdq] instructions.
665 * i386-tbl.h: Regenerated.
666
e184813f
AM		 6672018-03-01 Alan Modra <amodra@gmail.com>
668
669 * configure.ac (ALL_LINGUAS): Sort.
670 * configure: Regenerate.
671
5b616bef
TP		 6722018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
673
674 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
675 macro by assignements.
676
b6f8c7c4
L		 6772018-02-27 H.J. Lu <hongjiu.lu@intel.com>
678
679 PR gas/22871
680 * i386-gen.c (opcode_modifiers): Add Optimize.
681 * i386-opc.h (Optimize): New enum.
682 (i386_opcode_modifier): Add optimize.
683 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
684 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
685 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
686 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
687 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
688 vpxord and vpxorq.
689 * i386-tbl.h: Regenerated.
690
e95b887f
AM		 6912018-02-26 Alan Modra <amodra@gmail.com>
692
693 * crx-dis.c (getregliststring): Allocate a large enough buffer
694 to silence false positive gcc8 warning.
695
0bccfb29
JW		 6962018-02-22 Shea Levy <shea@shealevy.com>
697
698 * disassemble.c (ARCH_riscv): Define if ARCH_all.
699
6b6b6807
L		 7002018-02-22 H.J. Lu <hongjiu.lu@intel.com>
701
702 * i386-opc.tbl: Add {rex},
703 * i386-tbl.h: Regenerated.
704
75f31665
MR		 7052018-02-20 Maciej W. Rozycki <macro@mips.com>
706
707 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
708 (mips16_opcodes): Replace `M' with `m' for "restore".
709
e207bc53
TP		 7102018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
711
712 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
713
87993319
MR		 7142018-02-13 Maciej W. Rozycki <macro@mips.com>
715
716 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
717 variable to `function_index'.
718
68d20676
NC		 7192018-02-13 Nick Clifton <nickc@redhat.com>
720
721 PR 22823
722 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
723 about truncation of printing.
724
d2159fdc
HW		 7252018-02-12 Henry Wong <henry@stuffedcow.net>
726
727 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
728
f174ef9f
NC		 7292018-02-05 Nick Clifton <nickc@redhat.com>
730
731 * po/pt_BR.po: Updated Brazilian Portuguese translation.
732
be3a8dca
IT		 7332018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
734
735 * i386-dis.c (enum): Add pconfig.
736 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
737 (cpu_flags): Add CpuPCONFIG.
738 * i386-opc.h (enum): Add CpuPCONFIG.
739 (i386_cpu_flags): Add cpupconfig.
740 * i386-opc.tbl: Add PCONFIG instruction.
741 * i386-init.h: Regenerate.
742 * i386-tbl.h: Likewise.
743
3233d7d0
IT		 7442018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
745
746 * i386-dis.c (enum): Add PREFIX_0F09.
747 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
748 (cpu_flags): Add CpuWBNOINVD.
749 * i386-opc.h (enum): Add CpuWBNOINVD.
750 (i386_cpu_flags): Add cpuwbnoinvd.
751 * i386-opc.tbl: Add WBNOINVD instruction.
752 * i386-init.h: Regenerate.
753 * i386-tbl.h: Likewise.
754
e925c834
JW		 7552018-01-17 Jim Wilson <jimw@sifive.com>
756
757 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
758
d777820b
IT		 7592018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
760
761 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
762 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
763 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
764 (cpu_flags): Add CpuIBT, CpuSHSTK.
765 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
766 (i386_cpu_flags): Add cpuibt, cpushstk.
767 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
768 * i386-init.h: Regenerate.
769 * i386-tbl.h: Likewise.
770
f6efed01
NC		 7712018-01-16 Nick Clifton <nickc@redhat.com>
772
773 * po/pt_BR.po: Updated Brazilian Portugese translation.
774 * po/de.po: Updated German translation.
775
2721d702
JW		 7762018-01-15 Jim Wilson <jimw@sifive.com>
777
778 * riscv-opc.c (match_c_nop): New.
779 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
780
616dcb87
NC		 7812018-01-15 Nick Clifton <nickc@redhat.com>
782
783 * po/uk.po: Updated Ukranian translation.
784
3957a496
NC		 7852018-01-13 Nick Clifton <nickc@redhat.com>
786
787 * po/opcodes.pot: Regenerated.
788
769c7ea5
NC		 7892018-01-13 Nick Clifton <nickc@redhat.com>
790
791 * configure: Regenerate.
792
faf766e3
NC		 7932018-01-13 Nick Clifton <nickc@redhat.com>
794
795 2.30 branch created.
796
888a89da
IT		 7972018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
798
799 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
800 * i386-tbl.h: Regenerate.
801
cbda583a
JB		 8022018-01-10 Jan Beulich <jbeulich@suse.com>
803
804 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
805 * i386-tbl.h: Re-generate.
806
c9e92278
JB		 8072018-01-10 Jan Beulich <jbeulich@suse.com>
808
809 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
810 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
811 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
812 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
813 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
814 Disp8MemShift of AVX512VL forms.
815 * i386-tbl.h: Re-generate.
816
35fd2b2b
JW		 8172018-01-09 Jim Wilson <jimw@sifive.com>
818
819 * riscv-dis.c (maybe_print_address): If base_reg is zero,
820 then the hi_addr value is zero.
821
91d8b670
JG		 8222018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
823
824 * arm-dis.c (arm_opcodes): Add csdb.
825 (thumb32_opcodes): Add csdb.
826
be2e7d95
JG		 8272018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
828
829 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
830 * aarch64-asm-2.c: Regenerate.
831 * aarch64-dis-2.c: Regenerate.
832 * aarch64-opc-2.c: Regenerate.
833
704a705d
L		 8342018-01-08 H.J. Lu <hongjiu.lu@intel.com>
835
836 PR gas/22681
837 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
838 Remove AVX512 vmovd with 64-bit operands.
839 * i386-tbl.h: Regenerated.
840
35eeb78f
JW		 8412018-01-05 Jim Wilson <jimw@sifive.com>
842
843 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
844 jalr.
845
219d1afa
AM		 8462018-01-03 Alan Modra <amodra@gmail.com>
847
848 Update year range in copyright notice of all files.
849
1508bbf5
JB		 8502018-01-02 Jan Beulich <jbeulich@suse.com>
851
852 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
853 and OPERAND_TYPE_REGZMM entries.
854
1e563868 855For older changes see ChangeLog-2017
3499769a 856\f
1e563868 857Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 858
859Copying and distribution of this file, with or without modification,
860are permitted in any medium without royalty provided the copyright
861notice and this notice are preserved.
862
863Local Variables:
864mode: change-log
865left-margin: 8
866fill-column: 74
867version-control: never
868End:
GDB Binutils - Deliverables
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