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[PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registers
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
a97330e7
SD		 12018-10-09 Sudakshina Das <sudi.das@arm.com>
2
3 * aarch64-opc.c (aarch64_sys_regs): New entries for
4 scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
5 (aarch64_sys_reg_supported_p): New checks for above.
6
ff605452
SD		 72018-10-09 Sudakshina Das <sudi.das@arm.com>
8
9 * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
10 (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
11 with the hint immediate.
12 * aarch64-opc.c (aarch64_hint_options): New entries for
13 c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
14 (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
15 while checking for HINT_OPD_F_NOPRINT flag.
16 * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
17 extract value.
18 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
19 (aarch64_opcode_table): Add entry for BTI.
20 (AARCH64_OPERANDS): Add new description for BTI targets.
21 * aarch64-asm-2.c: Regenerate.
22 * aarch64-dis-2.c: Regenerate.
23 * aarch64-opc-2.c: Regenerate.
24
af4bcb4c
SD		 252018-10-09 Sudakshina Das <sudi.das@arm.com>
26
27 * aarch64-opc.c (aarch64_sys_regs): New entries for
28 rndr and rndrrs.
29 (aarch64_sys_reg_supported_p): New check for above.
30
3fd229a4
SD		 312018-10-09 Sudakshina Das <sudi.das@arm.com>
32
33 * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
34 (aarch64_sys_ins_reg_supported_p): New check for above.
35
2ac435d4
SD		 362018-10-09 Sudakshina Das <sudi.das@arm.com>
37
38 * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
39 AARCH64_OPND_SYSREG_SR.
40 * aarch64-opc.c (aarch64_print_operand): Likewise.
41 (aarch64_sys_regs_sr): Define table.
42 (aarch64_sys_ins_reg_supported_p): Check for RCTX with
43 AARCH64_FEATURE_PREDRES.
44 * aarch64-tbl.h (aarch64_feature_predres): New.
45 (PREDRES, PREDRES_INSN): New.
46 (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
47 (AARCH64_OPERANDS): Add new description for SYSREG_SR.
48 * aarch64-asm-2.c: Regenerate.
49 * aarch64-dis-2.c: Regenerate.
50 * aarch64-opc-2.c: Regenerate.
51
68dfbb92
SD		 522018-10-09 Sudakshina Das <sudi.das@arm.com>
53
54 * aarch64-tbl.h (aarch64_feature_sb): New.
55 (SB, SB_INSN): New.
56 (aarch64_opcode_table): Add entry for sb.
57 * aarch64-asm-2.c: Regenerate.
58 * aarch64-dis-2.c: Regenerate.
59 * aarch64-opc-2.c: Regenerate.
60
13c60ad7
SD		 612018-10-09 Sudakshina Das <sudi.das@arm.com>
62
63 * aarch64-tbl.h (aarch64_feature_flagmanip): New.
64 (aarch64_feature_frintts): New.
65 (FLAGMANIP, FRINTTS): New.
66 (aarch64_opcode_table): Add entries for xaflag, axflag
67 and frint[32,64][x,z] instructions.
68 * aarch64-asm-2.c: Regenerate.
69 * aarch64-dis-2.c: Regenerate.
70 * aarch64-opc-2.c: Regenerate.
71
70d56181
SD		 722018-10-09 Sudakshina Das <sudi.das@arm.com>
73
74 * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
75 (ARMV8_5, V8_5_INSN): New.
76
780f601c
TC		 772018-10-08 Tamar Christina <tamar.christina@arm.com>
78
79 * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
80
a4e78aa5
L		 812018-10-05 H.J. Lu <hongjiu.lu@intel.com>
82
83 * i386-dis.c (rm_table): Add enclv.
84 * i386-opc.tbl: Add enclv.
85 * i386-tbl.h: Regenerated.
86
7fadb25d
SD		 872018-10-05 Sudakshina Das <sudi.das@arm.com>
88
89 * arm-dis.c (arm_opcodes): Add sb.
90 (thumb32_opcodes): Likewise.
91
07f5f4c6
RH		 922018-10-05 Richard Henderson <rth@twiddle.net>
93 Stafford Horne <shorne@gmail.com>
94
95 * or1k-desc.c: Regenerate.
96 * or1k-desc.h: Regenerate.
97 * or1k-opc.c: Regenerate.
98 * or1k-opc.h: Regenerate.
99 * or1k-opinst.c: Regenerate.
100
c8e98e36
SH		 1012018-10-05 Richard Henderson <rth@twiddle.net>
102
103 * or1k-asm.c: Regenerated.
104 * or1k-desc.c: Regenerated.
105 * or1k-desc.h: Regenerated.
106 * or1k-dis.c: Regenerated.
107 * or1k-ibld.c: Regenerated.
108 * or1k-opc.c: Regenerated.
109 * or1k-opc.h: Regenerated.
110 * or1k-opinst.c: Regenerated.
111
1c4f3780
RH		 1122018-10-05 Richard Henderson <rth@twiddle.net>
113
114 * or1k-asm.c: Regenerate.
115
bde90be2
TC		 1162018-10-03 Tamar Christina <tamar.christina@arm.com>
117
118 * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
119 * aarch64-dis.c (print_operands): Refactor to take notes.
120 (print_verifier_notes): New.
121 (print_aarch64_insn): Apply constraint verifier.
122 (print_insn_aarch64_word): Update call to print_aarch64_insn.
123 * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
124
a68f4cd2
TC		 1252018-10-03 Tamar Christina <tamar.christina@arm.com>
126
127 * aarch64-opc.c (init_insn_block): New.
128 (verify_constraints, aarch64_is_destructive_by_operands): New.
129 * aarch64-opc.h (verify_constraints): New.
130
755b748f
TC		 1312018-10-03 Tamar Christina <tamar.christina@arm.com>
132
133 * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
134 * aarch64-opc.c (verify_ldpsw): Update arguments.
135
1d482394
TC		 1362018-10-03 Tamar Christina <tamar.christina@arm.com>
137
138 * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
139 (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
140
7e84b55d
TC		 1412018-10-03 Tamar Christina <tamar.christina@arm.com>
142
143 * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
144 * aarch64-dis.c (insn_sequence): New.
145
eae424ae
TC		 1462018-10-03 Tamar Christina <tamar.christina@arm.com>
147
148 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
149 _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
150 _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
151 V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
152 constraints.
153 (_SVE_INSNC): New.
154 (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
155 constraints.
156 (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
157 F_SCAN flags.
158 (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
159 sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
160 sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
161 sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
162 uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
163 uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
164 C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
165
64a336ac
PD		 1662018-10-02 Palmer Dabbelt <palmer@sifive.com>
167
168 * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
169
6031ac35
SL		 1702018-09-23 Sandra Loosemore <sandra@codesourcery.com>
171
172 * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
173 are used when extracting signed fields and converting them to
174 potentially 64-bit types.
175
f24ff6e9
SM		 1762018-09-21 Simon Marchi <simon.marchi@ericsson.com>
177
178 * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
179 * Makefile.in: Re-generate.
180 * aclocal.m4: Re-generate.
181 * configure: Re-generate.
182 * configure.ac: Remove check for -Wno-missing-field-initializers.
183 * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
184 (csky_v2_opcodes): Likewise.
185
53b6d6f5
MR		 1862018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
187
188 * arc-nps400-tbl.h: Append `ull' to large constants throughout.
189
fbaf61ad
NC		 1902018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
191
192 * nds32-asm.c (operand_fields): Remove the unused fields.
193 (nds32_opcodes): Remove the unused instructions.
194 * nds32-dis.c (nds32_ex9_info): Removed.
195 (nds32_parse_opcode): Updated.
196 (print_insn_nds32): Likewise.
197 * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
198 (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
199 (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
200 build_opcode_hash_table): New functions.
201 (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
202 nds32_opcode_table): New.
203 (hw_ktabs): Declare it to a pointer rather than an array.
204 (build_hash_table): Removed.
205 * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
206 SYN_ROPT and upadte HW_GPR and HW_INT.
207 * nds32-dis.c (keywords): Remove const.
208 (match_field): New function.
209 (nds32_parse_opcode): Updated.
210 * disassemble.c (disassemble_init_for_target):
211 Add disassemble_init_nds32.
212 * nds32-dis.c (eum map_type): New.
213 (nds32_private_data): Likewise.
214 (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
215 nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
216 (print_insn_nds32): Updated.
217 * nds32-asm.c (parse_aext_reg): Add new parameter.
218 (parse_re, parse_re2, parse_aext_reg): Only reduced registers
219 are allowed to use.
220 All callers changed.
221 * nds32-asm.c (keyword_usr, keyword_sr): Updated.
222 (operand_fields): Add new fields.
223 (nds32_opcodes): Add new instructions.
224 (keyword_aridxi_mx): New keyword.
225 * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
226 and NASM_ATTR_ZOL.
227 (ALU2_1, ALU2_2, ALU2_3): New macros.
228 * nds32-dis.c (nds32_filter_unknown_insn): Updated.
229
4e2b1898
JW		 2302018-09-17 Kito Cheng <kito@andestech.com>
231
232 * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
233
04e2a182
L		 2342018-09-17 H.J. Lu <hongjiu.lu@intel.com>
235
236 PR gas/23670
237 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
238 EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
239 (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
240 (EVEX_LEN_0F7E_P_1): Likewise.
241 (EVEX_LEN_0F7E_P_2): Likewise.
242 (EVEX_LEN_0FD6_P_2): Likewise.
243 * i386-dis.c (USE_EVEX_LEN_TABLE): New.
244 (EVEX_LEN_TABLE): Likewise.
245 (EVEX_LEN_0F6E_P_2): New enum.
246 (EVEX_LEN_0F7E_P_1): Likewise.
247 (EVEX_LEN_0F7E_P_2): Likewise.
248 (EVEX_LEN_0FD6_P_2): Likewise.
249 (evex_len_table): New.
250 (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
251 * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
252 * i386-tbl.h: Regenerated.
253
d5f787c2
L		 2542018-09-17 H.J. Lu <hongjiu.lu@intel.com>
255
256 PR gas/23665
257 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
258 VEX_LEN_0F7E_P_2 entries.
259 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
260 * i386-tbl.h: Regenerated.
261
ec6f095a
L		 2622018-09-17 H.J. Lu <hongjiu.lu@intel.com>
263
264 * i386-dis.c (VZERO_Fixup): Removed.
265 (VZERO): Likewise.
266 (VEX_LEN_0F10_P_1): Likewise.
267 (VEX_LEN_0F10_P_3): Likewise.
268 (VEX_LEN_0F11_P_1): Likewise.
269 (VEX_LEN_0F11_P_3): Likewise.
270 (VEX_LEN_0F2E_P_0): Likewise.
271 (VEX_LEN_0F2E_P_2): Likewise.
272 (VEX_LEN_0F2F_P_0): Likewise.
273 (VEX_LEN_0F2F_P_2): Likewise.
274 (VEX_LEN_0F51_P_1): Likewise.
275 (VEX_LEN_0F51_P_3): Likewise.
276 (VEX_LEN_0F52_P_1): Likewise.
277 (VEX_LEN_0F53_P_1): Likewise.
278 (VEX_LEN_0F58_P_1): Likewise.
279 (VEX_LEN_0F58_P_3): Likewise.
280 (VEX_LEN_0F59_P_1): Likewise.
281 (VEX_LEN_0F59_P_3): Likewise.
282 (VEX_LEN_0F5A_P_1): Likewise.
283 (VEX_LEN_0F5A_P_3): Likewise.
284 (VEX_LEN_0F5C_P_1): Likewise.
285 (VEX_LEN_0F5C_P_3): Likewise.
286 (VEX_LEN_0F5D_P_1): Likewise.
287 (VEX_LEN_0F5D_P_3): Likewise.
288 (VEX_LEN_0F5E_P_1): Likewise.
289 (VEX_LEN_0F5E_P_3): Likewise.
290 (VEX_LEN_0F5F_P_1): Likewise.
291 (VEX_LEN_0F5F_P_3): Likewise.
292 (VEX_LEN_0FC2_P_1): Likewise.
293 (VEX_LEN_0FC2_P_3): Likewise.
294 (VEX_LEN_0F3A0A_P_2): Likewise.
295 (VEX_LEN_0F3A0B_P_2): Likewise.
296 (VEX_W_0F10_P_0): Likewise.
297 (VEX_W_0F10_P_1): Likewise.
298 (VEX_W_0F10_P_2): Likewise.
299 (VEX_W_0F10_P_3): Likewise.
300 (VEX_W_0F11_P_0): Likewise.
301 (VEX_W_0F11_P_1): Likewise.
302 (VEX_W_0F11_P_2): Likewise.
303 (VEX_W_0F11_P_3): Likewise.
304 (VEX_W_0F12_P_0_M_0): Likewise.
305 (VEX_W_0F12_P_0_M_1): Likewise.
306 (VEX_W_0F12_P_1): Likewise.
307 (VEX_W_0F12_P_2): Likewise.
308 (VEX_W_0F12_P_3): Likewise.
309 (VEX_W_0F13_M_0): Likewise.
310 (VEX_W_0F14): Likewise.
311 (VEX_W_0F15): Likewise.
312 (VEX_W_0F16_P_0_M_0): Likewise.
313 (VEX_W_0F16_P_0_M_1): Likewise.
314 (VEX_W_0F16_P_1): Likewise.
315 (VEX_W_0F16_P_2): Likewise.
316 (VEX_W_0F17_M_0): Likewise.
317 (VEX_W_0F28): Likewise.
318 (VEX_W_0F29): Likewise.
319 (VEX_W_0F2B_M_0): Likewise.
320 (VEX_W_0F2E_P_0): Likewise.
321 (VEX_W_0F2E_P_2): Likewise.
322 (VEX_W_0F2F_P_0): Likewise.
323 (VEX_W_0F2F_P_2): Likewise.
324 (VEX_W_0F50_M_0): Likewise.
325 (VEX_W_0F51_P_0): Likewise.
326 (VEX_W_0F51_P_1): Likewise.
327 (VEX_W_0F51_P_2): Likewise.
328 (VEX_W_0F51_P_3): Likewise.
329 (VEX_W_0F52_P_0): Likewise.
330 (VEX_W_0F52_P_1): Likewise.
331 (VEX_W_0F53_P_0): Likewise.
332 (VEX_W_0F53_P_1): Likewise.
333 (VEX_W_0F58_P_0): Likewise.
334 (VEX_W_0F58_P_1): Likewise.
335 (VEX_W_0F58_P_2): Likewise.
336 (VEX_W_0F58_P_3): Likewise.
337 (VEX_W_0F59_P_0): Likewise.
338 (VEX_W_0F59_P_1): Likewise.
339 (VEX_W_0F59_P_2): Likewise.
340 (VEX_W_0F59_P_3): Likewise.
341 (VEX_W_0F5A_P_0): Likewise.
342 (VEX_W_0F5A_P_1): Likewise.
343 (VEX_W_0F5A_P_3): Likewise.
344 (VEX_W_0F5B_P_0): Likewise.
345 (VEX_W_0F5B_P_1): Likewise.
346 (VEX_W_0F5B_P_2): Likewise.
347 (VEX_W_0F5C_P_0): Likewise.
348 (VEX_W_0F5C_P_1): Likewise.
349 (VEX_W_0F5C_P_2): Likewise.
350 (VEX_W_0F5C_P_3): Likewise.
351 (VEX_W_0F5D_P_0): Likewise.
352 (VEX_W_0F5D_P_1): Likewise.
353 (VEX_W_0F5D_P_2): Likewise.
354 (VEX_W_0F5D_P_3): Likewise.
355 (VEX_W_0F5E_P_0): Likewise.
356 (VEX_W_0F5E_P_1): Likewise.
357 (VEX_W_0F5E_P_2): Likewise.
358 (VEX_W_0F5E_P_3): Likewise.
359 (VEX_W_0F5F_P_0): Likewise.
360 (VEX_W_0F5F_P_1): Likewise.
361 (VEX_W_0F5F_P_2): Likewise.
362 (VEX_W_0F5F_P_3): Likewise.
363 (VEX_W_0F60_P_2): Likewise.
364 (VEX_W_0F61_P_2): Likewise.
365 (VEX_W_0F62_P_2): Likewise.
366 (VEX_W_0F63_P_2): Likewise.
367 (VEX_W_0F64_P_2): Likewise.
368 (VEX_W_0F65_P_2): Likewise.
369 (VEX_W_0F66_P_2): Likewise.
370 (VEX_W_0F67_P_2): Likewise.
371 (VEX_W_0F68_P_2): Likewise.
372 (VEX_W_0F69_P_2): Likewise.
373 (VEX_W_0F6A_P_2): Likewise.
374 (VEX_W_0F6B_P_2): Likewise.
375 (VEX_W_0F6C_P_2): Likewise.
376 (VEX_W_0F6D_P_2): Likewise.
377 (VEX_W_0F6F_P_1): Likewise.
378 (VEX_W_0F6F_P_2): Likewise.
379 (VEX_W_0F70_P_1): Likewise.
380 (VEX_W_0F70_P_2): Likewise.
381 (VEX_W_0F70_P_3): Likewise.
382 (VEX_W_0F71_R_2_P_2): Likewise.
383 (VEX_W_0F71_R_4_P_2): Likewise.
384 (VEX_W_0F71_R_6_P_2): Likewise.
385 (VEX_W_0F72_R_2_P_2): Likewise.
386 (VEX_W_0F72_R_4_P_2): Likewise.
387 (VEX_W_0F72_R_6_P_2): Likewise.
388 (VEX_W_0F73_R_2_P_2): Likewise.
389 (VEX_W_0F73_R_3_P_2): Likewise.
390 (VEX_W_0F73_R_6_P_2): Likewise.
391 (VEX_W_0F73_R_7_P_2): Likewise.
392 (VEX_W_0F74_P_2): Likewise.
393 (VEX_W_0F75_P_2): Likewise.
394 (VEX_W_0F76_P_2): Likewise.
395 (VEX_W_0F77_P_0): Likewise.
396 (VEX_W_0F7C_P_2): Likewise.
397 (VEX_W_0F7C_P_3): Likewise.
398 (VEX_W_0F7D_P_2): Likewise.
399 (VEX_W_0F7D_P_3): Likewise.
400 (VEX_W_0F7E_P_1): Likewise.
401 (VEX_W_0F7F_P_1): Likewise.
402 (VEX_W_0F7F_P_2): Likewise.
403 (VEX_W_0FAE_R_2_M_0): Likewise.
404 (VEX_W_0FAE_R_3_M_0): Likewise.
405 (VEX_W_0FC2_P_0): Likewise.
406 (VEX_W_0FC2_P_1): Likewise.
407 (VEX_W_0FC2_P_2): Likewise.
408 (VEX_W_0FC2_P_3): Likewise.
409 (VEX_W_0FD0_P_2): Likewise.
410 (VEX_W_0FD0_P_3): Likewise.
411 (VEX_W_0FD1_P_2): Likewise.
412 (VEX_W_0FD2_P_2): Likewise.
413 (VEX_W_0FD3_P_2): Likewise.
414 (VEX_W_0FD4_P_2): Likewise.
415 (VEX_W_0FD5_P_2): Likewise.
416 (VEX_W_0FD6_P_2): Likewise.
417 (VEX_W_0FD7_P_2_M_1): Likewise.
418 (VEX_W_0FD8_P_2): Likewise.
419 (VEX_W_0FD9_P_2): Likewise.
420 (VEX_W_0FDA_P_2): Likewise.
421 (VEX_W_0FDB_P_2): Likewise.
422 (VEX_W_0FDC_P_2): Likewise.
423 (VEX_W_0FDD_P_2): Likewise.
424 (VEX_W_0FDE_P_2): Likewise.
425 (VEX_W_0FDF_P_2): Likewise.
426 (VEX_W_0FE0_P_2): Likewise.
427 (VEX_W_0FE1_P_2): Likewise.
428 (VEX_W_0FE2_P_2): Likewise.
429 (VEX_W_0FE3_P_2): Likewise.
430 (VEX_W_0FE4_P_2): Likewise.
431 (VEX_W_0FE5_P_2): Likewise.
432 (VEX_W_0FE6_P_1): Likewise.
433 (VEX_W_0FE6_P_2): Likewise.
434 (VEX_W_0FE6_P_3): Likewise.
435 (VEX_W_0FE7_P_2_M_0): Likewise.
436 (VEX_W_0FE8_P_2): Likewise.
437 (VEX_W_0FE9_P_2): Likewise.
438 (VEX_W_0FEA_P_2): Likewise.
439 (VEX_W_0FEB_P_2): Likewise.
440 (VEX_W_0FEC_P_2): Likewise.
441 (VEX_W_0FED_P_2): Likewise.
442 (VEX_W_0FEE_P_2): Likewise.
443 (VEX_W_0FEF_P_2): Likewise.
444 (VEX_W_0FF0_P_3_M_0): Likewise.
445 (VEX_W_0FF1_P_2): Likewise.
446 (VEX_W_0FF2_P_2): Likewise.
447 (VEX_W_0FF3_P_2): Likewise.
448 (VEX_W_0FF4_P_2): Likewise.
449 (VEX_W_0FF5_P_2): Likewise.
450 (VEX_W_0FF6_P_2): Likewise.
451 (VEX_W_0FF7_P_2): Likewise.
452 (VEX_W_0FF8_P_2): Likewise.
453 (VEX_W_0FF9_P_2): Likewise.
454 (VEX_W_0FFA_P_2): Likewise.
455 (VEX_W_0FFB_P_2): Likewise.
456 (VEX_W_0FFC_P_2): Likewise.
457 (VEX_W_0FFD_P_2): Likewise.
458 (VEX_W_0FFE_P_2): Likewise.
459 (VEX_W_0F3800_P_2): Likewise.
460 (VEX_W_0F3801_P_2): Likewise.
461 (VEX_W_0F3802_P_2): Likewise.
462 (VEX_W_0F3803_P_2): Likewise.
463 (VEX_W_0F3804_P_2): Likewise.
464 (VEX_W_0F3805_P_2): Likewise.
465 (VEX_W_0F3806_P_2): Likewise.
466 (VEX_W_0F3807_P_2): Likewise.
467 (VEX_W_0F3808_P_2): Likewise.
468 (VEX_W_0F3809_P_2): Likewise.
469 (VEX_W_0F380A_P_2): Likewise.
470 (VEX_W_0F380B_P_2): Likewise.
471 (VEX_W_0F3817_P_2): Likewise.
472 (VEX_W_0F381C_P_2): Likewise.
473 (VEX_W_0F381D_P_2): Likewise.
474 (VEX_W_0F381E_P_2): Likewise.
475 (VEX_W_0F3820_P_2): Likewise.
476 (VEX_W_0F3821_P_2): Likewise.
477 (VEX_W_0F3822_P_2): Likewise.
478 (VEX_W_0F3823_P_2): Likewise.
479 (VEX_W_0F3824_P_2): Likewise.
480 (VEX_W_0F3825_P_2): Likewise.
481 (VEX_W_0F3828_P_2): Likewise.
482 (VEX_W_0F3829_P_2): Likewise.
483 (VEX_W_0F382A_P_2_M_0): Likewise.
484 (VEX_W_0F382B_P_2): Likewise.
485 (VEX_W_0F3830_P_2): Likewise.
486 (VEX_W_0F3831_P_2): Likewise.
487 (VEX_W_0F3832_P_2): Likewise.
488 (VEX_W_0F3833_P_2): Likewise.
489 (VEX_W_0F3834_P_2): Likewise.
490 (VEX_W_0F3835_P_2): Likewise.
491 (VEX_W_0F3837_P_2): Likewise.
492 (VEX_W_0F3838_P_2): Likewise.
493 (VEX_W_0F3839_P_2): Likewise.
494 (VEX_W_0F383A_P_2): Likewise.
495 (VEX_W_0F383B_P_2): Likewise.
496 (VEX_W_0F383C_P_2): Likewise.
497 (VEX_W_0F383D_P_2): Likewise.
498 (VEX_W_0F383E_P_2): Likewise.
499 (VEX_W_0F383F_P_2): Likewise.
500 (VEX_W_0F3840_P_2): Likewise.
501 (VEX_W_0F3841_P_2): Likewise.
502 (VEX_W_0F38DB_P_2): Likewise.
503 (VEX_W_0F3A08_P_2): Likewise.
504 (VEX_W_0F3A09_P_2): Likewise.
505 (VEX_W_0F3A0A_P_2): Likewise.
506 (VEX_W_0F3A0B_P_2): Likewise.
507 (VEX_W_0F3A0C_P_2): Likewise.
508 (VEX_W_0F3A0D_P_2): Likewise.
509 (VEX_W_0F3A0E_P_2): Likewise.
510 (VEX_W_0F3A0F_P_2): Likewise.
511 (VEX_W_0F3A21_P_2): Likewise.
512 (VEX_W_0F3A40_P_2): Likewise.
513 (VEX_W_0F3A41_P_2): Likewise.
514 (VEX_W_0F3A42_P_2): Likewise.
515 (VEX_W_0F3A62_P_2): Likewise.
516 (VEX_W_0F3A63_P_2): Likewise.
517 (VEX_W_0F3ADF_P_2): Likewise.
518 (VEX_LEN_0F77_P_0): New.
519 (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
520 PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
521 PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
522 PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
523 PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
524 PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
525 PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
526 PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
527 PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
528 PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
529 PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
530 PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
531 PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
532 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
533 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
534 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
535 PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
536 PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
537 PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
538 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
539 PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
540 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
541 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
542 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
543 PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
544 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
545 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
546 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
547 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
548 PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
549 PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
550 PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
551 PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
552 PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
553 PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
554 PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
555 PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
556 PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
557 PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
558 PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
559 PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
560 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
561 PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
562 PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
563 PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
564 PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
565 PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
566 PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
567 PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
568 (vex_table): Update VEX 0F28 and 0F29 entries.
569 (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
570 VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
571 VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
572 VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
573 VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
574 VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
575 VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
576 VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
577 VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
578 VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
579 VEX_LEN_0F3A0B_P_2 entries.
580 (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
581 VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
582 VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
583 VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
584 VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
585 VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
586 VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
587 VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
588 VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
589 VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
590 VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
591 VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
592 VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
593 VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
594 VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
595 VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
596 VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
597 VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
598 VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
599 VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
600 VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
601 VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
602 VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
603 VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
604 VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
605 VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
606 VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
607 VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
608 VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
609 VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
610 VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
611 VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
612 VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
613 VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
614 VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
615 VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
616 VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
617 VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
618 VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
619 VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
620 VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
621 VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
622 VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
623 VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
624 VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
625 VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
626 VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
627 VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
628 VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
629 VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
630 VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
631 VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
632 VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
633 VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
634 VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
635 VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
636 VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
637 VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
638 VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
639 VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
640 VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
641 VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
642 VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
643 VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
644 VEX_W_0F3ADF_P_2 entries.
645 (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
646 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
647 MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
648
6fa52824
L		 6492018-09-17 H.J. Lu <hongjiu.lu@intel.com>
650
651 * i386-opc.tbl (VexWIG): New.
652 Replace VexW=3 with VexWIG.
653
db4cc665
L		 6542018-09-15 H.J. Lu <hongjiu.lu@intel.com>
655
656 * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
657 * i386-tbl.h: Regenerated.
658
3c374143
L		 6592018-09-15 H.J. Lu <hongjiu.lu@intel.com>
660
661 PR gas/23665
662 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
663 VEX_LEN_0FD6_P_2 entries.
664 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
665 * i386-tbl.h: Regenerated.
666
6865c043
L		 6672018-09-14 H.J. Lu <hongjiu.lu@intel.com>
668
669 PR gas/23642
670 * i386-opc.h (VEXWIG): New.
671 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
672 * i386-tbl.h: Regenerated.
673
70df6fc9
L		 6742018-09-14 H.J. Lu <hongjiu.lu@intel.com>
675
676 PR binutils/23655
677 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
678 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
679 * i386-dis.c (EXxEVexR64): New.
680 (evex_rounding_64_mode): Likewise.
681 (OP_Rounding): Handle evex_rounding_64_mode.
682
d20dee9e
L		 6832018-09-14 H.J. Lu <hongjiu.lu@intel.com>
684
685 PR binutils/23655
686 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
687 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
688 * i386-dis.c (Edqa): New.
689 (dqa_mode): Likewise.
690 (intel_operand_size): Handle dqa_mode as m_mode.
691 (OP_E_register): Handle dqa_mode as dq_mode.
692 (OP_E_memory): Set shift for dqa_mode based on address_mode.
693
5074ad8a
L		 6942018-09-14 H.J. Lu <hongjiu.lu@intel.com>
695
696 * i386-dis.c (OP_E_memory): Reformat.
697
556059dd
JB		 6982018-09-14 Jan Beulich <jbeulich@suse.com>
699
700 * i386-opc.tbl (crc32): Fold byte and word forms.
701 * i386-tbl.h: Re-generate.
702
41d1ab6a
L		 7032018-09-13 H.J. Lu <hongjiu.lu@intel.com>
704
705 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
706 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
707 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
708 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
709 * i386-tbl.h: Regenerated.
710
57f6375e
JB		 7112018-09-13 Jan Beulich <jbeulich@suse.com>
712
713 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
714 meaningless.
715 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
716 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
717 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
718 * i386-tbl.h: Re-generate.
719
2589a7e5
JB		 7202018-09-13 Jan Beulich <jbeulich@suse.com>
721
722 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
723 AVX512_4VNNIW insns.
724 * i386-tbl.h: Re-generate.
725
a760eb41
JB		 7262018-09-13 Jan Beulich <jbeulich@suse.com>
727
728 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
729 meaningless.
730 * i386-tbl.h: Re-generate.
731
e9042658
JB		 7322018-09-13 Jan Beulich <jbeulich@suse.com>
733
734 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
735 meaningless.
736 * i386-tbl.h: Re-generate.
737
9caa306f
JB		 7382018-09-13 Jan Beulich <jbeulich@suse.com>
739
740 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
741 meaningless.
742 * i386-tbl.h: Re-generate.
743
fb6ce599
JB		 7442018-09-13 Jan Beulich <jbeulich@suse.com>
745
746 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
747 meaningless.
748 * i386-tbl.h: Re-generate.
749
6a8da886
JB		 7502018-09-13 Jan Beulich <jbeulich@suse.com>
751
752 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
753 meaningless.
754 * i386-tbl.h: Re-generate.
755
c7f27919
JB		 7562018-09-13 Jan Beulich <jbeulich@suse.com>
757
758 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
759 * i386-tbl.h: Re-generate.
760
0f407ee9
JB		 7612018-09-13 Jan Beulich <jbeulich@suse.com>
762
763 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
764 * i386-tbl.h: Re-generate.
765
2fbbbee5
JB		 7662018-09-13 Jan Beulich <jbeulich@suse.com>
767
768 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
769 meaningless.
770 * i386-tbl.h: Re-generate.
771
2b02b9a2
JB		 7722018-09-13 Jan Beulich <jbeulich@suse.com>
773
774 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
775 meaningless.
776 * i386-tbl.h: Re-generate.
777
963c68aa
JB		 7782018-09-13 Jan Beulich <jbeulich@suse.com>
779
780 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
781 * i386-tbl.h: Re-generate.
782
64e025c3
JB		 7832018-09-13 Jan Beulich <jbeulich@suse.com>
784
785 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
786 * i386-tbl.h: Re-generate.
787
47603f88
JB		 7882018-09-13 Jan Beulich <jbeulich@suse.com>
789
790 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
791 * i386-tbl.h: Re-generate.
792
0001cfd0
JB		 7932018-09-13 Jan Beulich <jbeulich@suse.com>
794
795 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
796 meaningless.
797 * i386-tbl.h: Re-generate.
798
be4b452e
JB		 7992018-09-13 Jan Beulich <jbeulich@suse.com>
800
801 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
802 meaningless.
803 * i386-tbl.h: Re-generate.
804
d09a1394
JB		 8052018-09-13 Jan Beulich <jbeulich@suse.com>
806
807 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
808 meaningless.
809 * i386-tbl.h: Re-generate.
810
07599e13
JB		 8112018-09-13 Jan Beulich <jbeulich@suse.com>
812
813 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
814 * i386-tbl.h: Re-generate.
815
1ee3e487
JB		 8162018-09-13 Jan Beulich <jbeulich@suse.com>
817
818 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
819 * i386-tbl.h: Re-generate.
820
a5f580e5
JB		 8212018-09-13 Jan Beulich <jbeulich@suse.com>
822
823 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
824 * i386-tbl.h: Re-generate.
825
49d5d12d
JB		 8262018-09-13 Jan Beulich <jbeulich@suse.com>
827
828 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
829 (vpbroadcastw, rdpid): Drop NoRex64.
830 * i386-tbl.h: Re-generate.
831
f5eb1d70
JB		 8322018-09-13 Jan Beulich <jbeulich@suse.com>
833
834 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
835 store templates, adding D.
836 * i386-tbl.h: Re-generate.
837
dbbc8b7e
JB		 8382018-09-13 Jan Beulich <jbeulich@suse.com>
839
840 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
841 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
842 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
843 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
844 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
845 Fold load and store templates where possible, adding D. Drop
846 IgnoreSize where it was pointlessly present. Drop redundant
847 *word.
848 * i386-tbl.h: Re-generate.
849
d276ec69
JB		 8502018-09-13 Jan Beulich <jbeulich@suse.com>
851
852 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
853 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
854 (intel_operand_size): Handle v_bndmk_mode.
855 (OP_E_memory): Likewise. Produce (bad) when also riprel.
856
9da4dfd6
JD		 8572018-09-08 John Darrington <john@darrington.wattle.id.au>
858
859 * disassemble.c (ARCH_s12z): Define if ARCH_all.
860
be192bc2
JW		 8612018-08-31 Kito Cheng <kito@andestech.com>
862
863 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
864 compressed floating point instructions.
865
43135d3b
JW		 8662018-08-30 Kito Cheng <kito@andestech.com>
867
868 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
869 riscv_opcode.xlen_requirement.
870 * riscv-opc.c (riscv_opcodes): Update for struct change.
871
df28970f
MA		 8722018-08-29 Martin Aberg <maberg@gaisler.com>
873
874 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
875 psr (PWRPSR) instruction.
876
9108bc33
CX		 8772018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
878
879 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
880
bd782c07
CX		 8812018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
882
883 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
884
ac8cb70f
CX		 8852018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
886
887 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
888 loongson3a as an alias of gs464 for compatibility.
889 * mips-opc.c (mips_opcodes): Change Comments.
890
a693765e
CX		 8912018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
892
893 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
894 option.
895 (print_mips_disassembler_options): Document -M loongson-ext.
896 * mips-opc.c (LEXT2): New macro.
897 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
898
bdc6c06e
CX		 8992018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
900
901 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
902 descriptors.
903 (parse_mips_ase_option): Handle -M loongson-ext option.
904 (print_mips_disassembler_options): Document -M loongson-ext.
905 * mips-opc.c (IL3A): Delete.
906 * mips-opc.c (LEXT): New macro.
907 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
908 instructions.
909
716c08de
CX		 9102018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
911
912 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
913 descriptors.
914 (parse_mips_ase_option): Handle -M loongson-cam option.
915 (print_mips_disassembler_options): Document -M loongson-cam.
916 * mips-opc.c (LCAM): New macro.
917 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
918 instructions.
919
9cf7e568
AM		 9202018-08-21 Alan Modra <amodra@gmail.com>
921
922 * ppc-dis.c (operand_value_powerpc): Init "invalid".
923 (skip_optional_operands): Count optional operands, and update
924 ppc_optional_operand_value call.
925 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
926 (extract_vlensi): Likewise.
927 (extract_fxm): Return default value for missing optional operand.
928 (extract_ls, extract_raq, extract_tbr): Likewise.
929 (insert_sxl, extract_sxl): New functions.
930 (insert_esync, extract_esync): Remove Power9 handling and simplify.
931 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
932 flag and extra entry.
933 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
934 extract_sxl.
935
d203b41a 9362018-08-20 Alan Modra <amodra@gmail.com>
f4107842 937
d203b41a 938 * sh-opc.h (MASK): Simplify.
f4107842 939
08a8fe2f 9402018-08-18 John Darrington <john@darrington.wattle.id.au>
7ba3ba91 941
d203b41a
AM		 942 * s12z-dis.c (bm_decode): Deal with cases where the mode is
943 BM_RESERVED0 or BM_RESERVED1
08a8fe2f 944 (bm_rel_decode, bm_n_bytes): Ditto.
d203b41a 945
08a8fe2f 9462018-08-18 John Darrington <john@darrington.wattle.id.au>
d203b41a
AM		 947
948 * s12z.h: Delete.
7ba3ba91 949
1bc60e56
L		 9502018-08-14 H.J. Lu <hongjiu.lu@intel.com>
951
952 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
953 address with the addr32 prefix and without base nor index
954 registers.
955
d871f3f4
L		 9562018-08-11 H.J. Lu <hongjiu.lu@intel.com>
957
958 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
959 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
960 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
961 (cpu_flags): Add CpuCMOV and CpuFXSR.
962 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
963 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
964 * i386-init.h: Regenerated.
965 * i386-tbl.h: Likewise.
966
b6523c37 9672018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
968
969 * arc-regs.h: Update auxiliary registers.
970
e968fc9b
JB		 9712018-08-06 Jan Beulich <jbeulich@suse.com>
972
973 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
974 (RegIP, RegIZ): Define.
975 * i386-reg.tbl: Adjust comments.
976 (rip): Use Qword instead of BaseIndex. Use RegIP.
977 (eip): Use Dword instead of BaseIndex. Use RegIP.
978 (riz): Add Qword. Use RegIZ.
979 (eiz): Add Dword. Use RegIZ.
980 * i386-tbl.h: Re-generate.
981
dbf8be89
JB		 9822018-08-03 Jan Beulich <jbeulich@suse.com>
983
984 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
985 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
986 vpmovzxdq, vpmovzxwd): Remove NoRex64.
987 * i386-tbl.h: Re-generate.
988
c48dadc9
JB		 9892018-08-03 Jan Beulich <jbeulich@suse.com>
990
991 * i386-gen.c (operand_types): Remove Mem field.
992 * i386-opc.h (union i386_operand_type): Remove mem field.
993 * i386-init.h, i386-tbl.h: Re-generate.
994
cb86a42a
AM		 9952018-08-01 Alan Modra <amodra@gmail.com>
996
997 * po/POTFILES.in: Regenerate.
998
07cc0450
NC		 9992018-07-31 Nick Clifton <nickc@redhat.com>
1000
1001 * po/sv.po: Updated Swedish translation.
1002
1424ad86
JB		 10032018-07-31 Jan Beulich <jbeulich@suse.com>
1004
1005 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1006 * i386-init.h, i386-tbl.h: Re-generate.
1007
ae2387fe
JB		 10082018-07-31 Jan Beulich <jbeulich@suse.com>
1009
1010 * i386-opc.h (ZEROING_MASKING) Rename to ...
1011 (DYNAMIC_MASKING): ... this. Adjust comment.
1012 * i386-opc.tbl (MaskingMorZ): Define.
1013 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1014 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1015 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1016 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1017 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1018 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1019 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1020 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1021 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1022
6ff00b5e
JB		 10232018-07-31 Jan Beulich <jbeulich@suse.com>
1024
1025 * i386-opc.tbl: Use element rather than vector size for AVX512*
1026 scatter/gather insns.
1027 * i386-tbl.h: Re-generate.
1028
e951d5ca
JB		 10292018-07-31 Jan Beulich <jbeulich@suse.com>
1030
1031 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1032 (cpu_flags): Drop CpuVREX.
1033 * i386-opc.h (CpuVREX): Delete.
1034 (union i386_cpu_flags): Remove cpuvrex.
1035 * i386-init.h, i386-tbl.h: Re-generate.
1036
eb41b248
JW		 10372018-07-30 Jim Wilson <jimw@sifive.com>
1038
1039 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1040 fields.
1041 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1042
b8891f8d
AJ		 10432018-07-30 Andrew Jenner <andrew@codesourcery.com>
1044
1045 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1046 * Makefile.in: Regenerated.
1047 * configure.ac: Add C-SKY.
1048 * configure: Regenerated.
1049 * csky-dis.c: New file.
1050 * csky-opc.h: New file.
1051 * disassemble.c (ARCH_csky): Define.
1052 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1053 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1054
16065af1
AM		 10552018-07-27 Alan Modra <amodra@gmail.com>
1056
1057 * ppc-opc.c (insert_sprbat): Correct function parameter and
1058 return type.
1059 (extract_sprbat): Likewise, variable too.
1060
fa758a70
AC		 10612018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
1062 Alan Modra <amodra@gmail.com>
1063
1064 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1065 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1066 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1067 support disjointed BAT.
1068 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
1069 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1070 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1071
4a1b91ea
L		 10722018-07-25 H.J. Lu <hongjiu.lu@intel.com>
1073 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1074
1075 * i386-gen.c (adjust_broadcast_modifier): New function.
1076 (process_i386_opcode_modifier): Add an argument for operands.
1077 Adjust the Broadcast value based on operands.
1078 (output_i386_opcode): Pass operand_types to
1079 process_i386_opcode_modifier.
1080 (process_i386_opcodes): Pass NULL as operands to
1081 process_i386_opcode_modifier.
1082 * i386-opc.h (BYTE_BROADCAST): New.
1083 (WORD_BROADCAST): Likewise.
1084 (DWORD_BROADCAST): Likewise.
1085 (QWORD_BROADCAST): Likewise.
1086 (i386_opcode_modifier): Expand broadcast to 3 bits.
1087 * i386-tbl.h: Regenerated.
1088
67ce483b
AM		 10892018-07-24 Alan Modra <amodra@gmail.com>
1090
1091 PR 23430
1092 * or1k-desc.h: Regenerate.
1093
4174bfff
JB		 10942018-07-24 Jan Beulich <jbeulich@suse.com>
1095
1096 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1097 vcvtusi2ss, and vcvtusi2sd.
1098 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1099 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1100 * i386-tbl.h: Re-generate.
1101
04e65276
CZ		 11022018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1103
1104 * arc-opc.c (extract_w6): Fix extending the sign.
1105
47e6f81c
CZ		 11062018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1107
1108 * arc-tbl.h (vewt): Allow it for ARC EM family.
1109
bb71536f
AM		 11102018-07-23 Alan Modra <amodra@gmail.com>
1111
1112 PR 23419
1113 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1114 opcode variants for mtspr/mfspr encodings.
1115
8095d2f7
CX		 11162018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
1117 Maciej W. Rozycki <macro@mips.com>
1118
1119 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1120 loongson3a descriptors.
1121 (parse_mips_ase_option): Handle -M loongson-mmi option.
1122 (print_mips_disassembler_options): Document -M loongson-mmi.
1123 * mips-opc.c (LMMI): New macro.
1124 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1125 instructions.
1126
5f32791e
JB		 11272018-07-19 Jan Beulich <jbeulich@suse.com>
1128
1129 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1130 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1131 IgnoreSize and [XYZ]MMword where applicable.
1132 * i386-tbl.h: Re-generate.
1133
625cbd7a
JB		 11342018-07-19 Jan Beulich <jbeulich@suse.com>
1135
1136 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1137 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1138 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1139 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1140 * i386-tbl.h: Re-generate.
1141
86b15c32
JB		 11422018-07-19 Jan Beulich <jbeulich@suse.com>
1143
1144 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1145 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1146 VPCLMULQDQ templates into their respective AVX512VL counterparts
1147 where possible, using Disp8ShiftVL and CheckRegSize instead of
1148 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1149 * i386-tbl.h: Re-generate.
1150
cf769ed5
JB		 11512018-07-19 Jan Beulich <jbeulich@suse.com>
1152
1153 * i386-opc.tbl: Fold AVX512DQ templates into their respective
1154 AVX512VL counterparts where possible, using Disp8ShiftVL and
1155 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1156 IgnoreSize) as appropriate.
1157 * i386-tbl.h: Re-generate.
1158
8282b7ad
JB		 11592018-07-19 Jan Beulich <jbeulich@suse.com>
1160
1161 * i386-opc.tbl: Fold AVX512BW templates into their respective
1162 AVX512VL counterparts where possible, using Disp8ShiftVL and
1163 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1164 IgnoreSize) as appropriate.
1165 * i386-tbl.h: Re-generate.
1166
755908cc
JB		 11672018-07-19 Jan Beulich <jbeulich@suse.com>
1168
1169 * i386-opc.tbl: Fold AVX512CD templates into their respective
1170 AVX512VL counterparts where possible, using Disp8ShiftVL and
1171 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1172 IgnoreSize) as appropriate.
1173 * i386-tbl.h: Re-generate.
1174
7091c612
JB		 11752018-07-19 Jan Beulich <jbeulich@suse.com>
1176
1177 * i386-opc.h (DISP8_SHIFT_VL): New.
1178 * i386-opc.tbl (Disp8ShiftVL): Define.
1179 (various): Fold AVX512VL templates into their respective
1180 AVX512F counterparts where possible, using Disp8ShiftVL and
1181 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1182 IgnoreSize) as appropriate.
1183 * i386-tbl.h: Re-generate.
1184
c30be56e
JB		 11852018-07-19 Jan Beulich <jbeulich@suse.com>
1186
1187 * Makefile.am: Change dependencies and rule for
1188 $(srcdir)/i386-init.h.
1189 * Makefile.in: Re-generate.
1190 * i386-gen.c (process_i386_opcodes): New local variable
1191 "marker". Drop opening of input file. Recognize marker and line
1192 number directives.
1193 * i386-opc.tbl (OPCODE_I386_H): Define.
1194 (i386-opc.h): Include it.
1195 (None): Undefine.
1196
11a322db
L		 11972018-07-18 H.J. Lu <hongjiu.lu@intel.com>
1198
1199 PR gas/23418
1200 * i386-opc.h (Byte): Update comments.
1201 (Word): Likewise.
1202 (Dword): Likewise.
1203 (Fword): Likewise.
1204 (Qword): Likewise.
1205 (Tbyte): Likewise.
1206 (Xmmword): Likewise.
1207 (Ymmword): Likewise.
1208 (Zmmword): Likewise.
1209 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1210 vcvttps2uqq.
1211 * i386-tbl.h: Regenerated.
1212
cde3679e
NC		 12132018-07-12 Sudakshina Das <sudi.das@arm.com>
1214
1215 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1216 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1217 * aarch64-asm-2.c: Regenerate.
1218 * aarch64-dis-2.c: Regenerate.
1219 * aarch64-opc-2.c: Regenerate.
1220
45a28947
TC		 12212018-07-12 Tamar Christina <tamar.christina@arm.com>
1222
1223 PR binutils/23192
1224 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1225 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1226 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1227 sqdmulh, sqrdmulh): Use Em16.
1228
c597cc3d
SD		 12292018-07-11 Sudakshina Das <sudi.das@arm.com>
1230
1231 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1232 csdb together with them.
1233 (thumb32_opcodes): Likewise.
1234
a79eaed6
JB		 12352018-07-11 Jan Beulich <jbeulich@suse.com>
1236
1237 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1238 requiring 32-bit registers as operands 2 and 3. Improve
1239 comments.
1240 (mwait, mwaitx): Fold templates. Improve comments.
1241 OPERAND_TYPE_INOUTPORTREG.
1242 * i386-tbl.h: Re-generate.
1243
2fb5be8d
JB		 12442018-07-11 Jan Beulich <jbeulich@suse.com>
1245
1246 * i386-gen.c (operand_type_init): Remove
1247 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1248 OPERAND_TYPE_INOUTPORTREG.
1249 * i386-init.h: Re-generate.
1250
7f5cad30
JB		 12512018-07-11 Jan Beulich <jbeulich@suse.com>
1252
1253 * i386-opc.tbl (wrssd, wrussd): Add Dword.
1254 (wrssq, wrussq): Add Qword.
1255 * i386-tbl.h: Re-generate.
1256
f0a85b07
JB		 12572018-07-11 Jan Beulich <jbeulich@suse.com>
1258
1259 * i386-opc.h: Rename OTMax to OTNum.
1260 (OTNumOfUints): Adjust calculation.
1261 (OTUnused): Directly alias to OTNum.
1262
9dcb0ba4
MR		 12632018-07-09 Maciej W. Rozycki <macro@mips.com>
1264
1265 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1266 `reg_xys'.
1267 (lea_reg_xys): Likewise.
1268 (print_insn_loop_primitive): Rename `reg' local variable to
1269 `reg_dxy'.
1270
f311ba7e
TC		 12712018-07-06 Tamar Christina <tamar.christina@arm.com>
1272
1273 PR binutils/23242
1274 * aarch64-tbl.h (ldarh): Fix disassembly mask.
1275
cba05feb
TC		 12762018-07-06 Tamar Christina <tamar.christina@arm.com>
1277
1278 PR binutils/23369
1279 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1280 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1281
471b9d15
MR		 12822018-07-02 Maciej W. Rozycki <macro@mips.com>
1283
1284 PR tdep/8282
1285 * mips-dis.c (mips_option_arg_t): New enumeration.
1286 (mips_options): New variable.
1287 (disassembler_options_mips): New function.
1288 (print_mips_disassembler_options): Reimplement in terms of
1289 `disassembler_options_mips'.
1290 * arm-dis.c (disassembler_options_arm): Adapt to using the
1291 `disasm_options_and_args_t' structure.
1292 * ppc-dis.c (disassembler_options_powerpc): Likewise.
1293 * s390-dis.c (disassembler_options_s390): Likewise.
1294
c0c468d5
TP		 12952018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
1296
1297 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1298 expected result.
1299 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1300 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1301 * testsuite/ld-arm/tls-longplt.d: Likewise.
1302
369c9167
TC		 13032018-06-29 Tamar Christina <tamar.christina@arm.com>
1304
1305 PR binutils/23192
1306 * aarch64-asm-2.c: Regenerate.
1307 * aarch64-dis-2.c: Likewise.
1308 * aarch64-opc-2.c: Likewise.
1309 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1310 * aarch64-opc.c (operand_general_constraint_met_p,
1311 aarch64_print_operand): Likewise.
1312 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1313 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1314 fmlal2, fmlsl2.
1315 (AARCH64_OPERANDS): Add Em2.
1316
30aa1306
NC		 13172018-06-26 Nick Clifton <nickc@redhat.com>
1318
1319 * po/uk.po: Updated Ukranian translation.
1320 * po/de.po: Updated German translation.
1321 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1322
eca4b721
NC		 13232018-06-26 Nick Clifton <nickc@redhat.com>
1324
1325 * nfp-dis.c: Fix spelling mistake.
1326
71300e2c
NC		 13272018-06-24 Nick Clifton <nickc@redhat.com>
1328
1329 * configure: Regenerate.
1330 * po/opcodes.pot: Regenerate.
1331
719d8288
NC		 13322018-06-24 Nick Clifton <nickc@redhat.com>
1333
1334 2.31 branch created.
1335
514cd3a0
TC		 13362018-06-19 Tamar Christina <tamar.christina@arm.com>
1337
1338 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1339 * aarch64-asm-2.c: Regenerate.
1340 * aarch64-dis-2.c: Likewise.
1341
385e4d0f
MR		 13422018-06-21 Maciej W. Rozycki <macro@mips.com>
1343
1344 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1345 `-M ginv' option description.
1346
160d1b3d
SH		 13472018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
1348
1349 PR gas/23305
1350 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1351 la and lla.
1352
d0ac1c44
SM		 13532018-06-19 Simon Marchi <simon.marchi@ericsson.com>
1354
1355 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1356 * configure.ac: Remove AC_PREREQ.
1357 * Makefile.in: Re-generate.
1358 * aclocal.m4: Re-generate.
1359 * configure: Re-generate.
1360
6f20c942
FS		 13612018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1362
1363 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1364 mips64r6 descriptors.
1365 (parse_mips_ase_option): Handle -Mginv option.
1366 (print_mips_disassembler_options): Document -Mginv.
1367 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1368 (GINV): New macro.
1369 (mips_opcodes): Define ginvi and ginvt.
1370
730c3174
SE		 13712018-06-13 Scott Egerton <scott.egerton@imgtec.com>
1372 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1373
1374 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1375 * mips-opc.c (CRC, CRC64): New macros.
1376 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1377 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
1378 crc32cd for CRC64.
1379
cb366992
EB		 13802018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
1381
1382 PR 20319
1383 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1384 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1385
ce72cd46
AM		 13862018-06-06 Alan Modra <amodra@gmail.com>
1387
1388 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1389 setjmp. Move init for some other vars later too.
1390
4b8e28c7
MF		 13912018-06-04 Max Filippov <jcmvbkbc@gmail.com>
1392
1393 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1394 (dis_private): Add new fields for property section tracking.
1395 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1396 (xtensa_instruction_fits): New functions.
1397 (fetch_data): Bump minimal fetch size to 4.
1398 (print_insn_xtensa): Make struct dis_private static.
1399 Load and prepare property table on section change.
1400 Don't disassemble literals. Don't disassemble instructions that
1401 cross property table boundaries.
1402
55e99962
L		 14032018-06-01 H.J. Lu <hongjiu.lu@intel.com>
1404
1405 * configure: Regenerated.
1406
733bd0ab
JB		 14072018-06-01 Jan Beulich <jbeulich@suse.com>
1408
1409 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1410 * i386-tbl.h: Re-generate.
1411
dfd27d41
JB		 14122018-06-01 Jan Beulich <jbeulich@suse.com>
1413
1414 * i386-opc.tbl (sldt, str): Add NoRex64.
1415 * i386-tbl.h: Re-generate.
1416
64795710
JB		 14172018-06-01 Jan Beulich <jbeulich@suse.com>
1418
1419 * i386-opc.tbl (invpcid): Add Oword.
1420 * i386-tbl.h: Re-generate.
1421
030157d8
AM		 14222018-06-01 Alan Modra <amodra@gmail.com>
1423
1424 * sysdep.h (_bfd_error_handler): Don't declare.
1425 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
1426 * rl78-decode.opc: Likewise.
1427 * msp430-decode.c: Regenerate.
1428 * rl78-decode.c: Regenerate.
1429
a9660a6f
AP		 14302018-05-30 Amit Pawar <Amit.Pawar@amd.com>
1431
1432 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1433 * i386-init.h : Regenerated.
1434
277eb7f6
AM		 14352018-05-25 Alan Modra <amodra@gmail.com>
1436
1437 * Makefile.in: Regenerate.
1438 * po/POTFILES.in: Regenerate.
1439
98553ad3
PB		 14402018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
1441
1442 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1443 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1444 (insert_bab, extract_bab, insert_btab, extract_btab,
1445 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1446 (BAT, BBA VBA RBS XB6S): Delete macros.
1447 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1448 (BB, BD, RBX, XC6): Update for new macros.
1449 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1450 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1451 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1452 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1453
7b4ae824
JD		 14542018-05-18 John Darrington <john@darrington.wattle.id.au>
1455
1456 * Makefile.am: Add support for s12z architecture.
1457 * configure.ac: Likewise.
1458 * disassemble.c: Likewise.
1459 * disassemble.h: Likewise.
1460 * Makefile.in: Regenerate.
1461 * configure: Regenerate.
1462 * s12z-dis.c: New file.
1463 * s12z.h: New file.
1464
29e0f0a1
AM		 14652018-05-18 Alan Modra <amodra@gmail.com>
1466
1467 * nfp-dis.c: Don't #include libbfd.h.
1468 (init_nfp3200_priv): Use bfd_get_section_contents.
1469 (nit_nfp6000_mecsr_sec): Likewise.
1470
809276d2
NC		 14712018-05-17 Nick Clifton <nickc@redhat.com>
1472
1473 * po/zh_CN.po: Updated simplified Chinese translation.
1474
ff329288
TC		 14752018-05-16 Tamar Christina <tamar.christina@arm.com>
1476
1477 PR binutils/23109
1478 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1479 * aarch64-dis-2.c: Regenerate.
1480
f9830ec1
TC		 14812018-05-15 Tamar Christina <tamar.christina@arm.com>
1482
1483 PR binutils/21446
1484 * aarch64-asm.c (opintl.h): Include.
1485 (aarch64_ins_sysreg): Enforce read/write constraints.
1486 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1487 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1488 (F_REG_READ, F_REG_WRITE): New.
1489 * aarch64-opc.c (aarch64_print_operand): Generate notes for
1490 AARCH64_OPND_SYSREG.
1491 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1492 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1493 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1494 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1495 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1496 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1497 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1498 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1499 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1500 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1501 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1502 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1503 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1504 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1505 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1506 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1507 msr (F_SYS_WRITE), mrs (F_SYS_READ).
1508
7d02540a
TC		 15092018-05-15 Tamar Christina <tamar.christina@arm.com>
1510
1511 PR binutils/21446
1512 * aarch64-dis.c (no_notes: New.
1513 (parse_aarch64_dis_option): Support notes.
1514 (aarch64_decode_insn, print_operands): Likewise.
1515 (print_aarch64_disassembler_options): Document notes.
1516 * aarch64-opc.c (aarch64_print_operand): Support notes.
1517
561a72d4
TC		 15182018-05-15 Tamar Christina <tamar.christina@arm.com>
1519
1520 PR binutils/21446
1521 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1522 and take error struct.
1523 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1524 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1525 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1526 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1527 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1528 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1529 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1530 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1531 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1532 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1533 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1534 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1535 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1536 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1537 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1538 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1539 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1540 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1541 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1542 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1543 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1544 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1545 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1546 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1547 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1548 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1549 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1550 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1551 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1552 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1553 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1554 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1555 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1556 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1557 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1558 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1559 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1560 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1561 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1562 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1563 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1564 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1565 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1566 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1567 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1568 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1569 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1570 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1571 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1572 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1573 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1574 (determine_disassembling_preference, aarch64_decode_insn,
1575 print_insn_aarch64_word, print_insn_data): Take errors struct.
1576 (print_insn_aarch64): Use errors.
1577 * aarch64-asm-2.c: Regenerate.
1578 * aarch64-dis-2.c: Regenerate.
1579 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1580 boolean in aarch64_insert_operan.
1581 (print_operand_extractor): Likewise.
1582 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1583
1678bd35
FT		 15842018-05-15 Francois H. Theron <francois.theron@netronome.com>
1585
1586 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1587
06cfb1c8
L		 15882018-05-09 H.J. Lu <hongjiu.lu@intel.com>
1589
1590 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1591
84f9f8c3
AM		 15922018-05-09 Sebastian Rasmussen <sebras@gmail.com>
1593
1594 * cr16-opc.c (cr16_instruction): Comment typo fix.
1595 * hppa-dis.c (print_insn_hppa): Likewise.
1596
e6f372ba
JW		 15972018-05-08 Jim Wilson <jimw@sifive.com>
1598
1599 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1600 (match_c_slli64, match_srxi_as_c_srxi): New.
1601 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1602 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1603 <c.slli, c.srli, c.srai>: Use match_s_slli.
1604 <c.slli64, c.srli64, c.srai64>: New.
1605
f413a913
AM		 16062018-05-08 Alan Modra <amodra@gmail.com>
1607
1608 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1609 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1610 partition opcode space for index lookup.
1611
a87a6478
PB		 16122018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1613
1614 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1615 <insn_length>: ...with this. Update usage.
1616 Remove duplicate call to *info->memory_error_func.
1617
c0a30a9f
L		 16182018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1619 H.J. Lu <hongjiu.lu@intel.com>
1620
1621 * i386-dis.c (Gva): New.
1622 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1623 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1624 (prefix_table): New instructions (see prefix above).
1625 (mod_table): New instructions (see prefix above).
1626 (OP_G): Handle va_mode.
1627 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1628 CPU_MOVDIR64B_FLAGS.
1629 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1630 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1631 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1632 * i386-opc.tbl: Add movidir{i,64b}.
1633 * i386-init.h: Regenerated.
1634 * i386-tbl.h: Likewise.
1635
75c0a438
L		 16362018-05-07 H.J. Lu <hongjiu.lu@intel.com>
1637
1638 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1639 AddrPrefixOpReg.
1640 * i386-opc.h (AddrPrefixOp0): Renamed to ...
1641 (AddrPrefixOpReg): This.
1642 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1643 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1644
2ceb7719
PB		 16452018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1646
1647 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1648 (vle_num_opcodes): Likewise.
1649 (spe2_num_opcodes): Likewise.
1650 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1651 initialization loop.
1652 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1653 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
1654 only once.
1655
b3ac5c6c
TC		 16562018-05-01 Tamar Christina <tamar.christina@arm.com>
1657
1658 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1659
fe944acf
FT		 16602018-04-30 Francois H. Theron <francois.theron@netronome.com>
1661
1662 Makefile.am: Added nfp-dis.c.
1663 configure.ac: Added bfd_nfp_arch.
1664 disassemble.h: Added print_insn_nfp prototype.
1665 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1666 nfp-dis.c: New, for NFP support.
1667 po/POTFILES.in: Added nfp-dis.c to the list.
1668 Makefile.in: Regenerate.
1669 configure: Regenerate.
1670
e2195274
JB		 16712018-04-26 Jan Beulich <jbeulich@suse.com>
1672
1673 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1674 templates into their base ones.
1675 * i386-tlb.h: Re-generate.
1676
59ef5df4
JB		 16772018-04-26 Jan Beulich <jbeulich@suse.com>
1678
1679 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1680 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1681 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1682 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1683 * i386-init.h: Re-generate.
1684
6e041cf4
JB		 16852018-04-26 Jan Beulich <jbeulich@suse.com>
1686
1687 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1688 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1689 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1690 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1691 comment.
1692 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1693 and CpuRegMask.
1694 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1695 CpuRegMask: Delete.
1696 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1697 cpuregzmm, and cpuregmask.
1698 * i386-init.h: Re-generate.
1699 * i386-tbl.h: Re-generate.
1700
0e0eea78
JB		 17012018-04-26 Jan Beulich <jbeulich@suse.com>
1702
1703 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1704 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1705 * i386-init.h: Re-generate.
1706
2f1bada2
JB		 17072018-04-26 Jan Beulich <jbeulich@suse.com>
1708
1709 * i386-gen.c (VexImmExt): Delete.
1710 * i386-opc.h (VexImmExt, veximmext): Delete.
1711 * i386-opc.tbl: Drop all VexImmExt uses.
1712 * i386-tlb.h: Re-generate.
1713
bacd1457
JB		 17142018-04-25 Jan Beulich <jbeulich@suse.com>
1715
1716 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1717 register-only forms.
1718 * i386-tlb.h: Re-generate.
1719
10bba94b
TC		 17202018-04-25 Tamar Christina <tamar.christina@arm.com>
1721
1722 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1723
c48935d7
IT		 17242018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1725
1726 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1727 PREFIX_0F1C.
1728 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1729 (cpu_flags): Add CpuCLDEMOTE.
1730 * i386-init.h: Regenerate.
1731 * i386-opc.h (enum): Add CpuCLDEMOTE,
1732 (i386_cpu_flags): Add cpucldemote.
1733 * i386-opc.tbl: Add cldemote.
1734 * i386-tbl.h: Regenerate.
1735
211dc24b
AM		 17362018-04-16 Alan Modra <amodra@gmail.com>
1737
1738 * Makefile.am: Remove sh5 and sh64 support.
1739 * configure.ac: Likewise.
1740 * disassemble.c: Likewise.
1741 * disassemble.h: Likewise.
1742 * sh-dis.c: Likewise.
1743 * sh64-dis.c: Delete.
1744 * sh64-opc.c: Delete.
1745 * sh64-opc.h: Delete.
1746 * Makefile.in: Regenerate.
1747 * configure: Regenerate.
1748 * po/POTFILES.in: Regenerate.
1749
a9a4b302
AM		 17502018-04-16 Alan Modra <amodra@gmail.com>
1751
1752 * Makefile.am: Remove w65 support.
1753 * configure.ac: Likewise.
1754 * disassemble.c: Likewise.
1755 * disassemble.h: Likewise.
1756 * w65-dis.c: Delete.
1757 * w65-opc.h: Delete.
1758 * Makefile.in: Regenerate.
1759 * configure: Regenerate.
1760 * po/POTFILES.in: Regenerate.
1761
04cb01fd
AM		 17622018-04-16 Alan Modra <amodra@gmail.com>
1763
1764 * configure.ac: Remove we32k support.
1765 * configure: Regenerate.
1766
c2bf1eec
AM		 17672018-04-16 Alan Modra <amodra@gmail.com>
1768
1769 * Makefile.am: Remove m88k support.
1770 * configure.ac: Likewise.
1771 * disassemble.c: Likewise.
1772 * disassemble.h: Likewise.
1773 * m88k-dis.c: Delete.
1774 * Makefile.in: Regenerate.
1775 * configure: Regenerate.
1776 * po/POTFILES.in: Regenerate.
1777
6793974d
AM		 17782018-04-16 Alan Modra <amodra@gmail.com>
1779
1780 * Makefile.am: Remove i370 support.
1781 * configure.ac: Likewise.
1782 * disassemble.c: Likewise.
1783 * disassemble.h: Likewise.
1784 * i370-dis.c: Delete.
1785 * i370-opc.c: Delete.
1786 * Makefile.in: Regenerate.
1787 * configure: Regenerate.
1788 * po/POTFILES.in: Regenerate.
1789
e82aa794
AM		 17902018-04-16 Alan Modra <amodra@gmail.com>
1791
1792 * Makefile.am: Remove h8500 support.
1793 * configure.ac: Likewise.
1794 * disassemble.c: Likewise.
1795 * disassemble.h: Likewise.
1796 * h8500-dis.c: Delete.
1797 * h8500-opc.h: Delete.
1798 * Makefile.in: Regenerate.
1799 * configure: Regenerate.
1800 * po/POTFILES.in: Regenerate.
1801
fceadf09
AM		 18022018-04-16 Alan Modra <amodra@gmail.com>
1803
1804 * configure.ac: Remove tahoe support.
1805 * configure: Regenerate.
1806
ae1d3843
L		 18072018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1808
1809 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1810 umwait.
1811 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1812 64-bit mode.
1813 * i386-tbl.h: Regenerated.
1814
de89d0a3
IT		 18152018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1816
1817 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1818 PREFIX_MOD_1_0FAE_REG_6.
1819 (va_mode): New.
1820 (OP_E_register): Use va_mode.
1821 * i386-dis-evex.h (prefix_table):
1822 New instructions (see prefixes above).
1823 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1824 (cpu_flags): Likewise.
1825 * i386-opc.h (enum): Likewise.
1826 (i386_cpu_flags): Likewise.
1827 * i386-opc.tbl: Add umonitor, umwait, tpause.
1828 * i386-init.h: Regenerate.
1829 * i386-tbl.h: Likewise.
1830
a8eb42a8
AM		 18312018-04-11 Alan Modra <amodra@gmail.com>
1832
1833 * opcodes/i860-dis.c: Delete.
1834 * opcodes/i960-dis.c: Delete.
1835 * Makefile.am: Remove i860 and i960 support.
1836 * configure.ac: Likewise.
1837 * disassemble.c: Likewise.
1838 * disassemble.h: Likewise.
1839 * Makefile.in: Regenerate.
1840 * configure: Regenerate.
1841 * po/POTFILES.in: Regenerate.
1842
caf0678c
L		 18432018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1844
1845 PR binutils/23025
1846 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1847 to 0.
1848 (print_insn): Clear vex instead of vex.evex.
1849
4fb0d2b9
NC		 18502018-04-04 Nick Clifton <nickc@redhat.com>
1851
1852 * po/es.po: Updated Spanish translation.
1853
c39e5b26
JB		 18542018-03-28 Jan Beulich <jbeulich@suse.com>
1855
1856 * i386-gen.c (opcode_modifiers): Delete VecESize.
1857 * i386-opc.h (VecESize): Delete.
1858 (struct i386_opcode_modifier): Delete vecesize.
1859 * i386-opc.tbl: Drop VecESize.
1860 * i386-tlb.h: Re-generate.
1861
8e6e0792
JB		 18622018-03-28 Jan Beulich <jbeulich@suse.com>
1863
1864 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1865 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1866 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1867 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1868 * i386-tlb.h: Re-generate.
1869
9f123b91
JB		 18702018-03-28 Jan Beulich <jbeulich@suse.com>
1871
1872 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1873 Fold AVX512 forms
1874 * i386-tlb.h: Re-generate.
1875
9646c87b
JB		 18762018-03-28 Jan Beulich <jbeulich@suse.com>
1877
1878 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1879 (vex_len_table): Drop Y for vcvt*2si.
1880 (putop): Replace plain 'Y' handling by abort().
1881
c8d59609
NC		 18822018-03-28 Nick Clifton <nickc@redhat.com>
1883
1884 PR 22988
1885 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1886 instructions with only a base address register.
1887 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1888 handle AARHC64_OPND_SVE_ADDR_R.
1889 (aarch64_print_operand): Likewise.
1890 * aarch64-asm-2.c: Regenerate.
1891 * aarch64_dis-2.c: Regenerate.
1892 * aarch64-opc-2.c: Regenerate.
1893
b8c169f3
JB		 18942018-03-22 Jan Beulich <jbeulich@suse.com>
1895
1896 * i386-opc.tbl: Drop VecESize from register only insn forms and
1897 memory forms not allowing broadcast.
1898 * i386-tlb.h: Re-generate.
1899
96bc132a
JB		 19002018-03-22 Jan Beulich <jbeulich@suse.com>
1901
1902 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1903 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1904 sha256*): Drop Disp<N>.
1905
9f79e886
JB		 19062018-03-22 Jan Beulich <jbeulich@suse.com>
1907
1908 * i386-dis.c (EbndS, bnd_swap_mode): New.
1909 (prefix_table): Use EbndS.
1910 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1911 * i386-opc.tbl (bndmov): Move misplaced Load.
1912 * i386-tlb.h: Re-generate.
1913
d6793fa1
JB		 19142018-03-22 Jan Beulich <jbeulich@suse.com>
1915
1916 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1917 templates allowing memory operands and folded ones for register
1918 only flavors.
1919 * i386-tlb.h: Re-generate.
1920
f7768225
JB		 19212018-03-22 Jan Beulich <jbeulich@suse.com>
1922
1923 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1924 256-bit templates. Drop redundant leftover Disp<N>.
1925 * i386-tlb.h: Re-generate.
1926
0e35537d
JW		 19272018-03-14 Kito Cheng <kito.cheng@gmail.com>
1928
1929 * riscv-opc.c (riscv_insn_types): New.
1930
b4a3689a
NC		 19312018-03-13 Nick Clifton <nickc@redhat.com>
1932
1933 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1934
d3d50934
L		 19352018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1936
1937 * i386-opc.tbl: Add Optimize to clr.
1938 * i386-tbl.h: Regenerated.
1939
bd5dea88
L		 19402018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1941
1942 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1943 * i386-opc.h (OldGcc): Removed.
1944 (i386_opcode_modifier): Remove oldgcc.
1945 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1946 instructions for old (<= 2.8.1) versions of gcc.
1947 * i386-tbl.h: Regenerated.
1948
e771e7c9
JB		 19492018-03-08 Jan Beulich <jbeulich@suse.com>
1950
1951 * i386-opc.h (EVEXDYN): New.
1952 * i386-opc.tbl: Fold various AVX512VL templates.
1953 * i386-tlb.h: Re-generate.
1954
ed438a93
JB		 19552018-03-08 Jan Beulich <jbeulich@suse.com>
1956
1957 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1958 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1959 vpexpandd, vpexpandq): Fold AFX512VF templates.
1960 * i386-tlb.h: Re-generate.
1961
454172a9
JB		 19622018-03-08 Jan Beulich <jbeulich@suse.com>
1963
1964 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1965 Fold 128- and 256-bit VEX-encoded templates.
1966 * i386-tlb.h: Re-generate.
1967
36824150
JB		 19682018-03-08 Jan Beulich <jbeulich@suse.com>
1969
1970 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1971 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1972 vpexpandd, vpexpandq): Fold AVX512F templates.
1973 * i386-tlb.h: Re-generate.
1974
e7f5c0a9
JB		 19752018-03-08 Jan Beulich <jbeulich@suse.com>
1976
1977 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1978 64-bit templates. Drop Disp<N>.
1979 * i386-tlb.h: Re-generate.
1980
25a4277f
JB		 19812018-03-08 Jan Beulich <jbeulich@suse.com>
1982
1983 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1984 and 256-bit templates.
1985 * i386-tlb.h: Re-generate.
1986
d2224064
JB		 19872018-03-08 Jan Beulich <jbeulich@suse.com>
1988
1989 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1990 * i386-tlb.h: Re-generate.
1991
1b193f0b
JB		 19922018-03-08 Jan Beulich <jbeulich@suse.com>
1993
1994 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1995 Drop NoAVX.
1996 * i386-tlb.h: Re-generate.
1997
f2f6a710
JB		 19982018-03-08 Jan Beulich <jbeulich@suse.com>
1999
2000 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2001 * i386-tlb.h: Re-generate.
2002
38e314eb
JB		 20032018-03-08 Jan Beulich <jbeulich@suse.com>
2004
2005 * i386-gen.c (opcode_modifiers): Delete FloatD.
2006 * i386-opc.h (FloatD): Delete.
2007 (struct i386_opcode_modifier): Delete floatd.
2008 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2009 FloatD by D.
2010 * i386-tlb.h: Re-generate.
2011
d53e6b98
JB		 20122018-03-08 Jan Beulich <jbeulich@suse.com>
2013
2014 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2015
2907c2f5
JB		 20162018-03-08 Jan Beulich <jbeulich@suse.com>
2017
2018 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2019 * i386-tlb.h: Re-generate.
2020
73053c1f
JB		 20212018-03-08 Jan Beulich <jbeulich@suse.com>
2022
2023 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2024 forms.
2025 * i386-tlb.h: Re-generate.
2026
52fe4420
AM		 20272018-03-07 Alan Modra <amodra@gmail.com>
2028
2029 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2030 bfd_arch_rs6000.
2031 * disassemble.h (print_insn_rs6000): Delete.
2032 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2033 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2034 (print_insn_rs6000): Delete.
2035
a6743a54
AM		 20362018-03-03 Alan Modra <amodra@gmail.com>
2037
2038 * sysdep.h (opcodes_error_handler): Define.
2039 (_bfd_error_handler): Declare.
2040 * Makefile.am: Remove stray #.
2041 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
2042 EDIT" comment.
2043 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2044 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2045 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2046 opcodes_error_handler to print errors. Standardize error messages.
2047 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2048 and include opintl.h.
2049 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2050 * i386-gen.c: Standardize error messages.
2051 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2052 * Makefile.in: Regenerate.
2053 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2054 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2055 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2056 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2057 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2058 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2059 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2060 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2061 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2062 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2063 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2064 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2065 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2066
8305403a
L		 20672018-03-01 H.J. Lu <hongjiu.lu@intel.com>
2068
2069 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2070 vpsub[bwdq] instructions.
2071 * i386-tbl.h: Regenerated.
2072
e184813f
AM		 20732018-03-01 Alan Modra <amodra@gmail.com>
2074
2075 * configure.ac (ALL_LINGUAS): Sort.
2076 * configure: Regenerate.
2077
5b616bef
TP		 20782018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
2079
2080 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2081 macro by assignements.
2082
b6f8c7c4
L		 20832018-02-27 H.J. Lu <hongjiu.lu@intel.com>
2084
2085 PR gas/22871
2086 * i386-gen.c (opcode_modifiers): Add Optimize.
2087 * i386-opc.h (Optimize): New enum.
2088 (i386_opcode_modifier): Add optimize.
2089 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2090 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2091 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2092 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2093 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2094 vpxord and vpxorq.
2095 * i386-tbl.h: Regenerated.
2096
e95b887f
AM		 20972018-02-26 Alan Modra <amodra@gmail.com>
2098
2099 * crx-dis.c (getregliststring): Allocate a large enough buffer
2100 to silence false positive gcc8 warning.
2101
0bccfb29
JW		 21022018-02-22 Shea Levy <shea@shealevy.com>
2103
2104 * disassemble.c (ARCH_riscv): Define if ARCH_all.
2105
6b6b6807
L		 21062018-02-22 H.J. Lu <hongjiu.lu@intel.com>
2107
2108 * i386-opc.tbl: Add {rex},
2109 * i386-tbl.h: Regenerated.
2110
75f31665
MR		 21112018-02-20 Maciej W. Rozycki <macro@mips.com>
2112
2113 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2114 (mips16_opcodes): Replace `M' with `m' for "restore".
2115
e207bc53
TP		 21162018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
2117
2118 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2119
87993319
MR		 21202018-02-13 Maciej W. Rozycki <macro@mips.com>
2121
2122 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2123 variable to `function_index'.
2124
68d20676
NC		 21252018-02-13 Nick Clifton <nickc@redhat.com>
2126
2127 PR 22823
2128 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2129 about truncation of printing.
2130
d2159fdc
HW		 21312018-02-12 Henry Wong <henry@stuffedcow.net>
2132
2133 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2134
f174ef9f
NC		 21352018-02-05 Nick Clifton <nickc@redhat.com>
2136
2137 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2138
be3a8dca
IT		 21392018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2140
2141 * i386-dis.c (enum): Add pconfig.
2142 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2143 (cpu_flags): Add CpuPCONFIG.
2144 * i386-opc.h (enum): Add CpuPCONFIG.
2145 (i386_cpu_flags): Add cpupconfig.
2146 * i386-opc.tbl: Add PCONFIG instruction.
2147 * i386-init.h: Regenerate.
2148 * i386-tbl.h: Likewise.
2149
3233d7d0
IT		 21502018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2151
2152 * i386-dis.c (enum): Add PREFIX_0F09.
2153 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2154 (cpu_flags): Add CpuWBNOINVD.
2155 * i386-opc.h (enum): Add CpuWBNOINVD.
2156 (i386_cpu_flags): Add cpuwbnoinvd.
2157 * i386-opc.tbl: Add WBNOINVD instruction.
2158 * i386-init.h: Regenerate.
2159 * i386-tbl.h: Likewise.
2160
e925c834
JW		 21612018-01-17 Jim Wilson <jimw@sifive.com>
2162
2163 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2164
d777820b
IT		 21652018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2166
2167 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2168 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2169 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2170 (cpu_flags): Add CpuIBT, CpuSHSTK.
2171 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2172 (i386_cpu_flags): Add cpuibt, cpushstk.
2173 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2174 * i386-init.h: Regenerate.
2175 * i386-tbl.h: Likewise.
2176
f6efed01
NC		 21772018-01-16 Nick Clifton <nickc@redhat.com>
2178
2179 * po/pt_BR.po: Updated Brazilian Portugese translation.
2180 * po/de.po: Updated German translation.
2181
2721d702
JW		 21822018-01-15 Jim Wilson <jimw@sifive.com>
2183
2184 * riscv-opc.c (match_c_nop): New.
2185 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2186
616dcb87
NC		 21872018-01-15 Nick Clifton <nickc@redhat.com>
2188
2189 * po/uk.po: Updated Ukranian translation.
2190
3957a496
NC		 21912018-01-13 Nick Clifton <nickc@redhat.com>
2192
2193 * po/opcodes.pot: Regenerated.
2194
769c7ea5
NC		 21952018-01-13 Nick Clifton <nickc@redhat.com>
2196
2197 * configure: Regenerate.
2198
faf766e3
NC		 21992018-01-13 Nick Clifton <nickc@redhat.com>
2200
2201 2.30 branch created.
2202
888a89da
IT		 22032018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2204
2205 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2206 * i386-tbl.h: Regenerate.
2207
cbda583a
JB		 22082018-01-10 Jan Beulich <jbeulich@suse.com>
2209
2210 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2211 * i386-tbl.h: Re-generate.
2212
c9e92278
JB		 22132018-01-10 Jan Beulich <jbeulich@suse.com>
2214
2215 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2216 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2217 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2218 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2219 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2220 Disp8MemShift of AVX512VL forms.
2221 * i386-tbl.h: Re-generate.
2222
35fd2b2b
JW		 22232018-01-09 Jim Wilson <jimw@sifive.com>
2224
2225 * riscv-dis.c (maybe_print_address): If base_reg is zero,
2226 then the hi_addr value is zero.
2227
91d8b670
JG		 22282018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2229
2230 * arm-dis.c (arm_opcodes): Add csdb.
2231 (thumb32_opcodes): Add csdb.
2232
be2e7d95
JG		 22332018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2234
2235 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2236 * aarch64-asm-2.c: Regenerate.
2237 * aarch64-dis-2.c: Regenerate.
2238 * aarch64-opc-2.c: Regenerate.
2239
704a705d
L		 22402018-01-08 H.J. Lu <hongjiu.lu@intel.com>
2241
2242 PR gas/22681
2243 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2244 Remove AVX512 vmovd with 64-bit operands.
2245 * i386-tbl.h: Regenerated.
2246
35eeb78f
JW		 22472018-01-05 Jim Wilson <jimw@sifive.com>
2248
2249 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2250 jalr.
2251
219d1afa
AM		 22522018-01-03 Alan Modra <amodra@gmail.com>
2253
2254 Update year range in copyright notice of all files.
2255
1508bbf5
JB		 22562018-01-02 Jan Beulich <jbeulich@suse.com>
2257
2258 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2259 and OPERAND_TYPE_REGZMM entries.
2260
1e563868 2261For older changes see ChangeLog-2017
3499769a 2262\f
1e563868 2263Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 2264
2265Copying and distribution of this file, with or without modification,
2266are permitted in any medium without royalty provided the copyright
2267notice and this notice are preserved.
2268
2269Local Variables:
2270mode: change-log
2271left-margin: 8
2272fill-column: 74
2273version-control: never
2274End:
GDB Binutils - Deliverables
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