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m32r.opc (parse_slo16): Do not assume a 32-bit host word size.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
ab7c9a26
NC		 12005-10-14 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
2
3 * m32r-asm.c: Regenerate after updating m32r.opc.
4
19590ef7
RE		 52005-10-08 James Lemke <jim@wasabisystems.com>
6
7 * arm-dis.c (coprocessor_opcodes): Fix mask for various Maverick CDP
8 operations.
9
6edfbbad
DJ		 102005-10-06 Daniel Jacobowitz <dan@codesourcery.com>
11
12 * ppc-dis.c (struct dis_private): Remove.
13 (powerpc_dialect): Avoid aliasing warnings.
14 (print_insn_big_powerpc, print_insn_little_powerpc): Likewise.
15
095f2843
NC		 162005-09-30 Nick Clifton <nickc@redhat.com>
17
18 * po/ga.po: New Irish translation.
19 * configure.in (ALL_LINGUAS): Add "ga".
20 * configure: Regenerate.
21
fdd3b9b3
L		 222005-09-30 H.J. Lu <hongjiu.lu@intel.com>
23
24 * Makefile.am: Run "make dep-am".
25 * Makefile.in: Regenerated.
26 * aclocal.m4: Likewise.
27 * configure: Likewise.
28
4b7f6baa
CM		 292005-09-30 Catherine Moore <clm@cm00re.com>
30
31 * Makefile.am: Bfin support.
32 * Makefile.in: Regenerated.
33 * aclocal.m4: Regenerated.
34 * bfin-dis.c: New file.
35 * configure.in: Bfin support.
36 * configure: Regenerated.
37 * disassemble.c (ARCH_bfin): Define.
38 (disassembler): Add case for bfd_arch_bfin.
39
1a114b12
JB		 402005-09-28 Jan Beulich <jbeulich@novell.com>
41
42 * i386-dis.c (stack_v_mode): Renamed from branch_v_mode.
43 (indirEv): Use it.
44 (stackEv): New.
45 (Ob64, Ov64): Rename to Ob, Ov. Delete unused original definitions.
46 (dis386): Document and use new 'V' meta character. Use it for
47 single-byte push/pop opcode forms. Use stackEv for mod-r/m push/pop
48 opcode forms. Correct typo in 'pop ss'. Replace Ob64/Ov64 by Ob/Ov.
49 (putop): 'q' suffix for 'T' and 'U' meta depends on DFLAG. Mark
50 data prefix as used whenever DFLAG was examined. Handle 'V'.
51 (intel_operand_size): Use stack_v_mode.
52 (OP_E): Use stack_v_mode, but handle only the special case of
53 64-bit mode without operand size override here; fall through to
54 v_mode case otherwise.
55 (OP_REG): Special case rAX_reg ... rDI_reg only when 64-bit mode
56 and no operand size override is present.
57 (OP_J): Use get32s for obtaining the displacement also when rex64
58 is present.
59
3eb17e6b
PB		 602005-09-08 Paul Brook <paul@codesourcery.com>
61
62 * arm-dis.c (arm_opcodes, thumb32_opcodes): Rename smi to smc.
63
61cc0267
CF		 642005-09-06 Chao-ying Fu <fu@mips.com>
65
66 * mips-opc.c (MT32): New define.
67 (mips_builtin_opcodes): Move "bc0f", "bc0fl", "bc0t", "bc0tl" to the
68 bottom to avoid opcode collision with "mftr" and "mttr".
69 Add MT instructions.
70 * mips-dis.c (mips_arch_choices): Enable INSN_MT for mips32r2.
71 (print_insn_args): Add supports for +t, +T, !, $, *, &, g operand
72 formats.
73
b13dd07a
PB		 742005-09-02 Paul Brook <paul@codesourcery.com>
75
76 * arm-dis.c (coprocessor_opcodes): Add null terminator.
77
8f06b2d8
PB		 782005-09-02 Paul Brook <paul@codesourcery.com>
79
80 * arm-dis.c (coprocessor_opcodes): New.
81 (arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
82 (print_insn_coprocessor): New function.
83 (print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
84 format characters.
85 (print_insn_thumb32): Use print_insn_coprocessor.
86
a2dfd01f
PB		 872005-08-30 Paul Brook <paul@codesourcery.com>
88
89 * arm-dis.c (thumb_opcodes): Disassemble sub(3) as subs.
90
3f31e633
JB		 912005-08-26 Jan Beulich <jbeulich@novell.com>
92
93 * i386-dis.c (intel_operand_size): New, broken out from OP_E for
94 re-use.
95 (OP_E): Call intel_operand_size, move call site out of mode
96 dependent code.
97 (OP_OFF): Call intel_operand_size if suffix_always. Remove
98 ATTRIBUTE_UNUSED from parameters.
99 (OP_OFF64): Likewise.
100 (OP_ESreg): Call intel_operand_size.
101 (OP_DSreg): Likewise.
102 (OP_DIR): Use colon rather than semicolon as separator of far
103 jump/call operands.
104
fd25c5a9
CF		 1052005-08-25 Chao-ying Fu <fu@mips.com>
106
107 * mips-opc.c (WR_a, RD_a, MOD_a, DSP_VOLA, D32): New define.
108 (mips_builtin_opcodes): Add DSP instructions.
109 * mips-dis.c (mips_arch_choices): Enable INSN_DSP for mips32, mips32r2,
110 mips64, mips64r2.
111 (print_insn_args): Add supports for 3, 4, 5, 6, 7, 8, 9, 0, :, ', @
112 operand formats.
113
dd8b7c22
DU		 1142005-08-23 David Ung <davidu@mips.com>
115
116 * mips16-opc.c (mips16_opcodes): Add the MIPS16e jalrc/jrc
117 instructions to the table.
118
c17ae8a2
AM		 1192005-08-18 Alan Modra <amodra@bigpond.net.au>
120
848cf006 121 * a29k-dis.c: Delete.
c17ae8a2
AM		 122 * Makefile.am: Remove a29k support.
123 * configure.in: Likewise.
124 * disassemble.c: Likewise.
125 * Makefile.in: Regenerate.
126 * configure: Regenerate.
127 * po/POTFILES.in: Regenerate.
128
36ae0db3
DJ		 1292005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
130
131 * ppc-dis.c (powerpc_dialect): Handle e300.
132 (print_ppc_disassembler_options): Likewise.
133 * ppc-opc.c (PPCE300): Define.
134 (powerpc_opcodes): Mark icbt as available for the e300.
135
63a3357b
DA		 1362005-08-13 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
137
138 * hppa-dis.c (print_insn_hppa): Don't print '%' before register names.
139 Use "rp" instead of "%r2" in "b,l" insns.
140
ad101263
MS		 1412005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
142
143 * s390-dis.c (print_insn_s390): Print unsigned operands with %u.
144 * s390-mkopc.c (s390_opcode_cpu_val): Add support for cpu type z9-109.
145 (main): Likewise.
146 * s390-opc.c (I32_16, U32_16, M_16): Add defines 32 bit immediates
147 and 4 bit optional masks.
148 (INSTR_RIL_RI, INSTR_RIL_RU, INSTR_RRF_M0RR, INSTR_RSE_CCRD,
149 INSTR_RSY_CCRD, INSTR_SSF_RRDRD): Add new instruction formats.
150 (MASK_RIL_RI, MASK_RIL_RU, MASK_RRF_M0RR, MASK_RSE_CCRD,
151 MASK_RSY_CCRD, MASK_SSF_RRDRD): Likewise.
152 (s390_opformats): Likewise.
153 * s390-opc.txt: Add new instructions for cpu type z9-109.
154
f1fa1093
DA		 1552005-08-05 John David Anglin <dave.anglin@nrc-crnc.gc.ca>
156
157 * hppa-dis.c (print_insn_hppa): Prefix 21-bit values with "L%".
158
e9f89963
PB		 1592005-07-29 Paul Brook <paul@codesourcery.com>
160
161 * arm-dis.c: Fix disassebly of thumb2 writeback addressing modes.
162
92e90b6e
PB		 1632005-07-29 Paul Brook <paul@codesourcery.com>
164
165 * arm-dis.c (thumb32_opc): Fix addressing mode for tbh.
166 (print_insn_thumb32): Fix decoding of thumb2 'I' operands.
167
fd54057a
DD		 1682005-07-25 DJ Delorie <dj@redhat.com>
169
170 * m32c-asm.c Regenerate.
171 * m32c-dis.c Regenerate.
172
760c0f6a
DD		 1732005-07-20 DJ Delorie <dj@redhat.com>
174
175 * disassemble.c (disassemble_init_for_target): M32C ISAs are
176 enums, so convert them to bit masks, which attributes are.
177
85da3a56
NC		 1782005-07-18 Nick Clifton <nickc@redhat.com>
179
180 * configure.in: Restore alpha ordering to list of arches.
181 * configure: Regenerate.
182 * disassemble.c: Restore alpha ordering to list of arches.
183
1842005-07-18 Nick Clifton <nickc@redhat.com>
185
186 * m32c-asm.c: Regenerate.
187 * m32c-desc.c: Regenerate.
188 * m32c-desc.h: Regenerate.
189 * m32c-dis.c: Regenerate.
190 * m32c-ibld.h: Regenerate.
191 * m32c-opc.c: Regenerate.
192 * m32c-opc.h: Regenerate.
193
22cbf2e7
L		 1942005-07-18 H.J. Lu <hongjiu.lu@intel.com>
195
196 * i386-dis.c (PNI_Fixup): Update comment.
197 (VMX_Fixup): Properly handle the suffix check.
198
0aea0460
DA		 1992005-07-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
200
201 * hppa-dis.c (print_insn_hppa): Add space after 'w' in wide-mode
202 mfctl disassembly.
203
0f82ff91
AM		 2042005-07-16 Alan Modra <amodra@bigpond.net.au>
205
206 * Makefile.am: Run "make dep-am".
207 (stamp-m32c): Fix cpu dependencies.
208 * Makefile.in: Regenerate.
209 * ip2k-dis.c: Regenerate.
210
90700ea2
L		 2112007-07-15 H.J. Lu <hongjiu.lu@intel.com>
212
213 * i386-dis.c (OP_VMX): New. Handle Intel VMX Instructions.
214 (VMX_Fixup): New. Fix up Intel VMX Instructions.
215 (Em): New.
216 (Gm): New.
217 (VM): New.
218 (dis386_twobyte): Updated entries 0x78 and 0x79.
219 (twobyte_has_modrm): Likewise.
220 (grps): Use OP_VMX in the "sgdtIQ" entry. Updated GRP9.
221 (OP_G): Handle m_mode.
222
49f58d10
JB		 2232005-07-14 Jim Blandy <jimb@redhat.com>
224
225 Add support for the Renesas M32C and M16C.
226 * m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c: New.
227 * m32c-desc.h, m32c-opc.h: New.
228 * Makefile.am (HFILES): List m32c-desc.h and m32c-opc.h.
229 (CFILES): List m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c,
230 m32c-opc.c.
231 (ALL_MACHINES): List m32c-asm.lo, m32c-desc.lo, m32c-dis.lo,
232 m32c-ibld.lo, m32c-opc.lo.
233 (CLEANFILES): List stamp-m32c.
234 (M32C_DEPS): List stamp-m32c, if CGEN_MAINT.
235 (CGEN_CPUS): Add m32c.
236 (m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c)
237 (m32c-desc.h, m32c-opc.h): Depend on M32C_DEPS.
238 (m32c_opc_h): New variable.
239 (stamp-m32c, m32c-asm.lo, m32c-desc.lo, m32c-dis.lo, m32c-ibld.lo)
240 (m32c-opc.lo): New rules.
241 * Makefile.in: Regenerated.
242 * configure.in: Add case for bfd_m32c_arch.
243 * configure: Regenerated.
244 * disassemble.c (ARCH_m32c): New.
245 [ARCH_m32c]: #include "m32c-desc.h".
246 (disassembler) [ARCH_m32c]: Add case for bfd_arch_m32c.
247 (disassemble_init_for_target) [ARCH_m32c]: Same.
248
249 * cgen-ops.h, cgen-types.h: New files.
250 * Makefile.am (HFILES): List them.
251 * Makefile.in: Regenerated.
252
0fd3a477
JW		 2532005-07-07 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
254
255 * arc-dis.c, arm-dis.c, cris-dis.c, crx-dis.c, d10v-dis.c,
256 d30v-dis.c, fr30-dis.c, h8300-dis.c, h8500-dis.c, i860-dis.c,
257 ia64-dis.c, ip2k-dis.c, m10200-dis.c, m10300-dis.c,
258 m88k-dis.c, mcore-dis.c, mips-dis.c, ms1-dis.c, or32-dis.c,
259 ppc-dis.c, sh64-dis.c, sparc-dis.c, tic4x-dis.c, tic80-dis.c,
260 v850-dis.c: Fix format bugs.
261 * ia64-gen.c (fail, warn): Add format attribute.
262 * or32-opc.c (debug): Likewise.
263
22f8fcbd
NC		 2642005-07-07 Khem Raj <kraj@mvista.com>
265
266 * arm-dis.c (opcode32 arm_opcodes): Fix ARM VFP fadds instruction
267 disassembly pattern.
268
d125c27b
AM		 2692005-07-06 Alan Modra <amodra@bigpond.net.au>
270
271 * Makefile.am (stamp-m32r): Fix path to cpu files.
272 (stamp-m32r, stamp-iq2000): Likewise.
273 * Makefile.in: Regenerate.
274 * m32r-asm.c: Regenerate.
275 * po/POTFILES.in: Remove arm-opc.h. Add ms1-asm.c, ms1-desc.c,
276 ms1-desc.h, ms1-dis.c, ms1-ibld.c, ms1-opc.c, ms1-opc.h.
277
3ec2b351
NC		 2782005-07-05 Nick Clifton <nickc@redhat.com>
279
280 * iq2000-asm.c: Regenerate.
281 * ms1-asm.c: Regenerate.
282
30123838
JB		 2832005-07-05 Jan Beulich <jbeulich@novell.com>
284
285 * i386-dis.c (SVME_Fixup): New.
286 (grps): Use it for the lidt entry.
287 (PNI_Fixup): Call OP_M rather than OP_E.
288 (INVLPG_Fixup): Likewise.
289
b0eec63e
L		 2902005-07-04 H.J. Lu <hongjiu.lu@intel.com>
291
292 * tic30-dis.c (cnvt_tmsfloat_ieee): Use HUGE_VALF if defined.
293
47b0e7ad
NC		 2942005-07-01 Nick Clifton <nickc@redhat.com>
295
296 * a29k-dis.c: Update to ISO C90 style function declarations and
297 fix formatting.
298 * alpha-opc.c: Likewise.
299 * arc-dis.c: Likewise.
300 * arc-opc.c: Likewise.
301 * avr-dis.c: Likewise.
302 * cgen-asm.in: Likewise.
303 * cgen-dis.in: Likewise.
304 * cgen-ibld.in: Likewise.
305 * cgen-opc.c: Likewise.
306 * cris-dis.c: Likewise.
307 * d10v-dis.c: Likewise.
308 * d30v-dis.c: Likewise.
309 * d30v-opc.c: Likewise.
310 * dis-buf.c: Likewise.
311 * dlx-dis.c: Likewise.
312 * h8300-dis.c: Likewise.
313 * h8500-dis.c: Likewise.
314 * hppa-dis.c: Likewise.
315 * i370-dis.c: Likewise.
316 * i370-opc.c: Likewise.
317 * m10200-dis.c: Likewise.
318 * m10300-dis.c: Likewise.
319 * m68k-dis.c: Likewise.
320 * m88k-dis.c: Likewise.
321 * mips-dis.c: Likewise.
322 * mmix-dis.c: Likewise.
323 * msp430-dis.c: Likewise.
324 * ns32k-dis.c: Likewise.
325 * or32-dis.c: Likewise.
326 * or32-opc.c: Likewise.
327 * pdp11-dis.c: Likewise.
328 * pj-dis.c: Likewise.
329 * s390-dis.c: Likewise.
330 * sh-dis.c: Likewise.
331 * sh64-dis.c: Likewise.
332 * sparc-dis.c: Likewise.
333 * sparc-opc.c: Likewise.
334 * sysdep.h: Likewise.
335 * tic30-dis.c: Likewise.
336 * tic4x-dis.c: Likewise.
337 * tic80-dis.c: Likewise.
338 * v850-dis.c: Likewise.
339 * v850-opc.c: Likewise.
340 * vax-dis.c: Likewise.
341 * w65-dis.c: Likewise.
342 * z8kgen.c: Likewise.
343
344 * fr30-*: Regenerate.
345 * frv-*: Regenerate.
346 * ip2k-*: Regenerate.
347 * iq2000-*: Regenerate.
348 * m32r-*: Regenerate.
349 * ms1-*: Regenerate.
350 * openrisc-*: Regenerate.
351 * xstormy16-*: Regenerate.
352
cc16ba8c
BE		 3532005-06-23 Ben Elliston <bje@gnu.org>
354
355 * m68k-dis.c: Use ISC C90.
356 * m68k-opc.c: Formatting fixes.
357
4b185e97
DU		 3582005-06-16 David Ung <davidu@mips.com>
359
360 * mips16-opc.c (mips16_opcodes): Add the following MIPS16e
361 instructions to the table; seb/seh/sew/zeb/zeh/zew.
362
ac188222
DB		 3632005-06-15 Dave Brolley <brolley@redhat.com>
364
365 Contribute Morpho ms1 on behalf of Red Hat
366 * ms1-asm.c, ms1-desc.c, ms1-dis.c, ms1-ibld.c, ms1-opc.c,
367 ms1-opc.h: New files, Morpho ms1 target.
368
369 2004-05-14 Stan Cox <scox@redhat.com>
370
371 * disassemble.c (ARCH_ms1): Define.
372 (disassembler): Handle bfd_arch_ms1
373
374 2004-05-13 Michael Snyder <msnyder@redhat.com>
375
376 * Makefile.am, Makefile.in: Add ms1 target.
377 * configure.in: Ditto.
378
6b5d3a4d
ZW		 3792005-06-08 Zack Weinberg <zack@codesourcery.com>
380
381 * arm-opc.h: Delete; fold contents into ...
382 * arm-dis.c: ... here. Move includes of internal COFF headers
383 next to includes of internal ELF headers.
384 (streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused.
385 (struct arm_opcode): Rename struct opcode32. Make 'assembler' const.
386 (struct thumb_opcode): Rename struct opcode16. Make 'assembler' const.
387 (arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames)
388 (iwmmxt_wwnames, iwmmxt_wwssnames):
389 Make const.
390 (regnames): Remove iWMMXt coprocessor register sets.
391 (iwmmxt_regnames, iwmmxt_cregnames): New statics.
392 (get_arm_regnames): Adjust fourth argument to match above changes.
393 (set_iwmmxt_regnames): Delete.
394 (print_insn_arm): Constify 'c'. Use ISO syntax for function
395 pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames
396 and iwmmxt_cregnames, not set_iwmmxt_regnames.
397 (print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use
398 ISO syntax for function pointer calls.
399
4a5329c6
ZW		 4002005-06-07 Zack Weinberg <zack@codesourcery.com>
401
402 * arm-dis.c: Split up the comments describing the format codes, so
403 that the ARM and 16-bit Thumb opcode tables each have comments
404 preceding them that describe all the codes, and only the codes,
405 valid in those tables. (32-bit Thumb table is already like this.)
406 Reorder the lists in all three comments to match the order in
407 which the codes are implemented.
408 Remove all forward declarations of static functions. Convert all
409 function definitions to ISO C format.
410 (print_insn_arm, print_insn_thumb16, print_insn_thumb32):
411 Return nothing.
412 (print_insn_thumb16): Remove unused case 'I'.
413 (print_insn): Update for changed calling convention of subroutines.
414
3d456fa1
JB		 4152005-05-25 Jan Beulich <jbeulich@novell.com>
416
417 * i386-dis.c (OP_E): In Intel mode, display 32-bit displacements in
418 hex (but retain it being displayed as signed). Remove redundant
419 checks. Add handling of displacements for 16-bit addressing in Intel
420 mode.
421
2888cb7a
JB		 4222005-05-25 Jan Beulich <jbeulich@novell.com>
423
424 * i386-dis.c (prefix_name): Remove pointless mode_64bit check.
425 (OP_E): Remove redundant REX_EXTZ handling. Remove pointless
426 masking of 'rm' in 16-bit memory address handling.
427
1ed8e1e4
AM		 4282005-05-19 Anton Blanchard <anton@samba.org>
429
430 * ppc-dis.c (powerpc_dialect): Handle "-Mpower5".
431 (print_ppc_disassembler_options): Document it.
432 * ppc-opc.c (SVC_LEV): Define.
433 (LEV): Allow optional operand.
434 (POWER5): Define.
435 (powerpc_opcodes): Extend "sc". Adjust "svc" and "svcl". Add
436 "hrfid", "popcntb", "fsqrtes", "fsqrtes.", "fre" and "fre.".
437
49cc2e69
KC		 4382005-05-19 Kelley Cook <kcook@gcc.gnu.org>
439
440 * Makefile.in: Regenerate.
441
c19d1205
ZW		 4422005-05-17 Zack Weinberg <zack@codesourcery.com>
443
444 * arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
445 instructions. Adjust disassembly of some opcodes to match
446 unified syntax.
447 (thumb32_opcodes): New table.
448 (print_insn_thumb): Rename print_insn_thumb16; don't handle
449 two-halfword branches here.
450 (print_insn_thumb32): New function.
451 (print_insn): Choose among print_insn_arm, print_insn_thumb16,
452 and print_insn_thumb32. Be consistent about order of
453 halfwords when printing 32-bit instructions.
454
003519a7
L		 4552005-05-07 H.J. Lu <hongjiu.lu@intel.com>
456
457 PR 843
458 * i386-dis.c (branch_v_mode): New.
459 (indirEv): Use branch_v_mode instead of v_mode.
460 (OP_E): Handle branch_v_mode.
461
920a34a7
L		 4622005-05-07 H.J. Lu <hongjiu.lu@intel.com>
463
464 * d10v-dis.c (dis_2_short): Support 64bit host.
465
5de773c1
NC		 4662005-05-07 Nick Clifton <nickc@redhat.com>
467
468 * po/nl.po: Updated translation.
469
f4321104
NC		 4702005-05-07 Nick Clifton <nickc@redhat.com>
471
472 * Update the address and phone number of the FSF organization in
473 the GPL notices in the following files:
474 a29k-dis.c, aclocal.m4, alpha-dis.c, alpha-opc.c, arc-dis.c,
475 arc-dis.h, arc-ext.c, arc-ext.h, arc-opc.c, arm-dis.c, arm-opc.h,
476 avr-dis.c, cgen-asm.c, cgen-asm.in, cgen-dis.c, cgen-dis.in,
477 cgen-ibld.in, cgen-opc.c, cgen.sh, cris-dis.c, cris-opc.c,
478 crx-dis.c, crx-opc.c, d10v-dis.c, d10v-opc.c, d30v-dis.c,
479 d30v-opc.c, dis-buf.c, dis-init.c, disassemble.c, dlx-dis.c,
480 fr30-asm.c, fr30-desc.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c,
481 fr30-opc.c, fr30-opc.h, frv-asm.c, frv-desc.c, frv-desc.h,
482 frv-dis.c, frv-ibld.c, frv-opc.c, frv-opc.h, h8300-dis.c,
483 h8500-dis.c, h8500-opc.h, hppa-dis.c, i370-dis.c, i370-opc.c,
484 i386-dis.c, i860-dis.c, i960-dis.c, ia64-asmtab.h, ia64-dis.c,
485 ia64-gen.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-d.c,
486 ia64-opc-f.c, ia64-opc-i.c, ia64-opc-m.c, ia64-opc-x.c,
487 ia64-opc.c, ia64-opc.h, ip2k-asm.c, ip2k-desc.c, ip2k-desc.h,
488 ip2k-dis.c, ip2k-ibld.c, ip2k-opc.c, ip2k-opc.h, iq2000-asm.c,
489 iq2000-desc.c, iq2000-desc.h, iq2000-dis.c, iq2000-ibld.c,
490 iq2000-opc.c, iq2000-opc.h, m10200-dis.c, m10200-opc.c,
491 m10300-dis.c, m10300-opc.c, m32r-asm.c, m32r-desc.c, m32r-desc.h,
492 m32r-dis.c, m32r-ibld.c, m32r-opc.c, m32r-opc.h, m32r-opinst.c,
493 m68hc11-dis.c, m68hc11-opc.c, m68k-dis.c, m68k-opc.c, m88k-dis.c,
494 maxq-dis.c, mcore-dis.c, mcore-opc.h, mips-dis.c, mips-opc.c,
495 mips16-opc.c, mmix-dis.c, mmix-opc.c, msp430-dis.c, ns32k-dis.c,
496 openrisc-asm.c, openrisc-desc.c, openrisc-desc.h, openrisc-dis.c,
497 openrisc-ibld.c, openrisc-opc.c, openrisc-opc.h, opintl.h,
498 or32-dis.c, or32-opc.c, pdp11-dis.c, pdp11-opc.c, pj-dis.c,
499 pj-opc.c, ppc-dis.c, ppc-opc.c, s390-dis.c, s390-mkopc.c,
500 s390-opc.c, sh-dis.c, sh-opc.h, sh64-dis.c, sh64-opc.c,
501 sh64-opc.h, sparc-dis.c, sparc-opc.c, sysdep.h, tic30-dis.c,
502 tic4x-dis.c, tic54x-dis.c, tic54x-opc.c, tic80-dis.c, tic80-opc.c,
503 v850-dis.c, v850-opc.c, vax-dis.c, w65-dis.c, w65-opc.h,
504 xstormy16-asm.c, xstormy16-desc.c, xstormy16-desc.h,
505 xstormy16-dis.c, xstormy16-ibld.c, xstormy16-opc.c,
506 xstormy16-opc.h, xtensa-dis.c, z8k-dis.c, z8kgen.c
507
10b076a2
JW		 5082005-05-05 James E Wilson <wilson@specifixinc.com>
509
510 * ia64-opc.c: Include sysdep.h before libiberty.h.
511
022716b6
NC		 5122005-05-05 Nick Clifton <nickc@redhat.com>
513
514 * configure.in (ALL_LINGUAS): Add vi.
515 * configure: Regenerate.
516 * po/vi.po: New.
517
db5152b4
JG		 5182005-04-26 Jerome Guitton <guitton@gnat.com>
519
520 * configure.in: Fix the check for basename declaration.
521 * configure: Regenerate.
522
eed0d89a
AM		 5232005-04-19 Alan Modra <amodra@bigpond.net.au>
524
525 * ppc-opc.c (RTO): Define.
526 (powerpc_opcodes <tlbsx, tlbsx., tlbre>): Combine PPC403 and BOOKE
527 entries to suit PPC440.
528
791fe849
MK		 5292005-04-18 Mark Kettenis <kettenis@gnu.org>
530
531 * i386-dis.c: Insert hyphens into selected VIA PadLock extensions.
532 Add xcrypt-ctr.
533
ffe58f7c
NC		 5342005-04-14 Nick Clifton <nickc@redhat.com>
535
536 * po/fi.po: New translation: Finnish.
537 * configure.in (ALL_LINGUAS): Add fi.
538 * configure: Regenerate.
539
9e9b66a9
AM		 5402005-04-14 Alan Modra <amodra@bigpond.net.au>
541
542 * Makefile.am (NO_WERROR): Define.
543 * configure.in: Invoke AM_BINUTILS_WARNINGS.
544 * Makefile.in: Regenerate.
545 * aclocal.m4: Regenerate.
546 * configure: Regenerate.
547
9494d739
NC		 5482005-04-04 Nick Clifton <nickc@redhat.com>
549
550 * fr30-asm.c: Regenerate.
551 * frv-asm.c: Regenerate.
552 * iq2000-asm.c: Regenerate.
553 * m32r-asm.c: Regenerate.
554 * openrisc-asm.c: Regenerate.
555
6128c599
JB		 5562005-04-01 Jan Beulich <jbeulich@novell.com>
557
558 * i386-dis.c (PNI_Fixup): Neither mwait nor monitor have any
559 visible operands in Intel mode. The first operand of monitor is
560 %rax in 64-bit mode.
561
373ff435
JB		 5622005-04-01 Jan Beulich <jbeulich@novell.com>
563
564 * i386-dis.c (INVLPG_Fixup): Decode rdtscp; change code to allow for
565 easier future additions.
566
4bd60896
JG		 5672005-03-31 Jerome Guitton <guitton@gnat.com>
568
569 * configure.in: Check for basename.
570 * configure: Regenerate.
571 * config.in: Ditto.
572
4cc91dba
L		 5732005-03-29 H.J. Lu <hongjiu.lu@intel.com>
574
575 * i386-dis.c (SEG_Fixup): New.
576 (Sv): New.
577 (dis386): Use "Sv" for 0x8c and 0x8e.
578
ec72cfe5
NC		 5792005-03-21 Jan-Benedict Glaw <jbglaw@lug-owl.de>
580 Nick Clifton <nickc@redhat.com>
c19d1205 581
ec72cfe5
NC		 582 * vax-dis.c: (entry_addr): New varible: An array of user supplied
583 function entry mask addresses.
584 (entry_addr_occupied_slots): New variable: The number of occupied
c19d1205 585 elements in entry_addr.
ec72cfe5
NC		 586 (entry_addr_total_slots): New variable: The total number of
587 elements in entry_addr.
588 (parse_disassembler_options): New function. Fills in the entry_addr
589 array.
590 (free_entry_array): New function. Release the memory used by the
591 entry addr array. Suppressed because there is no way to call it.
592 (is_function_entry): Check if a given address is a function's
593 start address by looking at supplied entry mask addresses and
594 symbol information, if available.
595 (print_insn_vax): Use parse_disassembler_options and is_function_entry.
596
85064c79
L		 5972005-03-23 H.J. Lu <hongjiu.lu@intel.com>
598
599 * cris-dis.c (print_with_operands): Use ~31L for long instead
600 of ~31.
601
de7141c7
L		 6022005-03-20 H.J. Lu <hongjiu.lu@intel.com>
603
604 * mmix-opc.c (O): Revert the last change.
605 (Z): Likewise.
606
e493ab45
L		 6072005-03-19 H.J. Lu <hongjiu.lu@intel.com>
608
609 * mmix-opc.c (O): Use 24UL instead of 24 for unsigned long.
610 (Z): Likewise.
611
d8d7c459
HPN		 6122005-03-19 Hans-Peter Nilsson <hp@bitrange.com>
613
614 * mmix-opc.c (O, Z): Force expression as unsigned long.
615
ebdb0383
NC		 6162005-03-18 Nick Clifton <nickc@redhat.com>
617
618 * ip2k-asm.c: Regenerate.
619 * op/opcodes.pot: Regenerate.
620
1ad12f97
NC		 6212005-03-16 Nick Clifton <nickc@redhat.com>
622 Ben Elliston <bje@au.ibm.com>
623
569acd2c 624 * configure.in (werror): New switch: Add -Werror to the
1ad12f97 625 compiler command line. Enabled by default. Disable via
569acd2c 626 --disable-werror.
1ad12f97
NC		 627 * configure: Regenerate.
628
4eb30afc
AM		 6292005-03-16 Alan Modra <amodra@bigpond.net.au>
630
631 * ppc-dis.c (powerpc_dialect): Don't set PPC_OPCODE_ALTIVEC when
632 BOOKE.
633
ea8409f7
AM		 6342005-03-15 Alan Modra <amodra@bigpond.net.au>
635
729ae8d2
AM		 636 * po/es.po: Commit new Spanish translation.
637
ea8409f7
AM		 638 * po/fr.po: Commit new French translation.
639
4f495e61
NC		 6402005-03-14 Jan-Benedict Glaw <jbglaw@lug-owl.de>
641
642 * vax-dis.c: Fix spelling error
643 (print_insn_vax): Use ".word 0x0012 # Entry mask: r1 r2 >" instead
644 of just "Entry mask: < r1 ... >"
645
0a003adc
ZW		 6462005-03-12 Zack Weinberg <zack@codesourcery.com>
647
648 * arm-dis.c (arm_opcodes): Document %E and %V.
649 Add entries for v6T2 ARM instructions:
650 bfc bfi mls strht ldrht ldrsht ldrsbt movw movt rbit ubfx sbfx.
651 (print_insn_arm): Add support for %E and %V.
885fc257 652 (thumb_opcodes): Add ARMv6K instructions nop, sev, wfe, wfi, yield.
0a003adc 653
da99ee72
AM		 6542005-03-10 Jeff Baker <jbaker@qnx.com>
655 Alan Modra <amodra@bigpond.net.au>
656
657 * ppc-opc.c (insert_sprg, extract_sprg): New Functions.
658 (powerpc_operands <SPRG>): Call the above. Bit field is 5 bits.
659 (SPRG_MASK): Delete.
660 (XSPRG_MASK): Mask off extra bits now part of sprg field.
0a003adc 661 (powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask. Move
da99ee72
AM		 662 mfsprg4..7 after msprg and consolidate.
663
220abb21
AM		 6642005-03-09 Jan-Benedict Glaw <jbglaw@lug-owl.de>
665
666 * vax-dis.c (entry_mask_bit): New array.
667 (print_insn_vax): Decode function entry mask.
668
0e06657a
AH		 6692005-03-07 Aldy Hernandez <aldyh@redhat.com>
670
671 * ppc-opc.c (powerpc_opcodes): Fix encoding of efscfd.
672
06647dfd
AM		 6732005-03-05 Alan Modra <amodra@bigpond.net.au>
674
675 * po/opcodes.pot: Regenerate.
676
82b829a7
RR		 6772005-03-03 Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
678
220abb21 679 * arc-dis.c (a4_decoding_class): New enum.
06647dfd
AM		 680 (dsmOneArcInst): Use the enum values for the decoding class.
681 Remove redundant case in the switch for decodingClass value 11.
82b829a7 682
c4a530c5
JB		 6832005-03-02 Jan Beulich <jbeulich@novell.com>
684
685 * i386-dis.c (print_insn): Suppress lock prefix printing for cr8...15
686 accesses.
687 (OP_C): Consider lock prefix in non-64-bit modes.
688
47d8304e
AM		 6892005-02-24 Alan Modra <amodra@bigpond.net.au>
690
691 * cris-dis.c (format_hex): Remove ineffective warning fix.
692 * crx-dis.c (make_instruction): Warning fix.
693 * frv-asm.c: Regenerate.
694
ec36c4a4
NC		 6952005-02-23 Nick Clifton <nickc@redhat.com>
696
33b71eeb
NC		 697 * cgen-dis.in: Use bfd_byte for buffers that are passed to
698 read_memory.
06647dfd 699
33b71eeb 700 * ia64-opc.c (locate_opcode_ent): Initialise opval array.
06647dfd 701
ec36c4a4
NC		 702 * crx-dis.c (make_instruction): Move argument structure into inner
703 scope and ensure that all of its fields are initialised before
704 they are used.
705
33b71eeb
NC		 706 * fr30-asm.c: Regenerate.
707 * fr30-dis.c: Regenerate.
708 * frv-asm.c: Regenerate.
709 * frv-dis.c: Regenerate.
710 * ip2k-asm.c: Regenerate.
711 * ip2k-dis.c: Regenerate.
712 * iq2000-asm.c: Regenerate.
713 * iq2000-dis.c: Regenerate.
714 * m32r-asm.c: Regenerate.
715 * m32r-dis.c: Regenerate.
716 * openrisc-asm.c: Regenerate.
717 * openrisc-dis.c: Regenerate.
718 * xstormy16-asm.c: Regenerate.
719 * xstormy16-dis.c: Regenerate.
720
53c9ebc5
AM		 7212005-02-22 Alan Modra <amodra@bigpond.net.au>
722
723 * arc-ext.c: Warning fixes.
724 * arc-ext.h: Likewise.
725 * cgen-opc.c: Likewise.
726 * ia64-gen.c: Likewise.
727 * maxq-dis.c: Likewise.
728 * ns32k-dis.c: Likewise.
729 * w65-dis.c: Likewise.
730 * ia64-asmtab.c: Regenerate.
731
610ad19b
AM		 7322005-02-22 Alan Modra <amodra@bigpond.net.au>
733
734 * fr30-desc.c: Regenerate.
735 * fr30-desc.h: Regenerate.
736 * fr30-opc.c: Regenerate.
737 * fr30-opc.h: Regenerate.
738 * frv-desc.c: Regenerate.
739 * frv-desc.h: Regenerate.
740 * frv-opc.c: Regenerate.
741 * frv-opc.h: Regenerate.
742 * ip2k-desc.c: Regenerate.
743 * ip2k-desc.h: Regenerate.
744 * ip2k-opc.c: Regenerate.
745 * ip2k-opc.h: Regenerate.
746 * iq2000-desc.c: Regenerate.
747 * iq2000-desc.h: Regenerate.
748 * iq2000-opc.c: Regenerate.
749 * iq2000-opc.h: Regenerate.
750 * m32r-desc.c: Regenerate.
751 * m32r-desc.h: Regenerate.
752 * m32r-opc.c: Regenerate.
753 * m32r-opc.h: Regenerate.
754 * m32r-opinst.c: Regenerate.
755 * openrisc-desc.c: Regenerate.
756 * openrisc-desc.h: Regenerate.
757 * openrisc-opc.c: Regenerate.
758 * openrisc-opc.h: Regenerate.
759 * xstormy16-desc.c: Regenerate.
760 * xstormy16-desc.h: Regenerate.
761 * xstormy16-opc.c: Regenerate.
762 * xstormy16-opc.h: Regenerate.
763
db9db6f2
AM		 7642005-02-21 Alan Modra <amodra@bigpond.net.au>
765
766 * Makefile.am: Run "make dep-am"
767 * Makefile.in: Regenerate.
768
bf143b25
NC		 7692005-02-15 Nick Clifton <nickc@redhat.com>
770
771 * cgen-dis.in (print_address): Add an ATTRIBUTE_UNUSED to prevent
772 compile time warnings.
773 (print_keyword): Likewise.
774 (default_print_insn): Likewise.
775
776 * fr30-desc.c: Regenerated.
777 * fr30-desc.h: Regenerated.
778 * fr30-dis.c: Regenerated.
779 * fr30-opc.c: Regenerated.
780 * fr30-opc.h: Regenerated.
781 * frv-desc.c: Regenerated.
782 * frv-dis.c: Regenerated.
783 * frv-opc.c: Regenerated.
784 * ip2k-asm.c: Regenerated.
785 * ip2k-desc.c: Regenerated.
786 * ip2k-desc.h: Regenerated.
787 * ip2k-dis.c: Regenerated.
788 * ip2k-opc.c: Regenerated.
789 * ip2k-opc.h: Regenerated.
790 * iq2000-desc.c: Regenerated.
791 * iq2000-dis.c: Regenerated.
792 * iq2000-opc.c: Regenerated.
793 * m32r-asm.c: Regenerated.
794 * m32r-desc.c: Regenerated.
795 * m32r-desc.h: Regenerated.
796 * m32r-dis.c: Regenerated.
797 * m32r-opc.c: Regenerated.
798 * m32r-opc.h: Regenerated.
799 * m32r-opinst.c: Regenerated.
800 * openrisc-desc.c: Regenerated.
801 * openrisc-desc.h: Regenerated.
802 * openrisc-dis.c: Regenerated.
803 * openrisc-opc.c: Regenerated.
804 * openrisc-opc.h: Regenerated.
805 * xstormy16-desc.c: Regenerated.
806 * xstormy16-desc.h: Regenerated.
807 * xstormy16-dis.c: Regenerated.
808 * xstormy16-opc.c: Regenerated.
809 * xstormy16-opc.h: Regenerated.
810
d6098898
L		 8112005-02-14 H.J. Lu <hongjiu.lu@intel.com>
812
813 * dis-buf.c (perror_memory): Use sprintf_vma to print out
814 address.
815
5a84f3e0
NC		 8162005-02-11 Nick Clifton <nickc@redhat.com>
817
bc18c937
NC		 818 * iq2000-asm.c: Regenerate.
819
5a84f3e0
NC		 820 * frv-dis.c: Regenerate.
821
0a40490e
JB		 8222005-02-07 Jim Blandy <jimb@redhat.com>
823
824 * Makefile.am (CGEN): Load guile.scm before calling the main
825 application script.
826 * Makefile.in: Regenerated.
827 * cgen.sh: Be prepared for the 'cgen' argument to contain spaces.
828 Simply pass the cgen-opc.scm path to ${cgen} as its first
829 argument; ${cgen} itself now contains the '-s', or whatever is
830 appropriate for the Scheme being used.
831
c46f8c51
AC		 8322005-01-31 Andrew Cagney <cagney@gnu.org>
833
834 * configure: Regenerate to track ../gettext.m4.
835
60b9a617
JB		 8362005-01-31 Jan Beulich <jbeulich@novell.com>
837
838 * ia64-gen.c (NELEMS): Define.
839 (shrink): Generate alias with missing second predicate register when
840 opcode has two outputs and these are both predicates.
841 * ia64-opc-i.c (FULL17): Define.
842 (ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
843 here to generate output template.
844 (TBITCM, TNATCM): Undefine after use.
845 * ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
846 first input. Add ld16 aliases without ar.csd as second output. Add
847 st16 aliases without ar.csd as second input. Add cmpxchg aliases
848 without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
849 ar.ccv as third/fourth inputs. Consolidate through...
850 (CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
851 CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
852 * ia64-asmtab.c: Regenerate.
853
a53bf506
AC		 8542005-01-27 Andrew Cagney <cagney@gnu.org>
855
856 * configure: Regenerate to track ../gettext.m4 change.
857
90219bd0
AO		 8582005-01-25 Alexandre Oliva <aoliva@redhat.com>
859
860 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
861 * frv-asm.c: Rebuilt.
862 * frv-desc.c: Rebuilt.
863 * frv-desc.h: Rebuilt.
864 * frv-dis.c: Rebuilt.
865 * frv-ibld.c: Rebuilt.
866 * frv-opc.c: Rebuilt.
867 * frv-opc.h: Rebuilt.
868
45181ed1
AC		 8692005-01-24 Andrew Cagney <cagney@gnu.org>
870
871 * configure: Regenerate, ../gettext.m4 was updated.
872
9e836e3d
FF		 8732005-01-21 Fred Fish <fnf@specifixinc.com>
874
875 * mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS.
876 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
877 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
878 * mips-dis.c: Ditto.
879
5e8cb021
AM		 8802005-01-20 Alan Modra <amodra@bigpond.net.au>
881
882 * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
883
986e18a5
FF		 8842005-01-19 Fred Fish <fnf@specifixinc.com>
885
886 * mips-dis.c (no_aliases): New disassembly option flag.
887 (set_default_mips_dis_options): Init no_aliases to zero.
888 (parse_mips_dis_option): Handle no-aliases option.
889 (print_insn_mips): Ignore table entries that are aliases
890 if no_aliases is set.
891 (print_insn_mips16): Ditto.
892 * mips-opc.c (mips_builtin_opcodes): Add initializer column for
893 new pinfo2 member and add INSN_ALIAS initializers as needed. Also
894 move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
895 * mips16-opc.c (mips16_opcodes): Ditto.
896
e38bc3b5
NC		 8972005-01-17 Andrew Stubbs <andrew.stubbs@st.com>
898
899 * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
900 (inheritance diagram): Add missing edge.
901 (arch_sh1_up): Rename arch_sh_up to match external name to make life
902 easier for the testsuite.
903 (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
904 (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
610ad19b 905 (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
e38bc3b5
NC		 906 arch_sh2a_or_sh4_up child.
907 (sh_table): Do renaming as above.
908 Correct comment for ldc.l for gas testsuite to read.
909 Remove rogue mul.l from sh1 (duplicate of the one for sh2).
910 Correct comments for movy.w and movy.l for gas testsuite to read.
911 Correct comments for fmov.d and fmov.s for gas testsuite to read.
912
9df48ba9
L		 9132005-01-12 H.J. Lu <hongjiu.lu@intel.com>
914
915 * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
916
2033b4b9
L		 9172005-01-12 H.J. Lu <hongjiu.lu@intel.com>
918
919 * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
920
0bcb06d2
AS		 9212005-01-10 Andreas Schwab <schwab@suse.de>
922
923 * disassemble.c (disassemble_init_for_target) <case
924 bfd_arch_ia64>: Set skip_zeroes to 16.
925 <case bfd_arch_tic4x>: Set skip_zeroes to 32.
926
47add74d
TL		 9272004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
928
929 * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
930
246f4c05
SS		 9312004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
932
933 * avr-dis.c: Prettyprint. Added printing of symbol names in all
934 memory references. Convert avr_operand() to C90 formatting.
935
0e1200e5
TL		 9362004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
937
938 * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
939
89a649f7
TL		 9402004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
941
942 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
943 (no_op_insn): Initialize array with instructions that have no
944 operands.
945 * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
946
6255809c
RE		 9472004-11-29 Richard Earnshaw <rearnsha@arm.com>
948
949 * arm-dis.c: Correct top-level comment.
950
2fbad815
RE		 9512004-11-27 Richard Earnshaw <rearnsha@arm.com>
952
953 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
954 architecuture defining the insn.
955 (arm_opcodes, thumb_opcodes): Delete. Move to ...
6b8725b9
RE		 956 * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
957 field.
2fbad815
RE		 958 Also include opcode/arm.h.
959 * Makefile.am (arm-dis.lo): Update dependency list.
960 * Makefile.in: Regenerate.
961
d81acc42
NC		 9622004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
963
964 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
965 reflect the change to the short immediate syntax.
966
ca4f2377
AM		 9672004-11-19 Alan Modra <amodra@bigpond.net.au>
968
5da8bf1b
AM		 969 * or32-opc.c (debug): Warning fix.
970 * po/POTFILES.in: Regenerate.
971
ca4f2377
AM		 972 * maxq-dis.c: Formatting.
973 (print_insn): Warning fix.
974
b7693d02
DJ		 9752004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
976
977 * arm-dis.c (WORD_ADDRESS): Define.
978 (print_insn): Use it. Correct big-endian end-of-section handling.
979
300dac7e
NC		 9802004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
981 Vineet Sharma <vineets@noida.hcltech.com>
982
983 * maxq-dis.c: New file.
984 * disassemble.c (ARCH_maxq): Define.
610ad19b 985 (disassembler): Add 'print_insn_maxq_little' for handling maxq
300dac7e
NC		 986 instructions..
987 * configure.in: Add case for bfd_maxq_arch.
988 * configure: Regenerate.
989 * Makefile.am: Add support for maxq-dis.c
990 * Makefile.in: Regenerate.
991 * aclocal.m4: Regenerate.
992
42048ee7
TL		 9932004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
994
995 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
996 mode.
997 * crx-dis.c: Likewise.
998
bd21e58e
HPN		 9992004-11-04 Hans-Peter Nilsson <hp@axis.com>
1000
1001 Generally, handle CRISv32.
1002 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
1003 (struct cris_disasm_data): New type.
1004 (format_reg, format_hex, cris_constraint, print_flags)
1005 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
1006 callers changed.
1007 (format_sup_reg, print_insn_crisv32_with_register_prefix)
1008 (print_insn_crisv32_without_register_prefix)
1009 (print_insn_crisv10_v32_with_register_prefix)
1010 (print_insn_crisv10_v32_without_register_prefix)
1011 (cris_parse_disassembler_options): New functions.
1012 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
1013 parameter. All callers changed.
1014 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
1015 failure.
1016 (cris_constraint) <case 'Y', 'U'>: New cases.
1017 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
1018 for constraint 'n'.
1019 (print_with_operands) <case 'Y'>: New case.
1020 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
1021 <case 'N', 'Y', 'Q'>: New cases.
1022 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
1023 (print_insn_cris_with_register_prefix)
1024 (print_insn_cris_without_register_prefix): Call
1025 cris_parse_disassembler_options.
1026 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
1027 for CRISv32 and the size of immediate operands. New v32-only
1028 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
1029 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
1030 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
1031 Change brp to be v3..v10.
1032 (cris_support_regs): New vector.
1033 (cris_opcodes): Update head comment. New format characters '[',
1034 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
1035 Add new opcodes for v32 and adjust existing opcodes to accommodate
1036 differences to earlier variants.
1037 (cris_cond15s): New vector.
1038
9306ca4a
JB		 10392004-11-04 Jan Beulich <jbeulich@novell.com>
1040
1041 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
1042 (indirEb): Remove.
1043 (Mp): Use f_mode rather than none at all.
1044 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
1045 replaces what previously was x_mode; x_mode now means 128-bit SSE
1046 operands.
1047 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
1048 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
1049 pinsrw's second operand is Edqw.
1050 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
1051 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
1052 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
1053 mode when an operand size override is present or always suffixing.
1054 More instructions will need to be added to this group.
1055 (putop): Handle new macro chars 'C' (short/long suffix selector),
1056 'I' (Intel mode override for following macro char), and 'J' (for
1057 adding the 'l' prefix to far branches in AT&T mode). When an
1058 alternative was specified in the template, honor macro character when
1059 specified for Intel mode.
1060 (OP_E): Handle new *_mode values. Correct pointer specifications for
1061 memory operands. Consolidate output of index register.
1062 (OP_G): Handle new *_mode values.
1063 (OP_I): Handle const_1_mode.
1064 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
1065 respective opcode prefix bits have been consumed.
1066 (OP_EM, OP_EX): Provide some default handling for generating pointer
1067 specifications.
1068
f39c96a9
TL		 10692004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
1070
1071 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
1072 COP_INST macro.
1073
812337be
TL		 10742004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1075
1076 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
1077 (getregliststring): Support HI/LO and user registers.
610ad19b 1078 * crx-opc.c (crx_instruction): Update data structure according to the
812337be
TL		 1079 rearrangement done in CRX opcode header file.
1080 (crx_regtab): Likewise.
1081 (crx_optab): Likewise.
610ad19b 1082 (crx_instruction): Reorder load/stor instructions, remove unsupported
812337be
TL		 1083 formats.
1084 support new Co-Processor instruction 'cpi'.
1085
4030fa5a
NC		 10862004-10-27 Nick Clifton <nickc@redhat.com>
1087
1088 * opcodes/iq2000-asm.c: Regenerate.
1089 * opcodes/iq2000-desc.c: Regenerate.
1090 * opcodes/iq2000-desc.h: Regenerate.
1091 * opcodes/iq2000-dis.c: Regenerate.
1092 * opcodes/iq2000-ibld.c: Regenerate.
1093 * opcodes/iq2000-opc.c: Regenerate.
1094 * opcodes/iq2000-opc.h: Regenerate.
1095
fc3d45e8
TL		 10962004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1097
1098 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
1099 us4, us5 (respectively).
1100 Remove unsupported 'popa' instruction.
1101 Reverse operands order in store co-processor instructions.
1102
3c55da70
AM		 11032004-10-15 Alan Modra <amodra@bigpond.net.au>
1104
1105 * Makefile.am: Run "make dep-am"
1106 * Makefile.in: Regenerate.
1107
7fa3d080
BW		 11082004-10-12 Bob Wilson <bob.wilson@acm.org>
1109
1110 * xtensa-dis.c: Use ISO C90 formatting.
1111
e612bb4d
AM		 11122004-10-09 Alan Modra <amodra@bigpond.net.au>
1113
1114 * ppc-opc.c: Revert 2004-09-09 change.
1115
43cd72b9
BW		 11162004-10-07 Bob Wilson <bob.wilson@acm.org>
1117
1118 * xtensa-dis.c (state_names): Delete.
1119 (fetch_data): Use xtensa_isa_maxlength.
1120 (print_xtensa_operand): Replace operand parameter with opcode/operand
1121 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
1122 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
1123 instruction bundles. Use xmalloc instead of malloc.
1124
bbac1f2a
NC		 11252004-10-07 David Gibson <david@gibson.dropbear.id.au>
1126
1127 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
1128 initializers.
1129
48c9f030
NC		 11302004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1131
1132 * crx-opc.c (crx_instruction): Support Co-processor insns.
1133 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
1134 (getregliststring): Change function to use the above enum.
1135 (print_arg): Handle CO-Processor insns.
1136 (crx_cinvs): Add 'b' option to invalidate the branch-target
1137 cache.
1138
12c64a4e
AH		 11392004-10-06 Aldy Hernandez <aldyh@redhat.com>
1140
1141 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
1142 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
1143 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
1144 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
1145 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
1146
14127cc4
NC		 11472004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
1148
1149 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
1150 rather than add it.
1151
0dd132b6
NC		 11522004-09-30 Paul Brook <paul@codesourcery.com>
1153
1154 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
1155 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
1156
3f85e526
L		 11572004-09-17 H.J. Lu <hongjiu.lu@intel.com>
1158
1159 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
1160 (CONFIG_STATUS_DEPENDENCIES): New.
1161 (Makefile): Removed.
1162 (config.status): Likewise.
1163 * Makefile.in: Regenerated.
1164
8ae85421
AM		 11652004-09-17 Alan Modra <amodra@bigpond.net.au>
1166
1167 * Makefile.am: Run "make dep-am".
1168 * Makefile.in: Regenerate.
1169 * aclocal.m4: Regenerate.
1170 * configure: Regenerate.
1171 * po/POTFILES.in: Regenerate.
1172 * po/opcodes.pot: Regenerate.
1173
24443139
AS		 11742004-09-11 Andreas Schwab <schwab@suse.de>
1175
1176 * configure: Rebuild.
1177
2a309db0
AM		 11782004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1179
1180 * ppc-opc.c (L): Make this field not optional.
1181
42851540
NC		 11822004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
1183
1184 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
1185 Fix parameter to 'm[t|f]csr' insns.
1186
979273e3
NN		 11872004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
1188
1189 * configure.in: Autoupdate to autoconf 2.59.
1190 * aclocal.m4: Rebuild with aclocal 1.4p6.
1191 * configure: Rebuild with autoconf 2.59.
1192 * Makefile.in: Rebuild with automake 1.4p6 (picking up
1193 bfd changes for autoconf 2.59 on the way).
1194 * config.in: Rebuild with autoheader 2.59.
1195
ac28a1cb
RS		 11962004-08-27 Richard Sandiford <rsandifo@redhat.com>
1197
1198 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
1199
30d1c836
ML		 12002004-07-30 Michal Ludvig <mludvig@suse.cz>
1201
1202 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
1203 (GRPPADLCK2): New define.
1204 (twobyte_has_modrm): True for 0xA6.
1205 (grps): GRPPADLCK2 for opcode 0xA6.
1206
0b0ac059
AO		 12072004-07-29 Alexandre Oliva <aoliva@redhat.com>
1208
1209 Introduce SH2a support.
1210 * sh-opc.h (arch_sh2a_base): Renumber.
1211 (arch_sh2a_nofpu_base): Remove.
1212 (arch_sh_base_mask): Adjust.
1213 (arch_opann_mask): New.
1214 (arch_sh2a, arch_sh2a_nofpu): Adjust.
1215 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
1216 (sh_table): Adjust whitespace.
1217 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
1218 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
1219 instruction list throughout.
1220 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
1221 of arch_sh2a in instruction list throughout.
1222 (arch_sh2e_up): Accomodate above changes.
1223 (arch_sh2_up): Ditto.
1224 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
1225 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
1226 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
1227 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
1228 * sh-opc.h (arch_sh2a_nofpu): New.
1229 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
1230 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
1231 instruction.
1232 2004-01-20 DJ Delorie <dj@redhat.com>
1233 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
1234 2003-12-29 DJ Delorie <dj@redhat.com>
1235 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
1236 sh_opcode_info, sh_table): Add sh2a support.
1237 (arch_op32): New, to tag 32-bit opcodes.
1238 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
1239 2003-12-02 Michael Snyder <msnyder@redhat.com>
1240 * sh-opc.h (arch_sh2a): Add.
1241 * sh-dis.c (arch_sh2a): Handle.
1242 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
1243
670ec21d
NC		 12442004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
1245
1246 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
1247
ed049af3
NC		 12482004-07-22 Nick Clifton <nickc@redhat.com>
1249
1250 PR/280
1251 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
1252 insns - this is done by objdump itself.
1253 * h8500-dis.c (print_insn_h8500): Likewise.
1254
20f0a1fc
NC		 12552004-07-21 Jan Beulich <jbeulich@novell.com>
1256
1257 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
1258 regardless of address size prefix in effect.
1259 (ptr_reg): Size or address registers does not depend on rex64, but
1260 on the presence of an address size override.
1261 (OP_MMX): Use rex.x only for xmm registers.
1262 (OP_EM): Use rex.z only for xmm registers.
1263
6f14957b
MR		 12642004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
1265
1266 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
1267 move/branch operations to the bottom so that VR5400 multimedia
1268 instructions take precedence in disassembly.
1269
1586d91e
MR		 12702004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
1271
1272 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
1273 ISA-specific "break" encoding.
1274
982de27a
NC		 12752004-07-13 Elvis Chiang <elvisfb@gmail.com>
1276
1277 * arm-opc.h: Fix typo in comment.
1278
4300ab10
AS		 12792004-07-11 Andreas Schwab <schwab@suse.de>
1280
1281 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
1282
8577e690
AS		 12832004-07-09 Andreas Schwab <schwab@suse.de>
1284
1285 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
1286
1fe1f39c
NC		 12872004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1288
1289 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
1290 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
1291 (crx-dis.lo): New target.
1292 (crx-opc.lo): Likewise.
1293 * Makefile.in: Regenerate.
1294 * configure.in: Handle bfd_crx_arch.
1295 * configure: Regenerate.
1296 * crx-dis.c: New file.
1297 * crx-opc.c: New file.
1298 * disassemble.c (ARCH_crx): Define.
1299 (disassembler): Handle ARCH_crx.
1300
7a33b495
JW		 13012004-06-29 James E Wilson <wilson@specifixinc.com>
1302
1303 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
1304 * ia64-asmtab.c: Regnerate.
1305
98e69875
AM		 13062004-06-28 Alan Modra <amodra@bigpond.net.au>
1307
1308 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
1309 (extract_fxm): Don't test dialect.
1310 (XFXFXM_MASK): Include the power4 bit.
1311 (XFXM): Add p4 param.
1312 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
1313
a53b85e2
AO		 13142004-06-27 Alexandre Oliva <aoliva@redhat.com>
1315
1316 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
1317 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
1318
d0618d1c
AM		 13192004-06-26 Alan Modra <amodra@bigpond.net.au>
1320
1321 * ppc-opc.c (BH, XLBH_MASK): Define.
1322 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
1323
1d9f512f
AM		 13242004-06-24 Alan Modra <amodra@bigpond.net.au>
1325
1326 * i386-dis.c (x_mode): Comment.
1327 (two_source_ops): File scope.
1328 (float_mem): Correct fisttpll and fistpll.
1329 (float_mem_mode): New table.
1330 (dofloat): Use it.
1331 (OP_E): Correct intel mode PTR output.
1332 (ptr_reg): Use open_char and close_char.
1333 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
1334 operands. Set two_source_ops.
1335
52886d70
AM		 13362004-06-15 Alan Modra <amodra@bigpond.net.au>
1337
1338 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
1339 instead of _raw_size.
1340
bad9ceea
JJ		 13412004-06-08 Jakub Jelinek <jakub@redhat.com>
1342
1343 * ia64-gen.c (in_iclass): Handle more postinc st
1344 and ld variants.
1345 * ia64-asmtab.c: Rebuilt.
1346
0451f5df
MS		 13472004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
1348
1349 * s390-opc.txt: Correct architecture mask for some opcodes.
1350 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
1351 in the esa mode as well.
1352
f6f9408f
JR		 13532004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
1354
1355 * sh-dis.c (target_arch): Make unsigned.
1356 (print_insn_sh): Replace (most of) switch with a call to
1357 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
1358 * sh-opc.h: Redefine architecture flags values.
1359 Add sh3-nommu architecture.
1360 Reorganise <arch>_up macros so they make more visual sense.
1361 (SH_MERGE_ARCH_SET): Define new macro.
1362 (SH_VALID_BASE_ARCH_SET): Likewise.
1363 (SH_VALID_MMU_ARCH_SET): Likewise.
1364 (SH_VALID_CO_ARCH_SET): Likewise.
1365 (SH_VALID_ARCH_SET): Likewise.
1366 (SH_MERGE_ARCH_SET_VALID): Likewise.
1367 (SH_ARCH_SET_HAS_FPU): Likewise.
1368 (SH_ARCH_SET_HAS_DSP): Likewise.
1369 (SH_ARCH_UNKNOWN_ARCH): Likewise.
1370 (sh_get_arch_from_bfd_mach): Add prototype.
1371 (sh_get_arch_up_from_bfd_mach): Likewise.
1372 (sh_get_bfd_mach_from_arch_set): Likewise.
1373 (sh_merge_bfd_arc): Likewise.
1374
be8c092b
NC		 13752004-05-24 Peter Barada <peter@the-baradas.com>
1376
1377 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
610ad19b
AM		 1378 into new match_insn_m68k function. Loop over canidate
1379 matches and select first that completely matches.
be8c092b
NC		 1380 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
1381 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
610ad19b 1382 to verify addressing for MAC/EMAC.
be8c092b
NC		 1383 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
1384 reigster halves since 'fpu' and 'spl' look misleading.
1385 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
1386 * m68k-opc.c: Rearragne mac/emac cases to use longest for
1387 first, tighten up match masks.
1388 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
1389 'size' from special case code in print_insn_m68k to
1390 determine decode size of insns.
1391
a30e9cc4
AM		 13922004-05-19 Alan Modra <amodra@bigpond.net.au>
1393
1394 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
1395 well as when -mpower4.
1396
9598fbe5
NC		 13972004-05-13 Nick Clifton <nickc@redhat.com>
1398
1399 * po/fr.po: Updated French translation.
1400
6b6e92f4
NC		 14012004-05-05 Peter Barada <peter@the-baradas.com>
1402
1403 * m68k-dis.c(print_insn_m68k): Add new chips, use core
1404 variants in arch_mask. Only set m68881/68851 for 68k chips.
1405 * m68k-op.c: Switch from ColdFire chips to core variants.
1406
a404d431
AM		 14072004-05-05 Alan Modra <amodra@bigpond.net.au>
1408
a30e9cc4 1409 PR 147.
a404d431
AM		 1410 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
1411
f3806e43
BE		 14122004-04-29 Ben Elliston <bje@au.ibm.com>
1413
520ceea4
BE		 1414 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
1415 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
f3806e43 1416
1f1799d5
KK		 14172004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
1418
1419 * sh-dis.c (print_insn_sh): Print the value in constant pool
1420 as a symbol if it looks like a symbol.
1421
fd99574b
NC		 14222004-04-22 Peter Barada <peter@the-baradas.com>
1423
1424 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
1425 appropriate ColdFire architectures.
1426 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
1427 mask addressing.
1428 Add EMAC instructions, fix MAC instructions. Remove
1429 macmw/macml/msacmw/msacml instructions since mask addressing now
1430 supported.
1431
b4781d44
JJ		 14322004-04-20 Jakub Jelinek <jakub@redhat.com>
1433
1434 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
1435 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
1436 suffix. Use fmov*x macros, create all 3 fpsize variants in one
1437 macro. Adjust all users.
1438
91809fda 14392004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
610ad19b 1440
91809fda
NC		 1441 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
1442 separately.
1443
f4453dfa
NC		 14442004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
1445
1446 * m32r-asm.c: Regenerate.
1447
9b0de91a
SS		 14482004-03-29 Stan Shebs <shebs@apple.com>
1449
1450 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
1451 used.
1452
e20c0b3d
AM		 14532004-03-19 Alan Modra <amodra@bigpond.net.au>
1454
1455 * aclocal.m4: Regenerate.
1456 * config.in: Regenerate.
1457 * configure: Regenerate.
1458 * po/POTFILES.in: Regenerate.
1459 * po/opcodes.pot: Regenerate.
1460
fdd12ef3
AM		 14612004-03-16 Alan Modra <amodra@bigpond.net.au>
1462
1463 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
1464 PPC_OPERANDS_GPR_0.
1465 * ppc-opc.c (RA0): Define.
1466 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
1467 (RAOPT): Rename from RAO. Update all uses.
a9c3619e 1468 (powerpc_opcodes): Use RA0 as appropriate.
fdd12ef3 1469
2dc111b3 14702004-03-15 Aldy Hernandez <aldyh@redhat.com>
fdd12ef3
AM		 1471
1472 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
2dc111b3 1473
7bfeee7b
AM		 14742004-03-15 Alan Modra <amodra@bigpond.net.au>
1475
1476 * sparc-dis.c (print_insn_sparc): Update getword prototype.
1477
7ffdda93
ML		 14782004-03-12 Michal Ludvig <mludvig@suse.cz>
1479
1480 * i386-dis.c (GRPPLOCK): Delete.
7bfeee7b 1481 (grps): Delete GRPPLOCK entry.
7ffdda93 1482
cc0ec051
AM		 14832004-03-12 Alan Modra <amodra@bigpond.net.au>
1484
1485 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
1486 (M, Mp): Use OP_M.
1487 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
1488 (GRPPADLCK): Define.
1489 (dis386): Use NOP_Fixup on "nop".
1490 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
1491 (twobyte_has_modrm): Set for 0xa7.
1492 (padlock_table): Delete. Move to..
1493 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
1494 and clflush.
1495 (print_insn): Revert PADLOCK_SPECIAL code.
1496 (OP_E): Delete sfence, lfence, mfence checks.
1497
4fd61dcb
JJ		 14982004-03-12 Jakub Jelinek <jakub@redhat.com>
1499
1500 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
1501 (INVLPG_Fixup): New function.
1502 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
1503
0f10071e
ML		 15042004-03-12 Michal Ludvig <mludvig@suse.cz>
1505
1506 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
1507 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
1508 (padlock_table): New struct with PadLock instructions.
1509 (print_insn): Handle PADLOCK_SPECIAL.
1510
c02908d2
AM		 15112004-03-12 Alan Modra <amodra@bigpond.net.au>
1512
1513 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
1514 (OP_E): Twiddle clflush to sfence here.
1515
d5bb7600
NC		 15162004-03-08 Nick Clifton <nickc@redhat.com>
1517
1518 * po/de.po: Updated German translation.
1519
ae51a426
JR		 15202003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
1521
1522 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
1523 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
1524 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
1525 accordingly.
1526
676a64f4
RS		 15272004-03-01 Richard Sandiford <rsandifo@redhat.com>
1528
1529 * frv-asm.c: Regenerate.
1530 * frv-desc.c: Regenerate.
1531 * frv-desc.h: Regenerate.
1532 * frv-dis.c: Regenerate.
1533 * frv-ibld.c: Regenerate.
1534 * frv-opc.c: Regenerate.
1535 * frv-opc.h: Regenerate.
1536
c7a48b9a
RS		 15372004-03-01 Richard Sandiford <rsandifo@redhat.com>
1538
1539 * frv-desc.c, frv-opc.c: Regenerate.
1540
8ae0baa2
RS		 15412004-03-01 Richard Sandiford <rsandifo@redhat.com>
1542
1543 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
1544
ce11586c
JR		 15452004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
1546
1547 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
1548 Also correct mistake in the comment.
1549
6a5709a5
JR		 15502004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
1551
1552 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
1553 ensure that double registers have even numbers.
1554 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
1555 that reserved instruction 0xfffd does not decode the same
1556 as 0xfdfd (ftrv).
1557 * sh-opc.h: Add REG_N_D nibble type and use it whereever
1558 REG_N refers to a double register.
1559 Add REG_N_B01 nibble type and use it instead of REG_NM
1560 in ftrv.
1561 Adjust the bit patterns in a few comments.
1562
e5d2b64f 15632004-02-25 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1564
1565 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
e5d2b64f 1566
1f04b05f
AH		 15672004-02-20 Aldy Hernandez <aldyh@redhat.com>
1568
1569 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
1570
2f3b8700
AH		 15712004-02-20 Aldy Hernandez <aldyh@redhat.com>
1572
1573 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
1574
f0b26da6 15752004-02-20 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1576
1577 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
1578 mtivor32, mtivor33, mtivor34.
f0b26da6 1579
23d59c56 15802004-02-19 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1581
1582 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
23d59c56 1583
34920d91
NC		 15842004-02-10 Petko Manolov <petkan@nucleusys.com>
1585
1586 * arm-opc.h Maverick accumulator register opcode fixes.
1587
44d86481
BE		 15882004-02-13 Ben Elliston <bje@wasabisystems.com>
1589
1590 * m32r-dis.c: Regenerate.
1591
17707c23
MS		 15922004-01-27 Michael Snyder <msnyder@redhat.com>
1593
1594 * sh-opc.h (sh_table): "fsrra", not "fssra".
1595
fe3a9bc4
NC		 15962004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
1597
1598 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
1599 contraints.
1600
ff24f124
JJ		 16012004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
1602
1603 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
1604
a02a862a
AM		 16052004-01-19 Alan Modra <amodra@bigpond.net.au>
1606
1607 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
1608 1. Don't print scale factor on AT&T mode when index missing.
1609
d164ea7f
AO		 16102004-01-16 Alexandre Oliva <aoliva@redhat.com>
1611
1612 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
1613 when loaded into XR registers.
1614
cb10e79a
RS		 16152004-01-14 Richard Sandiford <rsandifo@redhat.com>
1616
1617 * frv-desc.h: Regenerate.
1618 * frv-desc.c: Regenerate.
1619 * frv-opc.c: Regenerate.
1620
f532f3fa
MS		 16212004-01-13 Michael Snyder <msnyder@redhat.com>
1622
1623 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
1624
e45d0630
PB		 16252004-01-09 Paul Brook <paul@codesourcery.com>
1626
1627 * arm-opc.h (arm_opcodes): Move generic mcrr after known
1628 specific opcodes.
1629
3ba7a1aa
DJ		 16302004-01-07 Daniel Jacobowitz <drow@mvista.com>
1631
1632 * Makefile.am (libopcodes_la_DEPENDENCIES)
1633 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
1634 comment about the problem.
1635 * Makefile.in: Regenerate.
1636
ba2d3f07
AO		 16372004-01-06 Alexandre Oliva <aoliva@redhat.com>
1638
1639 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
1640 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
1641 cut&paste errors in shifting/truncating numerical operands.
1642 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
1643 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
1644 (parse_uslo16): Likewise.
1645 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
1646 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
1647 (parse_s12): Likewise.
1648 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
1649 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
1650 (parse_uslo16): Likewise.
1651 (parse_uhi16): Parse gothi and gotfuncdeschi.
1652 (parse_d12): Parse got12 and gotfuncdesc12.
1653 (parse_s12): Likewise.
1654
3ab48931
NC		 16552004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
1656
1657 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
1658 instruction which looks similar to an 'rla' instruction.
a0bd404e 1659
c9e214e5 1660For older changes see ChangeLog-0203
252b5132
RH		 1661\f
1662Local Variables:
2f6d2f85
NC		 1663mode: change-log
1664left-margin: 8
1665fill-column: 74
252b5132
RH		 1666version-control: never
1667End:
GDB Binutils - Deliverables
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