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[MIPS] Add Loongson 3A1000 proccessor support.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
ac8cb70f
CX		 12018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
2
3 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
4 loongson3a as an alias of gs464 for compatibility.
5 * mips-opc.c (mips_opcodes): Change Comments.
6
a693765e
CX		 72018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
8
9 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
10 option.
11 (print_mips_disassembler_options): Document -M loongson-ext.
12 * mips-opc.c (LEXT2): New macro.
13 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
14
bdc6c06e
CX		 152018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
16
17 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
18 descriptors.
19 (parse_mips_ase_option): Handle -M loongson-ext option.
20 (print_mips_disassembler_options): Document -M loongson-ext.
21 * mips-opc.c (IL3A): Delete.
22 * mips-opc.c (LEXT): New macro.
23 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
24 instructions.
25
716c08de
CX		 262018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
27
28 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
29 descriptors.
30 (parse_mips_ase_option): Handle -M loongson-cam option.
31 (print_mips_disassembler_options): Document -M loongson-cam.
32 * mips-opc.c (LCAM): New macro.
33 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
34 instructions.
35
9cf7e568
AM		 362018-08-21 Alan Modra <amodra@gmail.com>
37
38 * ppc-dis.c (operand_value_powerpc): Init "invalid".
39 (skip_optional_operands): Count optional operands, and update
40 ppc_optional_operand_value call.
41 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
42 (extract_vlensi): Likewise.
43 (extract_fxm): Return default value for missing optional operand.
44 (extract_ls, extract_raq, extract_tbr): Likewise.
45 (insert_sxl, extract_sxl): New functions.
46 (insert_esync, extract_esync): Remove Power9 handling and simplify.
47 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
48 flag and extra entry.
49 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
50 extract_sxl.
51
d203b41a 522018-08-20 Alan Modra <amodra@gmail.com>
f4107842 53
d203b41a 54 * sh-opc.h (MASK): Simplify.
f4107842 55
08a8fe2f 562018-08-18 John Darrington <john@darrington.wattle.id.au>
7ba3ba91 57
d203b41a
AM		 58 * s12z-dis.c (bm_decode): Deal with cases where the mode is
59 BM_RESERVED0 or BM_RESERVED1
08a8fe2f 60 (bm_rel_decode, bm_n_bytes): Ditto.
d203b41a 61
08a8fe2f 622018-08-18 John Darrington <john@darrington.wattle.id.au>
d203b41a
AM		 63
64 * s12z.h: Delete.
7ba3ba91 65
1bc60e56
L		 662018-08-14 H.J. Lu <hongjiu.lu@intel.com>
67
68 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
69 address with the addr32 prefix and without base nor index
70 registers.
71
d871f3f4
L		 722018-08-11 H.J. Lu <hongjiu.lu@intel.com>
73
74 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
75 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
76 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
77 (cpu_flags): Add CpuCMOV and CpuFXSR.
78 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
79 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
80 * i386-init.h: Regenerated.
81 * i386-tbl.h: Likewise.
82
b6523c37 832018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
84
85 * arc-regs.h: Update auxiliary registers.
86
e968fc9b
JB		 872018-08-06 Jan Beulich <jbeulich@suse.com>
88
89 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
90 (RegIP, RegIZ): Define.
91 * i386-reg.tbl: Adjust comments.
92 (rip): Use Qword instead of BaseIndex. Use RegIP.
93 (eip): Use Dword instead of BaseIndex. Use RegIP.
94 (riz): Add Qword. Use RegIZ.
95 (eiz): Add Dword. Use RegIZ.
96 * i386-tbl.h: Re-generate.
97
dbf8be89
JB		 982018-08-03 Jan Beulich <jbeulich@suse.com>
99
100 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
101 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
102 vpmovzxdq, vpmovzxwd): Remove NoRex64.
103 * i386-tbl.h: Re-generate.
104
c48dadc9
JB		 1052018-08-03 Jan Beulich <jbeulich@suse.com>
106
107 * i386-gen.c (operand_types): Remove Mem field.
108 * i386-opc.h (union i386_operand_type): Remove mem field.
109 * i386-init.h, i386-tbl.h: Re-generate.
110
cb86a42a
AM		 1112018-08-01 Alan Modra <amodra@gmail.com>
112
113 * po/POTFILES.in: Regenerate.
114
07cc0450
NC		 1152018-07-31 Nick Clifton <nickc@redhat.com>
116
117 * po/sv.po: Updated Swedish translation.
118
1424ad86
JB		 1192018-07-31 Jan Beulich <jbeulich@suse.com>
120
121 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
122 * i386-init.h, i386-tbl.h: Re-generate.
123
ae2387fe
JB		 1242018-07-31 Jan Beulich <jbeulich@suse.com>
125
126 * i386-opc.h (ZEROING_MASKING) Rename to ...
127 (DYNAMIC_MASKING): ... this. Adjust comment.
128 * i386-opc.tbl (MaskingMorZ): Define.
129 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
130 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
131 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
132 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
133 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
134 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
135 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
136 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
137 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
138
6ff00b5e
JB		 1392018-07-31 Jan Beulich <jbeulich@suse.com>
140
141 * i386-opc.tbl: Use element rather than vector size for AVX512*
142 scatter/gather insns.
143 * i386-tbl.h: Re-generate.
144
e951d5ca
JB		 1452018-07-31 Jan Beulich <jbeulich@suse.com>
146
147 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
148 (cpu_flags): Drop CpuVREX.
149 * i386-opc.h (CpuVREX): Delete.
150 (union i386_cpu_flags): Remove cpuvrex.
151 * i386-init.h, i386-tbl.h: Re-generate.
152
eb41b248
JW		 1532018-07-30 Jim Wilson <jimw@sifive.com>
154
155 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
156 fields.
157 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
158
b8891f8d
AJ		 1592018-07-30 Andrew Jenner <andrew@codesourcery.com>
160
161 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
162 * Makefile.in: Regenerated.
163 * configure.ac: Add C-SKY.
164 * configure: Regenerated.
165 * csky-dis.c: New file.
166 * csky-opc.h: New file.
167 * disassemble.c (ARCH_csky): Define.
168 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
169 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
170
16065af1
AM		 1712018-07-27 Alan Modra <amodra@gmail.com>
172
173 * ppc-opc.c (insert_sprbat): Correct function parameter and
174 return type.
175 (extract_sprbat): Likewise, variable too.
176
fa758a70
AC		 1772018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
178 Alan Modra <amodra@gmail.com>
179
180 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
181 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
182 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
183 support disjointed BAT.
184 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
185 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
186 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
187
4a1b91ea
L		 1882018-07-25 H.J. Lu <hongjiu.lu@intel.com>
189 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
190
191 * i386-gen.c (adjust_broadcast_modifier): New function.
192 (process_i386_opcode_modifier): Add an argument for operands.
193 Adjust the Broadcast value based on operands.
194 (output_i386_opcode): Pass operand_types to
195 process_i386_opcode_modifier.
196 (process_i386_opcodes): Pass NULL as operands to
197 process_i386_opcode_modifier.
198 * i386-opc.h (BYTE_BROADCAST): New.
199 (WORD_BROADCAST): Likewise.
200 (DWORD_BROADCAST): Likewise.
201 (QWORD_BROADCAST): Likewise.
202 (i386_opcode_modifier): Expand broadcast to 3 bits.
203 * i386-tbl.h: Regenerated.
204
67ce483b
AM		 2052018-07-24 Alan Modra <amodra@gmail.com>
206
207 PR 23430
208 * or1k-desc.h: Regenerate.
209
4174bfff
JB		 2102018-07-24 Jan Beulich <jbeulich@suse.com>
211
212 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
213 vcvtusi2ss, and vcvtusi2sd.
214 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
215 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
216 * i386-tbl.h: Re-generate.
217
04e65276
CZ		 2182018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
219
220 * arc-opc.c (extract_w6): Fix extending the sign.
221
47e6f81c
CZ		 2222018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
223
224 * arc-tbl.h (vewt): Allow it for ARC EM family.
225
bb71536f
AM		 2262018-07-23 Alan Modra <amodra@gmail.com>
227
228 PR 23419
229 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
230 opcode variants for mtspr/mfspr encodings.
231
8095d2f7
CX		 2322018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
233 Maciej W. Rozycki <macro@mips.com>
234
235 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
236 loongson3a descriptors.
237 (parse_mips_ase_option): Handle -M loongson-mmi option.
238 (print_mips_disassembler_options): Document -M loongson-mmi.
239 * mips-opc.c (LMMI): New macro.
240 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
241 instructions.
242
5f32791e
JB		 2432018-07-19 Jan Beulich <jbeulich@suse.com>
244
245 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
246 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
247 IgnoreSize and [XYZ]MMword where applicable.
248 * i386-tbl.h: Re-generate.
249
625cbd7a
JB		 2502018-07-19 Jan Beulich <jbeulich@suse.com>
251
252 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
253 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
254 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
255 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
256 * i386-tbl.h: Re-generate.
257
86b15c32
JB		 2582018-07-19 Jan Beulich <jbeulich@suse.com>
259
260 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
261 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
262 VPCLMULQDQ templates into their respective AVX512VL counterparts
263 where possible, using Disp8ShiftVL and CheckRegSize instead of
264 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
265 * i386-tbl.h: Re-generate.
266
cf769ed5
JB		 2672018-07-19 Jan Beulich <jbeulich@suse.com>
268
269 * i386-opc.tbl: Fold AVX512DQ templates into their respective
270 AVX512VL counterparts where possible, using Disp8ShiftVL and
271 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
272 IgnoreSize) as appropriate.
273 * i386-tbl.h: Re-generate.
274
8282b7ad
JB		 2752018-07-19 Jan Beulich <jbeulich@suse.com>
276
277 * i386-opc.tbl: Fold AVX512BW templates into their respective
278 AVX512VL counterparts where possible, using Disp8ShiftVL and
279 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
280 IgnoreSize) as appropriate.
281 * i386-tbl.h: Re-generate.
282
755908cc
JB		 2832018-07-19 Jan Beulich <jbeulich@suse.com>
284
285 * i386-opc.tbl: Fold AVX512CD templates into their respective
286 AVX512VL counterparts where possible, using Disp8ShiftVL and
287 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
288 IgnoreSize) as appropriate.
289 * i386-tbl.h: Re-generate.
290
7091c612
JB		 2912018-07-19 Jan Beulich <jbeulich@suse.com>
292
293 * i386-opc.h (DISP8_SHIFT_VL): New.
294 * i386-opc.tbl (Disp8ShiftVL): Define.
295 (various): Fold AVX512VL templates into their respective
296 AVX512F counterparts where possible, using Disp8ShiftVL and
297 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
298 IgnoreSize) as appropriate.
299 * i386-tbl.h: Re-generate.
300
c30be56e
JB		 3012018-07-19 Jan Beulich <jbeulich@suse.com>
302
303 * Makefile.am: Change dependencies and rule for
304 $(srcdir)/i386-init.h.
305 * Makefile.in: Re-generate.
306 * i386-gen.c (process_i386_opcodes): New local variable
307 "marker". Drop opening of input file. Recognize marker and line
308 number directives.
309 * i386-opc.tbl (OPCODE_I386_H): Define.
310 (i386-opc.h): Include it.
311 (None): Undefine.
312
11a322db
L		 3132018-07-18 H.J. Lu <hongjiu.lu@intel.com>
314
315 PR gas/23418
316 * i386-opc.h (Byte): Update comments.
317 (Word): Likewise.
318 (Dword): Likewise.
319 (Fword): Likewise.
320 (Qword): Likewise.
321 (Tbyte): Likewise.
322 (Xmmword): Likewise.
323 (Ymmword): Likewise.
324 (Zmmword): Likewise.
325 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
326 vcvttps2uqq.
327 * i386-tbl.h: Regenerated.
328
cde3679e
NC		 3292018-07-12 Sudakshina Das <sudi.das@arm.com>
330
331 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
332 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
333 * aarch64-asm-2.c: Regenerate.
334 * aarch64-dis-2.c: Regenerate.
335 * aarch64-opc-2.c: Regenerate.
336
45a28947
TC		 3372018-07-12 Tamar Christina <tamar.christina@arm.com>
338
339 PR binutils/23192
340 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
341 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
342 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
343 sqdmulh, sqrdmulh): Use Em16.
344
c597cc3d
SD		 3452018-07-11 Sudakshina Das <sudi.das@arm.com>
346
347 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
348 csdb together with them.
349 (thumb32_opcodes): Likewise.
350
a79eaed6
JB		 3512018-07-11 Jan Beulich <jbeulich@suse.com>
352
353 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
354 requiring 32-bit registers as operands 2 and 3. Improve
355 comments.
356 (mwait, mwaitx): Fold templates. Improve comments.
357 OPERAND_TYPE_INOUTPORTREG.
358 * i386-tbl.h: Re-generate.
359
2fb5be8d
JB		 3602018-07-11 Jan Beulich <jbeulich@suse.com>
361
362 * i386-gen.c (operand_type_init): Remove
363 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
364 OPERAND_TYPE_INOUTPORTREG.
365 * i386-init.h: Re-generate.
366
7f5cad30
JB		 3672018-07-11 Jan Beulich <jbeulich@suse.com>
368
369 * i386-opc.tbl (wrssd, wrussd): Add Dword.
370 (wrssq, wrussq): Add Qword.
371 * i386-tbl.h: Re-generate.
372
f0a85b07
JB		 3732018-07-11 Jan Beulich <jbeulich@suse.com>
374
375 * i386-opc.h: Rename OTMax to OTNum.
376 (OTNumOfUints): Adjust calculation.
377 (OTUnused): Directly alias to OTNum.
378
9dcb0ba4
MR		 3792018-07-09 Maciej W. Rozycki <macro@mips.com>
380
381 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
382 `reg_xys'.
383 (lea_reg_xys): Likewise.
384 (print_insn_loop_primitive): Rename `reg' local variable to
385 `reg_dxy'.
386
f311ba7e
TC		 3872018-07-06 Tamar Christina <tamar.christina@arm.com>
388
389 PR binutils/23242
390 * aarch64-tbl.h (ldarh): Fix disassembly mask.
391
cba05feb
TC		 3922018-07-06 Tamar Christina <tamar.christina@arm.com>
393
394 PR binutils/23369
395 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
396 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
397
471b9d15
MR		 3982018-07-02 Maciej W. Rozycki <macro@mips.com>
399
400 PR tdep/8282
401 * mips-dis.c (mips_option_arg_t): New enumeration.
402 (mips_options): New variable.
403 (disassembler_options_mips): New function.
404 (print_mips_disassembler_options): Reimplement in terms of
405 `disassembler_options_mips'.
406 * arm-dis.c (disassembler_options_arm): Adapt to using the
407 `disasm_options_and_args_t' structure.
408 * ppc-dis.c (disassembler_options_powerpc): Likewise.
409 * s390-dis.c (disassembler_options_s390): Likewise.
410
c0c468d5
TP		 4112018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
412
413 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
414 expected result.
415 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
416 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
417 * testsuite/ld-arm/tls-longplt.d: Likewise.
418
369c9167
TC		 4192018-06-29 Tamar Christina <tamar.christina@arm.com>
420
421 PR binutils/23192
422 * aarch64-asm-2.c: Regenerate.
423 * aarch64-dis-2.c: Likewise.
424 * aarch64-opc-2.c: Likewise.
425 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
426 * aarch64-opc.c (operand_general_constraint_met_p,
427 aarch64_print_operand): Likewise.
428 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
429 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
430 fmlal2, fmlsl2.
431 (AARCH64_OPERANDS): Add Em2.
432
30aa1306
NC		 4332018-06-26 Nick Clifton <nickc@redhat.com>
434
435 * po/uk.po: Updated Ukranian translation.
436 * po/de.po: Updated German translation.
437 * po/pt_BR.po: Updated Brazilian Portuguese translation.
438
eca4b721
NC		 4392018-06-26 Nick Clifton <nickc@redhat.com>
440
441 * nfp-dis.c: Fix spelling mistake.
442
71300e2c
NC		 4432018-06-24 Nick Clifton <nickc@redhat.com>
444
445 * configure: Regenerate.
446 * po/opcodes.pot: Regenerate.
447
719d8288
NC		 4482018-06-24 Nick Clifton <nickc@redhat.com>
449
450 2.31 branch created.
451
514cd3a0
TC		 4522018-06-19 Tamar Christina <tamar.christina@arm.com>
453
454 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
455 * aarch64-asm-2.c: Regenerate.
456 * aarch64-dis-2.c: Likewise.
457
385e4d0f
MR		 4582018-06-21 Maciej W. Rozycki <macro@mips.com>
459
460 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
461 `-M ginv' option description.
462
160d1b3d
SH		 4632018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
464
465 PR gas/23305
466 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
467 la and lla.
468
d0ac1c44
SM		 4692018-06-19 Simon Marchi <simon.marchi@ericsson.com>
470
471 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
472 * configure.ac: Remove AC_PREREQ.
473 * Makefile.in: Re-generate.
474 * aclocal.m4: Re-generate.
475 * configure: Re-generate.
476
6f20c942
FS		 4772018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
478
479 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
480 mips64r6 descriptors.
481 (parse_mips_ase_option): Handle -Mginv option.
482 (print_mips_disassembler_options): Document -Mginv.
483 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
484 (GINV): New macro.
485 (mips_opcodes): Define ginvi and ginvt.
486
730c3174
SE		 4872018-06-13 Scott Egerton <scott.egerton@imgtec.com>
488 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
489
490 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
491 * mips-opc.c (CRC, CRC64): New macros.
492 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
493 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
494 crc32cd for CRC64.
495
cb366992
EB		 4962018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
497
498 PR 20319
499 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
500 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
501
ce72cd46
AM		 5022018-06-06 Alan Modra <amodra@gmail.com>
503
504 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
505 setjmp. Move init for some other vars later too.
506
4b8e28c7
MF		 5072018-06-04 Max Filippov <jcmvbkbc@gmail.com>
508
509 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
510 (dis_private): Add new fields for property section tracking.
511 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
512 (xtensa_instruction_fits): New functions.
513 (fetch_data): Bump minimal fetch size to 4.
514 (print_insn_xtensa): Make struct dis_private static.
515 Load and prepare property table on section change.
516 Don't disassemble literals. Don't disassemble instructions that
517 cross property table boundaries.
518
55e99962
L		 5192018-06-01 H.J. Lu <hongjiu.lu@intel.com>
520
521 * configure: Regenerated.
522
733bd0ab
JB		 5232018-06-01 Jan Beulich <jbeulich@suse.com>
524
525 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
526 * i386-tbl.h: Re-generate.
527
dfd27d41
JB		 5282018-06-01 Jan Beulich <jbeulich@suse.com>
529
530 * i386-opc.tbl (sldt, str): Add NoRex64.
531 * i386-tbl.h: Re-generate.
532
64795710
JB		 5332018-06-01 Jan Beulich <jbeulich@suse.com>
534
535 * i386-opc.tbl (invpcid): Add Oword.
536 * i386-tbl.h: Re-generate.
537
030157d8
AM		 5382018-06-01 Alan Modra <amodra@gmail.com>
539
540 * sysdep.h (_bfd_error_handler): Don't declare.
541 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
542 * rl78-decode.opc: Likewise.
543 * msp430-decode.c: Regenerate.
544 * rl78-decode.c: Regenerate.
545
a9660a6f
AP		 5462018-05-30 Amit Pawar <Amit.Pawar@amd.com>
547
548 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
549 * i386-init.h : Regenerated.
550
277eb7f6
AM		 5512018-05-25 Alan Modra <amodra@gmail.com>
552
553 * Makefile.in: Regenerate.
554 * po/POTFILES.in: Regenerate.
555
98553ad3
PB		 5562018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
557
558 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
559 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
560 (insert_bab, extract_bab, insert_btab, extract_btab,
561 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
562 (BAT, BBA VBA RBS XB6S): Delete macros.
563 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
564 (BB, BD, RBX, XC6): Update for new macros.
565 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
566 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
567 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
568 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
569
7b4ae824
JD		 5702018-05-18 John Darrington <john@darrington.wattle.id.au>
571
572 * Makefile.am: Add support for s12z architecture.
573 * configure.ac: Likewise.
574 * disassemble.c: Likewise.
575 * disassemble.h: Likewise.
576 * Makefile.in: Regenerate.
577 * configure: Regenerate.
578 * s12z-dis.c: New file.
579 * s12z.h: New file.
580
29e0f0a1
AM		 5812018-05-18 Alan Modra <amodra@gmail.com>
582
583 * nfp-dis.c: Don't #include libbfd.h.
584 (init_nfp3200_priv): Use bfd_get_section_contents.
585 (nit_nfp6000_mecsr_sec): Likewise.
586
809276d2
NC		 5872018-05-17 Nick Clifton <nickc@redhat.com>
588
589 * po/zh_CN.po: Updated simplified Chinese translation.
590
ff329288
TC		 5912018-05-16 Tamar Christina <tamar.christina@arm.com>
592
593 PR binutils/23109
594 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
595 * aarch64-dis-2.c: Regenerate.
596
f9830ec1
TC		 5972018-05-15 Tamar Christina <tamar.christina@arm.com>
598
599 PR binutils/21446
600 * aarch64-asm.c (opintl.h): Include.
601 (aarch64_ins_sysreg): Enforce read/write constraints.
602 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
603 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
604 (F_REG_READ, F_REG_WRITE): New.
605 * aarch64-opc.c (aarch64_print_operand): Generate notes for
606 AARCH64_OPND_SYSREG.
607 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
608 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
609 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
610 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
611 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
612 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
613 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
614 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
615 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
616 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
617 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
618 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
619 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
620 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
621 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
622 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
623 msr (F_SYS_WRITE), mrs (F_SYS_READ).
624
7d02540a
TC		 6252018-05-15 Tamar Christina <tamar.christina@arm.com>
626
627 PR binutils/21446
628 * aarch64-dis.c (no_notes: New.
629 (parse_aarch64_dis_option): Support notes.
630 (aarch64_decode_insn, print_operands): Likewise.
631 (print_aarch64_disassembler_options): Document notes.
632 * aarch64-opc.c (aarch64_print_operand): Support notes.
633
561a72d4
TC		 6342018-05-15 Tamar Christina <tamar.christina@arm.com>
635
636 PR binutils/21446
637 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
638 and take error struct.
639 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
640 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
641 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
642 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
643 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
644 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
645 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
646 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
647 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
648 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
649 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
650 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
651 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
652 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
653 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
654 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
655 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
656 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
657 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
658 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
659 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
660 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
661 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
662 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
663 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
664 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
665 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
666 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
667 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
668 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
669 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
670 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
671 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
672 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
673 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
674 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
675 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
676 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
677 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
678 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
679 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
680 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
681 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
682 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
683 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
684 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
685 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
686 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
687 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
688 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
689 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
690 (determine_disassembling_preference, aarch64_decode_insn,
691 print_insn_aarch64_word, print_insn_data): Take errors struct.
692 (print_insn_aarch64): Use errors.
693 * aarch64-asm-2.c: Regenerate.
694 * aarch64-dis-2.c: Regenerate.
695 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
696 boolean in aarch64_insert_operan.
697 (print_operand_extractor): Likewise.
698 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
699
1678bd35
FT		 7002018-05-15 Francois H. Theron <francois.theron@netronome.com>
701
702 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
703
06cfb1c8
L		 7042018-05-09 H.J. Lu <hongjiu.lu@intel.com>
705
706 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
707
84f9f8c3
AM		 7082018-05-09 Sebastian Rasmussen <sebras@gmail.com>
709
710 * cr16-opc.c (cr16_instruction): Comment typo fix.
711 * hppa-dis.c (print_insn_hppa): Likewise.
712
e6f372ba
JW		 7132018-05-08 Jim Wilson <jimw@sifive.com>
714
715 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
716 (match_c_slli64, match_srxi_as_c_srxi): New.
717 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
718 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
719 <c.slli, c.srli, c.srai>: Use match_s_slli.
720 <c.slli64, c.srli64, c.srai64>: New.
721
f413a913
AM		 7222018-05-08 Alan Modra <amodra@gmail.com>
723
724 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
725 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
726 partition opcode space for index lookup.
727
a87a6478
PB		 7282018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
729
730 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
731 <insn_length>: ...with this. Update usage.
732 Remove duplicate call to *info->memory_error_func.
733
c0a30a9f
L		 7342018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
735 H.J. Lu <hongjiu.lu@intel.com>
736
737 * i386-dis.c (Gva): New.
738 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
739 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
740 (prefix_table): New instructions (see prefix above).
741 (mod_table): New instructions (see prefix above).
742 (OP_G): Handle va_mode.
743 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
744 CPU_MOVDIR64B_FLAGS.
745 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
746 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
747 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
748 * i386-opc.tbl: Add movidir{i,64b}.
749 * i386-init.h: Regenerated.
750 * i386-tbl.h: Likewise.
751
75c0a438
L		 7522018-05-07 H.J. Lu <hongjiu.lu@intel.com>
753
754 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
755 AddrPrefixOpReg.
756 * i386-opc.h (AddrPrefixOp0): Renamed to ...
757 (AddrPrefixOpReg): This.
758 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
759 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
760
2ceb7719
PB		 7612018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
762
763 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
764 (vle_num_opcodes): Likewise.
765 (spe2_num_opcodes): Likewise.
766 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
767 initialization loop.
768 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
769 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
770 only once.
771
b3ac5c6c
TC		 7722018-05-01 Tamar Christina <tamar.christina@arm.com>
773
774 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
775
fe944acf
FT		 7762018-04-30 Francois H. Theron <francois.theron@netronome.com>
777
778 Makefile.am: Added nfp-dis.c.
779 configure.ac: Added bfd_nfp_arch.
780 disassemble.h: Added print_insn_nfp prototype.
781 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
782 nfp-dis.c: New, for NFP support.
783 po/POTFILES.in: Added nfp-dis.c to the list.
784 Makefile.in: Regenerate.
785 configure: Regenerate.
786
e2195274
JB		 7872018-04-26 Jan Beulich <jbeulich@suse.com>
788
789 * i386-opc.tbl: Fold various non-memory operand AVX512VL
790 templates into their base ones.
791 * i386-tlb.h: Re-generate.
792
59ef5df4
JB		 7932018-04-26 Jan Beulich <jbeulich@suse.com>
794
795 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
796 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
797 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
798 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
799 * i386-init.h: Re-generate.
800
6e041cf4
JB		 8012018-04-26 Jan Beulich <jbeulich@suse.com>
802
803 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
804 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
805 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
806 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
807 comment.
808 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
809 and CpuRegMask.
810 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
811 CpuRegMask: Delete.
812 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
813 cpuregzmm, and cpuregmask.
814 * i386-init.h: Re-generate.
815 * i386-tbl.h: Re-generate.
816
0e0eea78
JB		 8172018-04-26 Jan Beulich <jbeulich@suse.com>
818
819 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
820 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
821 * i386-init.h: Re-generate.
822
2f1bada2
JB		 8232018-04-26 Jan Beulich <jbeulich@suse.com>
824
825 * i386-gen.c (VexImmExt): Delete.
826 * i386-opc.h (VexImmExt, veximmext): Delete.
827 * i386-opc.tbl: Drop all VexImmExt uses.
828 * i386-tlb.h: Re-generate.
829
bacd1457
JB		 8302018-04-25 Jan Beulich <jbeulich@suse.com>
831
832 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
833 register-only forms.
834 * i386-tlb.h: Re-generate.
835
10bba94b
TC		 8362018-04-25 Tamar Christina <tamar.christina@arm.com>
837
838 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
839
c48935d7
IT		 8402018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
841
842 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
843 PREFIX_0F1C.
844 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
845 (cpu_flags): Add CpuCLDEMOTE.
846 * i386-init.h: Regenerate.
847 * i386-opc.h (enum): Add CpuCLDEMOTE,
848 (i386_cpu_flags): Add cpucldemote.
849 * i386-opc.tbl: Add cldemote.
850 * i386-tbl.h: Regenerate.
851
211dc24b
AM		 8522018-04-16 Alan Modra <amodra@gmail.com>
853
854 * Makefile.am: Remove sh5 and sh64 support.
855 * configure.ac: Likewise.
856 * disassemble.c: Likewise.
857 * disassemble.h: Likewise.
858 * sh-dis.c: Likewise.
859 * sh64-dis.c: Delete.
860 * sh64-opc.c: Delete.
861 * sh64-opc.h: Delete.
862 * Makefile.in: Regenerate.
863 * configure: Regenerate.
864 * po/POTFILES.in: Regenerate.
865
a9a4b302
AM		 8662018-04-16 Alan Modra <amodra@gmail.com>
867
868 * Makefile.am: Remove w65 support.
869 * configure.ac: Likewise.
870 * disassemble.c: Likewise.
871 * disassemble.h: Likewise.
872 * w65-dis.c: Delete.
873 * w65-opc.h: Delete.
874 * Makefile.in: Regenerate.
875 * configure: Regenerate.
876 * po/POTFILES.in: Regenerate.
877
04cb01fd
AM		 8782018-04-16 Alan Modra <amodra@gmail.com>
879
880 * configure.ac: Remove we32k support.
881 * configure: Regenerate.
882
c2bf1eec
AM		 8832018-04-16 Alan Modra <amodra@gmail.com>
884
885 * Makefile.am: Remove m88k support.
886 * configure.ac: Likewise.
887 * disassemble.c: Likewise.
888 * disassemble.h: Likewise.
889 * m88k-dis.c: Delete.
890 * Makefile.in: Regenerate.
891 * configure: Regenerate.
892 * po/POTFILES.in: Regenerate.
893
6793974d
AM		 8942018-04-16 Alan Modra <amodra@gmail.com>
895
896 * Makefile.am: Remove i370 support.
897 * configure.ac: Likewise.
898 * disassemble.c: Likewise.
899 * disassemble.h: Likewise.
900 * i370-dis.c: Delete.
901 * i370-opc.c: Delete.
902 * Makefile.in: Regenerate.
903 * configure: Regenerate.
904 * po/POTFILES.in: Regenerate.
905
e82aa794
AM		 9062018-04-16 Alan Modra <amodra@gmail.com>
907
908 * Makefile.am: Remove h8500 support.
909 * configure.ac: Likewise.
910 * disassemble.c: Likewise.
911 * disassemble.h: Likewise.
912 * h8500-dis.c: Delete.
913 * h8500-opc.h: Delete.
914 * Makefile.in: Regenerate.
915 * configure: Regenerate.
916 * po/POTFILES.in: Regenerate.
917
fceadf09
AM		 9182018-04-16 Alan Modra <amodra@gmail.com>
919
920 * configure.ac: Remove tahoe support.
921 * configure: Regenerate.
922
ae1d3843
L		 9232018-04-15 H.J. Lu <hongjiu.lu@intel.com>
924
925 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
926 umwait.
927 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
928 64-bit mode.
929 * i386-tbl.h: Regenerated.
930
de89d0a3
IT		 9312018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
932
933 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
934 PREFIX_MOD_1_0FAE_REG_6.
935 (va_mode): New.
936 (OP_E_register): Use va_mode.
937 * i386-dis-evex.h (prefix_table):
938 New instructions (see prefixes above).
939 * i386-gen.c (cpu_flag_init): Add WAITPKG.
940 (cpu_flags): Likewise.
941 * i386-opc.h (enum): Likewise.
942 (i386_cpu_flags): Likewise.
943 * i386-opc.tbl: Add umonitor, umwait, tpause.
944 * i386-init.h: Regenerate.
945 * i386-tbl.h: Likewise.
946
a8eb42a8
AM		 9472018-04-11 Alan Modra <amodra@gmail.com>
948
949 * opcodes/i860-dis.c: Delete.
950 * opcodes/i960-dis.c: Delete.
951 * Makefile.am: Remove i860 and i960 support.
952 * configure.ac: Likewise.
953 * disassemble.c: Likewise.
954 * disassemble.h: Likewise.
955 * Makefile.in: Regenerate.
956 * configure: Regenerate.
957 * po/POTFILES.in: Regenerate.
958
caf0678c
L		 9592018-04-04 H.J. Lu <hongjiu.lu@intel.com>
960
961 PR binutils/23025
962 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
963 to 0.
964 (print_insn): Clear vex instead of vex.evex.
965
4fb0d2b9
NC		 9662018-04-04 Nick Clifton <nickc@redhat.com>
967
968 * po/es.po: Updated Spanish translation.
969
c39e5b26
JB		 9702018-03-28 Jan Beulich <jbeulich@suse.com>
971
972 * i386-gen.c (opcode_modifiers): Delete VecESize.
973 * i386-opc.h (VecESize): Delete.
974 (struct i386_opcode_modifier): Delete vecesize.
975 * i386-opc.tbl: Drop VecESize.
976 * i386-tlb.h: Re-generate.
977
8e6e0792
JB		 9782018-03-28 Jan Beulich <jbeulich@suse.com>
979
980 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
981 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
982 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
983 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
984 * i386-tlb.h: Re-generate.
985
9f123b91
JB		 9862018-03-28 Jan Beulich <jbeulich@suse.com>
987
988 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
989 Fold AVX512 forms
990 * i386-tlb.h: Re-generate.
991
9646c87b
JB		 9922018-03-28 Jan Beulich <jbeulich@suse.com>
993
994 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
995 (vex_len_table): Drop Y for vcvt*2si.
996 (putop): Replace plain 'Y' handling by abort().
997
c8d59609
NC		 9982018-03-28 Nick Clifton <nickc@redhat.com>
999
1000 PR 22988
1001 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1002 instructions with only a base address register.
1003 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1004 handle AARHC64_OPND_SVE_ADDR_R.
1005 (aarch64_print_operand): Likewise.
1006 * aarch64-asm-2.c: Regenerate.
1007 * aarch64_dis-2.c: Regenerate.
1008 * aarch64-opc-2.c: Regenerate.
1009
b8c169f3
JB		 10102018-03-22 Jan Beulich <jbeulich@suse.com>
1011
1012 * i386-opc.tbl: Drop VecESize from register only insn forms and
1013 memory forms not allowing broadcast.
1014 * i386-tlb.h: Re-generate.
1015
96bc132a
JB		 10162018-03-22 Jan Beulich <jbeulich@suse.com>
1017
1018 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1019 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1020 sha256*): Drop Disp<N>.
1021
9f79e886
JB		 10222018-03-22 Jan Beulich <jbeulich@suse.com>
1023
1024 * i386-dis.c (EbndS, bnd_swap_mode): New.
1025 (prefix_table): Use EbndS.
1026 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1027 * i386-opc.tbl (bndmov): Move misplaced Load.
1028 * i386-tlb.h: Re-generate.
1029
d6793fa1
JB		 10302018-03-22 Jan Beulich <jbeulich@suse.com>
1031
1032 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1033 templates allowing memory operands and folded ones for register
1034 only flavors.
1035 * i386-tlb.h: Re-generate.
1036
f7768225
JB		 10372018-03-22 Jan Beulich <jbeulich@suse.com>
1038
1039 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1040 256-bit templates. Drop redundant leftover Disp<N>.
1041 * i386-tlb.h: Re-generate.
1042
0e35537d
JW		 10432018-03-14 Kito Cheng <kito.cheng@gmail.com>
1044
1045 * riscv-opc.c (riscv_insn_types): New.
1046
b4a3689a
NC		 10472018-03-13 Nick Clifton <nickc@redhat.com>
1048
1049 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1050
d3d50934
L		 10512018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1052
1053 * i386-opc.tbl: Add Optimize to clr.
1054 * i386-tbl.h: Regenerated.
1055
bd5dea88
L		 10562018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1057
1058 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1059 * i386-opc.h (OldGcc): Removed.
1060 (i386_opcode_modifier): Remove oldgcc.
1061 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1062 instructions for old (<= 2.8.1) versions of gcc.
1063 * i386-tbl.h: Regenerated.
1064
e771e7c9
JB		 10652018-03-08 Jan Beulich <jbeulich@suse.com>
1066
1067 * i386-opc.h (EVEXDYN): New.
1068 * i386-opc.tbl: Fold various AVX512VL templates.
1069 * i386-tlb.h: Re-generate.
1070
ed438a93
JB		 10712018-03-08 Jan Beulich <jbeulich@suse.com>
1072
1073 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1074 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1075 vpexpandd, vpexpandq): Fold AFX512VF templates.
1076 * i386-tlb.h: Re-generate.
1077
454172a9
JB		 10782018-03-08 Jan Beulich <jbeulich@suse.com>
1079
1080 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1081 Fold 128- and 256-bit VEX-encoded templates.
1082 * i386-tlb.h: Re-generate.
1083
36824150
JB		 10842018-03-08 Jan Beulich <jbeulich@suse.com>
1085
1086 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1087 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1088 vpexpandd, vpexpandq): Fold AVX512F templates.
1089 * i386-tlb.h: Re-generate.
1090
e7f5c0a9
JB		 10912018-03-08 Jan Beulich <jbeulich@suse.com>
1092
1093 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1094 64-bit templates. Drop Disp<N>.
1095 * i386-tlb.h: Re-generate.
1096
25a4277f
JB		 10972018-03-08 Jan Beulich <jbeulich@suse.com>
1098
1099 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1100 and 256-bit templates.
1101 * i386-tlb.h: Re-generate.
1102
d2224064
JB		 11032018-03-08 Jan Beulich <jbeulich@suse.com>
1104
1105 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1106 * i386-tlb.h: Re-generate.
1107
1b193f0b
JB		 11082018-03-08 Jan Beulich <jbeulich@suse.com>
1109
1110 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1111 Drop NoAVX.
1112 * i386-tlb.h: Re-generate.
1113
f2f6a710
JB		 11142018-03-08 Jan Beulich <jbeulich@suse.com>
1115
1116 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1117 * i386-tlb.h: Re-generate.
1118
38e314eb
JB		 11192018-03-08 Jan Beulich <jbeulich@suse.com>
1120
1121 * i386-gen.c (opcode_modifiers): Delete FloatD.
1122 * i386-opc.h (FloatD): Delete.
1123 (struct i386_opcode_modifier): Delete floatd.
1124 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1125 FloatD by D.
1126 * i386-tlb.h: Re-generate.
1127
d53e6b98
JB		 11282018-03-08 Jan Beulich <jbeulich@suse.com>
1129
1130 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1131
2907c2f5
JB		 11322018-03-08 Jan Beulich <jbeulich@suse.com>
1133
1134 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1135 * i386-tlb.h: Re-generate.
1136
73053c1f
JB		 11372018-03-08 Jan Beulich <jbeulich@suse.com>
1138
1139 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1140 forms.
1141 * i386-tlb.h: Re-generate.
1142
52fe4420
AM		 11432018-03-07 Alan Modra <amodra@gmail.com>
1144
1145 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1146 bfd_arch_rs6000.
1147 * disassemble.h (print_insn_rs6000): Delete.
1148 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1149 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1150 (print_insn_rs6000): Delete.
1151
a6743a54
AM		 11522018-03-03 Alan Modra <amodra@gmail.com>
1153
1154 * sysdep.h (opcodes_error_handler): Define.
1155 (_bfd_error_handler): Declare.
1156 * Makefile.am: Remove stray #.
1157 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1158 EDIT" comment.
1159 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1160 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1161 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1162 opcodes_error_handler to print errors. Standardize error messages.
1163 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1164 and include opintl.h.
1165 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1166 * i386-gen.c: Standardize error messages.
1167 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1168 * Makefile.in: Regenerate.
1169 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1170 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1171 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1172 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1173 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1174 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1175 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1176 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1177 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1178 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1179 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1180 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1181 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1182
8305403a
L		 11832018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1184
1185 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1186 vpsub[bwdq] instructions.
1187 * i386-tbl.h: Regenerated.
1188
e184813f
AM		 11892018-03-01 Alan Modra <amodra@gmail.com>
1190
1191 * configure.ac (ALL_LINGUAS): Sort.
1192 * configure: Regenerate.
1193
5b616bef
TP		 11942018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1195
1196 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1197 macro by assignements.
1198
b6f8c7c4
L		 11992018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1200
1201 PR gas/22871
1202 * i386-gen.c (opcode_modifiers): Add Optimize.
1203 * i386-opc.h (Optimize): New enum.
1204 (i386_opcode_modifier): Add optimize.
1205 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1206 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1207 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1208 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1209 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1210 vpxord and vpxorq.
1211 * i386-tbl.h: Regenerated.
1212
e95b887f
AM		 12132018-02-26 Alan Modra <amodra@gmail.com>
1214
1215 * crx-dis.c (getregliststring): Allocate a large enough buffer
1216 to silence false positive gcc8 warning.
1217
0bccfb29
JW		 12182018-02-22 Shea Levy <shea@shealevy.com>
1219
1220 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1221
6b6b6807
L		 12222018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1223
1224 * i386-opc.tbl: Add {rex},
1225 * i386-tbl.h: Regenerated.
1226
75f31665
MR		 12272018-02-20 Maciej W. Rozycki <macro@mips.com>
1228
1229 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1230 (mips16_opcodes): Replace `M' with `m' for "restore".
1231
e207bc53
TP		 12322018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1233
1234 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1235
87993319
MR		 12362018-02-13 Maciej W. Rozycki <macro@mips.com>
1237
1238 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1239 variable to `function_index'.
1240
68d20676
NC		 12412018-02-13 Nick Clifton <nickc@redhat.com>
1242
1243 PR 22823
1244 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1245 about truncation of printing.
1246
d2159fdc
HW		 12472018-02-12 Henry Wong <henry@stuffedcow.net>
1248
1249 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1250
f174ef9f
NC		 12512018-02-05 Nick Clifton <nickc@redhat.com>
1252
1253 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1254
be3a8dca
IT		 12552018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1256
1257 * i386-dis.c (enum): Add pconfig.
1258 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1259 (cpu_flags): Add CpuPCONFIG.
1260 * i386-opc.h (enum): Add CpuPCONFIG.
1261 (i386_cpu_flags): Add cpupconfig.
1262 * i386-opc.tbl: Add PCONFIG instruction.
1263 * i386-init.h: Regenerate.
1264 * i386-tbl.h: Likewise.
1265
3233d7d0
IT		 12662018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1267
1268 * i386-dis.c (enum): Add PREFIX_0F09.
1269 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1270 (cpu_flags): Add CpuWBNOINVD.
1271 * i386-opc.h (enum): Add CpuWBNOINVD.
1272 (i386_cpu_flags): Add cpuwbnoinvd.
1273 * i386-opc.tbl: Add WBNOINVD instruction.
1274 * i386-init.h: Regenerate.
1275 * i386-tbl.h: Likewise.
1276
e925c834
JW		 12772018-01-17 Jim Wilson <jimw@sifive.com>
1278
1279 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1280
d777820b
IT		 12812018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1282
1283 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1284 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1285 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1286 (cpu_flags): Add CpuIBT, CpuSHSTK.
1287 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1288 (i386_cpu_flags): Add cpuibt, cpushstk.
1289 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1290 * i386-init.h: Regenerate.
1291 * i386-tbl.h: Likewise.
1292
f6efed01
NC		 12932018-01-16 Nick Clifton <nickc@redhat.com>
1294
1295 * po/pt_BR.po: Updated Brazilian Portugese translation.
1296 * po/de.po: Updated German translation.
1297
2721d702
JW		 12982018-01-15 Jim Wilson <jimw@sifive.com>
1299
1300 * riscv-opc.c (match_c_nop): New.
1301 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1302
616dcb87
NC		 13032018-01-15 Nick Clifton <nickc@redhat.com>
1304
1305 * po/uk.po: Updated Ukranian translation.
1306
3957a496
NC		 13072018-01-13 Nick Clifton <nickc@redhat.com>
1308
1309 * po/opcodes.pot: Regenerated.
1310
769c7ea5
NC		 13112018-01-13 Nick Clifton <nickc@redhat.com>
1312
1313 * configure: Regenerate.
1314
faf766e3
NC		 13152018-01-13 Nick Clifton <nickc@redhat.com>
1316
1317 2.30 branch created.
1318
888a89da
IT		 13192018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1320
1321 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1322 * i386-tbl.h: Regenerate.
1323
cbda583a
JB		 13242018-01-10 Jan Beulich <jbeulich@suse.com>
1325
1326 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1327 * i386-tbl.h: Re-generate.
1328
c9e92278
JB		 13292018-01-10 Jan Beulich <jbeulich@suse.com>
1330
1331 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1332 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1333 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1334 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1335 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1336 Disp8MemShift of AVX512VL forms.
1337 * i386-tbl.h: Re-generate.
1338
35fd2b2b
JW		 13392018-01-09 Jim Wilson <jimw@sifive.com>
1340
1341 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1342 then the hi_addr value is zero.
1343
91d8b670
JG		 13442018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1345
1346 * arm-dis.c (arm_opcodes): Add csdb.
1347 (thumb32_opcodes): Add csdb.
1348
be2e7d95
JG		 13492018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1350
1351 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1352 * aarch64-asm-2.c: Regenerate.
1353 * aarch64-dis-2.c: Regenerate.
1354 * aarch64-opc-2.c: Regenerate.
1355
704a705d
L		 13562018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1357
1358 PR gas/22681
1359 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1360 Remove AVX512 vmovd with 64-bit operands.
1361 * i386-tbl.h: Regenerated.
1362
35eeb78f
JW		 13632018-01-05 Jim Wilson <jimw@sifive.com>
1364
1365 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1366 jalr.
1367
219d1afa
AM		 13682018-01-03 Alan Modra <amodra@gmail.com>
1369
1370 Update year range in copyright notice of all files.
1371
1508bbf5
JB		 13722018-01-02 Jan Beulich <jbeulich@suse.com>
1373
1374 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1375 and OPERAND_TYPE_REGZMM entries.
1376
1e563868 1377For older changes see ChangeLog-2017
3499769a 1378\f
1e563868 1379Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 1380
1381Copying and distribution of this file, with or without modification,
1382are permitted in any medium without royalty provided the copyright
1383notice and this notice are preserved.
1384
1385Local Variables:
1386mode: change-log
1387left-margin: 8
1388fill-column: 74
1389version-control: never
1390End:
GDB Binutils - Deliverables
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