projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[AArch64] Print spaces after commas in addresses
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
ad43e107
RS		 12016-09-21 Richard Sandiford <richard.sandiford@arm.com>
2
3 * aarch64-opc.c (print_immediate_offset_address): Print spaces
4 after commas in addresses.
5 (aarch64_print_operand): Likewise.
6
ab3b8fcf
RS		 72016-09-21 Richard Sandiford <richard.sandiford@arm.com>
8
9 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
10 rather than "should be" or "expected to be" in error messages.
11
bb7eff52
RS		 122016-09-21 Richard Sandiford <richard.sandiford@arm.com>
13
14 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
15 (print_mnemonic_name): ...here.
16 (print_comment): New function.
17 (print_aarch64_insn): Call it.
18 * aarch64-opc.c (aarch64_conds): Add SVE names.
19 (aarch64_print_operand): Print alternative condition names in
20 a comment.
21
c0890d26
RS		 222016-09-21 Richard Sandiford <richard.sandiford@arm.com>
23
24 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
25 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
26 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
27 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
28 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
29 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
30 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
31 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
32 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
33 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
34 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
35 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
36 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
37 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
38 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
39 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
40 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
41 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
42 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
43 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
44 (OP_SVE_XWU, OP_SVE_XXU): New macros.
45 (aarch64_feature_sve): New variable.
46 (SVE): New macro.
47 (_SVE_INSN): Likewise.
48 (aarch64_opcode_table): Add SVE instructions.
49 * aarch64-opc.h (extract_fields): Declare.
50 * aarch64-opc-2.c: Regenerate.
51 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
52 * aarch64-asm-2.c: Regenerate.
53 * aarch64-dis.c (extract_fields): Make global.
54 (do_misc_decoding): Handle the new SVE aarch64_ops.
55 * aarch64-dis-2.c: Regenerate.
56
116b6019
RS		 572016-09-21 Richard Sandiford <richard.sandiford@arm.com>
58
59 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
60 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
61 aarch64_field_kinds.
62 * aarch64-opc.c (fields): Add corresponding entries.
63 * aarch64-asm.c (aarch64_get_variant): New function.
64 (aarch64_encode_variant_using_iclass): Likewise.
65 (aarch64_opcode_encode): Call it.
66 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
67 (aarch64_opcode_decode): Call it.
68
047cd301
RS		 692016-09-21 Richard Sandiford <richard.sandiford@arm.com>
70
71 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
72 and FP register operands.
73 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
74 (FLD_SVE_Vn): New aarch64_field_kinds.
75 * aarch64-opc.c (fields): Add corresponding entries.
76 (aarch64_print_operand): Handle the new SVE core and FP register
77 operands.
78 * aarch64-opc-2.c: Regenerate.
79 * aarch64-asm-2.c: Likewise.
80 * aarch64-dis-2.c: Likewise.
81
165d4950
RS		 822016-09-21 Richard Sandiford <richard.sandiford@arm.com>
83
84 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
85 immediate operands.
86 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
87 * aarch64-opc.c (fields): Add corresponding entry.
88 (operand_general_constraint_met_p): Handle the new SVE FP immediate
89 operands.
90 (aarch64_print_operand): Likewise.
91 * aarch64-opc-2.c: Regenerate.
92 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
93 (ins_sve_float_zero_one): New inserters.
94 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
95 (aarch64_ins_sve_float_half_two): Likewise.
96 (aarch64_ins_sve_float_zero_one): Likewise.
97 * aarch64-asm-2.c: Regenerate.
98 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
99 (ext_sve_float_zero_one): New extractors.
100 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
101 (aarch64_ext_sve_float_half_two): Likewise.
102 (aarch64_ext_sve_float_zero_one): Likewise.
103 * aarch64-dis-2.c: Regenerate.
104
e950b345
RS		 1052016-09-21 Richard Sandiford <richard.sandiford@arm.com>
106
107 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
108 integer immediate operands.
109 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
110 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
111 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
112 * aarch64-opc.c (fields): Add corresponding entries.
113 (operand_general_constraint_met_p): Handle the new SVE integer
114 immediate operands.
115 (aarch64_print_operand): Likewise.
116 (aarch64_sve_dupm_mov_immediate_p): New function.
117 * aarch64-opc-2.c: Regenerate.
118 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
119 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
120 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
121 (aarch64_ins_limm): ...here.
122 (aarch64_ins_inv_limm): New function.
123 (aarch64_ins_sve_aimm): Likewise.
124 (aarch64_ins_sve_asimm): Likewise.
125 (aarch64_ins_sve_limm_mov): Likewise.
126 (aarch64_ins_sve_shlimm): Likewise.
127 (aarch64_ins_sve_shrimm): Likewise.
128 * aarch64-asm-2.c: Regenerate.
129 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
130 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
131 * aarch64-dis.c (decode_limm): New function, split out from...
132 (aarch64_ext_limm): ...here.
133 (aarch64_ext_inv_limm): New function.
134 (decode_sve_aimm): Likewise.
135 (aarch64_ext_sve_aimm): Likewise.
136 (aarch64_ext_sve_asimm): Likewise.
137 (aarch64_ext_sve_limm_mov): Likewise.
138 (aarch64_top_bit): Likewise.
139 (aarch64_ext_sve_shlimm): Likewise.
140 (aarch64_ext_sve_shrimm): Likewise.
141 * aarch64-dis-2.c: Regenerate.
142
98907a70
RS		 1432016-09-21 Richard Sandiford <richard.sandiford@arm.com>
144
145 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
146 operands.
147 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
148 the AARCH64_MOD_MUL_VL entry.
149 (value_aligned_p): Cope with non-power-of-two alignments.
150 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
151 (print_immediate_offset_address): Likewise.
152 (aarch64_print_operand): Likewise.
153 * aarch64-opc-2.c: Regenerate.
154 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
155 (ins_sve_addr_ri_s9xvl): New inserters.
156 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
157 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
158 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
159 * aarch64-asm-2.c: Regenerate.
160 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
161 (ext_sve_addr_ri_s9xvl): New extractors.
162 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
163 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
164 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
165 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
166 * aarch64-dis-2.c: Regenerate.
167
4df068de
RS		 1682016-09-21 Richard Sandiford <richard.sandiford@arm.com>
169
170 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
171 address operands.
172 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
173 (FLD_SVE_xs_22): New aarch64_field_kinds.
174 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
175 (get_operand_specific_data): New function.
176 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
177 FLD_SVE_xs_14 and FLD_SVE_xs_22.
178 (operand_general_constraint_met_p): Handle the new SVE address
179 operands.
180 (sve_reg): New array.
181 (get_addr_sve_reg_name): New function.
182 (aarch64_print_operand): Handle the new SVE address operands.
183 * aarch64-opc-2.c: Regenerate.
184 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
185 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
186 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
187 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
188 (aarch64_ins_sve_addr_rr_lsl): Likewise.
189 (aarch64_ins_sve_addr_rz_xtw): Likewise.
190 (aarch64_ins_sve_addr_zi_u5): Likewise.
191 (aarch64_ins_sve_addr_zz): Likewise.
192 (aarch64_ins_sve_addr_zz_lsl): Likewise.
193 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
194 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
195 * aarch64-asm-2.c: Regenerate.
196 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
197 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
198 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
199 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
200 (aarch64_ext_sve_addr_ri_u6): Likewise.
201 (aarch64_ext_sve_addr_rr_lsl): Likewise.
202 (aarch64_ext_sve_addr_rz_xtw): Likewise.
203 (aarch64_ext_sve_addr_zi_u5): Likewise.
204 (aarch64_ext_sve_addr_zz): Likewise.
205 (aarch64_ext_sve_addr_zz_lsl): Likewise.
206 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
207 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
208 * aarch64-dis-2.c: Regenerate.
209
2442d846
RS		 2102016-09-21 Richard Sandiford <richard.sandiford@arm.com>
211
212 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
213 AARCH64_OPND_SVE_PATTERN_SCALED.
214 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
215 * aarch64-opc.c (fields): Add a corresponding entry.
216 (set_multiplier_out_of_range_error): New function.
217 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
218 (operand_general_constraint_met_p): Handle
219 AARCH64_OPND_SVE_PATTERN_SCALED.
220 (print_register_offset_address): Use PRIi64 to print the
221 shift amount.
222 (aarch64_print_operand): Likewise. Handle
223 AARCH64_OPND_SVE_PATTERN_SCALED.
224 * aarch64-opc-2.c: Regenerate.
225 * aarch64-asm.h (ins_sve_scale): New inserter.
226 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
227 * aarch64-asm-2.c: Regenerate.
228 * aarch64-dis.h (ext_sve_scale): New inserter.
229 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
230 * aarch64-dis-2.c: Regenerate.
231
245d2e3f
RS		 2322016-09-21 Richard Sandiford <richard.sandiford@arm.com>
233
234 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
235 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
236 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
237 (FLD_SVE_prfop): Likewise.
238 * aarch64-opc.c: Include libiberty.h.
239 (aarch64_sve_pattern_array): New variable.
240 (aarch64_sve_prfop_array): Likewise.
241 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
242 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
243 AARCH64_OPND_SVE_PRFOP.
244 * aarch64-asm-2.c: Regenerate.
245 * aarch64-dis-2.c: Likewise.
246 * aarch64-opc-2.c: Likewise.
247
d50c751e
RS		 2482016-09-21 Richard Sandiford <richard.sandiford@arm.com>
249
250 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
251 AARCH64_OPND_QLF_P_[ZM].
252 (aarch64_print_operand): Print /z and /m where appropriate.
253
f11ad6bc
RS		 2542016-09-21 Richard Sandiford <richard.sandiford@arm.com>
255
256 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
257 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
258 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
259 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
260 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
261 * aarch64-opc.c (fields): Add corresponding entries here.
262 (operand_general_constraint_met_p): Check that SVE register lists
263 have the correct length. Check the ranges of SVE index registers.
264 Check for cases where p8-p15 are used in 3-bit predicate fields.
265 (aarch64_print_operand): Handle the new SVE operands.
266 * aarch64-opc-2.c: Regenerate.
267 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
268 * aarch64-asm.c (aarch64_ins_sve_index): New function.
269 (aarch64_ins_sve_reglist): Likewise.
270 * aarch64-asm-2.c: Regenerate.
271 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
272 * aarch64-dis.c (aarch64_ext_sve_index): New function.
273 (aarch64_ext_sve_reglist): Likewise.
274 * aarch64-dis-2.c: Regenerate.
275
0c608d6b
RS		 2762016-09-21 Richard Sandiford <richard.sandiford@arm.com>
277
278 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
279 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
280 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
281 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
282 tied operands.
283
01dbfe4c
RS		 2842016-09-21 Richard Sandiford <richard.sandiford@arm.com>
285
286 * aarch64-opc.c (get_offset_int_reg_name): New function.
287 (print_immediate_offset_address): Likewise.
288 (print_register_offset_address): Take the base and offset
289 registers as parameters.
290 (aarch64_print_operand): Update caller accordingly. Use
291 print_immediate_offset_address.
292
72e9f319
RS		 2932016-09-21 Richard Sandiford <richard.sandiford@arm.com>
294
295 * aarch64-opc.c (BANK): New macro.
296 (R32, R64): Take a register number as argument
297 (int_reg): Use BANK.
298
8a7f0c1b
RS		 2992016-09-21 Richard Sandiford <richard.sandiford@arm.com>
300
301 * aarch64-opc.c (print_register_list): Add a prefix parameter.
302 (aarch64_print_operand): Update accordingly.
303
aa2aa4c6
RS		 3042016-09-21 Richard Sandiford <richard.sandiford@arm.com>
305
306 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
307 for FPIMM.
308 * aarch64-asm.h (ins_fpimm): New inserter.
309 * aarch64-asm.c (aarch64_ins_fpimm): New function.
310 * aarch64-asm-2.c: Regenerate.
311 * aarch64-dis.h (ext_fpimm): New extractor.
312 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
313 (aarch64_ext_fpimm): New function.
314 * aarch64-dis-2.c: Regenerate.
315
b5464a68
RS		 3162016-09-21 Richard Sandiford <richard.sandiford@arm.com>
317
318 * aarch64-asm.c: Include libiberty.h.
319 (insert_fields): New function.
320 (aarch64_ins_imm): Use it.
321 * aarch64-dis.c (extract_fields): New function.
322 (aarch64_ext_imm): Use it.
323
42408347
RS		 3242016-09-21 Richard Sandiford <richard.sandiford@arm.com>
325
326 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
327 with an esize parameter.
328 (operand_general_constraint_met_p): Update accordingly.
329 Fix misindented code.
330 * aarch64-asm.c (aarch64_ins_limm): Update call to
331 aarch64_logical_immediate_p.
332
4989adac
RS		 3332016-09-21 Richard Sandiford <richard.sandiford@arm.com>
334
335 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
336
bd11d5d8
RS		 3372016-09-21 Richard Sandiford <richard.sandiford@arm.com>
338
339 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
340
f807f43d
CZ		 3412016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
342
343 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
344
fd486b63
PB		 3452016-09-14 Peter Bergner <bergner@vnet.ibm.com>
346
347 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
348 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
349 xor3>: Delete mnemonics.
350 <cp_abort>: Rename mnemonic from ...
351 <cpabort>: ...to this.
352 <setb>: Change to a X form instruction.
353 <sync>: Change to 1 operand form.
354 <copy>: Delete mnemonic.
355 <copy_first>: Rename mnemonic from ...
356 <copy>: ...to this.
357 <paste, paste.>: Delete mnemonics.
358 <paste_last>: Rename mnemonic from ...
359 <paste.>: ...to this.
360
dce08442
AK		 3612016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
362
363 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
364
952c3f51
AK		 3652016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
366
367 * s390-mkopc.c (main): Support alternate arch strings.
368
8b71537b
PS		 3692016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
370
371 * s390-opc.txt: Fix kmctr instruction type.
372
5b64d091
L		 3732016-09-07 H.J. Lu <hongjiu.lu@intel.com>
374
375 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
376 * i386-init.h: Regenerated.
377
7763838e
CM		 3782016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
379
380 * opcodes/arc-dis.c (print_insn_arc): Changed.
381
1b8b6532
JM		 3822016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
383
384 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
385 camellia_fl.
386
1a336194
TP		 3872016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
388
389 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
390 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
391 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
392
6b40c462
L		 3932016-08-24 H.J. Lu <hongjiu.lu@intel.com>
394
395 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
396 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
397 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
398 PREFIX_MOD_3_0FAE_REG_4.
399 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
400 PREFIX_MOD_3_0FAE_REG_4.
401 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
402 (cpu_flags): Add CpuPTWRITE.
403 * i386-opc.h (CpuPTWRITE): New.
404 (i386_cpu_flags): Add cpuptwrite.
405 * i386-opc.tbl: Add ptwrite instruction.
406 * i386-init.h: Regenerated.
407 * i386-tbl.h: Likewise.
408
ab548d2d
AK		 4092016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
410
411 * arc-dis.h: Wrap around in extern "C".
412
344bde0a
RS		 4132016-08-23 Richard Sandiford <richard.sandiford@arm.com>
414
415 * aarch64-tbl.h (V8_2_INSN): New macro.
416 (aarch64_opcode_table): Use it.
417
5ce912d8
RS		 4182016-08-23 Richard Sandiford <richard.sandiford@arm.com>
419
420 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
421 CORE_INSN, __FP_INSN and SIMD_INSN.
422
9d30b0bd
RS		 4232016-08-23 Richard Sandiford <richard.sandiford@arm.com>
424
425 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
426 (aarch64_opcode_table): Update uses accordingly.
427
dfdaec14
AJ		 4282016-07-25 Andrew Jenner <andrew@codesourcery.com>
429 Kwok Cheung Yeung <kcy@codesourcery.com>
430
431 opcodes/
432 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
433 'e_cmplwi' to 'e_cmpli' instead.
434 (OPVUPRT, OPVUPRT_MASK): Define.
435 (powerpc_opcodes): Add E200Z4 insns.
436 (vle_opcodes): Add context save/restore insns.
437
7bd374a4
MR		 4382016-07-27 Maciej W. Rozycki <macro@imgtec.com>
439
440 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
441 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
442 "j".
443
db18dbab
GM		 4442016-07-27 Graham Markall <graham.markall@embecosm.com>
445
446 * arc-nps400-tbl.h: Change block comments to GNU format.
447 * arc-dis.c: Add new globals addrtypenames,
448 addrtypenames_max, and addtypeunknown.
449 (get_addrtype): New function.
450 (print_insn_arc): Print colons and address types when
451 required.
452 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
453 define insert and extract functions for all address types.
454 (arc_operands): Add operands for colon and all address
455 types.
456 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
457 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
458 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
459 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
460 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
461 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
462
fecd57f9
L		 4632016-07-21 H.J. Lu <hongjiu.lu@intel.com>
464
465 * configure: Regenerated.
466
37fd5ef3
CZ		 4672016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
468
469 * arc-dis.c (skipclass): New structure.
470 (decodelist): New variable.
471 (is_compatible_p): New function.
472 (new_element): Likewise.
473 (skip_class_p): Likewise.
474 (find_format_from_table): Use skip_class_p function.
475 (find_format): Decode first the extension instructions.
476 (print_insn_arc): Select either ARCEM or ARCHS based on elf
477 e_flags.
478 (parse_option): New function.
479 (parse_disassembler_options): Likewise.
480 (print_arc_disassembler_options): Likewise.
481 (print_insn_arc): Use parse_disassembler_options function. Proper
482 select ARCv2 cpu variant.
483 * disassemble.c (disassembler_usage): Add ARC disassembler
484 options.
485
92281a5b
MR		 4862016-07-13 Maciej W. Rozycki <macro@imgtec.com>
487
488 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
489 annotation from the "nal" entry and reorder it beyond "bltzal".
490
6e7ced37
JM		 4912016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
492
493 * sparc-opc.c (ldtxa): New macro.
494 (sparc_opcodes): Use the macro defined above to add entries for
495 the LDTXA instructions.
496 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
497 instruction.
498
2f831b9a 4992016-07-07 James Bowman <james.bowman@ftdichip.com>
500
501 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
502 and "jmpc".
503
c07315e0
JB		 5042016-07-01 Jan Beulich <jbeulich@suse.com>
505
506 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
507 (movzb): Adjust to cover all permitted suffixes.
508 (movzw): New.
509 * i386-tbl.h: Re-generate.
510
9243100a
JB		 5112016-07-01 Jan Beulich <jbeulich@suse.com>
512
513 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
514 (lgdt): Remove Tbyte from non-64-bit variant.
515 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
516 xsaves64, xsavec64): Remove Disp16.
517 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
518 Remove Disp32S from non-64-bit variants. Remove Disp16 from
519 64-bit variants.
520 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
521 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
522 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
523 64-bit variants.
524 * i386-tbl.h: Re-generate.
525
8325cc63
JB		 5262016-07-01 Jan Beulich <jbeulich@suse.com>
527
528 * i386-opc.tbl (xlat): Remove RepPrefixOk.
529 * i386-tbl.h: Re-generate.
530
838441e4
YQ		 5312016-06-30 Yao Qi <yao.qi@linaro.org>
532
533 * arm-dis.c (print_insn): Fix typo in comment.
534
dab26bf4
RS		 5352016-06-28 Richard Sandiford <richard.sandiford@arm.com>
536
537 * aarch64-opc.c (operand_general_constraint_met_p): Check the
538 range of ldst_elemlist operands.
539 (print_register_list): Use PRIi64 to print the index.
540 (aarch64_print_operand): Likewise.
541
5703197e
TS		 5422016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
543
544 * mcore-opc.h: Remove sentinal.
545 * mcore-dis.c (print_insn_mcore): Adjust.
546
ce440d63
GM		 5472016-06-23 Graham Markall <graham.markall@embecosm.com>
548
549 * arc-opc.c: Correct description of availability of NPS400
550 features.
551
6fd3a02d
PB		 5522016-06-22 Peter Bergner <bergner@vnet.ibm.com>
553
554 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
555 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
556 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
557 xor3>: New mnemonics.
558 <setb>: Change to a VX form instruction.
559 (insert_sh6): Add support for rldixor.
560 (extract_sh6): Likewise.
561
6b477896
TS		 5622016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
563
564 * arc-ext.h: Wrap in extern C.
565
bdd582db
GM		 5662016-06-21 Graham Markall <graham.markall@embecosm.com>
567
568 * arc-dis.c (arc_insn_length): Add comment on instruction length.
569 Use same method for determining instruction length on ARC700 and
570 NPS-400.
571 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
572 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
573 with the NPS400 subclass.
574 * arc-opc.c: Likewise.
575
96074adc
JM		 5762016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
577
578 * sparc-opc.c (rdasr): New macro.
579 (wrasr): Likewise.
580 (rdpr): Likewise.
581 (wrpr): Likewise.
582 (rdhpr): Likewise.
583 (wrhpr): Likewise.
584 (sparc_opcodes): Use the macros above to fix and expand the
585 definition of read/write instructions from/to
586 asr/privileged/hyperprivileged instructions.
587 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
588 %hva_mask_nz. Prefer softint_set and softint_clear over
589 set_softint and clear_softint.
590 (print_insn_sparc): Support %ver in Rd.
591
7a10c22f
JM		 5922016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
593
594 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
595 architecture according to the hardware capabilities they require.
596
4f26fb3a
JM		 5972016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
598
599 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
600 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
601 bfd_mach_sparc_v9{c,d,e,v,m}.
602 * sparc-opc.c (MASK_V9C): Define.
603 (MASK_V9D): Likewise.
604 (MASK_V9E): Likewise.
605 (MASK_V9V): Likewise.
606 (MASK_V9M): Likewise.
607 (v6): Add MASK_V9{C,D,E,V,M}.
608 (v6notlet): Likewise.
609 (v7): Likewise.
610 (v8): Likewise.
611 (v9): Likewise.
612 (v9andleon): Likewise.
613 (v9a): Likewise.
614 (v9b): Likewise.
615 (v9c): Define.
616 (v9d): Likewise.
617 (v9e): Likewise.
618 (v9v): Likewise.
619 (v9m): Likewise.
620 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
621
3ee6e4fb
NC		 6222016-06-15 Nick Clifton <nickc@redhat.com>
623
624 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
625 constants to match expected behaviour.
626 (nds32_parse_opcode): Likewise. Also for whitespace.
627
02f3be19
AB		 6282016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
629
630 * arc-opc.c (extract_rhv1): Extract value from insn.
631
6f9f37ed 6322016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 633
634 * arc-nps400-tbl.h: Add ldbit instruction.
635 * arc-opc.c: Add flag classes required for ldbit.
636
6f9f37ed 6372016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 638
639 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
640 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
641 support the above instructions.
642
6f9f37ed 6432016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 644
645 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
646 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
647 csma, cbba, zncv, and hofs.
648 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
649 support the above instructions.
650
6512016-06-06 Graham Markall <graham.markall@embecosm.com>
652
653 * arc-nps400-tbl.h: Add andab and orab instructions.
654
6552016-06-06 Graham Markall <graham.markall@embecosm.com>
656
657 * arc-nps400-tbl.h: Add addl-like instructions.
658
6592016-06-06 Graham Markall <graham.markall@embecosm.com>
660
661 * arc-nps400-tbl.h: Add mxb and imxb instructions.
662
6632016-06-06 Graham Markall <graham.markall@embecosm.com>
664
665 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
666 instructions.
667
b2cc3f6f
AK		 6682016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
669
670 * s390-dis.c (option_use_insn_len_bits_p): New file scope
671 variable.
672 (init_disasm): Handle new command line option "insnlength".
673 (print_s390_disassembler_options): Mention new option in help
674 output.
675 (print_insn_s390): Use the encoded insn length when dumping
676 unknown instructions.
677
1857fe72
DC		 6782016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
679
680 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
681 to the address and set as symbol address for LDS/ STS immediate operands.
682
14b57c7c
AM		 6832016-06-07 Alan Modra <amodra@gmail.com>
684
685 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
686 cpu for "vle" to e500.
687 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
688 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
689 (PPCNONE): Delete, substitute throughout.
690 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
691 except for major opcode 4 and 31.
692 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
693
4d1464f2
MW		 6942016-06-07 Matthew Wahab <matthew.wahab@arm.com>
695
696 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
697 ARM_EXT_RAS in relevant entries.
698
026122a6
PB		 6992016-06-03 Peter Bergner <bergner@vnet.ibm.com>
700
701 PR binutils/20196
702 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
703 opcodes for E6500.
704
07f5af7d
L		 7052016-06-03 H.J. Lu <hongjiu.lu@intel.com>
706
707 PR binutis/18386
708 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
709 (indir_v_mode): New.
710 Add comments for '&'.
711 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
712 (putop): Handle '&'.
713 (intel_operand_size): Handle indir_v_mode.
714 (OP_E_register): Likewise.
715 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
716 64-bit indirect call/jmp for AMD64.
717 * i386-tbl.h: Regenerated
718
4eb6f892
AB		 7192016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
720
721 * arc-dis.c (struct arc_operand_iterator): New structure.
722 (find_format_from_table): All the old content from find_format,
723 with some minor adjustments, and parameter renaming.
724 (find_format_long_instructions): New function.
725 (find_format): Rewritten.
726 (arc_insn_length): Add LSB parameter.
727 (extract_operand_value): New function.
728 (operand_iterator_next): New function.
729 (print_insn_arc): Use new functions to find opcode, and iterator
730 over operands.
731 * arc-opc.c (insert_nps_3bit_dst_short): New function.
732 (extract_nps_3bit_dst_short): New function.
733 (insert_nps_3bit_src2_short): New function.
734 (extract_nps_3bit_src2_short): New function.
735 (insert_nps_bitop1_size): New function.
736 (extract_nps_bitop1_size): New function.
737 (insert_nps_bitop2_size): New function.
738 (extract_nps_bitop2_size): New function.
739 (insert_nps_bitop_mod4_msb): New function.
740 (extract_nps_bitop_mod4_msb): New function.
741 (insert_nps_bitop_mod4_lsb): New function.
742 (extract_nps_bitop_mod4_lsb): New function.
743 (insert_nps_bitop_dst_pos3_pos4): New function.
744 (extract_nps_bitop_dst_pos3_pos4): New function.
745 (insert_nps_bitop_ins_ext): New function.
746 (extract_nps_bitop_ins_ext): New function.
747 (arc_operands): Add new operands.
748 (arc_long_opcodes): New global array.
749 (arc_num_long_opcodes): New global.
750 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
751
1fe0971e
TS		 7522016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
753
754 * nds32-asm.h: Add extern "C".
755 * sh-opc.h: Likewise.
756
315f180f
GM		 7572016-06-01 Graham Markall <graham.markall@embecosm.com>
758
759 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
760 0,b,limm to the rflt instruction.
761
a2b5fccc
TS		 7622016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
763
764 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
765 constant.
766
0cbd0046
L		 7672016-05-29 H.J. Lu <hongjiu.lu@intel.com>
768
769 PR gas/20145
770 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
771 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
772 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
773 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
774 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
775 * i386-init.h: Regenerated.
776
1848e567
L		 7772016-05-27 H.J. Lu <hongjiu.lu@intel.com>
778
779 PR gas/20145
780 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
781 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
782 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
783 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
784 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
785 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
786 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
787 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
788 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
789 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
790 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
791 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
792 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
793 CpuRegMask for AVX512.
794 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
795 and CpuRegMask.
796 (set_bitfield_from_cpu_flag_init): New function.
797 (set_bitfield): Remove const on f. Call
798 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
799 * i386-opc.h (CpuRegMMX): New.
800 (CpuRegXMM): Likewise.
801 (CpuRegYMM): Likewise.
802 (CpuRegZMM): Likewise.
803 (CpuRegMask): Likewise.
804 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
805 and cpuregmask.
806 * i386-init.h: Regenerated.
807 * i386-tbl.h: Likewise.
808
e92bae62
L		 8092016-05-27 H.J. Lu <hongjiu.lu@intel.com>
810
811 PR gas/20154
812 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
813 (opcode_modifiers): Add AMD64 and Intel64.
814 (main): Properly verify CpuMax.
815 * i386-opc.h (CpuAMD64): Removed.
816 (CpuIntel64): Likewise.
817 (CpuMax): Set to CpuNo64.
818 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
819 (AMD64): New.
820 (Intel64): Likewise.
821 (i386_opcode_modifier): Add amd64 and intel64.
822 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
823 on call and jmp.
824 * i386-init.h: Regenerated.
825 * i386-tbl.h: Likewise.
826
e89c5eaa
L		 8272016-05-27 H.J. Lu <hongjiu.lu@intel.com>
828
829 PR gas/20154
830 * i386-gen.c (main): Fail if CpuMax is incorrect.
831 * i386-opc.h (CpuMax): Set to CpuIntel64.
832 * i386-tbl.h: Regenerated.
833
77d66e7b
NC		 8342016-05-27 Nick Clifton <nickc@redhat.com>
835
836 PR target/20150
837 * msp430-dis.c (msp430dis_read_two_bytes): New function.
838 (msp430dis_opcode_unsigned): New function.
839 (msp430dis_opcode_signed): New function.
840 (msp430_singleoperand): Use the new opcode reading functions.
841 Only disassenmble bytes if they were successfully read.
842 (msp430_doubleoperand): Likewise.
843 (msp430_branchinstr): Likewise.
844 (msp430x_callx_instr): Likewise.
845 (print_insn_msp430): Check that it is safe to read bytes before
846 attempting disassembly. Use the new opcode reading functions.
847
19dfcc89
PB		 8482016-05-26 Peter Bergner <bergner@vnet.ibm.com>
849
850 * ppc-opc.c (CY): New define. Document it.
851 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
852
f3ad7637
L		 8532016-05-25 H.J. Lu <hongjiu.lu@intel.com>
854
855 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
856 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
857 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
858 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
859 CPU_ANY_AVX_FLAGS.
860 * i386-init.h: Regenerated.
861
f1360d58
L		 8622016-05-25 H.J. Lu <hongjiu.lu@intel.com>
863
864 PR gas/20141
865 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
866 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
867 * i386-init.h: Regenerated.
868
293f5f65
L		 8692016-05-25 H.J. Lu <hongjiu.lu@intel.com>
870
871 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
872 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
873 * i386-init.h: Regenerated.
874
d9eca1df
CZ		 8752016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
876
877 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
878 information.
879 (print_insn_arc): Set insn_type information.
880 * arc-opc.c (C_CC): Add F_CLASS_COND.
881 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
882 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
883 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
884 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
885 (brne, brne_s, jeq_s, jne_s): Likewise.
886
87789e08
CZ		 8872016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
888
889 * arc-tbl.h (neg): New instruction variant.
890
c810e0b8
CZ		 8912016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
892
893 * arc-dis.c (find_format, find_format, get_auxreg)
894 (print_insn_arc): Changed.
895 * arc-ext.h (INSERT_XOP): Likewise.
896
3d207518
TS		 8972016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
898
899 * tic54x-dis.c (sprint_mmr): Adjust.
900 * tic54x-opc.c: Likewise.
901
514e58b7
AM		 9022016-05-19 Alan Modra <amodra@gmail.com>
903
904 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
905
e43de63c
AM		 9062016-05-19 Alan Modra <amodra@gmail.com>
907
908 * ppc-opc.c: Formatting.
909 (NSISIGNOPT): Define.
910 (powerpc_opcodes <subis>): Use NSISIGNOPT.
911
1401d2fe
MR		 9122016-05-18 Maciej W. Rozycki <macro@imgtec.com>
913
914 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
915 replacing references to `micromips_ase' throughout.
916 (_print_insn_mips): Don't use file-level microMIPS annotation to
917 determine the disassembly mode with the symbol table.
918
1178da44
PB		 9192016-05-13 Peter Bergner <bergner@vnet.ibm.com>
920
921 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
922
8f4f9071
MF		 9232016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
924
925 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
926 mips64r6.
927 * mips-opc.c (D34): New macro.
928 (mips_builtin_opcodes): Define bposge32c for DSPr3.
929
8bc52696
AF		 9302016-05-10 Alexander Fomin <alexander.fomin@intel.com>
931
932 * i386-dis.c (prefix_table): Add RDPID instruction.
933 * i386-gen.c (cpu_flag_init): Add RDPID flag.
934 (cpu_flags): Add RDPID bitfield.
935 * i386-opc.h (enum): Add RDPID element.
936 (i386_cpu_flags): Add RDPID field.
937 * i386-opc.tbl: Add RDPID instruction.
938 * i386-init.h: Regenerate.
939 * i386-tbl.h: Regenerate.
940
39d911fc
TP		 9412016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
942
943 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
944 branch type of a symbol.
945 (print_insn): Likewise.
946
16a1fa25
TP		 9472016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
948
949 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
950 Mainline Security Extensions instructions.
951 (thumb_opcodes): Add entries for narrow ARMv8-M Security
952 Extensions instructions.
953 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
954 instructions.
955 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
956 special registers.
957
d751b79e
JM		 9582016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
959
960 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
961
945e0f82
CZ		 9622016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
963
964 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
965 (arcExtMap_genOpcode): Likewise.
966 * arc-opc.c (arg_32bit_rc): Define new variable.
967 (arg_32bit_u6): Likewise.
968 (arg_32bit_limm): Likewise.
969
20f55f38
SN		 9702016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
971
972 * aarch64-gen.c (VERIFIER): Define.
973 * aarch64-opc.c (VERIFIER): Define.
974 (verify_ldpsw): Use static linkage.
975 * aarch64-opc.h (verify_ldpsw): Remove.
976 * aarch64-tbl.h: Use VERIFIER for verifiers.
977
4bd13cde
NC		 9782016-04-28 Nick Clifton <nickc@redhat.com>
979
980 PR target/19722
981 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
982 * aarch64-opc.c (verify_ldpsw): New function.
983 * aarch64-opc.h (verify_ldpsw): New prototype.
984 * aarch64-tbl.h: Add initialiser for verifier field.
985 (LDPSW): Set verifier to verify_ldpsw.
986
c0f92bf9
L		 9872016-04-23 H.J. Lu <hongjiu.lu@intel.com>
988
989 PR binutils/19983
990 PR binutils/19984
991 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
992 smaller than address size.
993
e6c7cdec
TS		 9942016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
995
996 * alpha-dis.c: Regenerate.
997 * crx-dis.c: Likewise.
998 * disassemble.c: Likewise.
999 * epiphany-opc.c: Likewise.
1000 * fr30-opc.c: Likewise.
1001 * frv-opc.c: Likewise.
1002 * ip2k-opc.c: Likewise.
1003 * iq2000-opc.c: Likewise.
1004 * lm32-opc.c: Likewise.
1005 * lm32-opinst.c: Likewise.
1006 * m32c-opc.c: Likewise.
1007 * m32r-opc.c: Likewise.
1008 * m32r-opinst.c: Likewise.
1009 * mep-opc.c: Likewise.
1010 * mt-opc.c: Likewise.
1011 * or1k-opc.c: Likewise.
1012 * or1k-opinst.c: Likewise.
1013 * tic80-opc.c: Likewise.
1014 * xc16x-opc.c: Likewise.
1015 * xstormy16-opc.c: Likewise.
1016
537aefaf
AB		 10172016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1018
1019 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1020 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1021 calcsd, and calcxd instructions.
1022 * arc-opc.c (insert_nps_bitop_size): Delete.
1023 (extract_nps_bitop_size): Delete.
1024 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1025 (extract_nps_qcmp_m3): Define.
1026 (extract_nps_qcmp_m2): Define.
1027 (extract_nps_qcmp_m1): Define.
1028 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1029 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1030 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1031 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1032 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1033 NPS_QCMP_M3.
1034
c8f785f2
AB		 10352016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1036
1037 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1038
6fd8e7c2
L		 10392016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1040
1041 * Makefile.in: Regenerated with automake 1.11.6.
1042 * aclocal.m4: Likewise.
1043
4b0c052e
AB		 10442016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1045
1046 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1047 instructions.
1048 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1049 (extract_nps_cmem_uimm16): New function.
1050 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1051
cb040366
AB		 10522016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1053
1054 * arc-dis.c (arc_insn_length): New function.
1055 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1056 (find_format): Change insnLen parameter to unsigned.
1057
accc0180
NC		 10582016-04-13 Nick Clifton <nickc@redhat.com>
1059
1060 PR target/19937
1061 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1062 the LD.B and LD.BU instructions.
1063
f36e33da
CZ		 10642016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1065
1066 * arc-dis.c (find_format): Check for extension flags.
1067 (print_flags): New function.
1068 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1069 .extAuxRegister.
1070 * arc-ext.c (arcExtMap_coreRegName): Use
1071 LAST_EXTENSION_CORE_REGISTER.
1072 (arcExtMap_coreReadWrite): Likewise.
1073 (dump_ARC_extmap): Update printing.
1074 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1075 (arc_aux_regs): Add cpu field.
1076 * arc-regs.h: Add cpu field, lower case name aux registers.
1077
1c2e355e
CZ		 10782016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1079
1080 * arc-tbl.h: Add rtsc, sleep with no arguments.
1081
b99747ae
CZ		 10822016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1083
1084 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1085 Initialize.
1086 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1087 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1088 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1089 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1090 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1091 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1092 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1093 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1094 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1095 (arc_opcode arc_opcodes): Null terminate the array.
1096 (arc_num_opcodes): Remove.
1097 * arc-ext.h (INSERT_XOP): Define.
1098 (extInstruction_t): Likewise.
1099 (arcExtMap_instName): Delete.
1100 (arcExtMap_insn): New function.
1101 (arcExtMap_genOpcode): Likewise.
1102 * arc-ext.c (ExtInstruction): Remove.
1103 (create_map): Zero initialize instruction fields.
1104 (arcExtMap_instName): Remove.
1105 (arcExtMap_insn): New function.
1106 (dump_ARC_extmap): More info while debuging.
1107 (arcExtMap_genOpcode): New function.
1108 * arc-dis.c (find_format): New function.
1109 (print_insn_arc): Use find_format.
1110 (arc_get_disassembler): Enable dump_ARC_extmap only when
1111 debugging.
1112
92708cec
MR		 11132016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1114
1115 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1116 instruction bits out.
1117
a42a4f84
AB		 11182016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1119
1120 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1121 * arc-opc.c (arc_flag_operands): Add new flags.
1122 (arc_flag_classes): Add new classes.
1123
1328504b
AB		 11242016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1125
1126 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1127
820f03ff
AB		 11282016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1129
1130 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1131 encode1, rflt, crc16, and crc32 instructions.
1132 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1133 (arc_flag_classes): Add C_NPS_R.
1134 (insert_nps_bitop_size_2b): New function.
1135 (extract_nps_bitop_size_2b): Likewise.
1136 (insert_nps_bitop_uimm8): Likewise.
1137 (extract_nps_bitop_uimm8): Likewise.
1138 (arc_operands): Add new operand entries.
1139
8ddf6b2a
CZ		 11402016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1141
b99747ae
CZ		 1142 * arc-regs.h: Add a new subclass field. Add double assist
1143 accumulator register values.
1144 * arc-tbl.h: Use DPA subclass to mark the double assist
1145 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1146 * arc-opc.c (RSP): Define instead of SP.
1147 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1148
589a7d88
JW		 11492016-04-05 Jiong Wang <jiong.wang@arm.com>
1150
1151 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1152
0a191de9 11532016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1154
1155 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1156 NPS_R_SRC1.
1157
0a106562
AB		 11582016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1159
1160 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1161 issues. No functional changes.
1162
bd05ac5f
CZ		 11632016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1164
b99747ae
CZ		 1165 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1166 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1167 (RTT): Remove duplicate.
1168 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1169 (PCT_CONFIG*): Remove.
1170 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1171
9885948f
CZ		 11722016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1173
b99747ae 1174 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1175
f2dd8838
CZ		 11762016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1177
b99747ae
CZ		 1178 * arc-tbl.h (invld07): Remove.
1179 * arc-ext-tbl.h: New file.
1180 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1181 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1182
0d2f91fe
JK		 11832016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1184
1185 Fix -Wstack-usage warnings.
1186 * aarch64-dis.c (print_operands): Substitute size.
1187 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1188
a6b71f42
JM		 11892016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1190
1191 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1192 to get a proper diagnostic when an invalid ASR register is used.
1193
9780e045
NC		 11942016-03-22 Nick Clifton <nickc@redhat.com>
1195
1196 * configure: Regenerate.
1197
e23e8ebe
AB		 11982016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1199
1200 * arc-nps400-tbl.h: New file.
1201 * arc-opc.c: Add top level comment.
1202 (insert_nps_3bit_dst): New function.
1203 (extract_nps_3bit_dst): New function.
1204 (insert_nps_3bit_src2): New function.
1205 (extract_nps_3bit_src2): New function.
1206 (insert_nps_bitop_size): New function.
1207 (extract_nps_bitop_size): New function.
1208 (arc_flag_operands): Add nps400 entries.
1209 (arc_flag_classes): Add nps400 entries.
1210 (arc_operands): Add nps400 entries.
1211 (arc_opcodes): Add nps400 include.
1212
1ae8ab47
AB		 12132016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1214
1215 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1216 the new class enum values.
1217
8699fc3e
AB		 12182016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1219
1220 * arc-dis.c (print_insn_arc): Handle nps400.
1221
24740d83
AB		 12222016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1223
1224 * arc-opc.c (BASE): Delete.
1225
8678914f
NC		 12262016-03-18 Nick Clifton <nickc@redhat.com>
1227
1228 PR target/19721
1229 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1230 of MOV insn that aliases an ORR insn.
1231
cc933301
JW		 12322016-03-16 Jiong Wang <jiong.wang@arm.com>
1233
1234 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1235
f86f5863
TS		 12362016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1237
1238 * mcore-opc.h: Add const qualifiers.
1239 * microblaze-opc.h (struct op_code_struct): Likewise.
1240 * sh-opc.h: Likewise.
1241 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1242 (tic4x_print_op): Likewise.
1243
62de1c63
AM		 12442016-03-02 Alan Modra <amodra@gmail.com>
1245
d11698cd 1246 * or1k-desc.h: Regenerate.
62de1c63 1247 * fr30-ibld.c: Regenerate.
c697cf0b 1248 * rl78-decode.c: Regenerate.
62de1c63 1249
020efce5
NC		 12502016-03-01 Nick Clifton <nickc@redhat.com>
1251
1252 PR target/19747
1253 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1254
b0c11777
RL		 12552016-02-24 Renlin Li <renlin.li@arm.com>
1256
1257 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1258 (print_insn_coprocessor): Support fp16 instructions.
1259
3e309328
RL		 12602016-02-24 Renlin Li <renlin.li@arm.com>
1261
1262 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1263 vminnm, vrint(mpna).
1264
8afc7bea
RL		 12652016-02-24 Renlin Li <renlin.li@arm.com>
1266
1267 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1268 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1269
4fd7268a
L		 12702016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1271
1272 * i386-dis.c (print_insn): Parenthesize expression to prevent
1273 truncated addresses.
1274 (OP_J): Likewise.
1275
4670103e
CZ		 12762016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1277 Janek van Oirschot <jvanoirs@synopsys.com>
1278
b99747ae
CZ		 1279 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1280 variable.
4670103e 1281
c1d9289f
NC		 12822016-02-04 Nick Clifton <nickc@redhat.com>
1283
1284 PR target/19561
1285 * msp430-dis.c (print_insn_msp430): Add a special case for
1286 decoding an RRC instruction with the ZC bit set in the extension
1287 word.
1288
a143b004
AB		 12892016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1290
1291 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1292 * epiphany-ibld.c: Regenerate.
1293 * fr30-ibld.c: Regenerate.
1294 * frv-ibld.c: Regenerate.
1295 * ip2k-ibld.c: Regenerate.
1296 * iq2000-ibld.c: Regenerate.
1297 * lm32-ibld.c: Regenerate.
1298 * m32c-ibld.c: Regenerate.
1299 * m32r-ibld.c: Regenerate.
1300 * mep-ibld.c: Regenerate.
1301 * mt-ibld.c: Regenerate.
1302 * or1k-ibld.c: Regenerate.
1303 * xc16x-ibld.c: Regenerate.
1304 * xstormy16-ibld.c: Regenerate.
1305
b89807c6
AB		 13062016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1307
1308 * epiphany-dis.c: Regenerated from latest cpu files.
1309
d8c823c8
MM		 13102016-02-01 Michael McConville <mmcco@mykolab.com>
1311
1312 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1313 test bit.
1314
5bc5ae88
RL		 13152016-01-25 Renlin Li <renlin.li@arm.com>
1316
1317 * arm-dis.c (mapping_symbol_for_insn): New function.
1318 (find_ifthen_state): Call mapping_symbol_for_insn().
1319
0bff6e2d
MW		 13202016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1321
1322 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1323 of MSR UAO immediate operand.
1324
100b4f2e
MR		 13252016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1326
1327 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1328 instruction support.
1329
5c14705f
AM		 13302016-01-17 Alan Modra <amodra@gmail.com>
1331
1332 * configure: Regenerate.
1333
4d82fe66
NC		 13342016-01-14 Nick Clifton <nickc@redhat.com>
1335
1336 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1337 instructions that can support stack pointer operations.
1338 * rl78-decode.c: Regenerate.
1339 * rl78-dis.c: Fix display of stack pointer in MOVW based
1340 instructions.
1341
651657fa
MW		 13422016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1343
1344 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1345 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1346 erxtatus_el1 and erxaddr_el1.
1347
105bde57
MW		 13482016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1349
1350 * arm-dis.c (arm_opcodes): Add "esb".
1351 (thumb_opcodes): Likewise.
1352
afa8d405
PB		 13532016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1354
1355 * ppc-opc.c <xscmpnedp>: Delete.
1356 <xvcmpnedp>: Likewise.
1357 <xvcmpnedp.>: Likewise.
1358 <xvcmpnesp>: Likewise.
1359 <xvcmpnesp.>: Likewise.
1360
83c3256e
AS		 13612016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1362
1363 PR gas/13050
1364 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1365 addition to ISA_A.
1366
6f2750fe
AM		 13672016-01-01 Alan Modra <amodra@gmail.com>
1368
1369 Update year range in copyright notice of all files.
1370
3499769a
AM		 1371For older changes see ChangeLog-2015
1372\f
1373Copyright (C) 2016 Free Software Foundation, Inc.
1374
1375Copying and distribution of this file, with or without modification,
1376are permitted in any medium without royalty provided the copyright
1377notice and this notice are preserved.
1378
1379Local Variables:
1380mode: change-log
1381left-margin: 8
1382fill-column: 74
1383version-control: never
1384End:
GDB Binutils - Deliverables
This page took 0.111776 seconds and 4 git commands to generate.