[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2013-05-09  Andrew Pinski  <apinski@cavium.com>

	* mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
	Add INSN_VIRT and INSN_VIRT64 to mips64r2.
	(parse_mips_dis_option): Handle the virt option.
	(print_insn_args): Handle "+J".
	(print_mips_disassembler_options): Print out message about virt64.
	* mips-opc.c (IVIRT): New define.
	(IVIRT64): New define.
	(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
	tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
	Move rfe to the bottom as it conflicts with tlbgp.

2013-05-09  Alan Modra  <amodra@gmail.com>

	* ppc-opc.c (extract_vlesi): Properly sign extend.
	(extract_vlensi): Likewise.  Comment reason for setting invalid.

2013-05-02  Nick Clifton  <nickc@redhat.com>

	* msp430-dis.c: Add support for MSP430X instructions.

2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>

	* nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
	to "eccinj".

2013-04-17  Wei-chen Wang  <cole945@gmail.com>

	PR binutils/15369
	* cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
	of CGEN_CPU_ENDIAN.
	(hash_insns_list): Likewise.

2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>

	* rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
	warning workaround.

2013-04-08  Jan Beulich <jbeulich@suse.com>

	* i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
	* i386-tbl.h: Re-generate.

2013-04-06  David S. Miller  <davem@davemloft.net>

	* sparc-dis.c (compare_opcodes): When encountering multiple aliases
	of an opcode, prefer the one with F_PREFERRED set.
	* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
	lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
	ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
	mark existing mnenomics as aliases.  Add "cc" suffix to edge
	instructions generating condition codes, mark existing mnenomics
	as aliases.  Add "fp" prefix to VIS compare instructions, mark
	existing mnenomics as aliases.

2013-04-03  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
	destination address by subtracting the operand from the current
	address.
	* v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
	a positive value in the insn.
	(extract_u16_loop): Do not negate the returned value.
	(D16_LOOP): Add V850_INVERSE_PCREL flag.

	(ceilf.sw): Remove duplicate entry.
	(cvtf.hs): New entry.
	(cvtf.sh): Likewise.
	(fmaf.s): Likewise.
	(fmsf.s): Likewise.
	(fnmaf.s): Likewise.
	(fnmsf.s): Likewise.
	(maddf.s): Restrict to E3V5 architectures.
	(msubf.s): Likewise.
	(nmaddf.s): Likewise.
	(nmsubf.s): Likewise.

2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (get_sib): Add the sizeflag argument.  Properly
	check address mode.
	(print_insn): Pass sizeflag to get_sib.

2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>

	PR binutils/15068
	* tic6x-dis.c: Add support for displaying 16-bit insns.

2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>

	PR gas/15095
	* tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
	individual msb and lsb halves in src1 & src2 fields.  Discard the
	src1 (lsb) value and only use src2 (msb), discarding bit 0, to
	follow what Ti SDK does in that case as any value in the src1
	field yields the same output with SDK disassembler.

2013-03-12  Michael Eager <eager@eagercon.com>

	* opcodes/mips-dis.c (print_insn_args): Modify def of reg.

2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>

	* nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.

2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>

	* nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.

2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>

	* nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.

2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* arm-dis.c (arm_opcodes): Add entries for CRC instructions.
	(thumb32_opcodes): Likewise.
	(print_insn_thumb32): Handle 'S' control char.

2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>

	* lm32-desc.c: Regenerate.

2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-reg.tbl (riz): Add RegRex64.
	* i386-tbl.h: Regenerated.

2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
	(aarch64_feature_crc): New static.
	(CRC): New macro.
	(aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
	crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
	* aarch64-asm-2.c: Re-generate.
	* aarch64-dis-2.c: Ditto.
	* aarch64-opc-2.c: Ditto.

2013-02-27  Alan Modra  <amodra@gmail.com>

	* rl78-decode.opc (rl78_decode_opcode): Fix typo.
	* rl78-decode.c: Regenerate.

2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>

	* rl78-decode.opc: Fix encoding of DIVWU insn.
	* rl78-decode.c: Regenerate.

2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/15159
	* i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.

	* i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
	(cpu_flags): Add CpuSMAP.

	* i386-opc.h (CpuSMAP): New.
	(i386_cpu_flags): Add cpusmap.

	* i386-opc.tbl: Add clac and stac.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>

	* metag-dis.c: Initialize outf->bytes_per_chunk to 4
	which also makes the disassembler output be in little
	endian like it should be.

2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
	fields to NULL.
	(aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.

2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>

	* mips-dis.c (is_compressed_mode_p): Only match symbols from the
	section disassembled.

2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* arm-dis.c: Update strht pattern.

2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>

	* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
	single-float.  Disable ll, lld, sc and scd for EE.  Disable the
	trunc.w.s macro for EE.

2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
            Andrew Jenner <andrew@codesourcery.com>

	Based on patches from Altera Corporation.

	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
	nios2-opc.c.
	* Makefile.in: Regenerated.
	* configure.in: Add case for bfd_nios2_arch.
	* configure: Regenerated.
	* disassemble.c (ARCH_nios2): Define.
	(disassembler): Add case for bfd_arch_nios2.
	* nios2-dis.c: New file.
	* nios2-opc.c: New file.

2013-02-04  Alan Modra  <amodra@gmail.com>

	* po/POTFILES.in: Regenerate.
	* rl78-decode.c: Regenerate.
	* rx-decode.c: Regenerate.

2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
	ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
	* aarch64-asm.c (convert_xtl_to_shll): New function.
	(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	calling convert_xtl_to_shll.
	* aarch64-dis.c (convert_shll_to_xtl): New function.
	(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	calling convert_shll_to_xtl.
	* aarch64-gen.c: Update copyright year.
	* aarch64-asm-2.c: Re-generate.
	* aarch64-dis-2.c: Re-generate.
	* aarch64-opc-2.c: Re-generate.

2013-01-24  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c: Add support for e3v5 architecture.
	* v850-opc.c: Likewise.

2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
	* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
	* aarch64-opc.c (operand_general_constraint_met_p): For
	AARCH64_MOD_LSL, move the range check on the shift amount before the
	alignment check; change to call set_sft_amount_out_of_range_error
	instead of set_imm_out_of_range_error.
	* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
	(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
	8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
	SIMD_IMM_SFT.

2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2013-01-15  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
	values.
	* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.

2013-01-14  Will Newton <will.newton@imgtec.com>

	* metag-dis.c (REG_WIDTH): Increase to 64.

2013-01-10  Peter Bergner <bergner@vnet.ibm.com>

	* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
	* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
	XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
	(SH6): Update.
	<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
	"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
	"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
	<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.

2013-01-10  Will Newton <will.newton@imgtec.com>

	* Makefile.am: Add Meta.
	* configure.in: Add Meta.
	* disassemble.c: Add Meta support.
	* metag-dis.c: New file.
	* Makefile.in: Regenerate.
	* configure: Regenerate.

2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>

	* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
	(match_opcode): Rename to cr16_match_opcode.

2013-01-04  Juergen Urban <JuergenUrban@gmx.de>

	* mips-dis.c: Add names for CP0 registers of r5900.
	* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
	instructions sq and lq.
	Add support for MIPS r5900 CPU.
	Add support for 128 bit MMI (Multimedia Instructions).
	Add support for EE instructions (Emotion Engine).
	Disable unsupported floating point instructions (64 bit and
	undefined compare operations).
	Enable instructions of MIPS ISA IV which are supported by r5900.
	Disable 64 bit co processor instructions.
	Disable 64 bit multiplication and division instructions.
	Disable instructions for co-processor 2 and 3, because these are
	not supported (preparation for later VU0 support (Vector Unit)).
	Disable cvt.w.s because this behaves like trunc.w.s and the
	correct execution can't be ensured on r5900.
	Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
	will confuse less developers and compilers.

2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_print_operand): Change to print
	AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
	in comment.
	* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
	from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
	OP_MOV_IMM_WIDE.

2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
	PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.

2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (process_copyright): Update copyright year to 2013.

2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>

	* cr16-dis.c (match_opcode,make_instruction): Remove static
	declaration.
	(dwordU,wordU): Moved typedefs to opcode/cr16.h
	(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.

For older changes see ChangeLog-2012
\f
Copyright (C) 2013 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
b015e599 AP	1	2013-05-09 Andrew Pinski <apinski@cavium.com>
	2
	3	* mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
	4	Add INSN_VIRT and INSN_VIRT64 to mips64r2.
	5	(parse_mips_dis_option): Handle the virt option.
	6	(print_insn_args): Handle "+J".
	7	(print_mips_disassembler_options): Print out message about virt64.
	8	* mips-opc.c (IVIRT): New define.
	9	(IVIRT64): New define.
	10	(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
	11	tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
	12	Move rfe to the bottom as it conflicts with tlbgp.
	13
9f0682fe AM	14	2013-05-09 Alan Modra <amodra@gmail.com>
	15
	16	* ppc-opc.c (extract_vlesi): Properly sign extend.
	17	(extract_vlensi): Likewise. Comment reason for setting invalid.
	18
13761a11 NC	19	2013-05-02 Nick Clifton <nickc@redhat.com>
	20
	21	* msp430-dis.c: Add support for MSP430X instructions.
	22
e3031850 SL	23	2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
	24
	25	* nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
	26	to "eccinj".
	27
17310e56 NC	28	2013-04-17 Wei-chen Wang <cole945@gmail.com>
	29
	30	PR binutils/15369
	31	* cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
	32	of CGEN_CPU_ENDIAN.
	33	(hash_insns_list): Likewise.
	34
731df338 JK	35	2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
	36
	37	* rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
	38	warning workaround.
	39
5f77db52 JB	40	2013-04-08 Jan Beulich <jbeulich@suse.com>
	41
	42	* i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
	43	* i386-tbl.h: Re-generate.
	44
0afd1215 DM	45	2013-04-06 David S. Miller <davem@davemloft.net>
	46
	47	* sparc-dis.c (compare_opcodes): When encountering multiple aliases
	48	of an opcode, prefer the one with F_PREFERRED set.
	49	* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
	50	lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
	51	ops. Make 64-bit VIS logical ops have "d" suffix in their names,
	52	mark existing mnenomics as aliases. Add "cc" suffix to edge
	53	instructions generating condition codes, mark existing mnenomics
	54	as aliases. Add "fp" prefix to VIS compare instructions, mark
	55	existing mnenomics as aliases.
	56
41702d50 NC	57	2013-04-03 Nick Clifton <nickc@redhat.com>
	58
	59	* v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
	60	destination address by subtracting the operand from the current
	61	address.
	62	* v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
	63	a positive value in the insn.
	64	(extract_u16_loop): Do not negate the returned value.
	65	(D16_LOOP): Add V850_INVERSE_PCREL flag.
	66
	67	(ceilf.sw): Remove duplicate entry.
	68	(cvtf.hs): New entry.
	69	(cvtf.sh): Likewise.
	70	(fmaf.s): Likewise.
	71	(fmsf.s): Likewise.
	72	(fnmaf.s): Likewise.
	73	(fnmsf.s): Likewise.
	74	(maddf.s): Restrict to E3V5 architectures.
	75	(msubf.s): Likewise.
	76	(nmaddf.s): Likewise.
	77	(nmsubf.s): Likewise.
	78
55cf16e1 L	79	2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
	80
	81	* i386-dis.c (get_sib): Add the sizeflag argument. Properly
	82	check address mode.
	83	(print_insn): Pass sizeflag to get_sib.
	84
51dcdd4d NC	85	2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
	86
	87	PR binutils/15068
	88	* tic6x-dis.c: Add support for displaying 16-bit insns.
	89
795b8e6b NC	90	2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
	91
	92	PR gas/15095
	93	* tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
	94	individual msb and lsb halves in src1 & src2 fields. Discard the
	95	src1 (lsb) value and only use src2 (msb), discarding bit 0, to
	96	follow what Ti SDK does in that case as any value in the src1
	97	field yields the same output with SDK disassembler.
	98
314d60dd ME	99	2013-03-12 Michael Eager <eager@eagercon.com>
314d60dd ME	100
795b8e6b	101	* opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd	102
dad60f8e SL	103	2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
	104
	105	* nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
	106
f5cb796a SL	107	2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
	108
	109	* nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
	110
21fde85c SL	111	2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
	112
	113	* nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
	114
dd5181d5 KT	115	2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
	116
	117	* arm-dis.c (arm_opcodes): Add entries for CRC instructions.
	118	(thumb32_opcodes): Likewise.
	119	(print_insn_thumb32): Handle 'S' control char.
	120
87a8d6cb NC	121	2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
	122
	123	* lm32-desc.c: Regenerate.
	124
99dce992 L	125	2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
	126
	127	* i386-reg.tbl (riz): Add RegRex64.
	128	* i386-tbl.h: Regenerated.
	129
e60bb1dd YZ	130	2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
	131
	132	* aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
	133	(aarch64_feature_crc): New static.
	134	(CRC): New macro.
	135	(aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
	136	crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
	137	* aarch64-asm-2.c: Re-generate.
	138	* aarch64-dis-2.c: Ditto.
	139	* aarch64-opc-2.c: Ditto.
	140
c7570fcd AM	141	2013-02-27 Alan Modra <amodra@gmail.com>
	142
	143	* rl78-decode.opc (rl78_decode_opcode): Fix typo.
	144	* rl78-decode.c: Regenerate.
	145
151fa98f NC	146	2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
	147
	148	* rl78-decode.opc: Fix encoding of DIVWU insn.
	149	* rl78-decode.c: Regenerate.
	150
5c111e37 L	151	2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
	152
	153	PR gas/15159
	154	* i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
	155
	156	* i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
	157	(cpu_flags): Add CpuSMAP.
	158
	159	* i386-opc.h (CpuSMAP): New.
	160	(i386_cpu_flags): Add cpusmap.
	161
	162	* i386-opc.tbl: Add clac and stac.
	163
	164	* i386-init.h: Regenerated.
	165	* i386-tbl.h: Likewise.
	166
9d1df426 NC	167	2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
	168
	169	* metag-dis.c: Initialize outf->bytes_per_chunk to 4
	170	which also makes the disassembler output be in little
	171	endian like it should be.
	172
a1ccaec9 YZ	173	2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
	174
	175	* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
	176	fields to NULL.
	177	(aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
	178
ef068ef4	179	2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e MR	180
	181	* mips-dis.c (is_compressed_mode_p): Only match symbols from the
	182	section disassembled.
	183
6fe6ded9 RE	184	2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
	185
	186	* arm-dis.c: Update strht pattern.
	187
0aa27725 RS	188	2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
	189
	190	* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
	191	single-float. Disable ll, lld, sc and scd for EE. Disable the
	192	trunc.w.s macro for EE.
	193
36591ba1 SL	194	2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
	195	Andrew Jenner <andrew@codesourcery.com>
	196
	197	Based on patches from Altera Corporation.
	198
	199	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
	200	nios2-opc.c.
	201	* Makefile.in: Regenerated.
	202	* configure.in: Add case for bfd_nios2_arch.
	203	* configure: Regenerated.
	204	* disassemble.c (ARCH_nios2): Define.
	205	(disassembler): Add case for bfd_arch_nios2.
	206	* nios2-dis.c: New file.
	207	* nios2-opc.c: New file.
	208
545093a4 AM	209	2013-02-04 Alan Modra <amodra@gmail.com>
	210
	211	* po/POTFILES.in: Regenerate.
	212	* rl78-decode.c: Regenerate.
	213	* rx-decode.c: Regenerate.
	214
e30181a5 YZ	215	2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
	216
	217	* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
	218	ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
	219	* aarch64-asm.c (convert_xtl_to_shll): New function.
	220	(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	221	calling convert_xtl_to_shll.
	222	* aarch64-dis.c (convert_shll_to_xtl): New function.
	223	(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	224	calling convert_shll_to_xtl.
	225	* aarch64-gen.c: Update copyright year.
	226	* aarch64-asm-2.c: Re-generate.
	227	* aarch64-dis-2.c: Re-generate.
	228	* aarch64-opc-2.c: Re-generate.
	229
78c8d46c NC	230	2013-01-24 Nick Clifton <nickc@redhat.com>
	231
	232	* v850-dis.c: Add support for e3v5 architecture.
	233	* v850-opc.c: Likewise.
	234
f5555712 YZ	235	2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
	236
	237	* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
	238	* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
	239	* aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c	240	AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712 YZ	241	alignment check; change to call set_sft_amount_out_of_range_error
	242	instead of set_imm_out_of_range_error.
	243	* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
	244	(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
	245	8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
	246	SIMD_IMM_SFT.
	247
2f81ff92 L	248	2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
	249
	250	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
	251
	252	* i386-init.h: Regenerated.
	253	* i386-tbl.h: Likewise.
	254
dd42f060 NC	255	2013-01-15 Nick Clifton <nickc@redhat.com>
	256
	257	* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
	258	values.
	259	* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
	260
a4533ed8 NC	261	2013-01-14 Will Newton <will.newton@imgtec.com>
	262
	263	* metag-dis.c (REG_WIDTH): Increase to 64.
	264
5817ffd1 PB	265	2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
	266
	267	* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
	268	* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
	269	XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
	270	(SH6): Update.
	271	<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
	272	"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
	273	"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
	274	<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
	275
a3c62988 NC	276	2013-01-10 Will Newton <will.newton@imgtec.com>
	277
	278	* Makefile.am: Add Meta.
	279	* configure.in: Add Meta.
	280	* disassemble.c: Add Meta support.
	281	* metag-dis.c: New file.
	282	* Makefile.in: Regenerate.
	283	* configure: Regenerate.
	284
73335eae NC	285	2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
	286
	287	* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
	288	(match_opcode): Rename to cr16_match_opcode.
	289
e407c74b NC	290	2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
	291
	292	* mips-dis.c: Add names for CP0 registers of r5900.
	293	* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
	294	instructions sq and lq.
	295	Add support for MIPS r5900 CPU.
	296	Add support for 128 bit MMI (Multimedia Instructions).
	297	Add support for EE instructions (Emotion Engine).
	298	Disable unsupported floating point instructions (64 bit and
	299	undefined compare operations).
	300	Enable instructions of MIPS ISA IV which are supported by r5900.
	301	Disable 64 bit co processor instructions.
	302	Disable 64 bit multiplication and division instructions.
	303	Disable instructions for co-processor 2 and 3, because these are
	304	not supported (preparation for later VU0 support (Vector Unit)).
	305	Disable cvt.w.s because this behaves like trunc.w.s and the
	306	correct execution can't be ensured on r5900.
	307	Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
	308	will confuse less developers and compilers.
	309
a32c3ff8 NC	310	2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
a32c3ff8 NC	311
fb098a1e YZ	312	* aarch64-opc.c (aarch64_print_operand): Change to print
	313	AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
	314	in comment.
	315	* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
	316	from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
	317	OP_MOV_IMM_WIDE.
	318
	319	2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
	320
	321	* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
	322	PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8	323
62658407 L	324	2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
	325
	326	* i386-gen.c (process_copyright): Update copyright year to 2013.
	327
bab4becb	328	2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7	329
bab4becb NC	330	* cr16-dis.c (match_opcode,make_instruction): Remove static
	331	declaration.
	332	(dwordU,wordU): Moved typedefs to opcode/cr16.h
	333	(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7	334
bab4becb	335	For older changes see ChangeLog-2012
252b5132	336	\f
bab4becb	337	Copyright (C) 2013 Free Software Foundation, Inc.
752937aa NC	338
	339	Copying and distribution of this file, with or without modification,
	340	are permitted in any medium without royalty provided the copyright
	341	notice and this notice are preserved.
	342
252b5132	343	Local Variables:
2f6d2f85 NC	344	mode: change-log
	345	left-margin: 8
	346	fill-column: 74
252b5132 RH	347	version-control: never
252b5132 RH	348	End: