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2005-06-15 Dave Brolley <brolley@redhat.com>
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
6b5d3a4d
ZW		 12005-06-08 Zack Weinberg <zack@codesourcery.com>
2
3 * arm-opc.h: Delete; fold contents into ...
4 * arm-dis.c: ... here. Move includes of internal COFF headers
5 next to includes of internal ELF headers.
6 (streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused.
7 (struct arm_opcode): Rename struct opcode32. Make 'assembler' const.
8 (struct thumb_opcode): Rename struct opcode16. Make 'assembler' const.
9 (arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames)
10 (iwmmxt_wwnames, iwmmxt_wwssnames):
11 Make const.
12 (regnames): Remove iWMMXt coprocessor register sets.
13 (iwmmxt_regnames, iwmmxt_cregnames): New statics.
14 (get_arm_regnames): Adjust fourth argument to match above changes.
15 (set_iwmmxt_regnames): Delete.
16 (print_insn_arm): Constify 'c'. Use ISO syntax for function
17 pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames
18 and iwmmxt_cregnames, not set_iwmmxt_regnames.
19 (print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use
20 ISO syntax for function pointer calls.
21
4a5329c6
ZW		 222005-06-07 Zack Weinberg <zack@codesourcery.com>
23
24 * arm-dis.c: Split up the comments describing the format codes, so
25 that the ARM and 16-bit Thumb opcode tables each have comments
26 preceding them that describe all the codes, and only the codes,
27 valid in those tables. (32-bit Thumb table is already like this.)
28 Reorder the lists in all three comments to match the order in
29 which the codes are implemented.
30 Remove all forward declarations of static functions. Convert all
31 function definitions to ISO C format.
32 (print_insn_arm, print_insn_thumb16, print_insn_thumb32):
33 Return nothing.
34 (print_insn_thumb16): Remove unused case 'I'.
35 (print_insn): Update for changed calling convention of subroutines.
36
3d456fa1
JB		 372005-05-25 Jan Beulich <jbeulich@novell.com>
38
39 * i386-dis.c (OP_E): In Intel mode, display 32-bit displacements in
40 hex (but retain it being displayed as signed). Remove redundant
41 checks. Add handling of displacements for 16-bit addressing in Intel
42 mode.
43
2888cb7a
JB		 442005-05-25 Jan Beulich <jbeulich@novell.com>
45
46 * i386-dis.c (prefix_name): Remove pointless mode_64bit check.
47 (OP_E): Remove redundant REX_EXTZ handling. Remove pointless
48 masking of 'rm' in 16-bit memory address handling.
49
1ed8e1e4
AM		 502005-05-19 Anton Blanchard <anton@samba.org>
51
52 * ppc-dis.c (powerpc_dialect): Handle "-Mpower5".
53 (print_ppc_disassembler_options): Document it.
54 * ppc-opc.c (SVC_LEV): Define.
55 (LEV): Allow optional operand.
56 (POWER5): Define.
57 (powerpc_opcodes): Extend "sc". Adjust "svc" and "svcl". Add
58 "hrfid", "popcntb", "fsqrtes", "fsqrtes.", "fre" and "fre.".
59
49cc2e69
KC		 602005-05-19 Kelley Cook <kcook@gcc.gnu.org>
61
62 * Makefile.in: Regenerate.
63
c19d1205
ZW		 642005-05-17 Zack Weinberg <zack@codesourcery.com>
65
66 * arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
67 instructions. Adjust disassembly of some opcodes to match
68 unified syntax.
69 (thumb32_opcodes): New table.
70 (print_insn_thumb): Rename print_insn_thumb16; don't handle
71 two-halfword branches here.
72 (print_insn_thumb32): New function.
73 (print_insn): Choose among print_insn_arm, print_insn_thumb16,
74 and print_insn_thumb32. Be consistent about order of
75 halfwords when printing 32-bit instructions.
76
003519a7
L		 772005-05-07 H.J. Lu <hongjiu.lu@intel.com>
78
79 PR 843
80 * i386-dis.c (branch_v_mode): New.
81 (indirEv): Use branch_v_mode instead of v_mode.
82 (OP_E): Handle branch_v_mode.
83
920a34a7
L		 842005-05-07 H.J. Lu <hongjiu.lu@intel.com>
85
86 * d10v-dis.c (dis_2_short): Support 64bit host.
87
5de773c1
NC		 882005-05-07 Nick Clifton <nickc@redhat.com>
89
90 * po/nl.po: Updated translation.
91
f4321104
NC		 922005-05-07 Nick Clifton <nickc@redhat.com>
93
94 * Update the address and phone number of the FSF organization in
95 the GPL notices in the following files:
96 a29k-dis.c, aclocal.m4, alpha-dis.c, alpha-opc.c, arc-dis.c,
97 arc-dis.h, arc-ext.c, arc-ext.h, arc-opc.c, arm-dis.c, arm-opc.h,
98 avr-dis.c, cgen-asm.c, cgen-asm.in, cgen-dis.c, cgen-dis.in,
99 cgen-ibld.in, cgen-opc.c, cgen.sh, cris-dis.c, cris-opc.c,
100 crx-dis.c, crx-opc.c, d10v-dis.c, d10v-opc.c, d30v-dis.c,
101 d30v-opc.c, dis-buf.c, dis-init.c, disassemble.c, dlx-dis.c,
102 fr30-asm.c, fr30-desc.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c,
103 fr30-opc.c, fr30-opc.h, frv-asm.c, frv-desc.c, frv-desc.h,
104 frv-dis.c, frv-ibld.c, frv-opc.c, frv-opc.h, h8300-dis.c,
105 h8500-dis.c, h8500-opc.h, hppa-dis.c, i370-dis.c, i370-opc.c,
106 i386-dis.c, i860-dis.c, i960-dis.c, ia64-asmtab.h, ia64-dis.c,
107 ia64-gen.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-d.c,
108 ia64-opc-f.c, ia64-opc-i.c, ia64-opc-m.c, ia64-opc-x.c,
109 ia64-opc.c, ia64-opc.h, ip2k-asm.c, ip2k-desc.c, ip2k-desc.h,
110 ip2k-dis.c, ip2k-ibld.c, ip2k-opc.c, ip2k-opc.h, iq2000-asm.c,
111 iq2000-desc.c, iq2000-desc.h, iq2000-dis.c, iq2000-ibld.c,
112 iq2000-opc.c, iq2000-opc.h, m10200-dis.c, m10200-opc.c,
113 m10300-dis.c, m10300-opc.c, m32r-asm.c, m32r-desc.c, m32r-desc.h,
114 m32r-dis.c, m32r-ibld.c, m32r-opc.c, m32r-opc.h, m32r-opinst.c,
115 m68hc11-dis.c, m68hc11-opc.c, m68k-dis.c, m68k-opc.c, m88k-dis.c,
116 maxq-dis.c, mcore-dis.c, mcore-opc.h, mips-dis.c, mips-opc.c,
117 mips16-opc.c, mmix-dis.c, mmix-opc.c, msp430-dis.c, ns32k-dis.c,
118 openrisc-asm.c, openrisc-desc.c, openrisc-desc.h, openrisc-dis.c,
119 openrisc-ibld.c, openrisc-opc.c, openrisc-opc.h, opintl.h,
120 or32-dis.c, or32-opc.c, pdp11-dis.c, pdp11-opc.c, pj-dis.c,
121 pj-opc.c, ppc-dis.c, ppc-opc.c, s390-dis.c, s390-mkopc.c,
122 s390-opc.c, sh-dis.c, sh-opc.h, sh64-dis.c, sh64-opc.c,
123 sh64-opc.h, sparc-dis.c, sparc-opc.c, sysdep.h, tic30-dis.c,
124 tic4x-dis.c, tic54x-dis.c, tic54x-opc.c, tic80-dis.c, tic80-opc.c,
125 v850-dis.c, v850-opc.c, vax-dis.c, w65-dis.c, w65-opc.h,
126 xstormy16-asm.c, xstormy16-desc.c, xstormy16-desc.h,
127 xstormy16-dis.c, xstormy16-ibld.c, xstormy16-opc.c,
128 xstormy16-opc.h, xtensa-dis.c, z8k-dis.c, z8kgen.c
129
10b076a2
JW		 1302005-05-05 James E Wilson <wilson@specifixinc.com>
131
132 * ia64-opc.c: Include sysdep.h before libiberty.h.
133
022716b6
NC		 1342005-05-05 Nick Clifton <nickc@redhat.com>
135
136 * configure.in (ALL_LINGUAS): Add vi.
137 * configure: Regenerate.
138 * po/vi.po: New.
139
db5152b4
JG		 1402005-04-26 Jerome Guitton <guitton@gnat.com>
141
142 * configure.in: Fix the check for basename declaration.
143 * configure: Regenerate.
144
eed0d89a
AM		 1452005-04-19 Alan Modra <amodra@bigpond.net.au>
146
147 * ppc-opc.c (RTO): Define.
148 (powerpc_opcodes <tlbsx, tlbsx., tlbre>): Combine PPC403 and BOOKE
149 entries to suit PPC440.
150
791fe849
MK		 1512005-04-18 Mark Kettenis <kettenis@gnu.org>
152
153 * i386-dis.c: Insert hyphens into selected VIA PadLock extensions.
154 Add xcrypt-ctr.
155
ffe58f7c
NC		 1562005-04-14 Nick Clifton <nickc@redhat.com>
157
158 * po/fi.po: New translation: Finnish.
159 * configure.in (ALL_LINGUAS): Add fi.
160 * configure: Regenerate.
161
9e9b66a9
AM		 1622005-04-14 Alan Modra <amodra@bigpond.net.au>
163
164 * Makefile.am (NO_WERROR): Define.
165 * configure.in: Invoke AM_BINUTILS_WARNINGS.
166 * Makefile.in: Regenerate.
167 * aclocal.m4: Regenerate.
168 * configure: Regenerate.
169
9494d739
NC		 1702005-04-04 Nick Clifton <nickc@redhat.com>
171
172 * fr30-asm.c: Regenerate.
173 * frv-asm.c: Regenerate.
174 * iq2000-asm.c: Regenerate.
175 * m32r-asm.c: Regenerate.
176 * openrisc-asm.c: Regenerate.
177
6128c599
JB		 1782005-04-01 Jan Beulich <jbeulich@novell.com>
179
180 * i386-dis.c (PNI_Fixup): Neither mwait nor monitor have any
181 visible operands in Intel mode. The first operand of monitor is
182 %rax in 64-bit mode.
183
373ff435
JB		 1842005-04-01 Jan Beulich <jbeulich@novell.com>
185
186 * i386-dis.c (INVLPG_Fixup): Decode rdtscp; change code to allow for
187 easier future additions.
188
4bd60896
JG		 1892005-03-31 Jerome Guitton <guitton@gnat.com>
190
191 * configure.in: Check for basename.
192 * configure: Regenerate.
193 * config.in: Ditto.
194
4cc91dba
L		 1952005-03-29 H.J. Lu <hongjiu.lu@intel.com>
196
197 * i386-dis.c (SEG_Fixup): New.
198 (Sv): New.
199 (dis386): Use "Sv" for 0x8c and 0x8e.
200
ec72cfe5
NC		 2012005-03-21 Jan-Benedict Glaw <jbglaw@lug-owl.de>
202 Nick Clifton <nickc@redhat.com>
c19d1205 203
ec72cfe5
NC		 204 * vax-dis.c: (entry_addr): New varible: An array of user supplied
205 function entry mask addresses.
206 (entry_addr_occupied_slots): New variable: The number of occupied
c19d1205 207 elements in entry_addr.
ec72cfe5
NC		 208 (entry_addr_total_slots): New variable: The total number of
209 elements in entry_addr.
210 (parse_disassembler_options): New function. Fills in the entry_addr
211 array.
212 (free_entry_array): New function. Release the memory used by the
213 entry addr array. Suppressed because there is no way to call it.
214 (is_function_entry): Check if a given address is a function's
215 start address by looking at supplied entry mask addresses and
216 symbol information, if available.
217 (print_insn_vax): Use parse_disassembler_options and is_function_entry.
218
85064c79
L		 2192005-03-23 H.J. Lu <hongjiu.lu@intel.com>
220
221 * cris-dis.c (print_with_operands): Use ~31L for long instead
222 of ~31.
223
de7141c7
L		 2242005-03-20 H.J. Lu <hongjiu.lu@intel.com>
225
226 * mmix-opc.c (O): Revert the last change.
227 (Z): Likewise.
228
e493ab45
L		 2292005-03-19 H.J. Lu <hongjiu.lu@intel.com>
230
231 * mmix-opc.c (O): Use 24UL instead of 24 for unsigned long.
232 (Z): Likewise.
233
d8d7c459
HPN		 2342005-03-19 Hans-Peter Nilsson <hp@bitrange.com>
235
236 * mmix-opc.c (O, Z): Force expression as unsigned long.
237
ebdb0383
NC		 2382005-03-18 Nick Clifton <nickc@redhat.com>
239
240 * ip2k-asm.c: Regenerate.
241 * op/opcodes.pot: Regenerate.
242
1ad12f97
NC		 2432005-03-16 Nick Clifton <nickc@redhat.com>
244 Ben Elliston <bje@au.ibm.com>
245
569acd2c 246 * configure.in (werror): New switch: Add -Werror to the
1ad12f97 247 compiler command line. Enabled by default. Disable via
569acd2c 248 --disable-werror.
1ad12f97
NC		 249 * configure: Regenerate.
250
4eb30afc
AM		 2512005-03-16 Alan Modra <amodra@bigpond.net.au>
252
253 * ppc-dis.c (powerpc_dialect): Don't set PPC_OPCODE_ALTIVEC when
254 BOOKE.
255
ea8409f7
AM		 2562005-03-15 Alan Modra <amodra@bigpond.net.au>
257
729ae8d2
AM		 258 * po/es.po: Commit new Spanish translation.
259
ea8409f7
AM		 260 * po/fr.po: Commit new French translation.
261
4f495e61
NC		 2622005-03-14 Jan-Benedict Glaw <jbglaw@lug-owl.de>
263
264 * vax-dis.c: Fix spelling error
265 (print_insn_vax): Use ".word 0x0012 # Entry mask: r1 r2 >" instead
266 of just "Entry mask: < r1 ... >"
267
0a003adc
ZW		 2682005-03-12 Zack Weinberg <zack@codesourcery.com>
269
270 * arm-dis.c (arm_opcodes): Document %E and %V.
271 Add entries for v6T2 ARM instructions:
272 bfc bfi mls strht ldrht ldrsht ldrsbt movw movt rbit ubfx sbfx.
273 (print_insn_arm): Add support for %E and %V.
885fc257 274 (thumb_opcodes): Add ARMv6K instructions nop, sev, wfe, wfi, yield.
0a003adc 275
da99ee72
AM		 2762005-03-10 Jeff Baker <jbaker@qnx.com>
277 Alan Modra <amodra@bigpond.net.au>
278
279 * ppc-opc.c (insert_sprg, extract_sprg): New Functions.
280 (powerpc_operands <SPRG>): Call the above. Bit field is 5 bits.
281 (SPRG_MASK): Delete.
282 (XSPRG_MASK): Mask off extra bits now part of sprg field.
0a003adc 283 (powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask. Move
da99ee72
AM		 284 mfsprg4..7 after msprg and consolidate.
285
220abb21
AM		 2862005-03-09 Jan-Benedict Glaw <jbglaw@lug-owl.de>
287
288 * vax-dis.c (entry_mask_bit): New array.
289 (print_insn_vax): Decode function entry mask.
290
0e06657a
AH		 2912005-03-07 Aldy Hernandez <aldyh@redhat.com>
292
293 * ppc-opc.c (powerpc_opcodes): Fix encoding of efscfd.
294
06647dfd
AM		 2952005-03-05 Alan Modra <amodra@bigpond.net.au>
296
297 * po/opcodes.pot: Regenerate.
298
82b829a7
RR		 2992005-03-03 Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
300
220abb21 301 * arc-dis.c (a4_decoding_class): New enum.
06647dfd
AM		 302 (dsmOneArcInst): Use the enum values for the decoding class.
303 Remove redundant case in the switch for decodingClass value 11.
82b829a7 304
c4a530c5
JB		 3052005-03-02 Jan Beulich <jbeulich@novell.com>
306
307 * i386-dis.c (print_insn): Suppress lock prefix printing for cr8...15
308 accesses.
309 (OP_C): Consider lock prefix in non-64-bit modes.
310
47d8304e
AM		 3112005-02-24 Alan Modra <amodra@bigpond.net.au>
312
313 * cris-dis.c (format_hex): Remove ineffective warning fix.
314 * crx-dis.c (make_instruction): Warning fix.
315 * frv-asm.c: Regenerate.
316
ec36c4a4
NC		 3172005-02-23 Nick Clifton <nickc@redhat.com>
318
33b71eeb
NC		 319 * cgen-dis.in: Use bfd_byte for buffers that are passed to
320 read_memory.
06647dfd 321
33b71eeb 322 * ia64-opc.c (locate_opcode_ent): Initialise opval array.
06647dfd 323
ec36c4a4
NC		 324 * crx-dis.c (make_instruction): Move argument structure into inner
325 scope and ensure that all of its fields are initialised before
326 they are used.
327
33b71eeb
NC		 328 * fr30-asm.c: Regenerate.
329 * fr30-dis.c: Regenerate.
330 * frv-asm.c: Regenerate.
331 * frv-dis.c: Regenerate.
332 * ip2k-asm.c: Regenerate.
333 * ip2k-dis.c: Regenerate.
334 * iq2000-asm.c: Regenerate.
335 * iq2000-dis.c: Regenerate.
336 * m32r-asm.c: Regenerate.
337 * m32r-dis.c: Regenerate.
338 * openrisc-asm.c: Regenerate.
339 * openrisc-dis.c: Regenerate.
340 * xstormy16-asm.c: Regenerate.
341 * xstormy16-dis.c: Regenerate.
342
53c9ebc5
AM		 3432005-02-22 Alan Modra <amodra@bigpond.net.au>
344
345 * arc-ext.c: Warning fixes.
346 * arc-ext.h: Likewise.
347 * cgen-opc.c: Likewise.
348 * ia64-gen.c: Likewise.
349 * maxq-dis.c: Likewise.
350 * ns32k-dis.c: Likewise.
351 * w65-dis.c: Likewise.
352 * ia64-asmtab.c: Regenerate.
353
610ad19b
AM		 3542005-02-22 Alan Modra <amodra@bigpond.net.au>
355
356 * fr30-desc.c: Regenerate.
357 * fr30-desc.h: Regenerate.
358 * fr30-opc.c: Regenerate.
359 * fr30-opc.h: Regenerate.
360 * frv-desc.c: Regenerate.
361 * frv-desc.h: Regenerate.
362 * frv-opc.c: Regenerate.
363 * frv-opc.h: Regenerate.
364 * ip2k-desc.c: Regenerate.
365 * ip2k-desc.h: Regenerate.
366 * ip2k-opc.c: Regenerate.
367 * ip2k-opc.h: Regenerate.
368 * iq2000-desc.c: Regenerate.
369 * iq2000-desc.h: Regenerate.
370 * iq2000-opc.c: Regenerate.
371 * iq2000-opc.h: Regenerate.
372 * m32r-desc.c: Regenerate.
373 * m32r-desc.h: Regenerate.
374 * m32r-opc.c: Regenerate.
375 * m32r-opc.h: Regenerate.
376 * m32r-opinst.c: Regenerate.
377 * openrisc-desc.c: Regenerate.
378 * openrisc-desc.h: Regenerate.
379 * openrisc-opc.c: Regenerate.
380 * openrisc-opc.h: Regenerate.
381 * xstormy16-desc.c: Regenerate.
382 * xstormy16-desc.h: Regenerate.
383 * xstormy16-opc.c: Regenerate.
384 * xstormy16-opc.h: Regenerate.
385
db9db6f2
AM		 3862005-02-21 Alan Modra <amodra@bigpond.net.au>
387
388 * Makefile.am: Run "make dep-am"
389 * Makefile.in: Regenerate.
390
bf143b25
NC		 3912005-02-15 Nick Clifton <nickc@redhat.com>
392
393 * cgen-dis.in (print_address): Add an ATTRIBUTE_UNUSED to prevent
394 compile time warnings.
395 (print_keyword): Likewise.
396 (default_print_insn): Likewise.
397
398 * fr30-desc.c: Regenerated.
399 * fr30-desc.h: Regenerated.
400 * fr30-dis.c: Regenerated.
401 * fr30-opc.c: Regenerated.
402 * fr30-opc.h: Regenerated.
403 * frv-desc.c: Regenerated.
404 * frv-dis.c: Regenerated.
405 * frv-opc.c: Regenerated.
406 * ip2k-asm.c: Regenerated.
407 * ip2k-desc.c: Regenerated.
408 * ip2k-desc.h: Regenerated.
409 * ip2k-dis.c: Regenerated.
410 * ip2k-opc.c: Regenerated.
411 * ip2k-opc.h: Regenerated.
412 * iq2000-desc.c: Regenerated.
413 * iq2000-dis.c: Regenerated.
414 * iq2000-opc.c: Regenerated.
415 * m32r-asm.c: Regenerated.
416 * m32r-desc.c: Regenerated.
417 * m32r-desc.h: Regenerated.
418 * m32r-dis.c: Regenerated.
419 * m32r-opc.c: Regenerated.
420 * m32r-opc.h: Regenerated.
421 * m32r-opinst.c: Regenerated.
422 * openrisc-desc.c: Regenerated.
423 * openrisc-desc.h: Regenerated.
424 * openrisc-dis.c: Regenerated.
425 * openrisc-opc.c: Regenerated.
426 * openrisc-opc.h: Regenerated.
427 * xstormy16-desc.c: Regenerated.
428 * xstormy16-desc.h: Regenerated.
429 * xstormy16-dis.c: Regenerated.
430 * xstormy16-opc.c: Regenerated.
431 * xstormy16-opc.h: Regenerated.
432
d6098898
L		 4332005-02-14 H.J. Lu <hongjiu.lu@intel.com>
434
435 * dis-buf.c (perror_memory): Use sprintf_vma to print out
436 address.
437
5a84f3e0
NC		 4382005-02-11 Nick Clifton <nickc@redhat.com>
439
bc18c937
NC		 440 * iq2000-asm.c: Regenerate.
441
5a84f3e0
NC		 442 * frv-dis.c: Regenerate.
443
0a40490e
JB		 4442005-02-07 Jim Blandy <jimb@redhat.com>
445
446 * Makefile.am (CGEN): Load guile.scm before calling the main
447 application script.
448 * Makefile.in: Regenerated.
449 * cgen.sh: Be prepared for the 'cgen' argument to contain spaces.
450 Simply pass the cgen-opc.scm path to ${cgen} as its first
451 argument; ${cgen} itself now contains the '-s', or whatever is
452 appropriate for the Scheme being used.
453
c46f8c51
AC		 4542005-01-31 Andrew Cagney <cagney@gnu.org>
455
456 * configure: Regenerate to track ../gettext.m4.
457
60b9a617
JB		 4582005-01-31 Jan Beulich <jbeulich@novell.com>
459
460 * ia64-gen.c (NELEMS): Define.
461 (shrink): Generate alias with missing second predicate register when
462 opcode has two outputs and these are both predicates.
463 * ia64-opc-i.c (FULL17): Define.
464 (ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
465 here to generate output template.
466 (TBITCM, TNATCM): Undefine after use.
467 * ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
468 first input. Add ld16 aliases without ar.csd as second output. Add
469 st16 aliases without ar.csd as second input. Add cmpxchg aliases
470 without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
471 ar.ccv as third/fourth inputs. Consolidate through...
472 (CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
473 CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
474 * ia64-asmtab.c: Regenerate.
475
a53bf506
AC		 4762005-01-27 Andrew Cagney <cagney@gnu.org>
477
478 * configure: Regenerate to track ../gettext.m4 change.
479
90219bd0
AO		 4802005-01-25 Alexandre Oliva <aoliva@redhat.com>
481
482 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
483 * frv-asm.c: Rebuilt.
484 * frv-desc.c: Rebuilt.
485 * frv-desc.h: Rebuilt.
486 * frv-dis.c: Rebuilt.
487 * frv-ibld.c: Rebuilt.
488 * frv-opc.c: Rebuilt.
489 * frv-opc.h: Rebuilt.
490
45181ed1
AC		 4912005-01-24 Andrew Cagney <cagney@gnu.org>
492
493 * configure: Regenerate, ../gettext.m4 was updated.
494
9e836e3d
FF		 4952005-01-21 Fred Fish <fnf@specifixinc.com>
496
497 * mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS.
498 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
499 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
500 * mips-dis.c: Ditto.
501
5e8cb021
AM		 5022005-01-20 Alan Modra <amodra@bigpond.net.au>
503
504 * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
505
986e18a5
FF		 5062005-01-19 Fred Fish <fnf@specifixinc.com>
507
508 * mips-dis.c (no_aliases): New disassembly option flag.
509 (set_default_mips_dis_options): Init no_aliases to zero.
510 (parse_mips_dis_option): Handle no-aliases option.
511 (print_insn_mips): Ignore table entries that are aliases
512 if no_aliases is set.
513 (print_insn_mips16): Ditto.
514 * mips-opc.c (mips_builtin_opcodes): Add initializer column for
515 new pinfo2 member and add INSN_ALIAS initializers as needed. Also
516 move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
517 * mips16-opc.c (mips16_opcodes): Ditto.
518
e38bc3b5
NC		 5192005-01-17 Andrew Stubbs <andrew.stubbs@st.com>
520
521 * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
522 (inheritance diagram): Add missing edge.
523 (arch_sh1_up): Rename arch_sh_up to match external name to make life
524 easier for the testsuite.
525 (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
526 (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
610ad19b 527 (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
e38bc3b5
NC		 528 arch_sh2a_or_sh4_up child.
529 (sh_table): Do renaming as above.
530 Correct comment for ldc.l for gas testsuite to read.
531 Remove rogue mul.l from sh1 (duplicate of the one for sh2).
532 Correct comments for movy.w and movy.l for gas testsuite to read.
533 Correct comments for fmov.d and fmov.s for gas testsuite to read.
534
9df48ba9
L		 5352005-01-12 H.J. Lu <hongjiu.lu@intel.com>
536
537 * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
538
2033b4b9
L		 5392005-01-12 H.J. Lu <hongjiu.lu@intel.com>
540
541 * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
542
0bcb06d2
AS		 5432005-01-10 Andreas Schwab <schwab@suse.de>
544
545 * disassemble.c (disassemble_init_for_target) <case
546 bfd_arch_ia64>: Set skip_zeroes to 16.
547 <case bfd_arch_tic4x>: Set skip_zeroes to 32.
548
47add74d
TL		 5492004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
550
551 * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
552
246f4c05
SS		 5532004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
554
555 * avr-dis.c: Prettyprint. Added printing of symbol names in all
556 memory references. Convert avr_operand() to C90 formatting.
557
0e1200e5
TL		 5582004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
559
560 * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
561
89a649f7
TL		 5622004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
563
564 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
565 (no_op_insn): Initialize array with instructions that have no
566 operands.
567 * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
568
6255809c
RE		 5692004-11-29 Richard Earnshaw <rearnsha@arm.com>
570
571 * arm-dis.c: Correct top-level comment.
572
2fbad815
RE		 5732004-11-27 Richard Earnshaw <rearnsha@arm.com>
574
575 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
576 architecuture defining the insn.
577 (arm_opcodes, thumb_opcodes): Delete. Move to ...
6b8725b9
RE		 578 * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
579 field.
2fbad815
RE		 580 Also include opcode/arm.h.
581 * Makefile.am (arm-dis.lo): Update dependency list.
582 * Makefile.in: Regenerate.
583
d81acc42
NC		 5842004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
585
586 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
587 reflect the change to the short immediate syntax.
588
ca4f2377
AM		 5892004-11-19 Alan Modra <amodra@bigpond.net.au>
590
5da8bf1b
AM		 591 * or32-opc.c (debug): Warning fix.
592 * po/POTFILES.in: Regenerate.
593
ca4f2377
AM		 594 * maxq-dis.c: Formatting.
595 (print_insn): Warning fix.
596
b7693d02
DJ		 5972004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
598
599 * arm-dis.c (WORD_ADDRESS): Define.
600 (print_insn): Use it. Correct big-endian end-of-section handling.
601
300dac7e
NC		 6022004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
603 Vineet Sharma <vineets@noida.hcltech.com>
604
605 * maxq-dis.c: New file.
606 * disassemble.c (ARCH_maxq): Define.
610ad19b 607 (disassembler): Add 'print_insn_maxq_little' for handling maxq
300dac7e
NC		 608 instructions..
609 * configure.in: Add case for bfd_maxq_arch.
610 * configure: Regenerate.
611 * Makefile.am: Add support for maxq-dis.c
612 * Makefile.in: Regenerate.
613 * aclocal.m4: Regenerate.
614
42048ee7
TL		 6152004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
616
617 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
618 mode.
619 * crx-dis.c: Likewise.
620
bd21e58e
HPN		 6212004-11-04 Hans-Peter Nilsson <hp@axis.com>
622
623 Generally, handle CRISv32.
624 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
625 (struct cris_disasm_data): New type.
626 (format_reg, format_hex, cris_constraint, print_flags)
627 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
628 callers changed.
629 (format_sup_reg, print_insn_crisv32_with_register_prefix)
630 (print_insn_crisv32_without_register_prefix)
631 (print_insn_crisv10_v32_with_register_prefix)
632 (print_insn_crisv10_v32_without_register_prefix)
633 (cris_parse_disassembler_options): New functions.
634 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
635 parameter. All callers changed.
636 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
637 failure.
638 (cris_constraint) <case 'Y', 'U'>: New cases.
639 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
640 for constraint 'n'.
641 (print_with_operands) <case 'Y'>: New case.
642 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
643 <case 'N', 'Y', 'Q'>: New cases.
644 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
645 (print_insn_cris_with_register_prefix)
646 (print_insn_cris_without_register_prefix): Call
647 cris_parse_disassembler_options.
648 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
649 for CRISv32 and the size of immediate operands. New v32-only
650 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
651 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
652 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
653 Change brp to be v3..v10.
654 (cris_support_regs): New vector.
655 (cris_opcodes): Update head comment. New format characters '[',
656 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
657 Add new opcodes for v32 and adjust existing opcodes to accommodate
658 differences to earlier variants.
659 (cris_cond15s): New vector.
660
9306ca4a
JB		 6612004-11-04 Jan Beulich <jbeulich@novell.com>
662
663 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
664 (indirEb): Remove.
665 (Mp): Use f_mode rather than none at all.
666 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
667 replaces what previously was x_mode; x_mode now means 128-bit SSE
668 operands.
669 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
670 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
671 pinsrw's second operand is Edqw.
672 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
673 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
674 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
675 mode when an operand size override is present or always suffixing.
676 More instructions will need to be added to this group.
677 (putop): Handle new macro chars 'C' (short/long suffix selector),
678 'I' (Intel mode override for following macro char), and 'J' (for
679 adding the 'l' prefix to far branches in AT&T mode). When an
680 alternative was specified in the template, honor macro character when
681 specified for Intel mode.
682 (OP_E): Handle new *_mode values. Correct pointer specifications for
683 memory operands. Consolidate output of index register.
684 (OP_G): Handle new *_mode values.
685 (OP_I): Handle const_1_mode.
686 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
687 respective opcode prefix bits have been consumed.
688 (OP_EM, OP_EX): Provide some default handling for generating pointer
689 specifications.
690
f39c96a9
TL		 6912004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
692
693 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
694 COP_INST macro.
695
812337be
TL		 6962004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
697
698 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
699 (getregliststring): Support HI/LO and user registers.
610ad19b 700 * crx-opc.c (crx_instruction): Update data structure according to the
812337be
TL		 701 rearrangement done in CRX opcode header file.
702 (crx_regtab): Likewise.
703 (crx_optab): Likewise.
610ad19b 704 (crx_instruction): Reorder load/stor instructions, remove unsupported
812337be
TL		 705 formats.
706 support new Co-Processor instruction 'cpi'.
707
4030fa5a
NC		 7082004-10-27 Nick Clifton <nickc@redhat.com>
709
710 * opcodes/iq2000-asm.c: Regenerate.
711 * opcodes/iq2000-desc.c: Regenerate.
712 * opcodes/iq2000-desc.h: Regenerate.
713 * opcodes/iq2000-dis.c: Regenerate.
714 * opcodes/iq2000-ibld.c: Regenerate.
715 * opcodes/iq2000-opc.c: Regenerate.
716 * opcodes/iq2000-opc.h: Regenerate.
717
fc3d45e8
TL		 7182004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
719
720 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
721 us4, us5 (respectively).
722 Remove unsupported 'popa' instruction.
723 Reverse operands order in store co-processor instructions.
724
3c55da70
AM		 7252004-10-15 Alan Modra <amodra@bigpond.net.au>
726
727 * Makefile.am: Run "make dep-am"
728 * Makefile.in: Regenerate.
729
7fa3d080
BW		 7302004-10-12 Bob Wilson <bob.wilson@acm.org>
731
732 * xtensa-dis.c: Use ISO C90 formatting.
733
e612bb4d
AM		 7342004-10-09 Alan Modra <amodra@bigpond.net.au>
735
736 * ppc-opc.c: Revert 2004-09-09 change.
737
43cd72b9
BW		 7382004-10-07 Bob Wilson <bob.wilson@acm.org>
739
740 * xtensa-dis.c (state_names): Delete.
741 (fetch_data): Use xtensa_isa_maxlength.
742 (print_xtensa_operand): Replace operand parameter with opcode/operand
743 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
744 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
745 instruction bundles. Use xmalloc instead of malloc.
746
bbac1f2a
NC		 7472004-10-07 David Gibson <david@gibson.dropbear.id.au>
748
749 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
750 initializers.
751
48c9f030
NC		 7522004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
753
754 * crx-opc.c (crx_instruction): Support Co-processor insns.
755 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
756 (getregliststring): Change function to use the above enum.
757 (print_arg): Handle CO-Processor insns.
758 (crx_cinvs): Add 'b' option to invalidate the branch-target
759 cache.
760
12c64a4e
AH		 7612004-10-06 Aldy Hernandez <aldyh@redhat.com>
762
763 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
764 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
765 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
766 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
767 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
768
14127cc4
NC		 7692004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
770
771 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
772 rather than add it.
773
0dd132b6
NC		 7742004-09-30 Paul Brook <paul@codesourcery.com>
775
776 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
777 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
778
3f85e526
L		 7792004-09-17 H.J. Lu <hongjiu.lu@intel.com>
780
781 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
782 (CONFIG_STATUS_DEPENDENCIES): New.
783 (Makefile): Removed.
784 (config.status): Likewise.
785 * Makefile.in: Regenerated.
786
8ae85421
AM		 7872004-09-17 Alan Modra <amodra@bigpond.net.au>
788
789 * Makefile.am: Run "make dep-am".
790 * Makefile.in: Regenerate.
791 * aclocal.m4: Regenerate.
792 * configure: Regenerate.
793 * po/POTFILES.in: Regenerate.
794 * po/opcodes.pot: Regenerate.
795
24443139
AS		 7962004-09-11 Andreas Schwab <schwab@suse.de>
797
798 * configure: Rebuild.
799
2a309db0
AM		 8002004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
801
802 * ppc-opc.c (L): Make this field not optional.
803
42851540
NC		 8042004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
805
806 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
807 Fix parameter to 'm[t|f]csr' insns.
808
979273e3
NN		 8092004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
810
811 * configure.in: Autoupdate to autoconf 2.59.
812 * aclocal.m4: Rebuild with aclocal 1.4p6.
813 * configure: Rebuild with autoconf 2.59.
814 * Makefile.in: Rebuild with automake 1.4p6 (picking up
815 bfd changes for autoconf 2.59 on the way).
816 * config.in: Rebuild with autoheader 2.59.
817
ac28a1cb
RS		 8182004-08-27 Richard Sandiford <rsandifo@redhat.com>
819
820 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
821
30d1c836
ML		 8222004-07-30 Michal Ludvig <mludvig@suse.cz>
823
824 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
825 (GRPPADLCK2): New define.
826 (twobyte_has_modrm): True for 0xA6.
827 (grps): GRPPADLCK2 for opcode 0xA6.
828
0b0ac059
AO		 8292004-07-29 Alexandre Oliva <aoliva@redhat.com>
830
831 Introduce SH2a support.
832 * sh-opc.h (arch_sh2a_base): Renumber.
833 (arch_sh2a_nofpu_base): Remove.
834 (arch_sh_base_mask): Adjust.
835 (arch_opann_mask): New.
836 (arch_sh2a, arch_sh2a_nofpu): Adjust.
837 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
838 (sh_table): Adjust whitespace.
839 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
840 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
841 instruction list throughout.
842 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
843 of arch_sh2a in instruction list throughout.
844 (arch_sh2e_up): Accomodate above changes.
845 (arch_sh2_up): Ditto.
846 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
847 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
848 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
849 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
850 * sh-opc.h (arch_sh2a_nofpu): New.
851 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
852 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
853 instruction.
854 2004-01-20 DJ Delorie <dj@redhat.com>
855 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
856 2003-12-29 DJ Delorie <dj@redhat.com>
857 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
858 sh_opcode_info, sh_table): Add sh2a support.
859 (arch_op32): New, to tag 32-bit opcodes.
860 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
861 2003-12-02 Michael Snyder <msnyder@redhat.com>
862 * sh-opc.h (arch_sh2a): Add.
863 * sh-dis.c (arch_sh2a): Handle.
864 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
865
670ec21d
NC		 8662004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
867
868 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
869
ed049af3
NC		 8702004-07-22 Nick Clifton <nickc@redhat.com>
871
872 PR/280
873 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
874 insns - this is done by objdump itself.
875 * h8500-dis.c (print_insn_h8500): Likewise.
876
20f0a1fc
NC		 8772004-07-21 Jan Beulich <jbeulich@novell.com>
878
879 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
880 regardless of address size prefix in effect.
881 (ptr_reg): Size or address registers does not depend on rex64, but
882 on the presence of an address size override.
883 (OP_MMX): Use rex.x only for xmm registers.
884 (OP_EM): Use rex.z only for xmm registers.
885
6f14957b
MR		 8862004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
887
888 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
889 move/branch operations to the bottom so that VR5400 multimedia
890 instructions take precedence in disassembly.
891
1586d91e
MR		 8922004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
893
894 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
895 ISA-specific "break" encoding.
896
982de27a
NC		 8972004-07-13 Elvis Chiang <elvisfb@gmail.com>
898
899 * arm-opc.h: Fix typo in comment.
900
4300ab10
AS		 9012004-07-11 Andreas Schwab <schwab@suse.de>
902
903 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
904
8577e690
AS		 9052004-07-09 Andreas Schwab <schwab@suse.de>
906
907 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
908
1fe1f39c
NC		 9092004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
910
911 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
912 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
913 (crx-dis.lo): New target.
914 (crx-opc.lo): Likewise.
915 * Makefile.in: Regenerate.
916 * configure.in: Handle bfd_crx_arch.
917 * configure: Regenerate.
918 * crx-dis.c: New file.
919 * crx-opc.c: New file.
920 * disassemble.c (ARCH_crx): Define.
921 (disassembler): Handle ARCH_crx.
922
7a33b495
JW		 9232004-06-29 James E Wilson <wilson@specifixinc.com>
924
925 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
926 * ia64-asmtab.c: Regnerate.
927
98e69875
AM		 9282004-06-28 Alan Modra <amodra@bigpond.net.au>
929
930 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
931 (extract_fxm): Don't test dialect.
932 (XFXFXM_MASK): Include the power4 bit.
933 (XFXM): Add p4 param.
934 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
935
a53b85e2
AO		 9362004-06-27 Alexandre Oliva <aoliva@redhat.com>
937
938 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
939 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
940
d0618d1c
AM		 9412004-06-26 Alan Modra <amodra@bigpond.net.au>
942
943 * ppc-opc.c (BH, XLBH_MASK): Define.
944 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
945
1d9f512f
AM		 9462004-06-24 Alan Modra <amodra@bigpond.net.au>
947
948 * i386-dis.c (x_mode): Comment.
949 (two_source_ops): File scope.
950 (float_mem): Correct fisttpll and fistpll.
951 (float_mem_mode): New table.
952 (dofloat): Use it.
953 (OP_E): Correct intel mode PTR output.
954 (ptr_reg): Use open_char and close_char.
955 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
956 operands. Set two_source_ops.
957
52886d70
AM		 9582004-06-15 Alan Modra <amodra@bigpond.net.au>
959
960 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
961 instead of _raw_size.
962
bad9ceea
JJ		 9632004-06-08 Jakub Jelinek <jakub@redhat.com>
964
965 * ia64-gen.c (in_iclass): Handle more postinc st
966 and ld variants.
967 * ia64-asmtab.c: Rebuilt.
968
0451f5df
MS		 9692004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
970
971 * s390-opc.txt: Correct architecture mask for some opcodes.
972 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
973 in the esa mode as well.
974
f6f9408f
JR		 9752004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
976
977 * sh-dis.c (target_arch): Make unsigned.
978 (print_insn_sh): Replace (most of) switch with a call to
979 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
980 * sh-opc.h: Redefine architecture flags values.
981 Add sh3-nommu architecture.
982 Reorganise <arch>_up macros so they make more visual sense.
983 (SH_MERGE_ARCH_SET): Define new macro.
984 (SH_VALID_BASE_ARCH_SET): Likewise.
985 (SH_VALID_MMU_ARCH_SET): Likewise.
986 (SH_VALID_CO_ARCH_SET): Likewise.
987 (SH_VALID_ARCH_SET): Likewise.
988 (SH_MERGE_ARCH_SET_VALID): Likewise.
989 (SH_ARCH_SET_HAS_FPU): Likewise.
990 (SH_ARCH_SET_HAS_DSP): Likewise.
991 (SH_ARCH_UNKNOWN_ARCH): Likewise.
992 (sh_get_arch_from_bfd_mach): Add prototype.
993 (sh_get_arch_up_from_bfd_mach): Likewise.
994 (sh_get_bfd_mach_from_arch_set): Likewise.
995 (sh_merge_bfd_arc): Likewise.
996
be8c092b
NC		 9972004-05-24 Peter Barada <peter@the-baradas.com>
998
999 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
610ad19b
AM		 1000 into new match_insn_m68k function. Loop over canidate
1001 matches and select first that completely matches.
be8c092b
NC		 1002 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
1003 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
610ad19b 1004 to verify addressing for MAC/EMAC.
be8c092b
NC		 1005 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
1006 reigster halves since 'fpu' and 'spl' look misleading.
1007 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
1008 * m68k-opc.c: Rearragne mac/emac cases to use longest for
1009 first, tighten up match masks.
1010 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
1011 'size' from special case code in print_insn_m68k to
1012 determine decode size of insns.
1013
a30e9cc4
AM		 10142004-05-19 Alan Modra <amodra@bigpond.net.au>
1015
1016 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
1017 well as when -mpower4.
1018
9598fbe5
NC		 10192004-05-13 Nick Clifton <nickc@redhat.com>
1020
1021 * po/fr.po: Updated French translation.
1022
6b6e92f4
NC		 10232004-05-05 Peter Barada <peter@the-baradas.com>
1024
1025 * m68k-dis.c(print_insn_m68k): Add new chips, use core
1026 variants in arch_mask. Only set m68881/68851 for 68k chips.
1027 * m68k-op.c: Switch from ColdFire chips to core variants.
1028
a404d431
AM		 10292004-05-05 Alan Modra <amodra@bigpond.net.au>
1030
a30e9cc4 1031 PR 147.
a404d431
AM		 1032 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
1033
f3806e43
BE		 10342004-04-29 Ben Elliston <bje@au.ibm.com>
1035
520ceea4
BE		 1036 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
1037 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
f3806e43 1038
1f1799d5
KK		 10392004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
1040
1041 * sh-dis.c (print_insn_sh): Print the value in constant pool
1042 as a symbol if it looks like a symbol.
1043
fd99574b
NC		 10442004-04-22 Peter Barada <peter@the-baradas.com>
1045
1046 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
1047 appropriate ColdFire architectures.
1048 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
1049 mask addressing.
1050 Add EMAC instructions, fix MAC instructions. Remove
1051 macmw/macml/msacmw/msacml instructions since mask addressing now
1052 supported.
1053
b4781d44
JJ		 10542004-04-20 Jakub Jelinek <jakub@redhat.com>
1055
1056 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
1057 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
1058 suffix. Use fmov*x macros, create all 3 fpsize variants in one
1059 macro. Adjust all users.
1060
91809fda 10612004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
610ad19b 1062
91809fda
NC		 1063 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
1064 separately.
1065
f4453dfa
NC		 10662004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
1067
1068 * m32r-asm.c: Regenerate.
1069
9b0de91a
SS		 10702004-03-29 Stan Shebs <shebs@apple.com>
1071
1072 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
1073 used.
1074
e20c0b3d
AM		 10752004-03-19 Alan Modra <amodra@bigpond.net.au>
1076
1077 * aclocal.m4: Regenerate.
1078 * config.in: Regenerate.
1079 * configure: Regenerate.
1080 * po/POTFILES.in: Regenerate.
1081 * po/opcodes.pot: Regenerate.
1082
fdd12ef3
AM		 10832004-03-16 Alan Modra <amodra@bigpond.net.au>
1084
1085 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
1086 PPC_OPERANDS_GPR_0.
1087 * ppc-opc.c (RA0): Define.
1088 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
1089 (RAOPT): Rename from RAO. Update all uses.
a9c3619e 1090 (powerpc_opcodes): Use RA0 as appropriate.
fdd12ef3 1091
2dc111b3 10922004-03-15 Aldy Hernandez <aldyh@redhat.com>
fdd12ef3
AM		 1093
1094 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
2dc111b3 1095
7bfeee7b
AM		 10962004-03-15 Alan Modra <amodra@bigpond.net.au>
1097
1098 * sparc-dis.c (print_insn_sparc): Update getword prototype.
1099
7ffdda93
ML		 11002004-03-12 Michal Ludvig <mludvig@suse.cz>
1101
1102 * i386-dis.c (GRPPLOCK): Delete.
7bfeee7b 1103 (grps): Delete GRPPLOCK entry.
7ffdda93 1104
cc0ec051
AM		 11052004-03-12 Alan Modra <amodra@bigpond.net.au>
1106
1107 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
1108 (M, Mp): Use OP_M.
1109 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
1110 (GRPPADLCK): Define.
1111 (dis386): Use NOP_Fixup on "nop".
1112 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
1113 (twobyte_has_modrm): Set for 0xa7.
1114 (padlock_table): Delete. Move to..
1115 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
1116 and clflush.
1117 (print_insn): Revert PADLOCK_SPECIAL code.
1118 (OP_E): Delete sfence, lfence, mfence checks.
1119
4fd61dcb
JJ		 11202004-03-12 Jakub Jelinek <jakub@redhat.com>
1121
1122 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
1123 (INVLPG_Fixup): New function.
1124 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
1125
0f10071e
ML		 11262004-03-12 Michal Ludvig <mludvig@suse.cz>
1127
1128 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
1129 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
1130 (padlock_table): New struct with PadLock instructions.
1131 (print_insn): Handle PADLOCK_SPECIAL.
1132
c02908d2
AM		 11332004-03-12 Alan Modra <amodra@bigpond.net.au>
1134
1135 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
1136 (OP_E): Twiddle clflush to sfence here.
1137
d5bb7600
NC		 11382004-03-08 Nick Clifton <nickc@redhat.com>
1139
1140 * po/de.po: Updated German translation.
1141
ae51a426
JR		 11422003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
1143
1144 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
1145 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
1146 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
1147 accordingly.
1148
676a64f4
RS		 11492004-03-01 Richard Sandiford <rsandifo@redhat.com>
1150
1151 * frv-asm.c: Regenerate.
1152 * frv-desc.c: Regenerate.
1153 * frv-desc.h: Regenerate.
1154 * frv-dis.c: Regenerate.
1155 * frv-ibld.c: Regenerate.
1156 * frv-opc.c: Regenerate.
1157 * frv-opc.h: Regenerate.
1158
c7a48b9a
RS		 11592004-03-01 Richard Sandiford <rsandifo@redhat.com>
1160
1161 * frv-desc.c, frv-opc.c: Regenerate.
1162
8ae0baa2
RS		 11632004-03-01 Richard Sandiford <rsandifo@redhat.com>
1164
1165 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
1166
ce11586c
JR		 11672004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
1168
1169 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
1170 Also correct mistake in the comment.
1171
6a5709a5
JR		 11722004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
1173
1174 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
1175 ensure that double registers have even numbers.
1176 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
1177 that reserved instruction 0xfffd does not decode the same
1178 as 0xfdfd (ftrv).
1179 * sh-opc.h: Add REG_N_D nibble type and use it whereever
1180 REG_N refers to a double register.
1181 Add REG_N_B01 nibble type and use it instead of REG_NM
1182 in ftrv.
1183 Adjust the bit patterns in a few comments.
1184
e5d2b64f 11852004-02-25 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1186
1187 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
e5d2b64f 1188
1f04b05f
AH		 11892004-02-20 Aldy Hernandez <aldyh@redhat.com>
1190
1191 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
1192
2f3b8700
AH		 11932004-02-20 Aldy Hernandez <aldyh@redhat.com>
1194
1195 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
1196
f0b26da6 11972004-02-20 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1198
1199 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
1200 mtivor32, mtivor33, mtivor34.
f0b26da6 1201
23d59c56 12022004-02-19 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1203
1204 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
23d59c56 1205
34920d91
NC		 12062004-02-10 Petko Manolov <petkan@nucleusys.com>
1207
1208 * arm-opc.h Maverick accumulator register opcode fixes.
1209
44d86481
BE		 12102004-02-13 Ben Elliston <bje@wasabisystems.com>
1211
1212 * m32r-dis.c: Regenerate.
1213
17707c23
MS		 12142004-01-27 Michael Snyder <msnyder@redhat.com>
1215
1216 * sh-opc.h (sh_table): "fsrra", not "fssra".
1217
fe3a9bc4
NC		 12182004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
1219
1220 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
1221 contraints.
1222
ff24f124
JJ		 12232004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
1224
1225 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
1226
a02a862a
AM		 12272004-01-19 Alan Modra <amodra@bigpond.net.au>
1228
1229 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
1230 1. Don't print scale factor on AT&T mode when index missing.
1231
d164ea7f
AO		 12322004-01-16 Alexandre Oliva <aoliva@redhat.com>
1233
1234 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
1235 when loaded into XR registers.
1236
cb10e79a
RS		 12372004-01-14 Richard Sandiford <rsandifo@redhat.com>
1238
1239 * frv-desc.h: Regenerate.
1240 * frv-desc.c: Regenerate.
1241 * frv-opc.c: Regenerate.
1242
f532f3fa
MS		 12432004-01-13 Michael Snyder <msnyder@redhat.com>
1244
1245 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
1246
e45d0630
PB		 12472004-01-09 Paul Brook <paul@codesourcery.com>
1248
1249 * arm-opc.h (arm_opcodes): Move generic mcrr after known
1250 specific opcodes.
1251
3ba7a1aa
DJ		 12522004-01-07 Daniel Jacobowitz <drow@mvista.com>
1253
1254 * Makefile.am (libopcodes_la_DEPENDENCIES)
1255 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
1256 comment about the problem.
1257 * Makefile.in: Regenerate.
1258
ba2d3f07
AO		 12592004-01-06 Alexandre Oliva <aoliva@redhat.com>
1260
1261 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
1262 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
1263 cut&paste errors in shifting/truncating numerical operands.
1264 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
1265 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
1266 (parse_uslo16): Likewise.
1267 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
1268 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
1269 (parse_s12): Likewise.
1270 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
1271 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
1272 (parse_uslo16): Likewise.
1273 (parse_uhi16): Parse gothi and gotfuncdeschi.
1274 (parse_d12): Parse got12 and gotfuncdesc12.
1275 (parse_s12): Likewise.
1276
3ab48931
NC		 12772004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
1278
1279 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
1280 instruction which looks similar to an 'rla' instruction.
a0bd404e 1281
c9e214e5 1282For older changes see ChangeLog-0203
252b5132
RH		 1283\f
1284Local Variables:
2f6d2f85
NC		 1285mode: change-log
1286left-margin: 8
1287fill-column: 74
252b5132
RH		 1288version-control: never
1289End:
GDB Binutils - Deliverables
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