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arc/nps400: Validate address type operands correctly
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
b437d035
AB		 12016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
2
3 * arc-opc.c (arc_flag_operands): Add F_DI14.
4 (arc_flag_classes): Add C_DI14.
5 * arc-nps400-tbl.h: Add new exc instructions.
6
5a736821
GM		 72016-11-03 Graham Markall <graham.markall@embecosm.com>
8
9 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
10 major opcode 0xa.
11 * arc-nps-400-tbl.h: Add dcmac instruction.
12 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
13 (insert_nps_rbdouble_64): Added.
14 (extract_nps_rbdouble_64): Added.
15 (insert_nps_proto_size): Added.
16 (extract_nps_proto_size): Added.
17
bdfe53e3
AB		 182016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
19
20 * arc-dis.c (struct arc_operand_iterator): Remove all fields
21 relating to long instruction processing, add new limm field.
22 (OPCODE): Rename to...
23 (OPCODE_32BIT_INSN): ...this.
24 (OPCODE_AC): Delete.
25 (skip_this_opcode): Handle different instruction lengths, update
26 macro name.
27 (special_flag_p): Update parameter type.
28 (find_format_from_table): Update for more instruction lengths.
29 (find_format_long_instructions): Delete.
30 (find_format): Update for more instruction lengths.
31 (arc_insn_length): Likewise.
32 (extract_operand_value): Update for more instruction lengths.
33 (operand_iterator_next): Remove code relating to long
34 instructions.
35 (arc_opcode_to_insn_type): New function.
36 (print_insn_arc):Update for more instructions lengths.
37 * arc-ext.c (extInstruction_t): Change argument type.
38 * arc-ext.h (extInstruction_t): Change argument type.
39 * arc-fxi.h: Change type unsigned to unsigned long long
40 extensively throughout.
41 * arc-nps400-tbl.h: Add long instructions taken from
42 arc_long_opcodes table in arc-opc.c.
43 * arc-opc.c: Update parameter types on insert/extract handlers.
44 (arc_long_opcodes): Delete.
45 (arc_num_long_opcodes): Delete.
46 (arc_opcode_len): Update for more instruction lengths.
47
90f61cce
GM		 482016-11-03 Graham Markall <graham.markall@embecosm.com>
49
50 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
51
06fe285f
GM		 522016-11-03 Graham Markall <graham.markall@embecosm.com>
53
54 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
55 with arc_opcode_len.
56 (find_format_long_instructions): Likewise.
57 * arc-opc.c (arc_opcode_len): New function.
58
ecf64ec6
AB		 592016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
60
61 * arc-nps400-tbl.h: Fix some instruction masks.
62
d039fef3
L		 632016-11-03 H.J. Lu <hongjiu.lu@intel.com>
64
65 * i386-dis.c (REG_82): Removed.
66 (X86_64_82_REG_0): Likewise.
67 (X86_64_82_REG_1): Likewise.
68 (X86_64_82_REG_2): Likewise.
69 (X86_64_82_REG_3): Likewise.
70 (X86_64_82_REG_4): Likewise.
71 (X86_64_82_REG_5): Likewise.
72 (X86_64_82_REG_6): Likewise.
73 (X86_64_82_REG_7): Likewise.
74 (X86_64_82): New.
75 (dis386): Use X86_64_82 instead of REG_82.
76 (reg_table): Remove REG_82.
77 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
78 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
79 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
80 X86_64_82_REG_7.
81
8b89fe14
L		 822016-11-03 H.J. Lu <hongjiu.lu@intel.com>
83
84 PR binutils/20754
85 * i386-dis.c (REG_82): New.
86 (X86_64_82_REG_0): Likewise.
87 (X86_64_82_REG_1): Likewise.
88 (X86_64_82_REG_2): Likewise.
89 (X86_64_82_REG_3): Likewise.
90 (X86_64_82_REG_4): Likewise.
91 (X86_64_82_REG_5): Likewise.
92 (X86_64_82_REG_6): Likewise.
93 (X86_64_82_REG_7): Likewise.
94 (dis386): Use REG_82.
95 (reg_table): Add REG_82.
96 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
97 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
98 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
99
7148c369
L		 1002016-11-03 H.J. Lu <hongjiu.lu@intel.com>
101
102 * i386-dis.c (REG_82): Renamed to ...
103 (REG_83): This.
104 (dis386): Updated.
105 (reg_table): Likewise.
106
47acf0bd
IT		 1072016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
108
109 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
110 * i386-dis-evex.h (evex_table): Updated.
111 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
112 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
113 (cpu_flags): Add CpuAVX512_4VNNIW.
114 * i386-opc.h (enum): (AVX512_4VNNIW): New.
115 (i386_cpu_flags): Add cpuavx512_4vnniw.
116 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
117 * i386-init.h: Regenerate.
118 * i386-tbl.h: Ditto.
119
920d2ddc
IT		 1202016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
121
122 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
123 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
124 * i386-dis-evex.h (evex_table): Updated.
125 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
126 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
127 (cpu_flags): Add CpuAVX512_4FMAPS.
128 (opcode_modifiers): Add ImplicitQuadGroup modifier.
129 * i386-opc.h (AVX512_4FMAP): New.
130 (i386_cpu_flags): Add cpuavx512_4fmaps.
131 (ImplicitQuadGroup): New.
132 (i386_opcode_modifier): Add implicitquadgroup.
133 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
134 * i386-init.h: Regenerate.
135 * i386-tbl.h: Ditto.
136
e23eba97
NC		 1372016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
138 Andrew Waterman <andrew@sifive.com>
139
140 Add support for RISC-V architecture.
141 * configure.ac: Add entry for bfd_riscv_arch.
142 * configure: Regenerate.
143 * disassemble.c (disassembler): Add support for riscv.
144 (disassembler_usage): Likewise.
145 * riscv-dis.c: New file.
146 * riscv-opc.c: New file.
147
b5cefcca
L		 1482016-10-21 H.J. Lu <hongjiu.lu@intel.com>
149
150 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
151 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
152 (rm_table): Update the RM_0FAE_REG_7 entry.
153 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
154 (cpu_flags): Remove CpuPCOMMIT.
155 * i386-opc.h (CpuPCOMMIT): Removed.
156 (i386_cpu_flags): Remove cpupcommit.
157 * i386-opc.tbl: Remove pcommit.
158 * i386-init.h: Regenerated.
159 * i386-tbl.h: Likewise.
160
9889cbb1
L		 1612016-10-20 H.J. Lu <hongjiu.lu@intel.com>
162
163 PR binutis/20705
164 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
165 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
166 32-bit mode. Don't check vex.register_specifier in 32-bit
167 mode.
168 (OP_VEX): Check for invalid mask registers.
169
28596323
L		 1702016-10-18 H.J. Lu <hongjiu.lu@intel.com>
171
172 PR binutis/20699
173 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
174 sizeflag.
175
da8d7d66
L		 1762016-10-18 H.J. Lu <hongjiu.lu@intel.com>
177
178 PR binutis/20704
179 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
180
eaf02703
MR		 1812016-10-18 Maciej W. Rozycki <macro@imgtec.com>
182
183 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
184 local variable to `index_regno'.
185
decf5bd1
CM		 1862016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
187
188 * arc-tbl.h: Removed any "inv.+" instructions from the table.
189
e5b06ef0
CZ		 1902016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
191
192 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
193 usage on ISA basis.
194
93562a34
JW		 1952016-10-11 Jiong Wang <jiong.wang@arm.com>
196
197 PR target/20666
198 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
199
362c0c4d
JW		 2002016-10-07 Jiong Wang <jiong.wang@arm.com>
201
202 PR target/20667
203 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
204 available.
205
1047201f
AM		 2062016-10-07 Alan Modra <amodra@gmail.com>
207
208 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
209
1a0670f3
AM		 2102016-10-06 Alan Modra <amodra@gmail.com>
211
212 * aarch64-opc.c: Spell fall through comments consistently.
213 * i386-dis.c: Likewise.
214 * aarch64-dis.c: Add missing fall through comments.
215 * aarch64-opc.c: Likewise.
216 * arc-dis.c: Likewise.
217 * arm-dis.c: Likewise.
218 * i386-dis.c: Likewise.
219 * m68k-dis.c: Likewise.
220 * mep-asm.c: Likewise.
221 * ns32k-dis.c: Likewise.
222 * sh-dis.c: Likewise.
223 * tic4x-dis.c: Likewise.
224 * tic6x-dis.c: Likewise.
225 * vax-dis.c: Likewise.
226
2b804145
AM		 2272016-10-06 Alan Modra <amodra@gmail.com>
228
229 * arc-ext.c (create_map): Add missing break.
230 * msp430-decode.opc (encode_as): Likewise.
231 * msp430-decode.c: Regenerate.
232
616ec358
AM		 2332016-10-06 Alan Modra <amodra@gmail.com>
234
235 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
236 * crx-dis.c (print_insn_crx): Likewise.
237
72da393d
L		 2382016-09-30 H.J. Lu <hongjiu.lu@intel.com>
239
240 PR binutils/20657
241 * i386-dis.c (putop): Don't assign alt twice.
242
744ce302
JW		 2432016-09-29 Jiong Wang <jiong.wang@arm.com>
244
245 PR target/20553
246 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
247
a5721ba2
AM		 2482016-09-29 Alan Modra <amodra@gmail.com>
249
250 * ppc-opc.c (L): Make compulsory.
251 (LOPT): New, optional form of L.
252 (HTM_R): Define as LOPT.
253 (L0, L1): Delete.
254 (L32OPT): New, optional for 32-bit L.
255 (L2OPT): New, 2-bit L for dcbf.
256 (SVC_LEC): Update.
257 (L2): Define.
258 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
259 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
260 <dcbf>: Use L2OPT.
261 <tlbiel, tlbie>: Use LOPT.
262 <wclr, wclrall>: Use L2.
263
c5da1932
VZ		 2642016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
265
266 * Makefile.in: Regenerate.
267 * configure: Likewise.
268
2b848ebd
CZ		 2692016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
270
271 * arc-ext-tbl.h (EXTINSN2OPF): Define.
272 (EXTINSN2OP): Use EXTINSN2OPF.
273 (bspeekm, bspop, modapp): New extension instructions.
274 * arc-opc.c (F_DNZ_ND): Define.
275 (F_DNZ_D): Likewise.
276 (F_SIZEB1): Changed.
277 (C_DNZ_D): Define.
278 (C_HARD): Changed.
279 * arc-tbl.h (dbnz): New instruction.
280 (prealloc): Allow it for ARC EM.
281 (xbfu): Likewise.
282
ad43e107
RS		 2832016-09-21 Richard Sandiford <richard.sandiford@arm.com>
284
285 * aarch64-opc.c (print_immediate_offset_address): Print spaces
286 after commas in addresses.
287 (aarch64_print_operand): Likewise.
288
ab3b8fcf
RS		 2892016-09-21 Richard Sandiford <richard.sandiford@arm.com>
290
291 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
292 rather than "should be" or "expected to be" in error messages.
293
bb7eff52
RS		 2942016-09-21 Richard Sandiford <richard.sandiford@arm.com>
295
296 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
297 (print_mnemonic_name): ...here.
298 (print_comment): New function.
299 (print_aarch64_insn): Call it.
300 * aarch64-opc.c (aarch64_conds): Add SVE names.
301 (aarch64_print_operand): Print alternative condition names in
302 a comment.
303
c0890d26
RS		 3042016-09-21 Richard Sandiford <richard.sandiford@arm.com>
305
306 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
307 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
308 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
309 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
310 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
311 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
312 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
313 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
314 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
315 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
316 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
317 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
318 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
319 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
320 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
321 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
322 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
323 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
324 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
325 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
326 (OP_SVE_XWU, OP_SVE_XXU): New macros.
327 (aarch64_feature_sve): New variable.
328 (SVE): New macro.
329 (_SVE_INSN): Likewise.
330 (aarch64_opcode_table): Add SVE instructions.
331 * aarch64-opc.h (extract_fields): Declare.
332 * aarch64-opc-2.c: Regenerate.
333 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
334 * aarch64-asm-2.c: Regenerate.
335 * aarch64-dis.c (extract_fields): Make global.
336 (do_misc_decoding): Handle the new SVE aarch64_ops.
337 * aarch64-dis-2.c: Regenerate.
338
116b6019
RS		 3392016-09-21 Richard Sandiford <richard.sandiford@arm.com>
340
341 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
342 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
343 aarch64_field_kinds.
344 * aarch64-opc.c (fields): Add corresponding entries.
345 * aarch64-asm.c (aarch64_get_variant): New function.
346 (aarch64_encode_variant_using_iclass): Likewise.
347 (aarch64_opcode_encode): Call it.
348 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
349 (aarch64_opcode_decode): Call it.
350
047cd301
RS		 3512016-09-21 Richard Sandiford <richard.sandiford@arm.com>
352
353 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
354 and FP register operands.
355 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
356 (FLD_SVE_Vn): New aarch64_field_kinds.
357 * aarch64-opc.c (fields): Add corresponding entries.
358 (aarch64_print_operand): Handle the new SVE core and FP register
359 operands.
360 * aarch64-opc-2.c: Regenerate.
361 * aarch64-asm-2.c: Likewise.
362 * aarch64-dis-2.c: Likewise.
363
165d4950
RS		 3642016-09-21 Richard Sandiford <richard.sandiford@arm.com>
365
366 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
367 immediate operands.
368 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
369 * aarch64-opc.c (fields): Add corresponding entry.
370 (operand_general_constraint_met_p): Handle the new SVE FP immediate
371 operands.
372 (aarch64_print_operand): Likewise.
373 * aarch64-opc-2.c: Regenerate.
374 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
375 (ins_sve_float_zero_one): New inserters.
376 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
377 (aarch64_ins_sve_float_half_two): Likewise.
378 (aarch64_ins_sve_float_zero_one): Likewise.
379 * aarch64-asm-2.c: Regenerate.
380 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
381 (ext_sve_float_zero_one): New extractors.
382 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
383 (aarch64_ext_sve_float_half_two): Likewise.
384 (aarch64_ext_sve_float_zero_one): Likewise.
385 * aarch64-dis-2.c: Regenerate.
386
e950b345
RS		 3872016-09-21 Richard Sandiford <richard.sandiford@arm.com>
388
389 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
390 integer immediate operands.
391 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
392 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
393 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
394 * aarch64-opc.c (fields): Add corresponding entries.
395 (operand_general_constraint_met_p): Handle the new SVE integer
396 immediate operands.
397 (aarch64_print_operand): Likewise.
398 (aarch64_sve_dupm_mov_immediate_p): New function.
399 * aarch64-opc-2.c: Regenerate.
400 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
401 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
402 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
403 (aarch64_ins_limm): ...here.
404 (aarch64_ins_inv_limm): New function.
405 (aarch64_ins_sve_aimm): Likewise.
406 (aarch64_ins_sve_asimm): Likewise.
407 (aarch64_ins_sve_limm_mov): Likewise.
408 (aarch64_ins_sve_shlimm): Likewise.
409 (aarch64_ins_sve_shrimm): Likewise.
410 * aarch64-asm-2.c: Regenerate.
411 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
412 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
413 * aarch64-dis.c (decode_limm): New function, split out from...
414 (aarch64_ext_limm): ...here.
415 (aarch64_ext_inv_limm): New function.
416 (decode_sve_aimm): Likewise.
417 (aarch64_ext_sve_aimm): Likewise.
418 (aarch64_ext_sve_asimm): Likewise.
419 (aarch64_ext_sve_limm_mov): Likewise.
420 (aarch64_top_bit): Likewise.
421 (aarch64_ext_sve_shlimm): Likewise.
422 (aarch64_ext_sve_shrimm): Likewise.
423 * aarch64-dis-2.c: Regenerate.
424
98907a70
RS		 4252016-09-21 Richard Sandiford <richard.sandiford@arm.com>
426
427 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
428 operands.
429 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
430 the AARCH64_MOD_MUL_VL entry.
431 (value_aligned_p): Cope with non-power-of-two alignments.
432 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
433 (print_immediate_offset_address): Likewise.
434 (aarch64_print_operand): Likewise.
435 * aarch64-opc-2.c: Regenerate.
436 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
437 (ins_sve_addr_ri_s9xvl): New inserters.
438 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
439 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
440 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
441 * aarch64-asm-2.c: Regenerate.
442 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
443 (ext_sve_addr_ri_s9xvl): New extractors.
444 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
445 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
446 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
447 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
448 * aarch64-dis-2.c: Regenerate.
449
4df068de
RS		 4502016-09-21 Richard Sandiford <richard.sandiford@arm.com>
451
452 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
453 address operands.
454 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
455 (FLD_SVE_xs_22): New aarch64_field_kinds.
456 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
457 (get_operand_specific_data): New function.
458 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
459 FLD_SVE_xs_14 and FLD_SVE_xs_22.
460 (operand_general_constraint_met_p): Handle the new SVE address
461 operands.
462 (sve_reg): New array.
463 (get_addr_sve_reg_name): New function.
464 (aarch64_print_operand): Handle the new SVE address operands.
465 * aarch64-opc-2.c: Regenerate.
466 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
467 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
468 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
469 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
470 (aarch64_ins_sve_addr_rr_lsl): Likewise.
471 (aarch64_ins_sve_addr_rz_xtw): Likewise.
472 (aarch64_ins_sve_addr_zi_u5): Likewise.
473 (aarch64_ins_sve_addr_zz): Likewise.
474 (aarch64_ins_sve_addr_zz_lsl): Likewise.
475 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
476 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
477 * aarch64-asm-2.c: Regenerate.
478 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
479 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
480 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
481 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
482 (aarch64_ext_sve_addr_ri_u6): Likewise.
483 (aarch64_ext_sve_addr_rr_lsl): Likewise.
484 (aarch64_ext_sve_addr_rz_xtw): Likewise.
485 (aarch64_ext_sve_addr_zi_u5): Likewise.
486 (aarch64_ext_sve_addr_zz): Likewise.
487 (aarch64_ext_sve_addr_zz_lsl): Likewise.
488 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
489 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
490 * aarch64-dis-2.c: Regenerate.
491
2442d846
RS		 4922016-09-21 Richard Sandiford <richard.sandiford@arm.com>
493
494 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
495 AARCH64_OPND_SVE_PATTERN_SCALED.
496 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
497 * aarch64-opc.c (fields): Add a corresponding entry.
498 (set_multiplier_out_of_range_error): New function.
499 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
500 (operand_general_constraint_met_p): Handle
501 AARCH64_OPND_SVE_PATTERN_SCALED.
502 (print_register_offset_address): Use PRIi64 to print the
503 shift amount.
504 (aarch64_print_operand): Likewise. Handle
505 AARCH64_OPND_SVE_PATTERN_SCALED.
506 * aarch64-opc-2.c: Regenerate.
507 * aarch64-asm.h (ins_sve_scale): New inserter.
508 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
509 * aarch64-asm-2.c: Regenerate.
510 * aarch64-dis.h (ext_sve_scale): New inserter.
511 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
512 * aarch64-dis-2.c: Regenerate.
513
245d2e3f
RS		 5142016-09-21 Richard Sandiford <richard.sandiford@arm.com>
515
516 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
517 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
518 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
519 (FLD_SVE_prfop): Likewise.
520 * aarch64-opc.c: Include libiberty.h.
521 (aarch64_sve_pattern_array): New variable.
522 (aarch64_sve_prfop_array): Likewise.
523 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
524 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
525 AARCH64_OPND_SVE_PRFOP.
526 * aarch64-asm-2.c: Regenerate.
527 * aarch64-dis-2.c: Likewise.
528 * aarch64-opc-2.c: Likewise.
529
d50c751e
RS		 5302016-09-21 Richard Sandiford <richard.sandiford@arm.com>
531
532 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
533 AARCH64_OPND_QLF_P_[ZM].
534 (aarch64_print_operand): Print /z and /m where appropriate.
535
f11ad6bc
RS		 5362016-09-21 Richard Sandiford <richard.sandiford@arm.com>
537
538 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
539 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
540 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
541 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
542 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
543 * aarch64-opc.c (fields): Add corresponding entries here.
544 (operand_general_constraint_met_p): Check that SVE register lists
545 have the correct length. Check the ranges of SVE index registers.
546 Check for cases where p8-p15 are used in 3-bit predicate fields.
547 (aarch64_print_operand): Handle the new SVE operands.
548 * aarch64-opc-2.c: Regenerate.
549 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
550 * aarch64-asm.c (aarch64_ins_sve_index): New function.
551 (aarch64_ins_sve_reglist): Likewise.
552 * aarch64-asm-2.c: Regenerate.
553 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
554 * aarch64-dis.c (aarch64_ext_sve_index): New function.
555 (aarch64_ext_sve_reglist): Likewise.
556 * aarch64-dis-2.c: Regenerate.
557
0c608d6b
RS		 5582016-09-21 Richard Sandiford <richard.sandiford@arm.com>
559
560 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
561 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
562 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
563 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
564 tied operands.
565
01dbfe4c
RS		 5662016-09-21 Richard Sandiford <richard.sandiford@arm.com>
567
568 * aarch64-opc.c (get_offset_int_reg_name): New function.
569 (print_immediate_offset_address): Likewise.
570 (print_register_offset_address): Take the base and offset
571 registers as parameters.
572 (aarch64_print_operand): Update caller accordingly. Use
573 print_immediate_offset_address.
574
72e9f319
RS		 5752016-09-21 Richard Sandiford <richard.sandiford@arm.com>
576
577 * aarch64-opc.c (BANK): New macro.
578 (R32, R64): Take a register number as argument
579 (int_reg): Use BANK.
580
8a7f0c1b
RS		 5812016-09-21 Richard Sandiford <richard.sandiford@arm.com>
582
583 * aarch64-opc.c (print_register_list): Add a prefix parameter.
584 (aarch64_print_operand): Update accordingly.
585
aa2aa4c6
RS		 5862016-09-21 Richard Sandiford <richard.sandiford@arm.com>
587
588 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
589 for FPIMM.
590 * aarch64-asm.h (ins_fpimm): New inserter.
591 * aarch64-asm.c (aarch64_ins_fpimm): New function.
592 * aarch64-asm-2.c: Regenerate.
593 * aarch64-dis.h (ext_fpimm): New extractor.
594 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
595 (aarch64_ext_fpimm): New function.
596 * aarch64-dis-2.c: Regenerate.
597
b5464a68
RS		 5982016-09-21 Richard Sandiford <richard.sandiford@arm.com>
599
600 * aarch64-asm.c: Include libiberty.h.
601 (insert_fields): New function.
602 (aarch64_ins_imm): Use it.
603 * aarch64-dis.c (extract_fields): New function.
604 (aarch64_ext_imm): Use it.
605
42408347
RS		 6062016-09-21 Richard Sandiford <richard.sandiford@arm.com>
607
608 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
609 with an esize parameter.
610 (operand_general_constraint_met_p): Update accordingly.
611 Fix misindented code.
612 * aarch64-asm.c (aarch64_ins_limm): Update call to
613 aarch64_logical_immediate_p.
614
4989adac
RS		 6152016-09-21 Richard Sandiford <richard.sandiford@arm.com>
616
617 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
618
bd11d5d8
RS		 6192016-09-21 Richard Sandiford <richard.sandiford@arm.com>
620
621 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
622
f807f43d
CZ		 6232016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
624
625 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
626
fd486b63
PB		 6272016-09-14 Peter Bergner <bergner@vnet.ibm.com>
628
629 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
630 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
631 xor3>: Delete mnemonics.
632 <cp_abort>: Rename mnemonic from ...
633 <cpabort>: ...to this.
634 <setb>: Change to a X form instruction.
635 <sync>: Change to 1 operand form.
636 <copy>: Delete mnemonic.
637 <copy_first>: Rename mnemonic from ...
638 <copy>: ...to this.
639 <paste, paste.>: Delete mnemonics.
640 <paste_last>: Rename mnemonic from ...
641 <paste.>: ...to this.
642
dce08442
AK		 6432016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
644
645 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
646
952c3f51
AK		 6472016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
648
649 * s390-mkopc.c (main): Support alternate arch strings.
650
8b71537b
PS		 6512016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
652
653 * s390-opc.txt: Fix kmctr instruction type.
654
5b64d091
L		 6552016-09-07 H.J. Lu <hongjiu.lu@intel.com>
656
657 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
658 * i386-init.h: Regenerated.
659
7763838e
CM		 6602016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
661
662 * opcodes/arc-dis.c (print_insn_arc): Changed.
663
1b8b6532
JM		 6642016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
665
666 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
667 camellia_fl.
668
1a336194
TP		 6692016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
670
671 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
672 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
673 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
674
6b40c462
L		 6752016-08-24 H.J. Lu <hongjiu.lu@intel.com>
676
677 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
678 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
679 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
680 PREFIX_MOD_3_0FAE_REG_4.
681 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
682 PREFIX_MOD_3_0FAE_REG_4.
683 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
684 (cpu_flags): Add CpuPTWRITE.
685 * i386-opc.h (CpuPTWRITE): New.
686 (i386_cpu_flags): Add cpuptwrite.
687 * i386-opc.tbl: Add ptwrite instruction.
688 * i386-init.h: Regenerated.
689 * i386-tbl.h: Likewise.
690
ab548d2d
AK		 6912016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
692
693 * arc-dis.h: Wrap around in extern "C".
694
344bde0a
RS		 6952016-08-23 Richard Sandiford <richard.sandiford@arm.com>
696
697 * aarch64-tbl.h (V8_2_INSN): New macro.
698 (aarch64_opcode_table): Use it.
699
5ce912d8
RS		 7002016-08-23 Richard Sandiford <richard.sandiford@arm.com>
701
702 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
703 CORE_INSN, __FP_INSN and SIMD_INSN.
704
9d30b0bd
RS		 7052016-08-23 Richard Sandiford <richard.sandiford@arm.com>
706
707 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
708 (aarch64_opcode_table): Update uses accordingly.
709
dfdaec14
AJ		 7102016-07-25 Andrew Jenner <andrew@codesourcery.com>
711 Kwok Cheung Yeung <kcy@codesourcery.com>
712
713 opcodes/
714 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
715 'e_cmplwi' to 'e_cmpli' instead.
716 (OPVUPRT, OPVUPRT_MASK): Define.
717 (powerpc_opcodes): Add E200Z4 insns.
718 (vle_opcodes): Add context save/restore insns.
719
7bd374a4
MR		 7202016-07-27 Maciej W. Rozycki <macro@imgtec.com>
721
722 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
723 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
724 "j".
725
db18dbab
GM		 7262016-07-27 Graham Markall <graham.markall@embecosm.com>
727
728 * arc-nps400-tbl.h: Change block comments to GNU format.
729 * arc-dis.c: Add new globals addrtypenames,
730 addrtypenames_max, and addtypeunknown.
731 (get_addrtype): New function.
732 (print_insn_arc): Print colons and address types when
733 required.
734 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
735 define insert and extract functions for all address types.
736 (arc_operands): Add operands for colon and all address
737 types.
738 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
739 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
740 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
741 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
742 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
743 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
744
fecd57f9
L		 7452016-07-21 H.J. Lu <hongjiu.lu@intel.com>
746
747 * configure: Regenerated.
748
37fd5ef3
CZ		 7492016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
750
751 * arc-dis.c (skipclass): New structure.
752 (decodelist): New variable.
753 (is_compatible_p): New function.
754 (new_element): Likewise.
755 (skip_class_p): Likewise.
756 (find_format_from_table): Use skip_class_p function.
757 (find_format): Decode first the extension instructions.
758 (print_insn_arc): Select either ARCEM or ARCHS based on elf
759 e_flags.
760 (parse_option): New function.
761 (parse_disassembler_options): Likewise.
762 (print_arc_disassembler_options): Likewise.
763 (print_insn_arc): Use parse_disassembler_options function. Proper
764 select ARCv2 cpu variant.
765 * disassemble.c (disassembler_usage): Add ARC disassembler
766 options.
767
92281a5b
MR		 7682016-07-13 Maciej W. Rozycki <macro@imgtec.com>
769
770 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
771 annotation from the "nal" entry and reorder it beyond "bltzal".
772
6e7ced37
JM		 7732016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
774
775 * sparc-opc.c (ldtxa): New macro.
776 (sparc_opcodes): Use the macro defined above to add entries for
777 the LDTXA instructions.
778 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
779 instruction.
780
2f831b9a 7812016-07-07 James Bowman <james.bowman@ftdichip.com>
782
783 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
784 and "jmpc".
785
c07315e0
JB		 7862016-07-01 Jan Beulich <jbeulich@suse.com>
787
788 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
789 (movzb): Adjust to cover all permitted suffixes.
790 (movzw): New.
791 * i386-tbl.h: Re-generate.
792
9243100a
JB		 7932016-07-01 Jan Beulich <jbeulich@suse.com>
794
795 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
796 (lgdt): Remove Tbyte from non-64-bit variant.
797 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
798 xsaves64, xsavec64): Remove Disp16.
799 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
800 Remove Disp32S from non-64-bit variants. Remove Disp16 from
801 64-bit variants.
802 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
803 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
804 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
805 64-bit variants.
806 * i386-tbl.h: Re-generate.
807
8325cc63
JB		 8082016-07-01 Jan Beulich <jbeulich@suse.com>
809
810 * i386-opc.tbl (xlat): Remove RepPrefixOk.
811 * i386-tbl.h: Re-generate.
812
838441e4
YQ		 8132016-06-30 Yao Qi <yao.qi@linaro.org>
814
815 * arm-dis.c (print_insn): Fix typo in comment.
816
dab26bf4
RS		 8172016-06-28 Richard Sandiford <richard.sandiford@arm.com>
818
819 * aarch64-opc.c (operand_general_constraint_met_p): Check the
820 range of ldst_elemlist operands.
821 (print_register_list): Use PRIi64 to print the index.
822 (aarch64_print_operand): Likewise.
823
5703197e
TS		 8242016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
825
826 * mcore-opc.h: Remove sentinal.
827 * mcore-dis.c (print_insn_mcore): Adjust.
828
ce440d63
GM		 8292016-06-23 Graham Markall <graham.markall@embecosm.com>
830
831 * arc-opc.c: Correct description of availability of NPS400
832 features.
833
6fd3a02d
PB		 8342016-06-22 Peter Bergner <bergner@vnet.ibm.com>
835
836 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
837 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
838 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
839 xor3>: New mnemonics.
840 <setb>: Change to a VX form instruction.
841 (insert_sh6): Add support for rldixor.
842 (extract_sh6): Likewise.
843
6b477896
TS		 8442016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
845
846 * arc-ext.h: Wrap in extern C.
847
bdd582db
GM		 8482016-06-21 Graham Markall <graham.markall@embecosm.com>
849
850 * arc-dis.c (arc_insn_length): Add comment on instruction length.
851 Use same method for determining instruction length on ARC700 and
852 NPS-400.
853 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
854 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
855 with the NPS400 subclass.
856 * arc-opc.c: Likewise.
857
96074adc
JM		 8582016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
859
860 * sparc-opc.c (rdasr): New macro.
861 (wrasr): Likewise.
862 (rdpr): Likewise.
863 (wrpr): Likewise.
864 (rdhpr): Likewise.
865 (wrhpr): Likewise.
866 (sparc_opcodes): Use the macros above to fix and expand the
867 definition of read/write instructions from/to
868 asr/privileged/hyperprivileged instructions.
869 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
870 %hva_mask_nz. Prefer softint_set and softint_clear over
871 set_softint and clear_softint.
872 (print_insn_sparc): Support %ver in Rd.
873
7a10c22f
JM		 8742016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
875
876 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
877 architecture according to the hardware capabilities they require.
878
4f26fb3a
JM		 8792016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
880
881 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
882 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
883 bfd_mach_sparc_v9{c,d,e,v,m}.
884 * sparc-opc.c (MASK_V9C): Define.
885 (MASK_V9D): Likewise.
886 (MASK_V9E): Likewise.
887 (MASK_V9V): Likewise.
888 (MASK_V9M): Likewise.
889 (v6): Add MASK_V9{C,D,E,V,M}.
890 (v6notlet): Likewise.
891 (v7): Likewise.
892 (v8): Likewise.
893 (v9): Likewise.
894 (v9andleon): Likewise.
895 (v9a): Likewise.
896 (v9b): Likewise.
897 (v9c): Define.
898 (v9d): Likewise.
899 (v9e): Likewise.
900 (v9v): Likewise.
901 (v9m): Likewise.
902 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
903
3ee6e4fb
NC		 9042016-06-15 Nick Clifton <nickc@redhat.com>
905
906 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
907 constants to match expected behaviour.
908 (nds32_parse_opcode): Likewise. Also for whitespace.
909
02f3be19
AB		 9102016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
911
912 * arc-opc.c (extract_rhv1): Extract value from insn.
913
6f9f37ed 9142016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 915
916 * arc-nps400-tbl.h: Add ldbit instruction.
917 * arc-opc.c: Add flag classes required for ldbit.
918
6f9f37ed 9192016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 920
921 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
922 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
923 support the above instructions.
924
6f9f37ed 9252016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 926
927 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
928 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
929 csma, cbba, zncv, and hofs.
930 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
931 support the above instructions.
932
9332016-06-06 Graham Markall <graham.markall@embecosm.com>
934
935 * arc-nps400-tbl.h: Add andab and orab instructions.
936
9372016-06-06 Graham Markall <graham.markall@embecosm.com>
938
939 * arc-nps400-tbl.h: Add addl-like instructions.
940
9412016-06-06 Graham Markall <graham.markall@embecosm.com>
942
943 * arc-nps400-tbl.h: Add mxb and imxb instructions.
944
9452016-06-06 Graham Markall <graham.markall@embecosm.com>
946
947 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
948 instructions.
949
b2cc3f6f
AK		 9502016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
951
952 * s390-dis.c (option_use_insn_len_bits_p): New file scope
953 variable.
954 (init_disasm): Handle new command line option "insnlength".
955 (print_s390_disassembler_options): Mention new option in help
956 output.
957 (print_insn_s390): Use the encoded insn length when dumping
958 unknown instructions.
959
1857fe72
DC		 9602016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
961
962 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
963 to the address and set as symbol address for LDS/ STS immediate operands.
964
14b57c7c
AM		 9652016-06-07 Alan Modra <amodra@gmail.com>
966
967 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
968 cpu for "vle" to e500.
969 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
970 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
971 (PPCNONE): Delete, substitute throughout.
972 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
973 except for major opcode 4 and 31.
974 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
975
4d1464f2
MW		 9762016-06-07 Matthew Wahab <matthew.wahab@arm.com>
977
978 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
979 ARM_EXT_RAS in relevant entries.
980
026122a6
PB		 9812016-06-03 Peter Bergner <bergner@vnet.ibm.com>
982
983 PR binutils/20196
984 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
985 opcodes for E6500.
986
07f5af7d
L		 9872016-06-03 H.J. Lu <hongjiu.lu@intel.com>
988
989 PR binutis/18386
990 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
991 (indir_v_mode): New.
992 Add comments for '&'.
993 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
994 (putop): Handle '&'.
995 (intel_operand_size): Handle indir_v_mode.
996 (OP_E_register): Likewise.
997 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
998 64-bit indirect call/jmp for AMD64.
999 * i386-tbl.h: Regenerated
1000
4eb6f892
AB		 10012016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1002
1003 * arc-dis.c (struct arc_operand_iterator): New structure.
1004 (find_format_from_table): All the old content from find_format,
1005 with some minor adjustments, and parameter renaming.
1006 (find_format_long_instructions): New function.
1007 (find_format): Rewritten.
1008 (arc_insn_length): Add LSB parameter.
1009 (extract_operand_value): New function.
1010 (operand_iterator_next): New function.
1011 (print_insn_arc): Use new functions to find opcode, and iterator
1012 over operands.
1013 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1014 (extract_nps_3bit_dst_short): New function.
1015 (insert_nps_3bit_src2_short): New function.
1016 (extract_nps_3bit_src2_short): New function.
1017 (insert_nps_bitop1_size): New function.
1018 (extract_nps_bitop1_size): New function.
1019 (insert_nps_bitop2_size): New function.
1020 (extract_nps_bitop2_size): New function.
1021 (insert_nps_bitop_mod4_msb): New function.
1022 (extract_nps_bitop_mod4_msb): New function.
1023 (insert_nps_bitop_mod4_lsb): New function.
1024 (extract_nps_bitop_mod4_lsb): New function.
1025 (insert_nps_bitop_dst_pos3_pos4): New function.
1026 (extract_nps_bitop_dst_pos3_pos4): New function.
1027 (insert_nps_bitop_ins_ext): New function.
1028 (extract_nps_bitop_ins_ext): New function.
1029 (arc_operands): Add new operands.
1030 (arc_long_opcodes): New global array.
1031 (arc_num_long_opcodes): New global.
1032 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1033
1fe0971e
TS		 10342016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1035
1036 * nds32-asm.h: Add extern "C".
1037 * sh-opc.h: Likewise.
1038
315f180f
GM		 10392016-06-01 Graham Markall <graham.markall@embecosm.com>
1040
1041 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1042 0,b,limm to the rflt instruction.
1043
a2b5fccc
TS		 10442016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1045
1046 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1047 constant.
1048
0cbd0046
L		 10492016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1050
1051 PR gas/20145
1052 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1053 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1054 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1055 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1056 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1057 * i386-init.h: Regenerated.
1058
1848e567
L		 10592016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1060
1061 PR gas/20145
1062 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1063 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1064 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1065 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1066 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1067 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1068 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1069 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1070 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1071 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1072 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1073 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1074 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1075 CpuRegMask for AVX512.
1076 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1077 and CpuRegMask.
1078 (set_bitfield_from_cpu_flag_init): New function.
1079 (set_bitfield): Remove const on f. Call
1080 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1081 * i386-opc.h (CpuRegMMX): New.
1082 (CpuRegXMM): Likewise.
1083 (CpuRegYMM): Likewise.
1084 (CpuRegZMM): Likewise.
1085 (CpuRegMask): Likewise.
1086 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1087 and cpuregmask.
1088 * i386-init.h: Regenerated.
1089 * i386-tbl.h: Likewise.
1090
e92bae62
L		 10912016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1092
1093 PR gas/20154
1094 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1095 (opcode_modifiers): Add AMD64 and Intel64.
1096 (main): Properly verify CpuMax.
1097 * i386-opc.h (CpuAMD64): Removed.
1098 (CpuIntel64): Likewise.
1099 (CpuMax): Set to CpuNo64.
1100 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1101 (AMD64): New.
1102 (Intel64): Likewise.
1103 (i386_opcode_modifier): Add amd64 and intel64.
1104 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1105 on call and jmp.
1106 * i386-init.h: Regenerated.
1107 * i386-tbl.h: Likewise.
1108
e89c5eaa
L		 11092016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1110
1111 PR gas/20154
1112 * i386-gen.c (main): Fail if CpuMax is incorrect.
1113 * i386-opc.h (CpuMax): Set to CpuIntel64.
1114 * i386-tbl.h: Regenerated.
1115
77d66e7b
NC		 11162016-05-27 Nick Clifton <nickc@redhat.com>
1117
1118 PR target/20150
1119 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1120 (msp430dis_opcode_unsigned): New function.
1121 (msp430dis_opcode_signed): New function.
1122 (msp430_singleoperand): Use the new opcode reading functions.
1123 Only disassenmble bytes if they were successfully read.
1124 (msp430_doubleoperand): Likewise.
1125 (msp430_branchinstr): Likewise.
1126 (msp430x_callx_instr): Likewise.
1127 (print_insn_msp430): Check that it is safe to read bytes before
1128 attempting disassembly. Use the new opcode reading functions.
1129
19dfcc89
PB		 11302016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1131
1132 * ppc-opc.c (CY): New define. Document it.
1133 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1134
f3ad7637
L		 11352016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1136
1137 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1138 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1139 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1140 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1141 CPU_ANY_AVX_FLAGS.
1142 * i386-init.h: Regenerated.
1143
f1360d58
L		 11442016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1145
1146 PR gas/20141
1147 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1148 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1149 * i386-init.h: Regenerated.
1150
293f5f65
L		 11512016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1152
1153 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1154 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1155 * i386-init.h: Regenerated.
1156
d9eca1df
CZ		 11572016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1158
1159 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1160 information.
1161 (print_insn_arc): Set insn_type information.
1162 * arc-opc.c (C_CC): Add F_CLASS_COND.
1163 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1164 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1165 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1166 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1167 (brne, brne_s, jeq_s, jne_s): Likewise.
1168
87789e08
CZ		 11692016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1170
1171 * arc-tbl.h (neg): New instruction variant.
1172
c810e0b8
CZ		 11732016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1174
1175 * arc-dis.c (find_format, find_format, get_auxreg)
1176 (print_insn_arc): Changed.
1177 * arc-ext.h (INSERT_XOP): Likewise.
1178
3d207518
TS		 11792016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1180
1181 * tic54x-dis.c (sprint_mmr): Adjust.
1182 * tic54x-opc.c: Likewise.
1183
514e58b7
AM		 11842016-05-19 Alan Modra <amodra@gmail.com>
1185
1186 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1187
e43de63c
AM		 11882016-05-19 Alan Modra <amodra@gmail.com>
1189
1190 * ppc-opc.c: Formatting.
1191 (NSISIGNOPT): Define.
1192 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1193
1401d2fe
MR		 11942016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1195
1196 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1197 replacing references to `micromips_ase' throughout.
1198 (_print_insn_mips): Don't use file-level microMIPS annotation to
1199 determine the disassembly mode with the symbol table.
1200
1178da44
PB		 12012016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1202
1203 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1204
8f4f9071
MF		 12052016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1206
1207 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1208 mips64r6.
1209 * mips-opc.c (D34): New macro.
1210 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1211
8bc52696
AF		 12122016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1213
1214 * i386-dis.c (prefix_table): Add RDPID instruction.
1215 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1216 (cpu_flags): Add RDPID bitfield.
1217 * i386-opc.h (enum): Add RDPID element.
1218 (i386_cpu_flags): Add RDPID field.
1219 * i386-opc.tbl: Add RDPID instruction.
1220 * i386-init.h: Regenerate.
1221 * i386-tbl.h: Regenerate.
1222
39d911fc
TP		 12232016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1224
1225 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1226 branch type of a symbol.
1227 (print_insn): Likewise.
1228
16a1fa25
TP		 12292016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1230
1231 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1232 Mainline Security Extensions instructions.
1233 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1234 Extensions instructions.
1235 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1236 instructions.
1237 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1238 special registers.
1239
d751b79e
JM		 12402016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1241
1242 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1243
945e0f82
CZ		 12442016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1245
1246 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1247 (arcExtMap_genOpcode): Likewise.
1248 * arc-opc.c (arg_32bit_rc): Define new variable.
1249 (arg_32bit_u6): Likewise.
1250 (arg_32bit_limm): Likewise.
1251
20f55f38
SN		 12522016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1253
1254 * aarch64-gen.c (VERIFIER): Define.
1255 * aarch64-opc.c (VERIFIER): Define.
1256 (verify_ldpsw): Use static linkage.
1257 * aarch64-opc.h (verify_ldpsw): Remove.
1258 * aarch64-tbl.h: Use VERIFIER for verifiers.
1259
4bd13cde
NC		 12602016-04-28 Nick Clifton <nickc@redhat.com>
1261
1262 PR target/19722
1263 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1264 * aarch64-opc.c (verify_ldpsw): New function.
1265 * aarch64-opc.h (verify_ldpsw): New prototype.
1266 * aarch64-tbl.h: Add initialiser for verifier field.
1267 (LDPSW): Set verifier to verify_ldpsw.
1268
c0f92bf9
L		 12692016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1270
1271 PR binutils/19983
1272 PR binutils/19984
1273 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1274 smaller than address size.
1275
e6c7cdec
TS		 12762016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1277
1278 * alpha-dis.c: Regenerate.
1279 * crx-dis.c: Likewise.
1280 * disassemble.c: Likewise.
1281 * epiphany-opc.c: Likewise.
1282 * fr30-opc.c: Likewise.
1283 * frv-opc.c: Likewise.
1284 * ip2k-opc.c: Likewise.
1285 * iq2000-opc.c: Likewise.
1286 * lm32-opc.c: Likewise.
1287 * lm32-opinst.c: Likewise.
1288 * m32c-opc.c: Likewise.
1289 * m32r-opc.c: Likewise.
1290 * m32r-opinst.c: Likewise.
1291 * mep-opc.c: Likewise.
1292 * mt-opc.c: Likewise.
1293 * or1k-opc.c: Likewise.
1294 * or1k-opinst.c: Likewise.
1295 * tic80-opc.c: Likewise.
1296 * xc16x-opc.c: Likewise.
1297 * xstormy16-opc.c: Likewise.
1298
537aefaf
AB		 12992016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1300
1301 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1302 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1303 calcsd, and calcxd instructions.
1304 * arc-opc.c (insert_nps_bitop_size): Delete.
1305 (extract_nps_bitop_size): Delete.
1306 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1307 (extract_nps_qcmp_m3): Define.
1308 (extract_nps_qcmp_m2): Define.
1309 (extract_nps_qcmp_m1): Define.
1310 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1311 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1312 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1313 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1314 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1315 NPS_QCMP_M3.
1316
c8f785f2
AB		 13172016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1318
1319 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1320
6fd8e7c2
L		 13212016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1322
1323 * Makefile.in: Regenerated with automake 1.11.6.
1324 * aclocal.m4: Likewise.
1325
4b0c052e
AB		 13262016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1327
1328 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1329 instructions.
1330 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1331 (extract_nps_cmem_uimm16): New function.
1332 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1333
cb040366
AB		 13342016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1335
1336 * arc-dis.c (arc_insn_length): New function.
1337 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1338 (find_format): Change insnLen parameter to unsigned.
1339
accc0180
NC		 13402016-04-13 Nick Clifton <nickc@redhat.com>
1341
1342 PR target/19937
1343 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1344 the LD.B and LD.BU instructions.
1345
f36e33da
CZ		 13462016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1347
1348 * arc-dis.c (find_format): Check for extension flags.
1349 (print_flags): New function.
1350 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1351 .extAuxRegister.
1352 * arc-ext.c (arcExtMap_coreRegName): Use
1353 LAST_EXTENSION_CORE_REGISTER.
1354 (arcExtMap_coreReadWrite): Likewise.
1355 (dump_ARC_extmap): Update printing.
1356 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1357 (arc_aux_regs): Add cpu field.
1358 * arc-regs.h: Add cpu field, lower case name aux registers.
1359
1c2e355e
CZ		 13602016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1361
1362 * arc-tbl.h: Add rtsc, sleep with no arguments.
1363
b99747ae
CZ		 13642016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1365
1366 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1367 Initialize.
1368 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1369 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1370 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1371 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1372 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1373 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1374 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1375 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1376 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1377 (arc_opcode arc_opcodes): Null terminate the array.
1378 (arc_num_opcodes): Remove.
1379 * arc-ext.h (INSERT_XOP): Define.
1380 (extInstruction_t): Likewise.
1381 (arcExtMap_instName): Delete.
1382 (arcExtMap_insn): New function.
1383 (arcExtMap_genOpcode): Likewise.
1384 * arc-ext.c (ExtInstruction): Remove.
1385 (create_map): Zero initialize instruction fields.
1386 (arcExtMap_instName): Remove.
1387 (arcExtMap_insn): New function.
1388 (dump_ARC_extmap): More info while debuging.
1389 (arcExtMap_genOpcode): New function.
1390 * arc-dis.c (find_format): New function.
1391 (print_insn_arc): Use find_format.
1392 (arc_get_disassembler): Enable dump_ARC_extmap only when
1393 debugging.
1394
92708cec
MR		 13952016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1396
1397 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1398 instruction bits out.
1399
a42a4f84
AB		 14002016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1401
1402 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1403 * arc-opc.c (arc_flag_operands): Add new flags.
1404 (arc_flag_classes): Add new classes.
1405
1328504b
AB		 14062016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1407
1408 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1409
820f03ff
AB		 14102016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1411
1412 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1413 encode1, rflt, crc16, and crc32 instructions.
1414 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1415 (arc_flag_classes): Add C_NPS_R.
1416 (insert_nps_bitop_size_2b): New function.
1417 (extract_nps_bitop_size_2b): Likewise.
1418 (insert_nps_bitop_uimm8): Likewise.
1419 (extract_nps_bitop_uimm8): Likewise.
1420 (arc_operands): Add new operand entries.
1421
8ddf6b2a
CZ		 14222016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1423
b99747ae
CZ		 1424 * arc-regs.h: Add a new subclass field. Add double assist
1425 accumulator register values.
1426 * arc-tbl.h: Use DPA subclass to mark the double assist
1427 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1428 * arc-opc.c (RSP): Define instead of SP.
1429 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1430
589a7d88
JW		 14312016-04-05 Jiong Wang <jiong.wang@arm.com>
1432
1433 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1434
0a191de9 14352016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1436
1437 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1438 NPS_R_SRC1.
1439
0a106562
AB		 14402016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1441
1442 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1443 issues. No functional changes.
1444
bd05ac5f
CZ		 14452016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1446
b99747ae
CZ		 1447 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1448 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1449 (RTT): Remove duplicate.
1450 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1451 (PCT_CONFIG*): Remove.
1452 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1453
9885948f
CZ		 14542016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1455
b99747ae 1456 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1457
f2dd8838
CZ		 14582016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1459
b99747ae
CZ		 1460 * arc-tbl.h (invld07): Remove.
1461 * arc-ext-tbl.h: New file.
1462 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1463 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1464
0d2f91fe
JK		 14652016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1466
1467 Fix -Wstack-usage warnings.
1468 * aarch64-dis.c (print_operands): Substitute size.
1469 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1470
a6b71f42
JM		 14712016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1472
1473 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1474 to get a proper diagnostic when an invalid ASR register is used.
1475
9780e045
NC		 14762016-03-22 Nick Clifton <nickc@redhat.com>
1477
1478 * configure: Regenerate.
1479
e23e8ebe
AB		 14802016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1481
1482 * arc-nps400-tbl.h: New file.
1483 * arc-opc.c: Add top level comment.
1484 (insert_nps_3bit_dst): New function.
1485 (extract_nps_3bit_dst): New function.
1486 (insert_nps_3bit_src2): New function.
1487 (extract_nps_3bit_src2): New function.
1488 (insert_nps_bitop_size): New function.
1489 (extract_nps_bitop_size): New function.
1490 (arc_flag_operands): Add nps400 entries.
1491 (arc_flag_classes): Add nps400 entries.
1492 (arc_operands): Add nps400 entries.
1493 (arc_opcodes): Add nps400 include.
1494
1ae8ab47
AB		 14952016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1496
1497 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1498 the new class enum values.
1499
8699fc3e
AB		 15002016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1501
1502 * arc-dis.c (print_insn_arc): Handle nps400.
1503
24740d83
AB		 15042016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1505
1506 * arc-opc.c (BASE): Delete.
1507
8678914f
NC		 15082016-03-18 Nick Clifton <nickc@redhat.com>
1509
1510 PR target/19721
1511 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1512 of MOV insn that aliases an ORR insn.
1513
cc933301
JW		 15142016-03-16 Jiong Wang <jiong.wang@arm.com>
1515
1516 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1517
f86f5863
TS		 15182016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1519
1520 * mcore-opc.h: Add const qualifiers.
1521 * microblaze-opc.h (struct op_code_struct): Likewise.
1522 * sh-opc.h: Likewise.
1523 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1524 (tic4x_print_op): Likewise.
1525
62de1c63
AM		 15262016-03-02 Alan Modra <amodra@gmail.com>
1527
d11698cd 1528 * or1k-desc.h: Regenerate.
62de1c63 1529 * fr30-ibld.c: Regenerate.
c697cf0b 1530 * rl78-decode.c: Regenerate.
62de1c63 1531
020efce5
NC		 15322016-03-01 Nick Clifton <nickc@redhat.com>
1533
1534 PR target/19747
1535 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1536
b0c11777
RL		 15372016-02-24 Renlin Li <renlin.li@arm.com>
1538
1539 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1540 (print_insn_coprocessor): Support fp16 instructions.
1541
3e309328
RL		 15422016-02-24 Renlin Li <renlin.li@arm.com>
1543
1544 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1545 vminnm, vrint(mpna).
1546
8afc7bea
RL		 15472016-02-24 Renlin Li <renlin.li@arm.com>
1548
1549 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1550 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1551
4fd7268a
L		 15522016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1553
1554 * i386-dis.c (print_insn): Parenthesize expression to prevent
1555 truncated addresses.
1556 (OP_J): Likewise.
1557
4670103e
CZ		 15582016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1559 Janek van Oirschot <jvanoirs@synopsys.com>
1560
b99747ae
CZ		 1561 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1562 variable.
4670103e 1563
c1d9289f
NC		 15642016-02-04 Nick Clifton <nickc@redhat.com>
1565
1566 PR target/19561
1567 * msp430-dis.c (print_insn_msp430): Add a special case for
1568 decoding an RRC instruction with the ZC bit set in the extension
1569 word.
1570
a143b004
AB		 15712016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1572
1573 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1574 * epiphany-ibld.c: Regenerate.
1575 * fr30-ibld.c: Regenerate.
1576 * frv-ibld.c: Regenerate.
1577 * ip2k-ibld.c: Regenerate.
1578 * iq2000-ibld.c: Regenerate.
1579 * lm32-ibld.c: Regenerate.
1580 * m32c-ibld.c: Regenerate.
1581 * m32r-ibld.c: Regenerate.
1582 * mep-ibld.c: Regenerate.
1583 * mt-ibld.c: Regenerate.
1584 * or1k-ibld.c: Regenerate.
1585 * xc16x-ibld.c: Regenerate.
1586 * xstormy16-ibld.c: Regenerate.
1587
b89807c6
AB		 15882016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1589
1590 * epiphany-dis.c: Regenerated from latest cpu files.
1591
d8c823c8
MM		 15922016-02-01 Michael McConville <mmcco@mykolab.com>
1593
1594 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1595 test bit.
1596
5bc5ae88
RL		 15972016-01-25 Renlin Li <renlin.li@arm.com>
1598
1599 * arm-dis.c (mapping_symbol_for_insn): New function.
1600 (find_ifthen_state): Call mapping_symbol_for_insn().
1601
0bff6e2d
MW		 16022016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1603
1604 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1605 of MSR UAO immediate operand.
1606
100b4f2e
MR		 16072016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1608
1609 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1610 instruction support.
1611
5c14705f
AM		 16122016-01-17 Alan Modra <amodra@gmail.com>
1613
1614 * configure: Regenerate.
1615
4d82fe66
NC		 16162016-01-14 Nick Clifton <nickc@redhat.com>
1617
1618 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1619 instructions that can support stack pointer operations.
1620 * rl78-decode.c: Regenerate.
1621 * rl78-dis.c: Fix display of stack pointer in MOVW based
1622 instructions.
1623
651657fa
MW		 16242016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1625
1626 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1627 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1628 erxtatus_el1 and erxaddr_el1.
1629
105bde57
MW		 16302016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1631
1632 * arm-dis.c (arm_opcodes): Add "esb".
1633 (thumb_opcodes): Likewise.
1634
afa8d405
PB		 16352016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1636
1637 * ppc-opc.c <xscmpnedp>: Delete.
1638 <xvcmpnedp>: Likewise.
1639 <xvcmpnedp.>: Likewise.
1640 <xvcmpnesp>: Likewise.
1641 <xvcmpnesp.>: Likewise.
1642
83c3256e
AS		 16432016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1644
1645 PR gas/13050
1646 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1647 addition to ISA_A.
1648
6f2750fe
AM		 16492016-01-01 Alan Modra <amodra@gmail.com>
1650
1651 Update year range in copyright notice of all files.
1652
3499769a
AM		 1653For older changes see ChangeLog-2015
1654\f
1655Copyright (C) 2016 Free Software Foundation, Inc.
1656
1657Copying and distribution of this file, with or without modification,
1658are permitted in any medium without royalty provided the copyright
1659notice and this notice are preserved.
1660
1661Local Variables:
1662mode: change-log
1663left-margin: 8
1664fill-column: 74
1665version-control: never
1666End:
GDB Binutils - Deliverables
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