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[AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift By Immediate instructions.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
b5b0f34c
MW		 12015-12-14 Matthew Wahab <matthew.wahab@arm.com>
2
3 * aarch64-asm-2.c: Regenerate.
4 * aarch64-dis-2.c: Regenerate.
5 * aarch64-opc-2.c: Regenerate.
6 * aarch64-tbl.h (QL_VSHIFT_H): New.
7 (aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
8 and fcvtzu to the Adv.SIMD shift by immediate group.
9
b195470d
MW		 102015-12-14 Matthew Wahab <matthew.wahab@arm.com>
11
12 * aarch64-asm-2.c: Regenerate.
13 * aarch64-dis-2.c: Regenerate.
14 * aarch64-opc-2.c: Regenerate.
15 * aarch64-tbl.h (QL_SISD_PAIR_H): New.
16 (aarch64_opcode_table): Add fp16 versions of fmaxnmp, faddp,
17 fmaxp, fminnmp, fminp to the Adv.SIMD scalar pairwise group.
18
3067d3b9
MW		 192015-12-14 Matthew Wahab <matthew.wahab@arm.coM>
20
21 * aarch64-dis.c (get_vreg_qualifier_from_value): Update comment
22 and adjust calculation to ignore qualifier for type 2H.
23 * aarch64-opc.c (aarch64_opnd_qualifier): Add "2H".
24
4b5fc357
MW		 252015-12-14 Matthew Wahab <matthew.wahab@arm.com>
26
27 * aarch64-asm-2.c: Regenerate.
28 * aarch64-dis-2.c: Regenerate.
29 * aarch64-opc-2.c: Regenerate.
30 * aarch64-tbl.h (QL_SIMD_IMM_H): New.
31 (aarch64_opcode_table): Add fp16 version of fmov to the Adv.SIMD
32 modified immediate group.
33
bb515fea
MW		 342015-12-14 Matthew Wahab <matthew.wahab@arm.com>
35
36 * aarch64-asm-2.c: Regenerate.
37 * aarch64-dis-2.c: Regenerate.
38 * aarch64-opc-2.c: Regenerate.
39 * aarch64-tbl.h (QL_XLANES_FP_H): New.
40 (aarch64_opcode_table): Add fp16 versions of fmaxnmv, fmaxv,
41 fminnmv, fminv to the Adv.SIMD across lanes group.
42
5f7728b7
MW		 432015-12-14 Matthew Wahab <matthew.wahab@arm.com>
44
45 * aarch64-asm-2.c: Regenerate.
46 * aarch64-dis-2.c: Regenerate.
47 * aarch64-opc-2.c: Regenerate.
48 * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmla,
49 fmls, fmul and fmulx to the scalar indexed element group.
50
42f23f62
MW		 512015-12-14 Matthew Wahab <matthew.wahab@arm.com>
52
53 * aarch64-asm-2.c: Regenerate.
54 * aarch64-dis-2.c: Regenerate.
55 * aarch64-opc-2.c: Regenerate.
56 * aarch64-tbl.h (QL_ELEMENT_FP_H): New.
57 (aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and
58 fmulx to the vector indexed element group.
59
80776b29
MW		 602015-12-14 Matthew Wahab <matthew.wahab@arm.com>
61
62 * aarch64-asm-2.c: Regenerate.
63 * aarch64-dis-2.c: Regenerate.
64 * aarch64-opc-2.c: Regenerate.
65 * aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
66 (QL_S_2SAMEH): New.
67 (aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
68 fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
69 frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
70 fcvtzu and frsqrte to the scalar two register misc. group.
71
f3aa142b
MW		 722015-12-14 Matthew Wahab <matthew.wahab@arm.com>
73
74 * aarch64-asm-2.c: Regenerate.
75 * aarch64-dis-2.c: Regenerate.
76 * aarch64-opc-2.c: Regenerate.
77 * aarch64-tbl.h (QL_V2SAMEH): New.
78 (aarch64_opcode_table): Add fp16 versions of frintn, frintm,
79 fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
80 frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
81 fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
82 and fsqrt to the vector register misc. group.
83
6b4680fb
MW		 842015-12-14 Matthew Wahab <matthew.wahab@arm.com>
85
86 * aarch64-asm-2.c: Regenerate.
87 * aarch64-dis-2.c: Regenerate.
88 * aarch64-opc-2.c: Regenerate.
89 * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
90 fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and facgt
91 to the scalar three same group.
92
51d543ed
MW		 932015-12-14 Matthew Wahab <matthew.wahab@arm.com>
94
95 * aarch64-asm-2.c: Regenerate.
96 * aarch64-dis-2.c: Regenerate.
97 * aarch64-opc-2.c: Regenerate.
98 * aarch64-tbl.h (QL_V3SAMEH): New.
99 (aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
100 fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
101 fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
102 fcmgt, facgt and fminp to the vector three same group.
103
40d16a76
MW		 1042015-12-14 Matthew Wahab <matthew.wahab@arm.com>
105
106 * aarch64-tbl.h (aarch64_feature_simd_f16): New.
107 (SIMD_F16): New.
108
63511907
MW		 1092015-12-14 Matthew Wahab <matthew.wahab@arm.com>
110
111 * aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly
112 removed statement.
113 (aarch64_pstatefield_supported_p): Move feature checks for AT
114 registers ..
115 (aarch64_sys_ins_reg_supported_p): .. to here.
116
b817670b
AM		 1172015-12-12 Alan Modra <amodra@gmail.com>
118
119 PR 19359
120 * ppc-opc.c (insert_fxm): Remove "ignored" from error message.
121 (powerpc_opcodes): Remove single-operand mfcr.
122
9ed608f9
MW		 1232015-12-11 Matthew Wahab <matthew.wahab@arm.com>
124
125 * aarch64-asm.c (aarch64_ins_hint): New.
126 * aarch64-asm.h (aarch64_ins_hint): Declare.
127 * aarch64-dis.c (aarch64_ext_hint): New.
128 * aarch64-dis.h (aarch64_ext_hint): Declare.
129 * aarch64-opc-2.c: Regenerate.
130 * aarch64-opc.c (aarch64_hint_options): New.
131 * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
132
a0f7013a
MW		 1332015-12-11 Matthew Wahab <matthew.wahab@arm.com>
134
135 * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
136
55c144e6
MW		 1372015-12-11 Matthew Wahab <matthew.wahab@arm.com>
138
139 * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
140 pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
141 pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
142 pmscr_el2.
143 (aarch64_sys_reg_supported_p): Add architecture feature tests for
144 the new registers.
145
22a5455c
MW		 1462015-12-10 Matthew Wahab <matthew.wahab@arm.com>
147
148 * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
149 (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
150 feature test for "s1e1rp" and "s1e1wp".
151
d6bf7ce6
MW		 1522015-12-10 Matthew Wahab <matthew.wahab@arm.com>
153
154 * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
155 (aarch64_sys_ins_reg_supported_p): New.
156
ea2deeec
MW		 1572015-12-10 Matthew Wahab <matthew.wahab@arm.com>
158
159 * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
160 with aarch64_sys_ins_reg_has_xt.
161 (aarch64_ext_sysins_op): Likewise.
162 * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
163 (F_HASXT): New.
164 (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
165 (aarch64_sys_regs_dc): Likewise.
166 (aarch64_sys_regs_at): Likewise.
167 (aarch64_sys_regs_tlbi): Likewise.
168 (aarch64_sys_ins_reg_has_xt): New.
169
6479e48e
MW		 1702015-12-10 Matthew Wahab <matthew.wahab@arm.com>
171
172 * aarch64-opc.c (aarch64_sys_regs): Add "uao".
173 (aarch64_sys_reg_supported_p): Add comment. Add checks for "uao".
174 (aarch64_pstatefields): Add "uao".
175 (aarch64_pstatefield_supported_p): Add checks for "uao".
176
47f81142
MW		 1772015-12-10 Matthew Wahab <matthew.wahab@arm.com>
178
179 * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
180 "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
181 "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
182 (aarch64_sys_reg_supported_p): Add architecture feature tests for
183 new registers.
184
c8a6db6f
MW		 1852015-12-10 Matthew Wahab <matthew.wahab@arm.com>
186
187 * aarch64-asm-2.c: Regenerate.
188 * aarch64-dis-2.c: Regenerate.
189 * aarch64-tbl.h (aarch64_feature_ras): New.
190 (RAS): New.
191 (aarch64_opcode_table): Add "esb".
192
8eab4136
L		 1932015-12-09 H.J. Lu <hongjiu.lu@intel.com>
194
195 * i386-dis.c (MOD_0F01_REG_5): New.
196 (RM_0F01_REG_5): Likewise.
197 (reg_table): Use MOD_0F01_REG_5.
198 (mod_table): Add MOD_0F01_REG_5.
199 (rm_table): Add RM_0F01_REG_5.
200 * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
201 (cpu_flags): Add CpuOSPKE.
202 * i386-opc.h (CpuOSPKE): New.
203 (i386_cpu_flags): Add cpuospke.
204 * i386-opc.tbl: Add rdpkru and wrpkru instructions.
205 * i386-init.h: Regenerated.
206 * i386-tbl.h: Likewise.
207
1eac08cc
DD		 2082015-12-07 DJ Delorie <dj@redhat.com>
209
210 * rl78-decode.opc: Enable MULU for all ISAs.
211 * rl78-decode.c: Regenerate.
212
dd2887fc
AM		 2132015-12-07 Alan Modra <amodra@gmail.com>
214
215 * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
216 major opcode/xop.
217
24b368f8
CZ		 2182015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
219
220 * arc-dis.c (special_flag_p): Match full mnemonic.
221 * arc-opc.c (print_insn_arc): Check section size to read
222 appropriate number of bytes. Fix printing.
223 * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
224 arguments.
225
3395762e
AV		 2262015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
227
228 * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
229 <ldah>: ... to this.
230
622b9eb1
MW		 2312015-11-27 Matthew Wahab <matthew.wahab@arm.com>
232
233 * aarch64-asm-2.c: Regenerate.
234 * aarch64-dis-2.c: Regenerate.
235 * aarch64-opc-2.c: Regenerate.
236 * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
237 (QL_INT2FP_H, QL_FP2INT_H): New.
238 (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
239 (QL_DST_H): New.
240 (QL_FCCMP_H): New.
241 (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
242 fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
243 fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
244 fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
245 frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
246 fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
247 fcsel.
248
cf86120b
MW		 2492015-11-27 Matthew Wahab <matthew.wahab@arm.com>
250
251 * aarch64-opc.c (half_conv_t): New.
252 (expand_fp_imm): Replace is_dp flag with the parameter size to
253 specify the number of bytes for the required expansion. Treat
254 a 16-bit expansion like a 32-bit expansion. Add check for an
255 unsupported size request. Update comment.
256 (aarch64_print_operand): Update to support 16-bit floating point
257 values. Update for changes to expand_fp_imm.
258
3bd894a7
MW		 2592015-11-27 Matthew Wahab <matthew.wahab@arm.com>
260
261 * aarch64-tbl.h (aarch64_feature_fp_f16): New.
262 (FP_F16): New.
263
64357d2e
MW		 2642015-11-27 Matthew Wahab <matthew.wahab@arm.com>
265
266 * aarch64-asm-2.c: Regenerate.
267 * aarch64-dis-2.c: Regenerate.
268 * aarch64-opc-2.c: Regenerate.
269 * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
270 "rev64".
271
d685192a
MW		 2722015-11-27 Matthew Wahab <matthew.wahab@arm.com>
273
274 * aarch64-asm-2.c: Regenerate.
275 * aarch64-asm.c (convert_bfc_to_bfm): New.
276 (convert_to_real): Add case for OP_BFC.
277 * aarch64-dis-2.c: Regenerate.
278 * aarch64-dis.c: (convert_bfm_to_bfc): New.
279 (convert_to_alias): Add case for OP_BFC.
280 * aarch64-opc-2.c: Regenerate.
281 * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
282 to allow width operand in three-operand instructions.
283 * aarch64-tbl.h (QL_BF1): New.
284 (aarch64_feature_v8_2): New.
285 (ARMV8_2): New.
286 (aarch64_opcode_table): Add "bfc".
287
35822b38
MW		 2882015-11-27 Matthew Wahab <matthew.wahab@arm.com>
289
290 * aarch64-asm-2.c: Regenerate.
291 * aarch64-dis-2.c: Regenerate.
292 * aarch64-dis.c: Weaken assert.
293 * aarch64-gen.c: Include the instruction in the list of its
294 possible aliases.
295
1a04d1a7
MW		 2962015-11-27 Matthew Wahab <matthew.wahab@arm.com>
297
298 * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
299 (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
300 feature test.
301
e49d43ff
TG		 3022015-11-23 Tristan Gingold <gingold@adacore.com>
303
304 * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
305
250aafa4
MW		 3062015-11-20 Matthew Wahab <matthew.wahab@arm.com>
307
308 * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
309 sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
310 tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
311 amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
312 cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
313 cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
314 cnthv_ctl_el2, cnthv_cval_el2.
315 (aarch64_sys_reg_supported_p): Update for the new system
316 registers.
317
a915c10f
NC		 3182015-11-20 Nick Clifton <nickc@redhat.com>
319
320 PR binutils/19224
321 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
322
f8c2a965
NC		 3232015-11-20 Nick Clifton <nickc@redhat.com>
324
325 * po/zh_CN.po: Updated simplified Chinese translation.
326
c2825638
MW		 3272015-11-19 Matthew Wahab <matthew.wahab@arm.com>
328
329 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
330 of MSR PAN immediate operand.
331
e7286c56
NC		 3322015-11-16 Nick Clifton <nickc@redhat.com>
333
334 * rx-dis.c (condition_names): Replace always and never with
335 invalid, since the always/never conditions can never be legal.
336
d8bd95ef
TG		 3372015-11-13 Tristan Gingold <gingold@adacore.com>
338
339 * configure: Regenerate.
340
a680de9a
PB		 3412015-11-11 Alan Modra <amodra@gmail.com>
342 Peter Bergner <bergner@vnet.ibm.com>
343
344 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
345 Add PPC_OPCODE_VSX3 to the vsx entry.
346 (powerpc_init_dialect): Set default dialect to power9.
347 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
348 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
349 extract_l1 insert_xtq6, extract_xtq6): New static functions.
350 (insert_esync): Test for illegal L operand value.
351 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
352 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
353 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
354 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
355 PPCVSX3): New defines.
356 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
357 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
358 <mcrxr>: Use XBFRARB_MASK.
359 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
360 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
361 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
362 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
363 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
364 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
365 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
366 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
367 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
368 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
369 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
370 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
371 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
372 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
373 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
374 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
375 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
376 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
377 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
378 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
379 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
380 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
381 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
382 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
383 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
384 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
385 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
386 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
387 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
388 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
389 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
390 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
391
854eb72b
NC		 3922015-11-02 Nick Clifton <nickc@redhat.com>
393
394 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
395 instructions.
396 * rx-decode.c: Regenerate.
397
e292aa7a
NC		 3982015-11-02 Nick Clifton <nickc@redhat.com>
399
400 * rx-decode.opc (rx_disp): If the displacement is zero, set the
401 type to RX_Operand_Zero_Indirect.
402 * rx-decode.c: Regenerate.
403 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
404
43cdf5ae
YQ		 4052015-10-28 Yao Qi <yao.qi@linaro.org>
406
407 * aarch64-dis.c (aarch64_decode_insn): Add one argument
408 noaliases_p. Update comments. Pass noaliases_p rather than
409 no_aliases to aarch64_opcode_decode.
410 (print_insn_aarch64_word): Pass no_aliases to
411 aarch64_decode_insn.
412
c2f28758
VK		 4132015-10-27 Vinay <Vinay.G@kpit.com>
414
415 PR binutils/19159
416 * rl78-decode.opc (MOV): Added offset to DE register in index
417 addressing mode.
418 * rl78-decode.c: Regenerate.
419
46662804
VK		 4202015-10-27 Vinay Kumar <vinay.g@kpit.com>
421
422 PR binutils/19158
423 * rl78-decode.opc: Add 's' print operator to instructions that
424 access system registers.
425 * rl78-decode.c: Regenerate.
426 * rl78-dis.c (print_insn_rl78_common): Decode all system
427 registers.
428
02f12cd4
VK		 4292015-10-27 Vinay Kumar <vinay.g@kpit.com>
430
431 PR binutils/19157
432 * rl78-decode.opc: Add 'a' print operator to mov instructions
433 using stack pointer plus index addressing.
434 * rl78-decode.c: Regenerate.
435
485f23cf
AK		 4362015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
437
438 * s390-opc.c: Fix comment.
439 * s390-opc.txt: Change instruction type for troo, trot, trto, and
440 trtt to RRF_U0RER since the second parameter does not need to be a
441 register pair.
442
3f94e60d
NC		 4432015-10-08 Nick Clifton <nickc@redhat.com>
444
445 * arc-dis.c (print_insn_arc): Initiallise insn array.
446
875880c6
YQ		 4472015-10-07 Yao Qi <yao.qi@linaro.org>
448
449 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
450 'name' rather than 'template'.
451 * aarch64-opc.c (aarch64_print_operand): Likewise.
452
886a2506
NC		 4532015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
454
455 * arc-dis.c: Revamped file for ARC support
456 * arc-dis.h: Likewise.
457 * arc-ext.c: Likewise.
458 * arc-ext.h: Likewise.
459 * arc-opc.c: Likewise.
460 * arc-fxi.h: New file.
461 * arc-regs.h: Likewise.
462 * arc-tbl.h: Likewise.
463
36f4aab1
YQ		 4642015-10-02 Yao Qi <yao.qi@linaro.org>
465
466 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
467 argument insn type to aarch64_insn. Rename to ...
468 (aarch64_decode_insn): ... it.
469 (print_insn_aarch64_word): Caller updated.
470
7232d389
YQ		 4712015-10-02 Yao Qi <yao.qi@linaro.org>
472
473 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
474 (print_insn_aarch64_word): Caller updated.
475
7ecc513a
DV		 4762015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
477
478 * s390-mkopc.c (main): Parse htm and vx flag.
479 * s390-opc.txt: Mark instructions from the hardware transactional
480 memory and vector facilities with the "htm"/"vx" flag.
481
b08b78e7
NC		 4822015-09-28 Nick Clifton <nickc@redhat.com>
483
484 * po/de.po: Updated German translation.
485
36f7a941
TR		 4862015-09-28 Tom Rix <tom@bumblecow.com>
487
488 * ppc-opc.c (PPC500): Mark some opcodes as invalid
489
b6518b38
NC		 4902015-09-23 Nick Clifton <nickc@redhat.com>
491
492 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
493 function.
494 * tic30-dis.c (print_branch): Likewise.
495 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
496 value before left shifting.
497 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
498 * hppa-dis.c (print_insn_hppa): Likewise.
499 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
500 array.
501 * msp430-dis.c (msp430_singleoperand): Likewise.
502 (msp430_doubleoperand): Likewise.
503 (print_insn_msp430): Likewise.
504 * nds32-asm.c (parse_operand): Likewise.
505 * sh-opc.h (MASK): Likewise.
506 * v850-dis.c (get_operand_value): Likewise.
507
f04265ec
NC		 5082015-09-22 Nick Clifton <nickc@redhat.com>
509
510 * rx-decode.opc (bwl): Use RX_Bad_Size.
511 (sbwl): Likewise.
512 (ubwl): Likewise. Rename to ubw.
513 (uBWL): Rename to uBW.
514 Replace all references to uBWL with uBW.
515 * rx-decode.c: Regenerate.
516 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
517 (opsize_names): Likewise.
518 (print_insn_rx): Detect and report RX_Bad_Size.
519
6dca4fd1
AB		 5202015-09-22 Anton Blanchard <anton@samba.org>
521
522 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
523
38074311
JM		 5242015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
525
526 * sparc-dis.c (print_insn_sparc): Handle the privileged register
527 %pmcdper.
528
5f40e14d
JS		 5292015-08-24 Jan Stancek <jstancek@redhat.com>
530
531 * i386-dis.c (print_insn): Fix decoding of three byte operands.
532
ab4e4ed5
AF		 5332015-08-21 Alexander Fomin <alexander.fomin@intel.com>
534
535 PR binutils/18257
536 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
537 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
538 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
539 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
540 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
541 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
542 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
543 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
544 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
545 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
546 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
547 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
548 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
549 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
550 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
551 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
552 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
553 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
554 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
555 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
556 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
557 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
558 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
559 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
560 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
561 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
562 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
563 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
564 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
565 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
566 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
567 (vex_w_table): Replace terminals with MOD_TABLE entries for
568 most of mask instructions.
569
919b75f7
AM		 5702015-08-17 Alan Modra <amodra@gmail.com>
571
572 * cgen.sh: Trim trailing space from cgen output.
573 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
574 (print_dis_table): Likewise.
575 * opc2c.c (dump_lines): Likewise.
576 (orig_filename): Warning fix.
577 * ia64-asmtab.c: Regenerate.
578
4ab90a7a
AV		 5792015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
580
581 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
582 and higher with ARM instruction set will now mark the 26-bit
583 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
584 (arm_opcodes): Fix for unpredictable nop being recognized as a
585 teq.
586
40fc1451
SD		 5872015-08-12 Simon Dardis <simon.dardis@imgtec.com>
588
589 * micromips-opc.c (micromips_opcodes): Re-order table so that move
590 based on 'or' is first.
591 * mips-opc.c (mips_builtin_opcodes): Ditto.
592
922c5db5
NC		 5932015-08-11 Nick Clifton <nickc@redhat.com>
594
595 PR 18800
596 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
597 instruction.
598
75fb7498
RS		 5992015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
600
601 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
602
36aed29d
AP		 6032015-08-07 Amit Pawar <Amit.Pawar@amd.com>
604
605 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
606 * i386-init.h: Regenerated.
607
a8484f96
L		 6082015-07-30 H.J. Lu <hongjiu.lu@intel.com>
609
610 PR binutils/13571
611 * i386-dis.c (MOD_0FC3): New.
612 (PREFIX_0FC3): Renamed to ...
613 (PREFIX_MOD_0_0FC3): This.
614 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
615 (prefix_table): Replace Ma with Ev on movntiS.
616 (mod_table): Add MOD_0FC3.
617
37a42ee9
L		 6182015-07-27 H.J. Lu <hongjiu.lu@intel.com>
619
620 * configure: Regenerated.
621
070fe95d
AM		 6222015-07-23 Alan Modra <amodra@gmail.com>
623
624 PR 18708
625 * i386-dis.c (get64): Avoid signed integer overflow.
626
20c2a615
L		 6272015-07-22 Alexander Fomin <alexander.fomin@intel.com>
628
629 PR binutils/18631
630 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
631 "EXEvexHalfBcstXmmq" for the second operand.
632 (EVEX_W_0F79_P_2): Likewise.
633 (EVEX_W_0F7A_P_2): Likewise.
634 (EVEX_W_0F7B_P_2): Likewise.
635
6f1c2142
AM		 6362015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
637
638 * arm-dis.c (print_insn_coprocessor): Added support for quarter
639 float bitfield format.
640 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
641 quarter float bitfield format.
642
8a643cc3
L		 6432015-07-14 H.J. Lu <hongjiu.lu@intel.com>
644
645 * configure: Regenerated.
646
ef5a96d5
AM		 6472015-07-03 Alan Modra <amodra@gmail.com>
648
649 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
650 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
651 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
652
c8c8175b
SL		 6532015-07-01 Sandra Loosemore <sandra@codesourcery.com>
654 Cesar Philippidis <cesar@codesourcery.com>
655
656 * nios2-dis.c (nios2_extract_opcode): New.
657 (nios2_disassembler_state): New.
658 (nios2_find_opcode_hash): Use mach parameter to select correct
659 disassembler state.
660 (nios2_print_insn_arg): Extend to support new R2 argument letters
661 and formats.
662 (print_insn_nios2): Check for 16-bit instruction at end of memory.
663 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
664 (NIOS2_NUM_OPCODES): Rename to...
665 (NIOS2_NUM_R1_OPCODES): This.
666 (nios2_r2_opcodes): New.
667 (NIOS2_NUM_R2_OPCODES): New.
668 (nios2_num_r2_opcodes): New.
669 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
670 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
671 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
672 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
673 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
674
9916071f
AP		 6752015-06-30 Amit Pawar <Amit.Pawar@amd.com>
676
677 * i386-dis.c (OP_Mwaitx): New.
678 (rm_table): Add monitorx/mwaitx.
679 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
680 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
681 (operand_type_init): Add CpuMWAITX.
682 * i386-opc.h (CpuMWAITX): New.
683 (i386_cpu_flags): Add cpumwaitx.
684 * i386-opc.tbl: Add monitorx and mwaitx.
685 * i386-init.h: Regenerated.
686 * i386-tbl.h: Likewise.
687
7b934113
PB		 6882015-06-22 Peter Bergner <bergner@vnet.ibm.com>
689
690 * ppc-opc.c (insert_ls): Test for invalid LS operands.
691 (insert_esync): New function.
692 (LS, WC): Use insert_ls.
693 (ESYNC): Use insert_esync.
694
bdc4de1b
NC		 6952015-06-22 Nick Clifton <nickc@redhat.com>
696
697 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
698 requested region lies beyond it.
699 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
700 looking for 32-bit insns.
701 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
702 data.
703 * sh-dis.c (print_insn_sh): Likewise.
704 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
705 blocks of instructions.
706 * vax-dis.c (print_insn_vax): Check that the requested address
707 does not clash with the stop_vma.
708
11a0cf2e
PB		 7092015-06-19 Peter Bergner <bergner@vnet.ibm.com>
710
070fe95d 711 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 712 * ppc-opc.c (FXM4): Add non-zero optional value.
713 (TBR): Likewise.
714 (SXL): Likewise.
715 (insert_fxm): Handle new default operand value.
716 (extract_fxm): Likewise.
717 (insert_tbr): Likewise.
718 (extract_tbr): Likewise.
719
bdfa8b95
MW		 7202015-06-16 Matthew Wahab <matthew.wahab@arm.com>
721
722 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
723
24b4cf66
SN		 7242015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
725
726 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
727
99a2c561
PB		 7282015-06-12 Peter Bergner <bergner@vnet.ibm.com>
729
730 * ppc-opc.c: Add comment accidentally removed by old commit.
731 (MTMSRD_L): Delete.
732
40f77f82
AM		 7332015-06-04 Peter Bergner <bergner@vnet.ibm.com>
734
735 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
736
13be46a2
NC		 7372015-06-04 Nick Clifton <nickc@redhat.com>
738
739 PR 18474
740 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
741
ddfded2f
MW		 7422015-06-02 Matthew Wahab <matthew.wahab@arm.com>
743
744 * arm-dis.c (arm_opcodes): Add "setpan".
745 (thumb_opcodes): Add "setpan".
746
1af1dd51
MW		 7472015-06-02 Matthew Wahab <matthew.wahab@arm.com>
748
749 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
750 macros.
751
9e1f0fa7
MW		 7522015-06-02 Matthew Wahab <matthew.wahab@arm.com>
753
754 * aarch64-tbl.h (aarch64_feature_rdma): New.
755 (RDMA): New.
756 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
757 * aarch64-asm-2.c: Regenerate.
758 * aarch64-dis-2.c: Regenerate.
759 * aarch64-opc-2.c: Regenerate.
760
290806fd
MW		 7612015-06-02 Matthew Wahab <matthew.wahab@arm.com>
762
763 * aarch64-tbl.h (aarch64_feature_lor): New.
764 (LOR): New.
765 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
766 "stllrb", "stllrh".
767 * aarch64-asm-2.c: Regenerate.
768 * aarch64-dis-2.c: Regenerate.
769 * aarch64-opc-2.c: Regenerate.
770
f21cce2c
MW		 7712015-06-01 Matthew Wahab <matthew.wahab@arm.com>
772
773 * aarch64-opc.c (F_ARCHEXT): New.
774 (aarch64_sys_regs): Add "pan".
775 (aarch64_sys_reg_supported_p): New.
776 (aarch64_pstatefields): Add "pan".
777 (aarch64_pstatefield_supported_p): New.
778
d194d186
JB		 7792015-06-01 Jan Beulich <jbeulich@suse.com>
780
781 * i386-tbl.h: Regenerate.
782
3a8547d2
JB		 7832015-06-01 Jan Beulich <jbeulich@suse.com>
784
785 * i386-dis.c (print_insn): Swap rounding mode specifier and
786 general purpose register in Intel mode.
787
015c54d5
JB		 7882015-06-01 Jan Beulich <jbeulich@suse.com>
789
790 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
791 * i386-tbl.h: Regenerate.
792
071f0063
L		 7932015-05-18 H.J. Lu <hongjiu.lu@intel.com>
794
795 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
796 * i386-init.h: Regenerated.
797
5db04b09
L		 7982015-05-15 H.J. Lu <hongjiu.lu@intel.com>
799
800 PR binutis/18386
801 * i386-dis.c: Add comments for '@'.
802 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
803 (enum x86_64_isa): New.
804 (isa64): Likewise.
805 (print_i386_disassembler_options): Add amd64 and intel64.
806 (print_insn): Handle amd64 and intel64.
807 (putop): Handle '@'.
808 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
809 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
810 * i386-opc.h (AMD64): New.
811 (CpuIntel64): Likewise.
812 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
813 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
814 Mark direct call/jmp without Disp16|Disp32 as Intel64.
815 * i386-init.h: Regenerated.
816 * i386-tbl.h: Likewise.
817
4bc0608a
PB		 8182015-05-14 Peter Bergner <bergner@vnet.ibm.com>
819
820 * ppc-opc.c (IH) New define.
821 (powerpc_opcodes) <wait>: Do not enable for POWER7.
822 <tlbie>: Add RS operand for POWER7.
823 <slbia>: Add IH operand for POWER6.
824
70cead07
L		 8252015-05-11 H.J. Lu <hongjiu.lu@intel.com>
826
827 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
828 direct branch.
829 (jmp): Likewise.
830 * i386-tbl.h: Regenerated.
831
7b6d09fb
L		 8322015-05-11 H.J. Lu <hongjiu.lu@intel.com>
833
834 * configure.ac: Support bfd_iamcu_arch.
835 * disassemble.c (disassembler): Support bfd_iamcu_arch.
836 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
837 CPU_IAMCU_COMPAT_FLAGS.
838 (cpu_flags): Add CpuIAMCU.
839 * i386-opc.h (CpuIAMCU): New.
840 (i386_cpu_flags): Add cpuiamcu.
841 * configure: Regenerated.
842 * i386-init.h: Likewise.
843 * i386-tbl.h: Likewise.
844
31955f99
L		 8452015-05-08 H.J. Lu <hongjiu.lu@intel.com>
846
847 PR binutis/18386
848 * i386-dis.c (X86_64_E8): New.
849 (X86_64_E9): Likewise.
850 Update comments on 'T', 'U', 'V'. Add comments for '^'.
851 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
852 (x86_64_table): Add X86_64_E8 and X86_64_E9.
853 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
854 (putop): Handle '^'.
855 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
856 REX_W.
857
0952813b
DD		 8582015-04-30 DJ Delorie <dj@redhat.com>
859
860 * disassemble.c (disassembler): Choose suitable disassembler based
861 on E_ABI.
862 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
863 it to decode mul/div insns.
864 * rl78-decode.c: Regenerate.
865 * rl78-dis.c (print_insn_rl78): Rename to...
866 (print_insn_rl78_common): ...this, take ISA parameter.
867 (print_insn_rl78): New.
868 (print_insn_rl78_g10): New.
869 (print_insn_rl78_g13): New.
870 (print_insn_rl78_g14): New.
871 (rl78_get_disassembler): New.
872
f9d3ecaa
NC		 8732015-04-29 Nick Clifton <nickc@redhat.com>
874
875 * po/fr.po: Updated French translation.
876
4fff86c5
PB		 8772015-04-27 Peter Bergner <bergner@vnet.ibm.com>
878
879 * ppc-opc.c (DCBT_EO): New define.
880 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
881 <lharx>: Likewise.
882 <stbcx.>: Likewise.
883 <sthcx.>: Likewise.
884 <waitrsv>: Do not enable for POWER7 and later.
885 <waitimpl>: Likewise.
886 <dcbt>: Default to the two operand form of the instruction for all
887 "old" cpus. For "new" cpus, use the operand ordering that matches
888 whether the cpu is server or embedded.
889 <dcbtst>: Likewise.
890
3b78cfe1
AK		 8912015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
892
893 * s390-opc.c: New instruction type VV0UU2.
894 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
895 and WFC.
896
04d824a4
JB		 8972015-04-23 Jan Beulich <jbeulich@suse.com>
898
899 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
900 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
901 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
902 (vfpclasspd, vfpclassps): Add %XZ.
903
09708981
L		 9042015-04-15 H.J. Lu <hongjiu.lu@intel.com>
905
906 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
907 (PREFIX_UD_REPZ): Likewise.
908 (PREFIX_UD_REPNZ): Likewise.
909 (PREFIX_UD_DATA): Likewise.
910 (PREFIX_UD_ADDR): Likewise.
911 (PREFIX_UD_LOCK): Likewise.
912
3888916d
L		 9132015-04-15 H.J. Lu <hongjiu.lu@intel.com>
914
915 * i386-dis.c (prefix_requirement): Removed.
916 (print_insn): Don't set prefix_requirement. Check
917 dp->prefix_requirement instead of prefix_requirement.
918
f24bcbaa
L		 9192015-04-15 H.J. Lu <hongjiu.lu@intel.com>
920
921 PR binutils/17898
922 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
923 (PREFIX_MOD_0_0FC7_REG_6): This.
924 (PREFIX_MOD_3_0FC7_REG_6): New.
925 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
926 (prefix_table): Replace PREFIX_0FC7_REG_6 with
927 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
928 PREFIX_MOD_3_0FC7_REG_7.
929 (mod_table): Replace PREFIX_0FC7_REG_6 with
930 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
931 PREFIX_MOD_3_0FC7_REG_7.
932
507bd325
L		 9332015-04-15 H.J. Lu <hongjiu.lu@intel.com>
934
935 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
936 (PREFIX_MANDATORY_REPNZ): Likewise.
937 (PREFIX_MANDATORY_DATA): Likewise.
938 (PREFIX_MANDATORY_ADDR): Likewise.
939 (PREFIX_MANDATORY_LOCK): Likewise.
940 (PREFIX_MANDATORY): Likewise.
941 (PREFIX_UD_SHIFT): Set to 8
942 (PREFIX_UD_REPZ): Updated.
943 (PREFIX_UD_REPNZ): Likewise.
944 (PREFIX_UD_DATA): Likewise.
945 (PREFIX_UD_ADDR): Likewise.
946 (PREFIX_UD_LOCK): Likewise.
947 (PREFIX_IGNORED_SHIFT): New.
948 (PREFIX_IGNORED_REPZ): Likewise.
949 (PREFIX_IGNORED_REPNZ): Likewise.
950 (PREFIX_IGNORED_DATA): Likewise.
951 (PREFIX_IGNORED_ADDR): Likewise.
952 (PREFIX_IGNORED_LOCK): Likewise.
953 (PREFIX_OPCODE): Likewise.
954 (PREFIX_IGNORED): Likewise.
955 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
956 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
957 (three_byte_table): Likewise.
958 (mod_table): Likewise.
959 (mandatory_prefix): Renamed to ...
960 (prefix_requirement): This.
961 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
962 Update PREFIX_90 entry.
963 (get_valid_dis386): Check prefix_requirement to see if a prefix
964 should be ignored.
965 (print_insn): Replace mandatory_prefix with prefix_requirement.
966
f0fba320
RL		 9672015-04-15 Renlin Li <renlin.li@arm.com>
968
969 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
970 use it for ssat and ssat16.
971 (print_insn_thumb32): Add handle case for 'D' control code.
972
bf890a93
IT		 9732015-04-06 Ilya Tocar <ilya.tocar@intel.com>
974 H.J. Lu <hongjiu.lu@intel.com>
975
976 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
977 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
978 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
979 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
980 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
981 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
982 Fill prefix_requirement field.
983 (struct dis386): Add prefix_requirement field.
984 (dis386): Fill prefix_requirement field.
985 (dis386_twobyte): Ditto.
986 (twobyte_has_mandatory_prefix_: Remove.
987 (reg_table): Fill prefix_requirement field.
988 (prefix_table): Ditto.
989 (x86_64_table): Ditto.
990 (three_byte_table): Ditto.
991 (xop_table): Ditto.
992 (vex_table): Ditto.
993 (vex_len_table): Ditto.
994 (vex_w_table): Ditto.
995 (mod_table): Ditto.
996 (bad_opcode): Ditto.
997 (print_insn): Use prefix_requirement.
998 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
999 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
1000 (float_reg): Ditto.
1001
2f783c1f
MF		 10022015-03-30 Mike Frysinger <vapier@gentoo.org>
1003
1004 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
1005
b9d94d62
L		 10062015-03-29 H.J. Lu <hongjiu.lu@intel.com>
1007
1008 * Makefile.in: Regenerated.
1009
27c49e9a
AB		 10102015-03-25 Anton Blanchard <anton@samba.org>
1011
1012 * ppc-dis.c (disassemble_init_powerpc): Only initialise
1013 powerpc_opcd_indices and vle_opcd_indices once.
1014
c4e676f1
AB		 10152015-03-25 Anton Blanchard <anton@samba.org>
1016
1017 * ppc-opc.c (powerpc_opcodes): Add slbfee.
1018
823d2571
TG		 10192015-03-24 Terry Guo <terry.guo@arm.com>
1020
1021 * arm-dis.c (opcode32): Updated to use new arm feature struct.
1022 (opcode16): Likewise.
1023 (coprocessor_opcodes): Replace bit with feature struct.
1024 (neon_opcodes): Likewise.
1025 (arm_opcodes): Likewise.
1026 (thumb_opcodes): Likewise.
1027 (thumb32_opcodes): Likewise.
1028 (print_insn_coprocessor): Likewise.
1029 (print_insn_arm): Likewise.
1030 (select_arm_features): Follow new feature struct.
1031
029f3522
GG		 10322015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
1033
1034 * i386-dis.c (rm_table): Add clzero.
1035 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
1036 Add CPU_CLZERO_FLAGS.
1037 (cpu_flags): Add CpuCLZERO.
1038 * i386-opc.h: Add CpuCLZERO.
1039 * i386-opc.tbl: Add clzero.
1040 * i386-init.h: Re-generated.
1041 * i386-tbl.h: Re-generated.
1042
6914869a
AB		 10432015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
1044
1045 * mips-opc.c (decode_mips_operand): Fix constraint issues
1046 with u and y operands.
1047
21e20815
AB		 10482015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
1049
1050 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
1051
6b1d7593
AK		 10522015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1053
1054 * s390-opc.c: Add new IBM z13 instructions.
1055 * s390-opc.txt: Likewise.
1056
c8f89a34
JW		 10572015-03-10 Renlin Li <renlin.li@arm.com>
1058
1059 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
1060 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
1061 related alias.
1062 * aarch64-asm-2.c: Regenerate.
1063 * aarch64-dis-2.c: Likewise.
1064 * aarch64-opc-2.c: Likewise.
1065
d8282f0e
JW		 10662015-03-03 Jiong Wang <jiong.wang@arm.com>
1067
1068 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
1069
ac994365
OE		 10702015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
1071
1072 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
1073 arch_sh_up.
1074 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
1075 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
1076
fd63f640
V		 10772015-02-23 Vinay <Vinay.G@kpit.com>
1078
1079 * rl78-decode.opc (MOV): Added space between two operands for
1080 'mov' instruction in index addressing mode.
1081 * rl78-decode.c: Regenerate.
1082
f63c1776
PA		 10832015-02-19 Pedro Alves <palves@redhat.com>
1084
1085 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
1086
07774fcc
PA		 10872015-02-10 Pedro Alves <palves@redhat.com>
1088 Tom Tromey <tromey@redhat.com>
1089
1090 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
1091 microblaze_and, microblaze_xor.
1092 * microblaze-opc.h (opcodes): Adjust.
1093
3f8107ab
AM		 10942015-01-28 James Bowman <james.bowman@ftdichip.com>
1095
1096 * Makefile.am: Add FT32 files.
1097 * configure.ac: Handle FT32.
1098 * disassemble.c (disassembler): Call print_insn_ft32.
1099 * ft32-dis.c: New file.
1100 * ft32-opc.c: New file.
1101 * Makefile.in: Regenerate.
1102 * configure: Regenerate.
1103 * po/POTFILES.in: Regenerate.
1104
e5fe4957
KLC		 11052015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
1106
1107 * nds32-asm.c (keyword_sr): Add new system registers.
1108
1e2e8c52
AK		 11092015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1110
1111 * s390-dis.c (s390_extract_operand): Support vector register
1112 operands.
1113 (s390_print_insn_with_opcode): Support new operands types and add
1114 new handling of optional operands.
1115 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
1116 and include opcode/s390.h instead.
1117 (struct op_struct): New field `flags'.
1118 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
1119 (dumpTable): Dump flags.
1120 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
1121 string.
1122 * s390-opc.c: Add new operands types, instruction formats, and
1123 instruction masks.
1124 (s390_opformats): Add new formats for .insn.
1125 * s390-opc.txt: Add new instructions.
1126
b90efa5b 11272015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 1128
b90efa5b 1129 Update year range in copyright notice of all files.
bffb6004 1130
b90efa5b 1131For older changes see ChangeLog-2014
252b5132 1132\f
b90efa5b 1133Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 1134
1135Copying and distribution of this file, with or without modification,
1136are permitted in any medium without royalty provided the copyright
1137notice and this notice are preserved.
1138
252b5132 1139Local Variables:
2f6d2f85
NC		 1140mode: change-log
1141left-margin: 8
1142fill-column: 74
252b5132
RH		 1143version-control: never
1144End:
GDB Binutils - Deliverables
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