[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2006-05-05  Thiemo Seufer  <ths@mips.com>
            David Ung  <davidu@mips.com>

	* mips-opc.c: Add macro for cache instruction.

2006-05-04  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>
	    David Ung  <davidu@mips.com>

	* mips-dis.c (mips_arch_choices): Add smartmips instruction
	decoding to MIPS32 and MIPS32R2.  Limit DSP decoding to release
	2 ISAs.  Add MIPS3D decoding to MIPS32R2.  Add MT decoding to
	MIPS64R2.
	* mips-opc.c: fix random typos in comments.
	(INSN_SMARTMIPS): New defines.
	(mips_builtin_opcodes): Add paired single support for MIPS32R2.
	Move bc3f, bc3fl, bc3t, bc3tl downwards.  Move flushi, flushd,
	flushid, wb upwards.  Move cfc3, ctc3 downwards.  Rework the
	FP_S and FP_D flags to denote single and double register
	accesses separately.  Move dmfc3, dmtc3, mfc3, mtc3 downwards.
	Allow jr.hb and jalr.hb for release 1 ISAs.  Allow luxc1, suxc1
	for MIPS32R2.  Add SmartMIPS instructions.  Add two-argument
	variants of bc2f, bc2fl, bc2t, bc2tl.  Add mfhc2, mthc2 to
	release 2 ISAs.
	* mips16-opc.c (mips16_opcodes): Add sdbbp instruction.

2006-05-03  Thiemo Seufer  <ths@mips.com>

	* mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.

2006-05-02  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>
            David Ung  <davidu@mips.com>

	* mips-dis.c (print_insn_args): Force mips16 to odd addresses.
	(print_mips16_insn_arg): Force mips16 to odd addresses.

2006-04-30  Thiemo Seufer  <ths@mips.com>
            David Ung  <davidu@mips.com>

	* mips-opc.c (mips_builtin_opcodes): Add udi instructions
	"udi0" to "udi15".
	* mips-dis.c (print_insn_args): Adds udi argument handling.

2006-04-28  James E Wilson  <wilson@specifix.com>

	* m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
	error message.

2006-04-28  Thiemo Seufer  <ths@mips.com>
            David Ung  <davidu@mips.com>
	    Nigel Stephens  <nigel@mips.com>

	* mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
	names.

2006-04-28  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>
            David Ung  <davidu@mips.com>

	* mips-dis.c (print_insn_args): Add mips_opcode argument.
	(print_insn_mips):  Adjust print_insn_args call.

2006-04-28  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>

	* mips-dis.c (print_insn_args): Print $fcc only for FP
	instructions, use $cc elsewise.

2006-04-28  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>

	* opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
	Map MIPS16 registers to O32 names.
	(print_mips16_insn_arg): Use mips16_reg_names.

2006-04-26  Julian Brown  <julian@codesourcery.com>

	* arm-dis.c (print_insn_neon): Disassemble floating-point constant
	VMOV.

2006-04-26  Nathan Sidwell  <nathan@codesourcery.com>
	    Julian Brown  <julian@codesourcery.com>

	* opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
	%<code>[zy] into %[zy]<code>.  Expand meaning of %<bitfield>['`?].
	Add unified load/store instruction names.
	(neon_opcode_table): New.
	(arm_opcodes): Expand meaning of %<bitfield>['`?].
	(arm_decode_bitfield): New.
	(print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
	Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
	(print_insn_neon): New.
	(print_insn_arm): Adjust print_insn_coprocessor call. Call
	print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
	(print_insn_thumb32): Likewise.

2006-04-19  Alan Modra  <amodra@bigpond.net.au>

	* Makefile.am: Run "make dep-am".
	* Makefile.in: Regenerate.

2006-04-19  Alan Modra  <amodra@bigpond.net.au>

	* avr-dis.c (avr_operand): Warning fix.

	* configure: Regenerate.

2006-04-16  Daniel Jacobowitz  <dan@codesourcery.com>

	* po/POTFILES.in: Regenerated.

2006-04-12   Hochstein  <hochstein@algo.informatik.tu-darmstadt.de>

	PR binutils/2454
	* avr-dis.c (avr_operand): Arrange for a comment to appear before
	the symolic form of an address, so that the output of objdump -d
	can be reassembled.

2006-04-10  DJ Delorie  <dj@redhat.com>

	* m32c-asm.c: Regenerate.

2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>

	* Makefile.am: Add install-html target.
	* Makefile.in: Regenerate.

2006-04-06  Nick Clifton  <nickc@redhat.com>

	* po/vi/po: Updated Vietnamese translation.

2006-03-31  Paul Koning  <ni1d@arrl.net>

	* pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.

2006-03-16  Bernd Schmidt  <bernd.schmidt@analog.com>

	* bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
	logic to identify halfword shifts.

2006-03-16  Paul Brook  <paul@codesourcery.com>

	* arm-dis.c (arm_opcodes): Rename swi to svc.
	(thumb_opcodes): Ditto.

2006-03-13  DJ Delorie  <dj@redhat.com>

	* m32c-asm.c: Regenerate.
	* m32c-desc.c: Likewise.
	* m32c-desc.h: Likewise.
	* m32c-dis.c: Likewise.
	* m32c-ibld.c: Likewise.
	* m32c-opc.c: Likewise.
	* m32c-opc.h: Likewise.

2006-03-10  DJ Delorie  <dj@redhat.com>

	* m32c-desc.c: Regenerate with mul.l, mulu.l.
	* m32c-opc.c: Likewise.
	* m32c-opc.h: Likewise.


2006-03-09  Nick Clifton  <nickc@redhat.com>

	* po/sv.po: Updated Swedish translation.

2006-03-07  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutils/2428
	* i386-dis.c (REP_Fixup): New function.
	(AL): Remove duplicate.
	(Xbr): New.
	(Xvr): Likewise.
	(Ybr): Likewise.
	(Yvr): Likewise.
	(indirDXr): Likewise.
	(ALr): Likewise.
	(eAXr): Likewise.
	(dis386): Updated entries of ins, outs, movs, lods and stos.

2006-03-05  Nick Clifton  <nickc@redhat.com>

	* cgen-ibld.in (insert_normal): Cope with attempts to insert a
	signed 32-bit value into an unsigned 32-bit field when the host is
	a 64-bit machine.
	* fr30-ibld.c: Regenerate.
	* frv-ibld.c: Regenerate.
	* ip2k-ibld.c: Regenerate.
	* iq2000-asm.c: Regenerate.
	* iq2000-ibld.c: Regenerate.
	* m32c-ibld.c: Regenerate.
	* m32r-ibld.c: Regenerate.
	* openrisc-ibld.c: Regenerate.
	* xc16x-ibld.c: Regenerate.
	* xstormy16-ibld.c: Regenerate.

2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)

	* xc16x-asm.c: Regenerate.
	* xc16x-dis.c: Regenerate.

2006-02-27  Carlos O'Donell  <carlos@codesourcery.com>

	* po/Make-in: Add html target.

2006-02-27  H.J. Lu <hongjiu.lu@intel.com>

	* i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
	Intel Merom New Instructions.
	(THREE_BYTE_0): Likewise.
	(THREE_BYTE_1): Likewise.
	(three_byte_table): Likewise.
	(dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
	THREE_BYTE_1 for entry 0x3a.
	(twobyte_has_modrm): Updated.
	(twobyte_uses_SSE_prefix): Likewise.
	(print_insn): Handle 3-byte opcodes used by Intel Merom New
	Instructions.

2006-02-24  David S. Miller  <davem@sunset.davemloft.net>

	* sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
	(v9_hpriv_reg_names): New table.
	(print_insn_sparc): Allow values up to 16 for '?' and '!'.
	New cases '$' and '%' for read/write hyperprivileged register.
	* sparc-opc.c (sparc_opcodes): Add new entries for UA2005
	window handling and rdhpr/wrhpr instructions.
	
2006-02-24  DJ Delorie  <dj@redhat.com>

	* m32c-desc.c: Regenerate with linker relaxation attributes.
	* m32c-desc.h: Likewise.
	* m32c-dis.c: Likewise.
	* m32c-opc.c: Likewise.

2006-02-24  Paul Brook  <paul@codesourcery.com>

	* arm-dis.c (arm_opcodes): Add V7 instructions.
	(thumb32_opcodes): Ditto.  Handle V7M MSR/MRS variants.
	(print_arm_address): New function.
	(print_insn_arm): Use it.  Add 'P' and 'U' cases.
	(psr_name): New function.
	(print_insn_thumb32): Add 'U', 'C' and 'D' cases.

2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* ia64-opc-i.c (bXc): New.
	(mXc): Likewise.
	(OpX2TaTbYaXcC): Likewise.
	(TF). Likewise.
	(TFCM). Likewise.
	(ia64_opcodes_i): Add instructions for tf.

	* ia64-opc.h (IMMU5b): New.

	* ia64-asmtab.c: Regenerated.

2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* ia64-gen.c: Update copyright years.
	* ia64-opc-b.c: Likewise.

2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>

	* ia64-gen.c (lookup_regindex): Handle ".vm".
	(print_dependency_table): Handle '\"'.

	* ia64-ic.tbl: Updated from SDM 2.2.
	* ia64-raw.tbl: Likewise.
	* ia64-waw.tbl: Likewise.
	* ia64-asmtab.c: Regenerated.

	* ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.

2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
            Anil Paranjape   <anilp1@kpitcummins.com>
            Shilin Shakti    <shilins@kpitcummins.com>

	* xc16x-desc.h: New file
	* xc16x-desc.c: New file
	* xc16x-opc.h: New file	
	* xc16x-opc.c: New file
	* xc16x-ibld.c: New file
	* xc16x-asm.c: New file
	* xc16x-dis.c: New file
	* Makefile.am: Entries for xc16x 
	* Makefile.in: Regenerate 
	* cofigure.in: Add xc16x target information.
	* configure: Regenerate.
	* disassemble.c: Add xc16x target information.

2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (dis386_twobyte): Use "movZ" for debug register
	moves.

2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c ('Z'): Add a new macro.
	(dis386_twobyte): Use "movZ" for control register moves.

2006-02-10  Nick Clifton  <nickc@redhat.com>

	* iq2000-asm.c: Regenerate.

2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>

	* m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.

2006-01-26  David Ung  <davidu@mips.com>

	* mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
	ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
	floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
	nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
	rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.

2006-01-18  Arnold Metselaar  <arnoldm@sourceware.org>

	* z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
	ld_d_r, pref_xd_cb): Use signed char to hold data to be
	disassembled.	
	* z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
	buffer overflows when disassembling instructions like
	ld (ix+123),0x23
	* z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
	operand, if the offset is negative.

2006-01-17  Arnold Metselaar  <arnoldm@sourceware.org>

	* z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
	unsigned char to hold data to be disassembled.

2006-01-17  Andreas Schwab  <schwab@suse.de>

	PR binutils/1486
	* disassemble.c (disassemble_init_for_target): Set
	disassembler_needs_relocs for bfd_arch_arm.

2006-01-16  Paul Brook  <paul@codesourcery.com>

	* m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
	f?add?, and f?sub? instructions.

2006-01-16  Nick Clifton  <nickc@redhat.com>

	* po/zh_CN.po: New Chinese (simplified) translation.
	* configure.in (ALL_LINGUAS): Add "zh_CH".
	* configure: Regenerate.

2006-01-05  Paul Brook  <paul@codesourcery.com>

	* m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.

2006-01-06  DJ Delorie  <dj@redhat.com>

	* m32c-desc.c: Regenerate.
	* m32c-opc.c: Regenerate.
	* m32c-opc.h: Regenerate.

2006-01-03  DJ Delorie  <dj@redhat.com>

	* cgen-ibld.in (extract_normal): Avoid memory range errors.
	* m32c-ibld.c: Regenerated.

For older changes see ChangeLog-2005
\f
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
d43b4baf TS	1	2006-05-05 Thiemo Seufer <ths@mips.com>
	2	David Ung <davidu@mips.com>
	3
	4	* mips-opc.c: Add macro for cache instruction.
	5
39a7806d TS	6	2006-05-04 Thiemo Seufer <ths@mips.com>
	7	Nigel Stephens <nigel@mips.com>
	8	David Ung <davidu@mips.com>
	9
	10	* mips-dis.c (mips_arch_choices): Add smartmips instruction
	11	decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release
	12	2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to
	13	MIPS64R2.
	14	* mips-opc.c: fix random typos in comments.
	15	(INSN_SMARTMIPS): New defines.
	16	(mips_builtin_opcodes): Add paired single support for MIPS32R2.
	17	Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd,
	18	flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the
	19	FP_S and FP_D flags to denote single and double register
	20	accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards.
	21	Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1
	22	for MIPS32R2. Add SmartMIPS instructions. Add two-argument
	23	variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to
	24	release 2 ISAs.
	25	* mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
	26
104b4fab TS	27	2006-05-03 Thiemo Seufer <ths@mips.com>
	28
	29	* mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
	30
022fac6d TS	31	2006-05-02 Thiemo Seufer <ths@mips.com>
	32	Nigel Stephens <nigel@mips.com>
	33	David Ung <davidu@mips.com>
	34
	35	* mips-dis.c (print_insn_args): Force mips16 to odd addresses.
	36	(print_mips16_insn_arg): Force mips16 to odd addresses.
	37
9bcd4f99 TS	38	2006-04-30 Thiemo Seufer <ths@mips.com>
	39	David Ung <davidu@mips.com>
	40
	41	* mips-opc.c (mips_builtin_opcodes): Add udi instructions
	42	"udi0" to "udi15".
	43	* mips-dis.c (print_insn_args): Adds udi argument handling.
	44
f095b97b JW	45	2006-04-28 James E Wilson <wilson@specifix.com>
	46
	47	* m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
	48	error message.
	49
59c455b3 TS	50	2006-04-28 Thiemo Seufer <ths@mips.com>
59c455b3 TS	51	David Ung <davidu@mips.com>
bdb09db1	52	Nigel Stephens <nigel@mips.com>
59c455b3 TS	53
	54	* mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
	55	names.
	56
cc0ca239	57	2006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1	58	Nigel Stephens <nigel@mips.com>
cc0ca239 TS	59	David Ung <davidu@mips.com>
	60
	61	* mips-dis.c (print_insn_args): Add mips_opcode argument.
	62	(print_insn_mips): Adjust print_insn_args call.
	63
0d09bfe6	64	2006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1	65	Nigel Stephens <nigel@mips.com>
0d09bfe6 TS	66
	67	* mips-dis.c (print_insn_args): Print $fcc only for FP
	68	instructions, use $cc elsewise.
	69
654c225a	70	2006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1	71	Nigel Stephens <nigel@mips.com>
654c225a TS	72
	73	* opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
	74	Map MIPS16 registers to O32 names.
	75	(print_mips16_insn_arg): Use mips16_reg_names.
	76
0dbde4cf JB	77	2006-04-26 Julian Brown <julian@codesourcery.com>
	78
	79	* arm-dis.c (print_insn_neon): Disassemble floating-point constant
	80	VMOV.
	81
16980d0b JB	82	2006-04-26 Nathan Sidwell <nathan@codesourcery.com>
	83	Julian Brown <julian@codesourcery.com>
	84
	85	* opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
	86	%<code>[zy] into %[zy]<code>. Expand meaning of %<bitfield>['`?].
	87	Add unified load/store instruction names.
	88	(neon_opcode_table): New.
	89	(arm_opcodes): Expand meaning of %<bitfield>['`?].
	90	(arm_decode_bitfield): New.
	91	(print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
	92	Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
	93	(print_insn_neon): New.
	94	(print_insn_arm): Adjust print_insn_coprocessor call. Call
	95	print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
	96	(print_insn_thumb32): Likewise.
	97
ec3fcc56 AM	98	2006-04-19 Alan Modra <amodra@bigpond.net.au>
	99
	100	* Makefile.am: Run "make dep-am".
	101	* Makefile.in: Regenerate.
	102
241a6c40 AM	103	2006-04-19 Alan Modra <amodra@bigpond.net.au>
241a6c40 AM	104
7c6646cd AM	105	* avr-dis.c (avr_operand): Warning fix.
7c6646cd AM	106
241a6c40 AM	107	* configure: Regenerate.
241a6c40 AM	108
e7403566 DJ	109	2006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
	110
	111	* po/POTFILES.in: Regenerated.
	112
52f16a0e NC	113	2006-04-12 Hochstein <hochstein@algo.informatik.tu-darmstadt.de>
	114
	115	PR binutils/2454
	116	* avr-dis.c (avr_operand): Arrange for a comment to appear before
	117	the symolic form of an address, so that the output of objdump -d
	118	can be reassembled.
	119
e78efa90 DD	120	2006-04-10 DJ Delorie <dj@redhat.com>
	121
	122	* m32c-asm.c: Regenerate.
	123
108a6f8e CD	124	2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
	125
	126	* Makefile.am: Add install-html target.
	127	* Makefile.in: Regenerate.
	128
a135cb2c NC	129	2006-04-06 Nick Clifton <nickc@redhat.com>
	130
	131	* po/vi/po: Updated Vietnamese translation.
	132
47426b41 AM	133	2006-03-31 Paul Koning <ni1d@arrl.net>
	134
	135	* pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
	136
331f1cbe BS	137	2006-03-16 Bernd Schmidt <bernd.schmidt@analog.com>
	138
	139	* bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
	140	logic to identify halfword shifts.
	141
c16d2bf0 PB	142	2006-03-16 Paul Brook <paul@codesourcery.com>
	143
	144	* arm-dis.c (arm_opcodes): Rename swi to svc.
	145	(thumb_opcodes): Ditto.
	146
5348b81e DD	147	2006-03-13 DJ Delorie <dj@redhat.com>
5348b81e DD	148
5398310a DD	149	* m32c-asm.c: Regenerate.
	150	* m32c-desc.c: Likewise.
	151	* m32c-desc.h: Likewise.
	152	* m32c-dis.c: Likewise.
	153	* m32c-ibld.c: Likewise.
5348b81e DD	154	* m32c-opc.c: Likewise.
	155	* m32c-opc.h: Likewise.
	156
253d272c DD	157	2006-03-10 DJ Delorie <dj@redhat.com>
	158
	159	* m32c-desc.c: Regenerate with mul.l, mulu.l.
	160	* m32c-opc.c: Likewise.
	161	* m32c-opc.h: Likewise.
	162
	163
f530741d NC	164	2006-03-09 Nick Clifton <nickc@redhat.com>
	165
	166	* po/sv.po: Updated Swedish translation.
	167
35c52694 L	168	2006-03-07 H.J. Lu <hongjiu.lu@intel.com>
	169
	170	PR binutils/2428
	171	* i386-dis.c (REP_Fixup): New function.
	172	(AL): Remove duplicate.
	173	(Xbr): New.
	174	(Xvr): Likewise.
	175	(Ybr): Likewise.
	176	(Yvr): Likewise.
	177	(indirDXr): Likewise.
	178	(ALr): Likewise.
	179	(eAXr): Likewise.
	180	(dis386): Updated entries of ins, outs, movs, lods and stos.
	181
ed963e2d NC	182	2006-03-05 Nick Clifton <nickc@redhat.com>
	183
	184	* cgen-ibld.in (insert_normal): Cope with attempts to insert a
	185	signed 32-bit value into an unsigned 32-bit field when the host is
	186	a 64-bit machine.
	187	* fr30-ibld.c: Regenerate.
	188	* frv-ibld.c: Regenerate.
	189	* ip2k-ibld.c: Regenerate.
	190	* iq2000-asm.c: Regenerate.
	191	* iq2000-ibld.c: Regenerate.
	192	* m32c-ibld.c: Regenerate.
	193	* m32r-ibld.c: Regenerate.
	194	* openrisc-ibld.c: Regenerate.
	195	* xc16x-ibld.c: Regenerate.
	196	* xstormy16-ibld.c: Regenerate.
	197
c7d41dc5 NC	198	2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
	199
	200	* xc16x-asm.c: Regenerate.
	201	* xc16x-dis.c: Regenerate.
c7d41dc5	202
f7d9e5c3 CD	203	2006-02-27 Carlos O'Donell <carlos@codesourcery.com>
	204
	205	* po/Make-in: Add html target.
	206
331d2d0d L	207	2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
	208
	209	* i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
	210	Intel Merom New Instructions.
	211	(THREE_BYTE_0): Likewise.
	212	(THREE_BYTE_1): Likewise.
	213	(three_byte_table): Likewise.
	214	(dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
	215	THREE_BYTE_1 for entry 0x3a.
	216	(twobyte_has_modrm): Updated.
	217	(twobyte_uses_SSE_prefix): Likewise.
	218	(print_insn): Handle 3-byte opcodes used by Intel Merom New
	219	Instructions.
	220
ff3f9d5b DM	221	2006-02-24 David S. Miller <davem@sunset.davemloft.net>
	222
	223	* sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
	224	(v9_hpriv_reg_names): New table.
	225	(print_insn_sparc): Allow values up to 16 for '?' and '!'.
	226	New cases '$' and '%' for read/write hyperprivileged register.
	227	* sparc-opc.c (sparc_opcodes): Add new entries for UA2005
	228	window handling and rdhpr/wrhpr instructions.
	229
6772dd07 DD	230	2006-02-24 DJ Delorie <dj@redhat.com>
	231
	232	* m32c-desc.c: Regenerate with linker relaxation attributes.
	233	* m32c-desc.h: Likewise.
	234	* m32c-dis.c: Likewise.
	235	* m32c-opc.c: Likewise.
	236
62b3e311 PB	237	2006-02-24 Paul Brook <paul@codesourcery.com>
	238
	239	* arm-dis.c (arm_opcodes): Add V7 instructions.
	240	(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
	241	(print_arm_address): New function.
	242	(print_insn_arm): Use it. Add 'P' and 'U' cases.
	243	(psr_name): New function.
	244	(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
	245
59cf82fe L	246	2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
	247
	248	* ia64-opc-i.c (bXc): New.
	249	(mXc): Likewise.
	250	(OpX2TaTbYaXcC): Likewise.
	251	(TF). Likewise.
	252	(TFCM). Likewise.
	253	(ia64_opcodes_i): Add instructions for tf.
	254
	255	* ia64-opc.h (IMMU5b): New.
	256
	257	* ia64-asmtab.c: Regenerated.
	258
19a7219f L	259	2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
	260
	261	* ia64-gen.c: Update copyright years.
	262	* ia64-opc-b.c: Likewise.
	263
7f3dfb9c L	264	2006-02-22 H.J. Lu <hongjiu.lu@intel.com>
	265
	266	* ia64-gen.c (lookup_regindex): Handle ".vm".
	267	(print_dependency_table): Handle '\"'.
	268
	269	* ia64-ic.tbl: Updated from SDM 2.2.
	270	* ia64-raw.tbl: Likewise.
	271	* ia64-waw.tbl: Likewise.
	272	* ia64-asmtab.c: Regenerated.
	273
	274	* ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
	275
d70c5fc7 NC	276	2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
	277	Anil Paranjape <anilp1@kpitcummins.com>
	278	Shilin Shakti <shilins@kpitcummins.com>
	279
	280	* xc16x-desc.h: New file
	281	* xc16x-desc.c: New file
	282	* xc16x-opc.h: New file
	283	* xc16x-opc.c: New file
	284	* xc16x-ibld.c: New file
	285	* xc16x-asm.c: New file
	286	* xc16x-dis.c: New file
	287	* Makefile.am: Entries for xc16x
	288	* Makefile.in: Regenerate
	289	* cofigure.in: Add xc16x target information.
	290	* configure: Regenerate.
	291	* disassemble.c: Add xc16x target information.
	292
a1cfb73e L	293	2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
	294
	295	* i386-dis.c (dis386_twobyte): Use "movZ" for debug register
	296	moves.
	297
6dd5059a L	298	2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
	299
	300	* i386-dis.c ('Z'): Add a new macro.
	301	(dis386_twobyte): Use "movZ" for control register moves.
	302
8536c657 NC	303	2006-02-10 Nick Clifton <nickc@redhat.com>
	304
	305	* iq2000-asm.c: Regenerate.
	306
266abb8f NS	307	2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
	308
	309	* m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
	310
f1a64f49 DU	311	2006-01-26 David Ung <davidu@mips.com>
	312
	313	* mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
	314	ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
	315	floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
	316	nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
	317	rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
	318
9e919b5f AM	319	2006-01-18 Arnold Metselaar <arnoldm@sourceware.org>
	320
	321	* z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
	322	ld_d_r, pref_xd_cb): Use signed char to hold data to be
	323	disassembled.
	324	* z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
	325	buffer overflows when disassembling instructions like
	326	ld (ix+123),0x23
	327	* z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
	328	operand, if the offset is negative.
	329
c9021189 AM	330	2006-01-17 Arnold Metselaar <arnoldm@sourceware.org>
	331
	332	* z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
	333	unsigned char to hold data to be disassembled.
	334
d99b6465 AS	335	2006-01-17 Andreas Schwab <schwab@suse.de>
	336
	337	PR binutils/1486
	338	* disassemble.c (disassemble_init_for_target): Set
	339	disassembler_needs_relocs for bfd_arch_arm.
	340
c2fe9327 PB	341	2006-01-16 Paul Brook <paul@codesourcery.com>
c2fe9327 PB	342
e88d958a	343	* m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
c2fe9327 PB	344	f?add?, and f?sub? instructions.
c2fe9327 PB	345
32fba81d NC	346	2006-01-16 Nick Clifton <nickc@redhat.com>
	347
	348	* po/zh_CN.po: New Chinese (simplified) translation.
	349	* configure.in (ALL_LINGUAS): Add "zh_CH".
	350	* configure: Regenerate.
	351
1b3a26b5 PB	352	2006-01-05 Paul Brook <paul@codesourcery.com>
	353
	354	* m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
	355
db313fa6 DD	356	2006-01-06 DJ Delorie <dj@redhat.com>
	357
	358	* m32c-desc.c: Regenerate.
	359	* m32c-opc.c: Regenerate.
	360	* m32c-opc.h: Regenerate.
	361
54d46aca DD	362	2006-01-03 DJ Delorie <dj@redhat.com>
	363
	364	* cgen-ibld.in (extract_normal): Avoid memory range errors.
	365	* m32c-ibld.c: Regenerated.
	366
e88d958a	367	For older changes see ChangeLog-2005
252b5132 RH	368	\f
252b5132 RH	369	Local Variables:
2f6d2f85 NC	370	mode: change-log
	371	left-margin: 8
	372	fill-column: 74
252b5132 RH	373	version-control: never
252b5132 RH	374	End: