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Enable 2 operand form of powerpc mfcr with -many
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
b817670b
AM		 12015-12-12 Alan Modra <amodra@gmail.com>
2
3 PR 19359
4 * ppc-opc.c (insert_fxm): Remove "ignored" from error message.
5 (powerpc_opcodes): Remove single-operand mfcr.
6
9ed608f9
MW		 72015-12-11 Matthew Wahab <matthew.wahab@arm.com>
8
9 * aarch64-asm.c (aarch64_ins_hint): New.
10 * aarch64-asm.h (aarch64_ins_hint): Declare.
11 * aarch64-dis.c (aarch64_ext_hint): New.
12 * aarch64-dis.h (aarch64_ext_hint): Declare.
13 * aarch64-opc-2.c: Regenerate.
14 * aarch64-opc.c (aarch64_hint_options): New.
15 * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
16
a0f7013a
MW		 172015-12-11 Matthew Wahab <matthew.wahab@arm.com>
18
19 * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
20
55c144e6
MW		 212015-12-11 Matthew Wahab <matthew.wahab@arm.com>
22
23 * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
24 pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
25 pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
26 pmscr_el2.
27 (aarch64_sys_reg_supported_p): Add architecture feature tests for
28 the new registers.
29
22a5455c
MW		 302015-12-10 Matthew Wahab <matthew.wahab@arm.com>
31
32 * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
33 (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
34 feature test for "s1e1rp" and "s1e1wp".
35
d6bf7ce6
MW		 362015-12-10 Matthew Wahab <matthew.wahab@arm.com>
37
38 * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
39 (aarch64_sys_ins_reg_supported_p): New.
40
ea2deeec
MW		 412015-12-10 Matthew Wahab <matthew.wahab@arm.com>
42
43 * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
44 with aarch64_sys_ins_reg_has_xt.
45 (aarch64_ext_sysins_op): Likewise.
46 * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
47 (F_HASXT): New.
48 (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
49 (aarch64_sys_regs_dc): Likewise.
50 (aarch64_sys_regs_at): Likewise.
51 (aarch64_sys_regs_tlbi): Likewise.
52 (aarch64_sys_ins_reg_has_xt): New.
53
6479e48e
MW		 542015-12-10 Matthew Wahab <matthew.wahab@arm.com>
55
56 * aarch64-opc.c (aarch64_sys_regs): Add "uao".
57 (aarch64_sys_reg_supported_p): Add comment. Add checks for "uao".
58 (aarch64_pstatefields): Add "uao".
59 (aarch64_pstatefield_supported_p): Add checks for "uao".
60
47f81142
MW		 612015-12-10 Matthew Wahab <matthew.wahab@arm.com>
62
63 * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
64 "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
65 "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
66 (aarch64_sys_reg_supported_p): Add architecture feature tests for
67 new registers.
68
c8a6db6f
MW		 692015-12-10 Matthew Wahab <matthew.wahab@arm.com>
70
71 * aarch64-asm-2.c: Regenerate.
72 * aarch64-dis-2.c: Regenerate.
73 * aarch64-tbl.h (aarch64_feature_ras): New.
74 (RAS): New.
75 (aarch64_opcode_table): Add "esb".
76
8eab4136
L		 772015-12-09 H.J. Lu <hongjiu.lu@intel.com>
78
79 * i386-dis.c (MOD_0F01_REG_5): New.
80 (RM_0F01_REG_5): Likewise.
81 (reg_table): Use MOD_0F01_REG_5.
82 (mod_table): Add MOD_0F01_REG_5.
83 (rm_table): Add RM_0F01_REG_5.
84 * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
85 (cpu_flags): Add CpuOSPKE.
86 * i386-opc.h (CpuOSPKE): New.
87 (i386_cpu_flags): Add cpuospke.
88 * i386-opc.tbl: Add rdpkru and wrpkru instructions.
89 * i386-init.h: Regenerated.
90 * i386-tbl.h: Likewise.
91
1eac08cc
DD		 922015-12-07 DJ Delorie <dj@redhat.com>
93
94 * rl78-decode.opc: Enable MULU for all ISAs.
95 * rl78-decode.c: Regenerate.
96
dd2887fc
AM		 972015-12-07 Alan Modra <amodra@gmail.com>
98
99 * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
100 major opcode/xop.
101
24b368f8
CZ		 1022015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
103
104 * arc-dis.c (special_flag_p): Match full mnemonic.
105 * arc-opc.c (print_insn_arc): Check section size to read
106 appropriate number of bytes. Fix printing.
107 * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
108 arguments.
109
3395762e
AV		 1102015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
111
112 * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
113 <ldah>: ... to this.
114
622b9eb1
MW		 1152015-11-27 Matthew Wahab <matthew.wahab@arm.com>
116
117 * aarch64-asm-2.c: Regenerate.
118 * aarch64-dis-2.c: Regenerate.
119 * aarch64-opc-2.c: Regenerate.
120 * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
121 (QL_INT2FP_H, QL_FP2INT_H): New.
122 (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
123 (QL_DST_H): New.
124 (QL_FCCMP_H): New.
125 (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
126 fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
127 fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
128 fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
129 frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
130 fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
131 fcsel.
132
cf86120b
MW		 1332015-11-27 Matthew Wahab <matthew.wahab@arm.com>
134
135 * aarch64-opc.c (half_conv_t): New.
136 (expand_fp_imm): Replace is_dp flag with the parameter size to
137 specify the number of bytes for the required expansion. Treat
138 a 16-bit expansion like a 32-bit expansion. Add check for an
139 unsupported size request. Update comment.
140 (aarch64_print_operand): Update to support 16-bit floating point
141 values. Update for changes to expand_fp_imm.
142
3bd894a7
MW		 1432015-11-27 Matthew Wahab <matthew.wahab@arm.com>
144
145 * aarch64-tbl.h (aarch64_feature_fp_f16): New.
146 (FP_F16): New.
147
64357d2e
MW		 1482015-11-27 Matthew Wahab <matthew.wahab@arm.com>
149
150 * aarch64-asm-2.c: Regenerate.
151 * aarch64-dis-2.c: Regenerate.
152 * aarch64-opc-2.c: Regenerate.
153 * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
154 "rev64".
155
d685192a
MW		 1562015-11-27 Matthew Wahab <matthew.wahab@arm.com>
157
158 * aarch64-asm-2.c: Regenerate.
159 * aarch64-asm.c (convert_bfc_to_bfm): New.
160 (convert_to_real): Add case for OP_BFC.
161 * aarch64-dis-2.c: Regenerate.
162 * aarch64-dis.c: (convert_bfm_to_bfc): New.
163 (convert_to_alias): Add case for OP_BFC.
164 * aarch64-opc-2.c: Regenerate.
165 * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
166 to allow width operand in three-operand instructions.
167 * aarch64-tbl.h (QL_BF1): New.
168 (aarch64_feature_v8_2): New.
169 (ARMV8_2): New.
170 (aarch64_opcode_table): Add "bfc".
171
35822b38
MW		 1722015-11-27 Matthew Wahab <matthew.wahab@arm.com>
173
174 * aarch64-asm-2.c: Regenerate.
175 * aarch64-dis-2.c: Regenerate.
176 * aarch64-dis.c: Weaken assert.
177 * aarch64-gen.c: Include the instruction in the list of its
178 possible aliases.
179
1a04d1a7
MW		 1802015-11-27 Matthew Wahab <matthew.wahab@arm.com>
181
182 * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
183 (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
184 feature test.
185
e49d43ff
TG		 1862015-11-23 Tristan Gingold <gingold@adacore.com>
187
188 * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
189
250aafa4
MW		 1902015-11-20 Matthew Wahab <matthew.wahab@arm.com>
191
192 * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
193 sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
194 tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
195 amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
196 cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
197 cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
198 cnthv_ctl_el2, cnthv_cval_el2.
199 (aarch64_sys_reg_supported_p): Update for the new system
200 registers.
201
a915c10f
NC		 2022015-11-20 Nick Clifton <nickc@redhat.com>
203
204 PR binutils/19224
205 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
206
f8c2a965
NC		 2072015-11-20 Nick Clifton <nickc@redhat.com>
208
209 * po/zh_CN.po: Updated simplified Chinese translation.
210
c2825638
MW		 2112015-11-19 Matthew Wahab <matthew.wahab@arm.com>
212
213 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
214 of MSR PAN immediate operand.
215
e7286c56
NC		 2162015-11-16 Nick Clifton <nickc@redhat.com>
217
218 * rx-dis.c (condition_names): Replace always and never with
219 invalid, since the always/never conditions can never be legal.
220
d8bd95ef
TG		 2212015-11-13 Tristan Gingold <gingold@adacore.com>
222
223 * configure: Regenerate.
224
a680de9a
PB		 2252015-11-11 Alan Modra <amodra@gmail.com>
226 Peter Bergner <bergner@vnet.ibm.com>
227
228 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
229 Add PPC_OPCODE_VSX3 to the vsx entry.
230 (powerpc_init_dialect): Set default dialect to power9.
231 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
232 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
233 extract_l1 insert_xtq6, extract_xtq6): New static functions.
234 (insert_esync): Test for illegal L operand value.
235 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
236 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
237 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
238 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
239 PPCVSX3): New defines.
240 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
241 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
242 <mcrxr>: Use XBFRARB_MASK.
243 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
244 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
245 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
246 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
247 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
248 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
249 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
250 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
251 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
252 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
253 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
254 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
255 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
256 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
257 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
258 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
259 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
260 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
261 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
262 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
263 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
264 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
265 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
266 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
267 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
268 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
269 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
270 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
271 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
272 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
273 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
274 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
275
854eb72b
NC		 2762015-11-02 Nick Clifton <nickc@redhat.com>
277
278 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
279 instructions.
280 * rx-decode.c: Regenerate.
281
e292aa7a
NC		 2822015-11-02 Nick Clifton <nickc@redhat.com>
283
284 * rx-decode.opc (rx_disp): If the displacement is zero, set the
285 type to RX_Operand_Zero_Indirect.
286 * rx-decode.c: Regenerate.
287 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
288
43cdf5ae
YQ		 2892015-10-28 Yao Qi <yao.qi@linaro.org>
290
291 * aarch64-dis.c (aarch64_decode_insn): Add one argument
292 noaliases_p. Update comments. Pass noaliases_p rather than
293 no_aliases to aarch64_opcode_decode.
294 (print_insn_aarch64_word): Pass no_aliases to
295 aarch64_decode_insn.
296
c2f28758
VK		 2972015-10-27 Vinay <Vinay.G@kpit.com>
298
299 PR binutils/19159
300 * rl78-decode.opc (MOV): Added offset to DE register in index
301 addressing mode.
302 * rl78-decode.c: Regenerate.
303
46662804
VK		 3042015-10-27 Vinay Kumar <vinay.g@kpit.com>
305
306 PR binutils/19158
307 * rl78-decode.opc: Add 's' print operator to instructions that
308 access system registers.
309 * rl78-decode.c: Regenerate.
310 * rl78-dis.c (print_insn_rl78_common): Decode all system
311 registers.
312
02f12cd4
VK		 3132015-10-27 Vinay Kumar <vinay.g@kpit.com>
314
315 PR binutils/19157
316 * rl78-decode.opc: Add 'a' print operator to mov instructions
317 using stack pointer plus index addressing.
318 * rl78-decode.c: Regenerate.
319
485f23cf
AK		 3202015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
321
322 * s390-opc.c: Fix comment.
323 * s390-opc.txt: Change instruction type for troo, trot, trto, and
324 trtt to RRF_U0RER since the second parameter does not need to be a
325 register pair.
326
3f94e60d
NC		 3272015-10-08 Nick Clifton <nickc@redhat.com>
328
329 * arc-dis.c (print_insn_arc): Initiallise insn array.
330
875880c6
YQ		 3312015-10-07 Yao Qi <yao.qi@linaro.org>
332
333 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
334 'name' rather than 'template'.
335 * aarch64-opc.c (aarch64_print_operand): Likewise.
336
886a2506
NC		 3372015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
338
339 * arc-dis.c: Revamped file for ARC support
340 * arc-dis.h: Likewise.
341 * arc-ext.c: Likewise.
342 * arc-ext.h: Likewise.
343 * arc-opc.c: Likewise.
344 * arc-fxi.h: New file.
345 * arc-regs.h: Likewise.
346 * arc-tbl.h: Likewise.
347
36f4aab1
YQ		 3482015-10-02 Yao Qi <yao.qi@linaro.org>
349
350 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
351 argument insn type to aarch64_insn. Rename to ...
352 (aarch64_decode_insn): ... it.
353 (print_insn_aarch64_word): Caller updated.
354
7232d389
YQ		 3552015-10-02 Yao Qi <yao.qi@linaro.org>
356
357 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
358 (print_insn_aarch64_word): Caller updated.
359
7ecc513a
DV		 3602015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
361
362 * s390-mkopc.c (main): Parse htm and vx flag.
363 * s390-opc.txt: Mark instructions from the hardware transactional
364 memory and vector facilities with the "htm"/"vx" flag.
365
b08b78e7
NC		 3662015-09-28 Nick Clifton <nickc@redhat.com>
367
368 * po/de.po: Updated German translation.
369
36f7a941
TR		 3702015-09-28 Tom Rix <tom@bumblecow.com>
371
372 * ppc-opc.c (PPC500): Mark some opcodes as invalid
373
b6518b38
NC		 3742015-09-23 Nick Clifton <nickc@redhat.com>
375
376 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
377 function.
378 * tic30-dis.c (print_branch): Likewise.
379 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
380 value before left shifting.
381 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
382 * hppa-dis.c (print_insn_hppa): Likewise.
383 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
384 array.
385 * msp430-dis.c (msp430_singleoperand): Likewise.
386 (msp430_doubleoperand): Likewise.
387 (print_insn_msp430): Likewise.
388 * nds32-asm.c (parse_operand): Likewise.
389 * sh-opc.h (MASK): Likewise.
390 * v850-dis.c (get_operand_value): Likewise.
391
f04265ec
NC		 3922015-09-22 Nick Clifton <nickc@redhat.com>
393
394 * rx-decode.opc (bwl): Use RX_Bad_Size.
395 (sbwl): Likewise.
396 (ubwl): Likewise. Rename to ubw.
397 (uBWL): Rename to uBW.
398 Replace all references to uBWL with uBW.
399 * rx-decode.c: Regenerate.
400 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
401 (opsize_names): Likewise.
402 (print_insn_rx): Detect and report RX_Bad_Size.
403
6dca4fd1
AB		 4042015-09-22 Anton Blanchard <anton@samba.org>
405
406 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
407
38074311
JM		 4082015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
409
410 * sparc-dis.c (print_insn_sparc): Handle the privileged register
411 %pmcdper.
412
5f40e14d
JS		 4132015-08-24 Jan Stancek <jstancek@redhat.com>
414
415 * i386-dis.c (print_insn): Fix decoding of three byte operands.
416
ab4e4ed5
AF		 4172015-08-21 Alexander Fomin <alexander.fomin@intel.com>
418
419 PR binutils/18257
420 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
421 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
422 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
423 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
424 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
425 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
426 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
427 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
428 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
429 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
430 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
431 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
432 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
433 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
434 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
435 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
436 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
437 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
438 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
439 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
440 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
441 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
442 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
443 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
444 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
445 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
446 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
447 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
448 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
449 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
450 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
451 (vex_w_table): Replace terminals with MOD_TABLE entries for
452 most of mask instructions.
453
919b75f7
AM		 4542015-08-17 Alan Modra <amodra@gmail.com>
455
456 * cgen.sh: Trim trailing space from cgen output.
457 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
458 (print_dis_table): Likewise.
459 * opc2c.c (dump_lines): Likewise.
460 (orig_filename): Warning fix.
461 * ia64-asmtab.c: Regenerate.
462
4ab90a7a
AV		 4632015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
464
465 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
466 and higher with ARM instruction set will now mark the 26-bit
467 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
468 (arm_opcodes): Fix for unpredictable nop being recognized as a
469 teq.
470
40fc1451
SD		 4712015-08-12 Simon Dardis <simon.dardis@imgtec.com>
472
473 * micromips-opc.c (micromips_opcodes): Re-order table so that move
474 based on 'or' is first.
475 * mips-opc.c (mips_builtin_opcodes): Ditto.
476
922c5db5
NC		 4772015-08-11 Nick Clifton <nickc@redhat.com>
478
479 PR 18800
480 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
481 instruction.
482
75fb7498
RS		 4832015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
484
485 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
486
36aed29d
AP		 4872015-08-07 Amit Pawar <Amit.Pawar@amd.com>
488
489 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
490 * i386-init.h: Regenerated.
491
a8484f96
L		 4922015-07-30 H.J. Lu <hongjiu.lu@intel.com>
493
494 PR binutils/13571
495 * i386-dis.c (MOD_0FC3): New.
496 (PREFIX_0FC3): Renamed to ...
497 (PREFIX_MOD_0_0FC3): This.
498 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
499 (prefix_table): Replace Ma with Ev on movntiS.
500 (mod_table): Add MOD_0FC3.
501
37a42ee9
L		 5022015-07-27 H.J. Lu <hongjiu.lu@intel.com>
503
504 * configure: Regenerated.
505
070fe95d
AM		 5062015-07-23 Alan Modra <amodra@gmail.com>
507
508 PR 18708
509 * i386-dis.c (get64): Avoid signed integer overflow.
510
20c2a615
L		 5112015-07-22 Alexander Fomin <alexander.fomin@intel.com>
512
513 PR binutils/18631
514 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
515 "EXEvexHalfBcstXmmq" for the second operand.
516 (EVEX_W_0F79_P_2): Likewise.
517 (EVEX_W_0F7A_P_2): Likewise.
518 (EVEX_W_0F7B_P_2): Likewise.
519
6f1c2142
AM		 5202015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
521
522 * arm-dis.c (print_insn_coprocessor): Added support for quarter
523 float bitfield format.
524 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
525 quarter float bitfield format.
526
8a643cc3
L		 5272015-07-14 H.J. Lu <hongjiu.lu@intel.com>
528
529 * configure: Regenerated.
530
ef5a96d5
AM		 5312015-07-03 Alan Modra <amodra@gmail.com>
532
533 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
534 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
535 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
536
c8c8175b
SL		 5372015-07-01 Sandra Loosemore <sandra@codesourcery.com>
538 Cesar Philippidis <cesar@codesourcery.com>
539
540 * nios2-dis.c (nios2_extract_opcode): New.
541 (nios2_disassembler_state): New.
542 (nios2_find_opcode_hash): Use mach parameter to select correct
543 disassembler state.
544 (nios2_print_insn_arg): Extend to support new R2 argument letters
545 and formats.
546 (print_insn_nios2): Check for 16-bit instruction at end of memory.
547 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
548 (NIOS2_NUM_OPCODES): Rename to...
549 (NIOS2_NUM_R1_OPCODES): This.
550 (nios2_r2_opcodes): New.
551 (NIOS2_NUM_R2_OPCODES): New.
552 (nios2_num_r2_opcodes): New.
553 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
554 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
555 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
556 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
557 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
558
9916071f
AP		 5592015-06-30 Amit Pawar <Amit.Pawar@amd.com>
560
561 * i386-dis.c (OP_Mwaitx): New.
562 (rm_table): Add monitorx/mwaitx.
563 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
564 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
565 (operand_type_init): Add CpuMWAITX.
566 * i386-opc.h (CpuMWAITX): New.
567 (i386_cpu_flags): Add cpumwaitx.
568 * i386-opc.tbl: Add monitorx and mwaitx.
569 * i386-init.h: Regenerated.
570 * i386-tbl.h: Likewise.
571
7b934113
PB		 5722015-06-22 Peter Bergner <bergner@vnet.ibm.com>
573
574 * ppc-opc.c (insert_ls): Test for invalid LS operands.
575 (insert_esync): New function.
576 (LS, WC): Use insert_ls.
577 (ESYNC): Use insert_esync.
578
bdc4de1b
NC		 5792015-06-22 Nick Clifton <nickc@redhat.com>
580
581 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
582 requested region lies beyond it.
583 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
584 looking for 32-bit insns.
585 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
586 data.
587 * sh-dis.c (print_insn_sh): Likewise.
588 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
589 blocks of instructions.
590 * vax-dis.c (print_insn_vax): Check that the requested address
591 does not clash with the stop_vma.
592
11a0cf2e
PB		 5932015-06-19 Peter Bergner <bergner@vnet.ibm.com>
594
070fe95d 595 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 596 * ppc-opc.c (FXM4): Add non-zero optional value.
597 (TBR): Likewise.
598 (SXL): Likewise.
599 (insert_fxm): Handle new default operand value.
600 (extract_fxm): Likewise.
601 (insert_tbr): Likewise.
602 (extract_tbr): Likewise.
603
bdfa8b95
MW		 6042015-06-16 Matthew Wahab <matthew.wahab@arm.com>
605
606 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
607
24b4cf66
SN		 6082015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
609
610 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
611
99a2c561
PB		 6122015-06-12 Peter Bergner <bergner@vnet.ibm.com>
613
614 * ppc-opc.c: Add comment accidentally removed by old commit.
615 (MTMSRD_L): Delete.
616
40f77f82
AM		 6172015-06-04 Peter Bergner <bergner@vnet.ibm.com>
618
619 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
620
13be46a2
NC		 6212015-06-04 Nick Clifton <nickc@redhat.com>
622
623 PR 18474
624 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
625
ddfded2f
MW		 6262015-06-02 Matthew Wahab <matthew.wahab@arm.com>
627
628 * arm-dis.c (arm_opcodes): Add "setpan".
629 (thumb_opcodes): Add "setpan".
630
1af1dd51
MW		 6312015-06-02 Matthew Wahab <matthew.wahab@arm.com>
632
633 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
634 macros.
635
9e1f0fa7
MW		 6362015-06-02 Matthew Wahab <matthew.wahab@arm.com>
637
638 * aarch64-tbl.h (aarch64_feature_rdma): New.
639 (RDMA): New.
640 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
641 * aarch64-asm-2.c: Regenerate.
642 * aarch64-dis-2.c: Regenerate.
643 * aarch64-opc-2.c: Regenerate.
644
290806fd
MW		 6452015-06-02 Matthew Wahab <matthew.wahab@arm.com>
646
647 * aarch64-tbl.h (aarch64_feature_lor): New.
648 (LOR): New.
649 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
650 "stllrb", "stllrh".
651 * aarch64-asm-2.c: Regenerate.
652 * aarch64-dis-2.c: Regenerate.
653 * aarch64-opc-2.c: Regenerate.
654
f21cce2c
MW		 6552015-06-01 Matthew Wahab <matthew.wahab@arm.com>
656
657 * aarch64-opc.c (F_ARCHEXT): New.
658 (aarch64_sys_regs): Add "pan".
659 (aarch64_sys_reg_supported_p): New.
660 (aarch64_pstatefields): Add "pan".
661 (aarch64_pstatefield_supported_p): New.
662
d194d186
JB		 6632015-06-01 Jan Beulich <jbeulich@suse.com>
664
665 * i386-tbl.h: Regenerate.
666
3a8547d2
JB		 6672015-06-01 Jan Beulich <jbeulich@suse.com>
668
669 * i386-dis.c (print_insn): Swap rounding mode specifier and
670 general purpose register in Intel mode.
671
015c54d5
JB		 6722015-06-01 Jan Beulich <jbeulich@suse.com>
673
674 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
675 * i386-tbl.h: Regenerate.
676
071f0063
L		 6772015-05-18 H.J. Lu <hongjiu.lu@intel.com>
678
679 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
680 * i386-init.h: Regenerated.
681
5db04b09
L		 6822015-05-15 H.J. Lu <hongjiu.lu@intel.com>
683
684 PR binutis/18386
685 * i386-dis.c: Add comments for '@'.
686 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
687 (enum x86_64_isa): New.
688 (isa64): Likewise.
689 (print_i386_disassembler_options): Add amd64 and intel64.
690 (print_insn): Handle amd64 and intel64.
691 (putop): Handle '@'.
692 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
693 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
694 * i386-opc.h (AMD64): New.
695 (CpuIntel64): Likewise.
696 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
697 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
698 Mark direct call/jmp without Disp16|Disp32 as Intel64.
699 * i386-init.h: Regenerated.
700 * i386-tbl.h: Likewise.
701
4bc0608a
PB		 7022015-05-14 Peter Bergner <bergner@vnet.ibm.com>
703
704 * ppc-opc.c (IH) New define.
705 (powerpc_opcodes) <wait>: Do not enable for POWER7.
706 <tlbie>: Add RS operand for POWER7.
707 <slbia>: Add IH operand for POWER6.
708
70cead07
L		 7092015-05-11 H.J. Lu <hongjiu.lu@intel.com>
710
711 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
712 direct branch.
713 (jmp): Likewise.
714 * i386-tbl.h: Regenerated.
715
7b6d09fb
L		 7162015-05-11 H.J. Lu <hongjiu.lu@intel.com>
717
718 * configure.ac: Support bfd_iamcu_arch.
719 * disassemble.c (disassembler): Support bfd_iamcu_arch.
720 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
721 CPU_IAMCU_COMPAT_FLAGS.
722 (cpu_flags): Add CpuIAMCU.
723 * i386-opc.h (CpuIAMCU): New.
724 (i386_cpu_flags): Add cpuiamcu.
725 * configure: Regenerated.
726 * i386-init.h: Likewise.
727 * i386-tbl.h: Likewise.
728
31955f99
L		 7292015-05-08 H.J. Lu <hongjiu.lu@intel.com>
730
731 PR binutis/18386
732 * i386-dis.c (X86_64_E8): New.
733 (X86_64_E9): Likewise.
734 Update comments on 'T', 'U', 'V'. Add comments for '^'.
735 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
736 (x86_64_table): Add X86_64_E8 and X86_64_E9.
737 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
738 (putop): Handle '^'.
739 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
740 REX_W.
741
0952813b
DD		 7422015-04-30 DJ Delorie <dj@redhat.com>
743
744 * disassemble.c (disassembler): Choose suitable disassembler based
745 on E_ABI.
746 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
747 it to decode mul/div insns.
748 * rl78-decode.c: Regenerate.
749 * rl78-dis.c (print_insn_rl78): Rename to...
750 (print_insn_rl78_common): ...this, take ISA parameter.
751 (print_insn_rl78): New.
752 (print_insn_rl78_g10): New.
753 (print_insn_rl78_g13): New.
754 (print_insn_rl78_g14): New.
755 (rl78_get_disassembler): New.
756
f9d3ecaa
NC		 7572015-04-29 Nick Clifton <nickc@redhat.com>
758
759 * po/fr.po: Updated French translation.
760
4fff86c5
PB		 7612015-04-27 Peter Bergner <bergner@vnet.ibm.com>
762
763 * ppc-opc.c (DCBT_EO): New define.
764 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
765 <lharx>: Likewise.
766 <stbcx.>: Likewise.
767 <sthcx.>: Likewise.
768 <waitrsv>: Do not enable for POWER7 and later.
769 <waitimpl>: Likewise.
770 <dcbt>: Default to the two operand form of the instruction for all
771 "old" cpus. For "new" cpus, use the operand ordering that matches
772 whether the cpu is server or embedded.
773 <dcbtst>: Likewise.
774
3b78cfe1
AK		 7752015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
776
777 * s390-opc.c: New instruction type VV0UU2.
778 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
779 and WFC.
780
04d824a4
JB		 7812015-04-23 Jan Beulich <jbeulich@suse.com>
782
783 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
784 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
785 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
786 (vfpclasspd, vfpclassps): Add %XZ.
787
09708981
L		 7882015-04-15 H.J. Lu <hongjiu.lu@intel.com>
789
790 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
791 (PREFIX_UD_REPZ): Likewise.
792 (PREFIX_UD_REPNZ): Likewise.
793 (PREFIX_UD_DATA): Likewise.
794 (PREFIX_UD_ADDR): Likewise.
795 (PREFIX_UD_LOCK): Likewise.
796
3888916d
L		 7972015-04-15 H.J. Lu <hongjiu.lu@intel.com>
798
799 * i386-dis.c (prefix_requirement): Removed.
800 (print_insn): Don't set prefix_requirement. Check
801 dp->prefix_requirement instead of prefix_requirement.
802
f24bcbaa
L		 8032015-04-15 H.J. Lu <hongjiu.lu@intel.com>
804
805 PR binutils/17898
806 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
807 (PREFIX_MOD_0_0FC7_REG_6): This.
808 (PREFIX_MOD_3_0FC7_REG_6): New.
809 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
810 (prefix_table): Replace PREFIX_0FC7_REG_6 with
811 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
812 PREFIX_MOD_3_0FC7_REG_7.
813 (mod_table): Replace PREFIX_0FC7_REG_6 with
814 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
815 PREFIX_MOD_3_0FC7_REG_7.
816
507bd325
L		 8172015-04-15 H.J. Lu <hongjiu.lu@intel.com>
818
819 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
820 (PREFIX_MANDATORY_REPNZ): Likewise.
821 (PREFIX_MANDATORY_DATA): Likewise.
822 (PREFIX_MANDATORY_ADDR): Likewise.
823 (PREFIX_MANDATORY_LOCK): Likewise.
824 (PREFIX_MANDATORY): Likewise.
825 (PREFIX_UD_SHIFT): Set to 8
826 (PREFIX_UD_REPZ): Updated.
827 (PREFIX_UD_REPNZ): Likewise.
828 (PREFIX_UD_DATA): Likewise.
829 (PREFIX_UD_ADDR): Likewise.
830 (PREFIX_UD_LOCK): Likewise.
831 (PREFIX_IGNORED_SHIFT): New.
832 (PREFIX_IGNORED_REPZ): Likewise.
833 (PREFIX_IGNORED_REPNZ): Likewise.
834 (PREFIX_IGNORED_DATA): Likewise.
835 (PREFIX_IGNORED_ADDR): Likewise.
836 (PREFIX_IGNORED_LOCK): Likewise.
837 (PREFIX_OPCODE): Likewise.
838 (PREFIX_IGNORED): Likewise.
839 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
840 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
841 (three_byte_table): Likewise.
842 (mod_table): Likewise.
843 (mandatory_prefix): Renamed to ...
844 (prefix_requirement): This.
845 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
846 Update PREFIX_90 entry.
847 (get_valid_dis386): Check prefix_requirement to see if a prefix
848 should be ignored.
849 (print_insn): Replace mandatory_prefix with prefix_requirement.
850
f0fba320
RL		 8512015-04-15 Renlin Li <renlin.li@arm.com>
852
853 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
854 use it for ssat and ssat16.
855 (print_insn_thumb32): Add handle case for 'D' control code.
856
bf890a93
IT		 8572015-04-06 Ilya Tocar <ilya.tocar@intel.com>
858 H.J. Lu <hongjiu.lu@intel.com>
859
860 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
861 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
862 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
863 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
864 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
865 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
866 Fill prefix_requirement field.
867 (struct dis386): Add prefix_requirement field.
868 (dis386): Fill prefix_requirement field.
869 (dis386_twobyte): Ditto.
870 (twobyte_has_mandatory_prefix_: Remove.
871 (reg_table): Fill prefix_requirement field.
872 (prefix_table): Ditto.
873 (x86_64_table): Ditto.
874 (three_byte_table): Ditto.
875 (xop_table): Ditto.
876 (vex_table): Ditto.
877 (vex_len_table): Ditto.
878 (vex_w_table): Ditto.
879 (mod_table): Ditto.
880 (bad_opcode): Ditto.
881 (print_insn): Use prefix_requirement.
882 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
883 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
884 (float_reg): Ditto.
885
2f783c1f
MF		 8862015-03-30 Mike Frysinger <vapier@gentoo.org>
887
888 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
889
b9d94d62
L		 8902015-03-29 H.J. Lu <hongjiu.lu@intel.com>
891
892 * Makefile.in: Regenerated.
893
27c49e9a
AB		 8942015-03-25 Anton Blanchard <anton@samba.org>
895
896 * ppc-dis.c (disassemble_init_powerpc): Only initialise
897 powerpc_opcd_indices and vle_opcd_indices once.
898
c4e676f1
AB		 8992015-03-25 Anton Blanchard <anton@samba.org>
900
901 * ppc-opc.c (powerpc_opcodes): Add slbfee.
902
823d2571
TG		 9032015-03-24 Terry Guo <terry.guo@arm.com>
904
905 * arm-dis.c (opcode32): Updated to use new arm feature struct.
906 (opcode16): Likewise.
907 (coprocessor_opcodes): Replace bit with feature struct.
908 (neon_opcodes): Likewise.
909 (arm_opcodes): Likewise.
910 (thumb_opcodes): Likewise.
911 (thumb32_opcodes): Likewise.
912 (print_insn_coprocessor): Likewise.
913 (print_insn_arm): Likewise.
914 (select_arm_features): Follow new feature struct.
915
029f3522
GG		 9162015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
917
918 * i386-dis.c (rm_table): Add clzero.
919 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
920 Add CPU_CLZERO_FLAGS.
921 (cpu_flags): Add CpuCLZERO.
922 * i386-opc.h: Add CpuCLZERO.
923 * i386-opc.tbl: Add clzero.
924 * i386-init.h: Re-generated.
925 * i386-tbl.h: Re-generated.
926
6914869a
AB		 9272015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
928
929 * mips-opc.c (decode_mips_operand): Fix constraint issues
930 with u and y operands.
931
21e20815
AB		 9322015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
933
934 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
935
6b1d7593
AK		 9362015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
937
938 * s390-opc.c: Add new IBM z13 instructions.
939 * s390-opc.txt: Likewise.
940
c8f89a34
JW		 9412015-03-10 Renlin Li <renlin.li@arm.com>
942
943 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
944 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
945 related alias.
946 * aarch64-asm-2.c: Regenerate.
947 * aarch64-dis-2.c: Likewise.
948 * aarch64-opc-2.c: Likewise.
949
d8282f0e
JW		 9502015-03-03 Jiong Wang <jiong.wang@arm.com>
951
952 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
953
ac994365
OE		 9542015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
955
956 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
957 arch_sh_up.
958 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
959 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
960
fd63f640
V		 9612015-02-23 Vinay <Vinay.G@kpit.com>
962
963 * rl78-decode.opc (MOV): Added space between two operands for
964 'mov' instruction in index addressing mode.
965 * rl78-decode.c: Regenerate.
966
f63c1776
PA		 9672015-02-19 Pedro Alves <palves@redhat.com>
968
969 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
970
07774fcc
PA		 9712015-02-10 Pedro Alves <palves@redhat.com>
972 Tom Tromey <tromey@redhat.com>
973
974 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
975 microblaze_and, microblaze_xor.
976 * microblaze-opc.h (opcodes): Adjust.
977
3f8107ab
AM		 9782015-01-28 James Bowman <james.bowman@ftdichip.com>
979
980 * Makefile.am: Add FT32 files.
981 * configure.ac: Handle FT32.
982 * disassemble.c (disassembler): Call print_insn_ft32.
983 * ft32-dis.c: New file.
984 * ft32-opc.c: New file.
985 * Makefile.in: Regenerate.
986 * configure: Regenerate.
987 * po/POTFILES.in: Regenerate.
988
e5fe4957
KLC		 9892015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
990
991 * nds32-asm.c (keyword_sr): Add new system registers.
992
1e2e8c52
AK		 9932015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
994
995 * s390-dis.c (s390_extract_operand): Support vector register
996 operands.
997 (s390_print_insn_with_opcode): Support new operands types and add
998 new handling of optional operands.
999 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
1000 and include opcode/s390.h instead.
1001 (struct op_struct): New field `flags'.
1002 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
1003 (dumpTable): Dump flags.
1004 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
1005 string.
1006 * s390-opc.c: Add new operands types, instruction formats, and
1007 instruction masks.
1008 (s390_opformats): Add new formats for .insn.
1009 * s390-opc.txt: Add new instructions.
1010
b90efa5b 10112015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 1012
b90efa5b 1013 Update year range in copyright notice of all files.
bffb6004 1014
b90efa5b 1015For older changes see ChangeLog-2014
252b5132 1016\f
b90efa5b 1017Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 1018
1019Copying and distribution of this file, with or without modification,
1020are permitted in any medium without royalty provided the copyright
1021notice and this notice are preserved.
1022
252b5132 1023Local Variables:
2f6d2f85
NC		 1024mode: change-log
1025left-margin: 8
1026fill-column: 74
252b5132
RH		 1027version-control: never
1028End:
GDB Binutils - Deliverables
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