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[AArch64] Add SVE condition codes
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
bb7eff52
RS		 12016-09-21 Richard Sandiford <richard.sandiford@arm.com>
2
3 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
4 (print_mnemonic_name): ...here.
5 (print_comment): New function.
6 (print_aarch64_insn): Call it.
7 * aarch64-opc.c (aarch64_conds): Add SVE names.
8 (aarch64_print_operand): Print alternative condition names in
9 a comment.
10
c0890d26
RS		 112016-09-21 Richard Sandiford <richard.sandiford@arm.com>
12
13 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
14 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
15 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
16 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
17 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
18 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
19 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
20 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
21 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
22 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
23 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
24 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
25 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
26 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
27 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
28 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
29 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
30 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
31 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
32 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
33 (OP_SVE_XWU, OP_SVE_XXU): New macros.
34 (aarch64_feature_sve): New variable.
35 (SVE): New macro.
36 (_SVE_INSN): Likewise.
37 (aarch64_opcode_table): Add SVE instructions.
38 * aarch64-opc.h (extract_fields): Declare.
39 * aarch64-opc-2.c: Regenerate.
40 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
41 * aarch64-asm-2.c: Regenerate.
42 * aarch64-dis.c (extract_fields): Make global.
43 (do_misc_decoding): Handle the new SVE aarch64_ops.
44 * aarch64-dis-2.c: Regenerate.
45
116b6019
RS		 462016-09-21 Richard Sandiford <richard.sandiford@arm.com>
47
48 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
49 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
50 aarch64_field_kinds.
51 * aarch64-opc.c (fields): Add corresponding entries.
52 * aarch64-asm.c (aarch64_get_variant): New function.
53 (aarch64_encode_variant_using_iclass): Likewise.
54 (aarch64_opcode_encode): Call it.
55 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
56 (aarch64_opcode_decode): Call it.
57
047cd301
RS		 582016-09-21 Richard Sandiford <richard.sandiford@arm.com>
59
60 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
61 and FP register operands.
62 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
63 (FLD_SVE_Vn): New aarch64_field_kinds.
64 * aarch64-opc.c (fields): Add corresponding entries.
65 (aarch64_print_operand): Handle the new SVE core and FP register
66 operands.
67 * aarch64-opc-2.c: Regenerate.
68 * aarch64-asm-2.c: Likewise.
69 * aarch64-dis-2.c: Likewise.
70
165d4950
RS		 712016-09-21 Richard Sandiford <richard.sandiford@arm.com>
72
73 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
74 immediate operands.
75 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
76 * aarch64-opc.c (fields): Add corresponding entry.
77 (operand_general_constraint_met_p): Handle the new SVE FP immediate
78 operands.
79 (aarch64_print_operand): Likewise.
80 * aarch64-opc-2.c: Regenerate.
81 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
82 (ins_sve_float_zero_one): New inserters.
83 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
84 (aarch64_ins_sve_float_half_two): Likewise.
85 (aarch64_ins_sve_float_zero_one): Likewise.
86 * aarch64-asm-2.c: Regenerate.
87 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
88 (ext_sve_float_zero_one): New extractors.
89 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
90 (aarch64_ext_sve_float_half_two): Likewise.
91 (aarch64_ext_sve_float_zero_one): Likewise.
92 * aarch64-dis-2.c: Regenerate.
93
e950b345
RS		 942016-09-21 Richard Sandiford <richard.sandiford@arm.com>
95
96 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
97 integer immediate operands.
98 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
99 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
100 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
101 * aarch64-opc.c (fields): Add corresponding entries.
102 (operand_general_constraint_met_p): Handle the new SVE integer
103 immediate operands.
104 (aarch64_print_operand): Likewise.
105 (aarch64_sve_dupm_mov_immediate_p): New function.
106 * aarch64-opc-2.c: Regenerate.
107 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
108 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
109 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
110 (aarch64_ins_limm): ...here.
111 (aarch64_ins_inv_limm): New function.
112 (aarch64_ins_sve_aimm): Likewise.
113 (aarch64_ins_sve_asimm): Likewise.
114 (aarch64_ins_sve_limm_mov): Likewise.
115 (aarch64_ins_sve_shlimm): Likewise.
116 (aarch64_ins_sve_shrimm): Likewise.
117 * aarch64-asm-2.c: Regenerate.
118 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
119 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
120 * aarch64-dis.c (decode_limm): New function, split out from...
121 (aarch64_ext_limm): ...here.
122 (aarch64_ext_inv_limm): New function.
123 (decode_sve_aimm): Likewise.
124 (aarch64_ext_sve_aimm): Likewise.
125 (aarch64_ext_sve_asimm): Likewise.
126 (aarch64_ext_sve_limm_mov): Likewise.
127 (aarch64_top_bit): Likewise.
128 (aarch64_ext_sve_shlimm): Likewise.
129 (aarch64_ext_sve_shrimm): Likewise.
130 * aarch64-dis-2.c: Regenerate.
131
98907a70
RS		 1322016-09-21 Richard Sandiford <richard.sandiford@arm.com>
133
134 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
135 operands.
136 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
137 the AARCH64_MOD_MUL_VL entry.
138 (value_aligned_p): Cope with non-power-of-two alignments.
139 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
140 (print_immediate_offset_address): Likewise.
141 (aarch64_print_operand): Likewise.
142 * aarch64-opc-2.c: Regenerate.
143 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
144 (ins_sve_addr_ri_s9xvl): New inserters.
145 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
146 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
147 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
148 * aarch64-asm-2.c: Regenerate.
149 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
150 (ext_sve_addr_ri_s9xvl): New extractors.
151 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
152 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
153 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
154 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
155 * aarch64-dis-2.c: Regenerate.
156
4df068de
RS		 1572016-09-21 Richard Sandiford <richard.sandiford@arm.com>
158
159 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
160 address operands.
161 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
162 (FLD_SVE_xs_22): New aarch64_field_kinds.
163 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
164 (get_operand_specific_data): New function.
165 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
166 FLD_SVE_xs_14 and FLD_SVE_xs_22.
167 (operand_general_constraint_met_p): Handle the new SVE address
168 operands.
169 (sve_reg): New array.
170 (get_addr_sve_reg_name): New function.
171 (aarch64_print_operand): Handle the new SVE address operands.
172 * aarch64-opc-2.c: Regenerate.
173 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
174 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
175 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
176 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
177 (aarch64_ins_sve_addr_rr_lsl): Likewise.
178 (aarch64_ins_sve_addr_rz_xtw): Likewise.
179 (aarch64_ins_sve_addr_zi_u5): Likewise.
180 (aarch64_ins_sve_addr_zz): Likewise.
181 (aarch64_ins_sve_addr_zz_lsl): Likewise.
182 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
183 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
184 * aarch64-asm-2.c: Regenerate.
185 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
186 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
187 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
188 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
189 (aarch64_ext_sve_addr_ri_u6): Likewise.
190 (aarch64_ext_sve_addr_rr_lsl): Likewise.
191 (aarch64_ext_sve_addr_rz_xtw): Likewise.
192 (aarch64_ext_sve_addr_zi_u5): Likewise.
193 (aarch64_ext_sve_addr_zz): Likewise.
194 (aarch64_ext_sve_addr_zz_lsl): Likewise.
195 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
196 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
197 * aarch64-dis-2.c: Regenerate.
198
2442d846
RS		 1992016-09-21 Richard Sandiford <richard.sandiford@arm.com>
200
201 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
202 AARCH64_OPND_SVE_PATTERN_SCALED.
203 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
204 * aarch64-opc.c (fields): Add a corresponding entry.
205 (set_multiplier_out_of_range_error): New function.
206 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
207 (operand_general_constraint_met_p): Handle
208 AARCH64_OPND_SVE_PATTERN_SCALED.
209 (print_register_offset_address): Use PRIi64 to print the
210 shift amount.
211 (aarch64_print_operand): Likewise. Handle
212 AARCH64_OPND_SVE_PATTERN_SCALED.
213 * aarch64-opc-2.c: Regenerate.
214 * aarch64-asm.h (ins_sve_scale): New inserter.
215 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
216 * aarch64-asm-2.c: Regenerate.
217 * aarch64-dis.h (ext_sve_scale): New inserter.
218 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
219 * aarch64-dis-2.c: Regenerate.
220
245d2e3f
RS		 2212016-09-21 Richard Sandiford <richard.sandiford@arm.com>
222
223 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
224 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
225 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
226 (FLD_SVE_prfop): Likewise.
227 * aarch64-opc.c: Include libiberty.h.
228 (aarch64_sve_pattern_array): New variable.
229 (aarch64_sve_prfop_array): Likewise.
230 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
231 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
232 AARCH64_OPND_SVE_PRFOP.
233 * aarch64-asm-2.c: Regenerate.
234 * aarch64-dis-2.c: Likewise.
235 * aarch64-opc-2.c: Likewise.
236
d50c751e
RS		 2372016-09-21 Richard Sandiford <richard.sandiford@arm.com>
238
239 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
240 AARCH64_OPND_QLF_P_[ZM].
241 (aarch64_print_operand): Print /z and /m where appropriate.
242
f11ad6bc
RS		 2432016-09-21 Richard Sandiford <richard.sandiford@arm.com>
244
245 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
246 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
247 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
248 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
249 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
250 * aarch64-opc.c (fields): Add corresponding entries here.
251 (operand_general_constraint_met_p): Check that SVE register lists
252 have the correct length. Check the ranges of SVE index registers.
253 Check for cases where p8-p15 are used in 3-bit predicate fields.
254 (aarch64_print_operand): Handle the new SVE operands.
255 * aarch64-opc-2.c: Regenerate.
256 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
257 * aarch64-asm.c (aarch64_ins_sve_index): New function.
258 (aarch64_ins_sve_reglist): Likewise.
259 * aarch64-asm-2.c: Regenerate.
260 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
261 * aarch64-dis.c (aarch64_ext_sve_index): New function.
262 (aarch64_ext_sve_reglist): Likewise.
263 * aarch64-dis-2.c: Regenerate.
264
0c608d6b
RS		 2652016-09-21 Richard Sandiford <richard.sandiford@arm.com>
266
267 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
268 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
269 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
270 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
271 tied operands.
272
01dbfe4c
RS		 2732016-09-21 Richard Sandiford <richard.sandiford@arm.com>
274
275 * aarch64-opc.c (get_offset_int_reg_name): New function.
276 (print_immediate_offset_address): Likewise.
277 (print_register_offset_address): Take the base and offset
278 registers as parameters.
279 (aarch64_print_operand): Update caller accordingly. Use
280 print_immediate_offset_address.
281
72e9f319
RS		 2822016-09-21 Richard Sandiford <richard.sandiford@arm.com>
283
284 * aarch64-opc.c (BANK): New macro.
285 (R32, R64): Take a register number as argument
286 (int_reg): Use BANK.
287
8a7f0c1b
RS		 2882016-09-21 Richard Sandiford <richard.sandiford@arm.com>
289
290 * aarch64-opc.c (print_register_list): Add a prefix parameter.
291 (aarch64_print_operand): Update accordingly.
292
aa2aa4c6
RS		 2932016-09-21 Richard Sandiford <richard.sandiford@arm.com>
294
295 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
296 for FPIMM.
297 * aarch64-asm.h (ins_fpimm): New inserter.
298 * aarch64-asm.c (aarch64_ins_fpimm): New function.
299 * aarch64-asm-2.c: Regenerate.
300 * aarch64-dis.h (ext_fpimm): New extractor.
301 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
302 (aarch64_ext_fpimm): New function.
303 * aarch64-dis-2.c: Regenerate.
304
b5464a68
RS		 3052016-09-21 Richard Sandiford <richard.sandiford@arm.com>
306
307 * aarch64-asm.c: Include libiberty.h.
308 (insert_fields): New function.
309 (aarch64_ins_imm): Use it.
310 * aarch64-dis.c (extract_fields): New function.
311 (aarch64_ext_imm): Use it.
312
42408347
RS		 3132016-09-21 Richard Sandiford <richard.sandiford@arm.com>
314
315 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
316 with an esize parameter.
317 (operand_general_constraint_met_p): Update accordingly.
318 Fix misindented code.
319 * aarch64-asm.c (aarch64_ins_limm): Update call to
320 aarch64_logical_immediate_p.
321
4989adac
RS		 3222016-09-21 Richard Sandiford <richard.sandiford@arm.com>
323
324 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
325
bd11d5d8
RS		 3262016-09-21 Richard Sandiford <richard.sandiford@arm.com>
327
328 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
329
f807f43d
CZ		 3302016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
331
332 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
333
fd486b63
PB		 3342016-09-14 Peter Bergner <bergner@vnet.ibm.com>
335
336 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
337 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
338 xor3>: Delete mnemonics.
339 <cp_abort>: Rename mnemonic from ...
340 <cpabort>: ...to this.
341 <setb>: Change to a X form instruction.
342 <sync>: Change to 1 operand form.
343 <copy>: Delete mnemonic.
344 <copy_first>: Rename mnemonic from ...
345 <copy>: ...to this.
346 <paste, paste.>: Delete mnemonics.
347 <paste_last>: Rename mnemonic from ...
348 <paste.>: ...to this.
349
dce08442
AK		 3502016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
351
352 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
353
952c3f51
AK		 3542016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
355
356 * s390-mkopc.c (main): Support alternate arch strings.
357
8b71537b
PS		 3582016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
359
360 * s390-opc.txt: Fix kmctr instruction type.
361
5b64d091
L		 3622016-09-07 H.J. Lu <hongjiu.lu@intel.com>
363
364 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
365 * i386-init.h: Regenerated.
366
7763838e
CM		 3672016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
368
369 * opcodes/arc-dis.c (print_insn_arc): Changed.
370
1b8b6532
JM		 3712016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
372
373 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
374 camellia_fl.
375
1a336194
TP		 3762016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
377
378 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
379 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
380 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
381
6b40c462
L		 3822016-08-24 H.J. Lu <hongjiu.lu@intel.com>
383
384 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
385 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
386 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
387 PREFIX_MOD_3_0FAE_REG_4.
388 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
389 PREFIX_MOD_3_0FAE_REG_4.
390 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
391 (cpu_flags): Add CpuPTWRITE.
392 * i386-opc.h (CpuPTWRITE): New.
393 (i386_cpu_flags): Add cpuptwrite.
394 * i386-opc.tbl: Add ptwrite instruction.
395 * i386-init.h: Regenerated.
396 * i386-tbl.h: Likewise.
397
ab548d2d
AK		 3982016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
399
400 * arc-dis.h: Wrap around in extern "C".
401
344bde0a
RS		 4022016-08-23 Richard Sandiford <richard.sandiford@arm.com>
403
404 * aarch64-tbl.h (V8_2_INSN): New macro.
405 (aarch64_opcode_table): Use it.
406
5ce912d8
RS		 4072016-08-23 Richard Sandiford <richard.sandiford@arm.com>
408
409 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
410 CORE_INSN, __FP_INSN and SIMD_INSN.
411
9d30b0bd
RS		 4122016-08-23 Richard Sandiford <richard.sandiford@arm.com>
413
414 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
415 (aarch64_opcode_table): Update uses accordingly.
416
dfdaec14
AJ		 4172016-07-25 Andrew Jenner <andrew@codesourcery.com>
418 Kwok Cheung Yeung <kcy@codesourcery.com>
419
420 opcodes/
421 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
422 'e_cmplwi' to 'e_cmpli' instead.
423 (OPVUPRT, OPVUPRT_MASK): Define.
424 (powerpc_opcodes): Add E200Z4 insns.
425 (vle_opcodes): Add context save/restore insns.
426
7bd374a4
MR		 4272016-07-27 Maciej W. Rozycki <macro@imgtec.com>
428
429 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
430 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
431 "j".
432
db18dbab
GM		 4332016-07-27 Graham Markall <graham.markall@embecosm.com>
434
435 * arc-nps400-tbl.h: Change block comments to GNU format.
436 * arc-dis.c: Add new globals addrtypenames,
437 addrtypenames_max, and addtypeunknown.
438 (get_addrtype): New function.
439 (print_insn_arc): Print colons and address types when
440 required.
441 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
442 define insert and extract functions for all address types.
443 (arc_operands): Add operands for colon and all address
444 types.
445 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
446 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
447 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
448 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
449 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
450 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
451
fecd57f9
L		 4522016-07-21 H.J. Lu <hongjiu.lu@intel.com>
453
454 * configure: Regenerated.
455
37fd5ef3
CZ		 4562016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
457
458 * arc-dis.c (skipclass): New structure.
459 (decodelist): New variable.
460 (is_compatible_p): New function.
461 (new_element): Likewise.
462 (skip_class_p): Likewise.
463 (find_format_from_table): Use skip_class_p function.
464 (find_format): Decode first the extension instructions.
465 (print_insn_arc): Select either ARCEM or ARCHS based on elf
466 e_flags.
467 (parse_option): New function.
468 (parse_disassembler_options): Likewise.
469 (print_arc_disassembler_options): Likewise.
470 (print_insn_arc): Use parse_disassembler_options function. Proper
471 select ARCv2 cpu variant.
472 * disassemble.c (disassembler_usage): Add ARC disassembler
473 options.
474
92281a5b
MR		 4752016-07-13 Maciej W. Rozycki <macro@imgtec.com>
476
477 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
478 annotation from the "nal" entry and reorder it beyond "bltzal".
479
6e7ced37
JM		 4802016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
481
482 * sparc-opc.c (ldtxa): New macro.
483 (sparc_opcodes): Use the macro defined above to add entries for
484 the LDTXA instructions.
485 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
486 instruction.
487
2f831b9a 4882016-07-07 James Bowman <james.bowman@ftdichip.com>
489
490 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
491 and "jmpc".
492
c07315e0
JB		 4932016-07-01 Jan Beulich <jbeulich@suse.com>
494
495 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
496 (movzb): Adjust to cover all permitted suffixes.
497 (movzw): New.
498 * i386-tbl.h: Re-generate.
499
9243100a
JB		 5002016-07-01 Jan Beulich <jbeulich@suse.com>
501
502 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
503 (lgdt): Remove Tbyte from non-64-bit variant.
504 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
505 xsaves64, xsavec64): Remove Disp16.
506 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
507 Remove Disp32S from non-64-bit variants. Remove Disp16 from
508 64-bit variants.
509 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
510 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
511 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
512 64-bit variants.
513 * i386-tbl.h: Re-generate.
514
8325cc63
JB		 5152016-07-01 Jan Beulich <jbeulich@suse.com>
516
517 * i386-opc.tbl (xlat): Remove RepPrefixOk.
518 * i386-tbl.h: Re-generate.
519
838441e4
YQ		 5202016-06-30 Yao Qi <yao.qi@linaro.org>
521
522 * arm-dis.c (print_insn): Fix typo in comment.
523
dab26bf4
RS		 5242016-06-28 Richard Sandiford <richard.sandiford@arm.com>
525
526 * aarch64-opc.c (operand_general_constraint_met_p): Check the
527 range of ldst_elemlist operands.
528 (print_register_list): Use PRIi64 to print the index.
529 (aarch64_print_operand): Likewise.
530
5703197e
TS		 5312016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
532
533 * mcore-opc.h: Remove sentinal.
534 * mcore-dis.c (print_insn_mcore): Adjust.
535
ce440d63
GM		 5362016-06-23 Graham Markall <graham.markall@embecosm.com>
537
538 * arc-opc.c: Correct description of availability of NPS400
539 features.
540
6fd3a02d
PB		 5412016-06-22 Peter Bergner <bergner@vnet.ibm.com>
542
543 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
544 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
545 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
546 xor3>: New mnemonics.
547 <setb>: Change to a VX form instruction.
548 (insert_sh6): Add support for rldixor.
549 (extract_sh6): Likewise.
550
6b477896
TS		 5512016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
552
553 * arc-ext.h: Wrap in extern C.
554
bdd582db
GM		 5552016-06-21 Graham Markall <graham.markall@embecosm.com>
556
557 * arc-dis.c (arc_insn_length): Add comment on instruction length.
558 Use same method for determining instruction length on ARC700 and
559 NPS-400.
560 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
561 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
562 with the NPS400 subclass.
563 * arc-opc.c: Likewise.
564
96074adc
JM		 5652016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
566
567 * sparc-opc.c (rdasr): New macro.
568 (wrasr): Likewise.
569 (rdpr): Likewise.
570 (wrpr): Likewise.
571 (rdhpr): Likewise.
572 (wrhpr): Likewise.
573 (sparc_opcodes): Use the macros above to fix and expand the
574 definition of read/write instructions from/to
575 asr/privileged/hyperprivileged instructions.
576 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
577 %hva_mask_nz. Prefer softint_set and softint_clear over
578 set_softint and clear_softint.
579 (print_insn_sparc): Support %ver in Rd.
580
7a10c22f
JM		 5812016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
582
583 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
584 architecture according to the hardware capabilities they require.
585
4f26fb3a
JM		 5862016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
587
588 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
589 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
590 bfd_mach_sparc_v9{c,d,e,v,m}.
591 * sparc-opc.c (MASK_V9C): Define.
592 (MASK_V9D): Likewise.
593 (MASK_V9E): Likewise.
594 (MASK_V9V): Likewise.
595 (MASK_V9M): Likewise.
596 (v6): Add MASK_V9{C,D,E,V,M}.
597 (v6notlet): Likewise.
598 (v7): Likewise.
599 (v8): Likewise.
600 (v9): Likewise.
601 (v9andleon): Likewise.
602 (v9a): Likewise.
603 (v9b): Likewise.
604 (v9c): Define.
605 (v9d): Likewise.
606 (v9e): Likewise.
607 (v9v): Likewise.
608 (v9m): Likewise.
609 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
610
3ee6e4fb
NC		 6112016-06-15 Nick Clifton <nickc@redhat.com>
612
613 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
614 constants to match expected behaviour.
615 (nds32_parse_opcode): Likewise. Also for whitespace.
616
02f3be19
AB		 6172016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
618
619 * arc-opc.c (extract_rhv1): Extract value from insn.
620
6f9f37ed 6212016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 622
623 * arc-nps400-tbl.h: Add ldbit instruction.
624 * arc-opc.c: Add flag classes required for ldbit.
625
6f9f37ed 6262016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 627
628 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
629 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
630 support the above instructions.
631
6f9f37ed 6322016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 633
634 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
635 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
636 csma, cbba, zncv, and hofs.
637 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
638 support the above instructions.
639
6402016-06-06 Graham Markall <graham.markall@embecosm.com>
641
642 * arc-nps400-tbl.h: Add andab and orab instructions.
643
6442016-06-06 Graham Markall <graham.markall@embecosm.com>
645
646 * arc-nps400-tbl.h: Add addl-like instructions.
647
6482016-06-06 Graham Markall <graham.markall@embecosm.com>
649
650 * arc-nps400-tbl.h: Add mxb and imxb instructions.
651
6522016-06-06 Graham Markall <graham.markall@embecosm.com>
653
654 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
655 instructions.
656
b2cc3f6f
AK		 6572016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
658
659 * s390-dis.c (option_use_insn_len_bits_p): New file scope
660 variable.
661 (init_disasm): Handle new command line option "insnlength".
662 (print_s390_disassembler_options): Mention new option in help
663 output.
664 (print_insn_s390): Use the encoded insn length when dumping
665 unknown instructions.
666
1857fe72
DC		 6672016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
668
669 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
670 to the address and set as symbol address for LDS/ STS immediate operands.
671
14b57c7c
AM		 6722016-06-07 Alan Modra <amodra@gmail.com>
673
674 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
675 cpu for "vle" to e500.
676 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
677 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
678 (PPCNONE): Delete, substitute throughout.
679 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
680 except for major opcode 4 and 31.
681 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
682
4d1464f2
MW		 6832016-06-07 Matthew Wahab <matthew.wahab@arm.com>
684
685 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
686 ARM_EXT_RAS in relevant entries.
687
026122a6
PB		 6882016-06-03 Peter Bergner <bergner@vnet.ibm.com>
689
690 PR binutils/20196
691 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
692 opcodes for E6500.
693
07f5af7d
L		 6942016-06-03 H.J. Lu <hongjiu.lu@intel.com>
695
696 PR binutis/18386
697 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
698 (indir_v_mode): New.
699 Add comments for '&'.
700 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
701 (putop): Handle '&'.
702 (intel_operand_size): Handle indir_v_mode.
703 (OP_E_register): Likewise.
704 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
705 64-bit indirect call/jmp for AMD64.
706 * i386-tbl.h: Regenerated
707
4eb6f892
AB		 7082016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
709
710 * arc-dis.c (struct arc_operand_iterator): New structure.
711 (find_format_from_table): All the old content from find_format,
712 with some minor adjustments, and parameter renaming.
713 (find_format_long_instructions): New function.
714 (find_format): Rewritten.
715 (arc_insn_length): Add LSB parameter.
716 (extract_operand_value): New function.
717 (operand_iterator_next): New function.
718 (print_insn_arc): Use new functions to find opcode, and iterator
719 over operands.
720 * arc-opc.c (insert_nps_3bit_dst_short): New function.
721 (extract_nps_3bit_dst_short): New function.
722 (insert_nps_3bit_src2_short): New function.
723 (extract_nps_3bit_src2_short): New function.
724 (insert_nps_bitop1_size): New function.
725 (extract_nps_bitop1_size): New function.
726 (insert_nps_bitop2_size): New function.
727 (extract_nps_bitop2_size): New function.
728 (insert_nps_bitop_mod4_msb): New function.
729 (extract_nps_bitop_mod4_msb): New function.
730 (insert_nps_bitop_mod4_lsb): New function.
731 (extract_nps_bitop_mod4_lsb): New function.
732 (insert_nps_bitop_dst_pos3_pos4): New function.
733 (extract_nps_bitop_dst_pos3_pos4): New function.
734 (insert_nps_bitop_ins_ext): New function.
735 (extract_nps_bitop_ins_ext): New function.
736 (arc_operands): Add new operands.
737 (arc_long_opcodes): New global array.
738 (arc_num_long_opcodes): New global.
739 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
740
1fe0971e
TS		 7412016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
742
743 * nds32-asm.h: Add extern "C".
744 * sh-opc.h: Likewise.
745
315f180f
GM		 7462016-06-01 Graham Markall <graham.markall@embecosm.com>
747
748 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
749 0,b,limm to the rflt instruction.
750
a2b5fccc
TS		 7512016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
752
753 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
754 constant.
755
0cbd0046
L		 7562016-05-29 H.J. Lu <hongjiu.lu@intel.com>
757
758 PR gas/20145
759 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
760 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
761 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
762 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
763 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
764 * i386-init.h: Regenerated.
765
1848e567
L		 7662016-05-27 H.J. Lu <hongjiu.lu@intel.com>
767
768 PR gas/20145
769 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
770 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
771 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
772 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
773 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
774 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
775 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
776 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
777 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
778 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
779 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
780 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
781 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
782 CpuRegMask for AVX512.
783 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
784 and CpuRegMask.
785 (set_bitfield_from_cpu_flag_init): New function.
786 (set_bitfield): Remove const on f. Call
787 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
788 * i386-opc.h (CpuRegMMX): New.
789 (CpuRegXMM): Likewise.
790 (CpuRegYMM): Likewise.
791 (CpuRegZMM): Likewise.
792 (CpuRegMask): Likewise.
793 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
794 and cpuregmask.
795 * i386-init.h: Regenerated.
796 * i386-tbl.h: Likewise.
797
e92bae62
L		 7982016-05-27 H.J. Lu <hongjiu.lu@intel.com>
799
800 PR gas/20154
801 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
802 (opcode_modifiers): Add AMD64 and Intel64.
803 (main): Properly verify CpuMax.
804 * i386-opc.h (CpuAMD64): Removed.
805 (CpuIntel64): Likewise.
806 (CpuMax): Set to CpuNo64.
807 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
808 (AMD64): New.
809 (Intel64): Likewise.
810 (i386_opcode_modifier): Add amd64 and intel64.
811 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
812 on call and jmp.
813 * i386-init.h: Regenerated.
814 * i386-tbl.h: Likewise.
815
e89c5eaa
L		 8162016-05-27 H.J. Lu <hongjiu.lu@intel.com>
817
818 PR gas/20154
819 * i386-gen.c (main): Fail if CpuMax is incorrect.
820 * i386-opc.h (CpuMax): Set to CpuIntel64.
821 * i386-tbl.h: Regenerated.
822
77d66e7b
NC		 8232016-05-27 Nick Clifton <nickc@redhat.com>
824
825 PR target/20150
826 * msp430-dis.c (msp430dis_read_two_bytes): New function.
827 (msp430dis_opcode_unsigned): New function.
828 (msp430dis_opcode_signed): New function.
829 (msp430_singleoperand): Use the new opcode reading functions.
830 Only disassenmble bytes if they were successfully read.
831 (msp430_doubleoperand): Likewise.
832 (msp430_branchinstr): Likewise.
833 (msp430x_callx_instr): Likewise.
834 (print_insn_msp430): Check that it is safe to read bytes before
835 attempting disassembly. Use the new opcode reading functions.
836
19dfcc89
PB		 8372016-05-26 Peter Bergner <bergner@vnet.ibm.com>
838
839 * ppc-opc.c (CY): New define. Document it.
840 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
841
f3ad7637
L		 8422016-05-25 H.J. Lu <hongjiu.lu@intel.com>
843
844 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
845 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
846 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
847 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
848 CPU_ANY_AVX_FLAGS.
849 * i386-init.h: Regenerated.
850
f1360d58
L		 8512016-05-25 H.J. Lu <hongjiu.lu@intel.com>
852
853 PR gas/20141
854 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
855 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
856 * i386-init.h: Regenerated.
857
293f5f65
L		 8582016-05-25 H.J. Lu <hongjiu.lu@intel.com>
859
860 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
861 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
862 * i386-init.h: Regenerated.
863
d9eca1df
CZ		 8642016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
865
866 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
867 information.
868 (print_insn_arc): Set insn_type information.
869 * arc-opc.c (C_CC): Add F_CLASS_COND.
870 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
871 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
872 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
873 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
874 (brne, brne_s, jeq_s, jne_s): Likewise.
875
87789e08
CZ		 8762016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
877
878 * arc-tbl.h (neg): New instruction variant.
879
c810e0b8
CZ		 8802016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
881
882 * arc-dis.c (find_format, find_format, get_auxreg)
883 (print_insn_arc): Changed.
884 * arc-ext.h (INSERT_XOP): Likewise.
885
3d207518
TS		 8862016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
887
888 * tic54x-dis.c (sprint_mmr): Adjust.
889 * tic54x-opc.c: Likewise.
890
514e58b7
AM		 8912016-05-19 Alan Modra <amodra@gmail.com>
892
893 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
894
e43de63c
AM		 8952016-05-19 Alan Modra <amodra@gmail.com>
896
897 * ppc-opc.c: Formatting.
898 (NSISIGNOPT): Define.
899 (powerpc_opcodes <subis>): Use NSISIGNOPT.
900
1401d2fe
MR		 9012016-05-18 Maciej W. Rozycki <macro@imgtec.com>
902
903 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
904 replacing references to `micromips_ase' throughout.
905 (_print_insn_mips): Don't use file-level microMIPS annotation to
906 determine the disassembly mode with the symbol table.
907
1178da44
PB		 9082016-05-13 Peter Bergner <bergner@vnet.ibm.com>
909
910 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
911
8f4f9071
MF		 9122016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
913
914 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
915 mips64r6.
916 * mips-opc.c (D34): New macro.
917 (mips_builtin_opcodes): Define bposge32c for DSPr3.
918
8bc52696
AF		 9192016-05-10 Alexander Fomin <alexander.fomin@intel.com>
920
921 * i386-dis.c (prefix_table): Add RDPID instruction.
922 * i386-gen.c (cpu_flag_init): Add RDPID flag.
923 (cpu_flags): Add RDPID bitfield.
924 * i386-opc.h (enum): Add RDPID element.
925 (i386_cpu_flags): Add RDPID field.
926 * i386-opc.tbl: Add RDPID instruction.
927 * i386-init.h: Regenerate.
928 * i386-tbl.h: Regenerate.
929
39d911fc
TP		 9302016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
931
932 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
933 branch type of a symbol.
934 (print_insn): Likewise.
935
16a1fa25
TP		 9362016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
937
938 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
939 Mainline Security Extensions instructions.
940 (thumb_opcodes): Add entries for narrow ARMv8-M Security
941 Extensions instructions.
942 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
943 instructions.
944 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
945 special registers.
946
d751b79e
JM		 9472016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
948
949 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
950
945e0f82
CZ		 9512016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
952
953 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
954 (arcExtMap_genOpcode): Likewise.
955 * arc-opc.c (arg_32bit_rc): Define new variable.
956 (arg_32bit_u6): Likewise.
957 (arg_32bit_limm): Likewise.
958
20f55f38
SN		 9592016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
960
961 * aarch64-gen.c (VERIFIER): Define.
962 * aarch64-opc.c (VERIFIER): Define.
963 (verify_ldpsw): Use static linkage.
964 * aarch64-opc.h (verify_ldpsw): Remove.
965 * aarch64-tbl.h: Use VERIFIER for verifiers.
966
4bd13cde
NC		 9672016-04-28 Nick Clifton <nickc@redhat.com>
968
969 PR target/19722
970 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
971 * aarch64-opc.c (verify_ldpsw): New function.
972 * aarch64-opc.h (verify_ldpsw): New prototype.
973 * aarch64-tbl.h: Add initialiser for verifier field.
974 (LDPSW): Set verifier to verify_ldpsw.
975
c0f92bf9
L		 9762016-04-23 H.J. Lu <hongjiu.lu@intel.com>
977
978 PR binutils/19983
979 PR binutils/19984
980 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
981 smaller than address size.
982
e6c7cdec
TS		 9832016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
984
985 * alpha-dis.c: Regenerate.
986 * crx-dis.c: Likewise.
987 * disassemble.c: Likewise.
988 * epiphany-opc.c: Likewise.
989 * fr30-opc.c: Likewise.
990 * frv-opc.c: Likewise.
991 * ip2k-opc.c: Likewise.
992 * iq2000-opc.c: Likewise.
993 * lm32-opc.c: Likewise.
994 * lm32-opinst.c: Likewise.
995 * m32c-opc.c: Likewise.
996 * m32r-opc.c: Likewise.
997 * m32r-opinst.c: Likewise.
998 * mep-opc.c: Likewise.
999 * mt-opc.c: Likewise.
1000 * or1k-opc.c: Likewise.
1001 * or1k-opinst.c: Likewise.
1002 * tic80-opc.c: Likewise.
1003 * xc16x-opc.c: Likewise.
1004 * xstormy16-opc.c: Likewise.
1005
537aefaf
AB		 10062016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1007
1008 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1009 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1010 calcsd, and calcxd instructions.
1011 * arc-opc.c (insert_nps_bitop_size): Delete.
1012 (extract_nps_bitop_size): Delete.
1013 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1014 (extract_nps_qcmp_m3): Define.
1015 (extract_nps_qcmp_m2): Define.
1016 (extract_nps_qcmp_m1): Define.
1017 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1018 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1019 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1020 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1021 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1022 NPS_QCMP_M3.
1023
c8f785f2
AB		 10242016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1025
1026 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1027
6fd8e7c2
L		 10282016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1029
1030 * Makefile.in: Regenerated with automake 1.11.6.
1031 * aclocal.m4: Likewise.
1032
4b0c052e
AB		 10332016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1034
1035 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1036 instructions.
1037 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1038 (extract_nps_cmem_uimm16): New function.
1039 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1040
cb040366
AB		 10412016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1042
1043 * arc-dis.c (arc_insn_length): New function.
1044 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1045 (find_format): Change insnLen parameter to unsigned.
1046
accc0180
NC		 10472016-04-13 Nick Clifton <nickc@redhat.com>
1048
1049 PR target/19937
1050 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1051 the LD.B and LD.BU instructions.
1052
f36e33da
CZ		 10532016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1054
1055 * arc-dis.c (find_format): Check for extension flags.
1056 (print_flags): New function.
1057 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1058 .extAuxRegister.
1059 * arc-ext.c (arcExtMap_coreRegName): Use
1060 LAST_EXTENSION_CORE_REGISTER.
1061 (arcExtMap_coreReadWrite): Likewise.
1062 (dump_ARC_extmap): Update printing.
1063 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1064 (arc_aux_regs): Add cpu field.
1065 * arc-regs.h: Add cpu field, lower case name aux registers.
1066
1c2e355e
CZ		 10672016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1068
1069 * arc-tbl.h: Add rtsc, sleep with no arguments.
1070
b99747ae
CZ		 10712016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1072
1073 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1074 Initialize.
1075 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1076 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1077 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1078 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1079 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1080 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1081 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1082 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1083 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1084 (arc_opcode arc_opcodes): Null terminate the array.
1085 (arc_num_opcodes): Remove.
1086 * arc-ext.h (INSERT_XOP): Define.
1087 (extInstruction_t): Likewise.
1088 (arcExtMap_instName): Delete.
1089 (arcExtMap_insn): New function.
1090 (arcExtMap_genOpcode): Likewise.
1091 * arc-ext.c (ExtInstruction): Remove.
1092 (create_map): Zero initialize instruction fields.
1093 (arcExtMap_instName): Remove.
1094 (arcExtMap_insn): New function.
1095 (dump_ARC_extmap): More info while debuging.
1096 (arcExtMap_genOpcode): New function.
1097 * arc-dis.c (find_format): New function.
1098 (print_insn_arc): Use find_format.
1099 (arc_get_disassembler): Enable dump_ARC_extmap only when
1100 debugging.
1101
92708cec
MR		 11022016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1103
1104 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1105 instruction bits out.
1106
a42a4f84
AB		 11072016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1108
1109 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1110 * arc-opc.c (arc_flag_operands): Add new flags.
1111 (arc_flag_classes): Add new classes.
1112
1328504b
AB		 11132016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1114
1115 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1116
820f03ff
AB		 11172016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1118
1119 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1120 encode1, rflt, crc16, and crc32 instructions.
1121 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1122 (arc_flag_classes): Add C_NPS_R.
1123 (insert_nps_bitop_size_2b): New function.
1124 (extract_nps_bitop_size_2b): Likewise.
1125 (insert_nps_bitop_uimm8): Likewise.
1126 (extract_nps_bitop_uimm8): Likewise.
1127 (arc_operands): Add new operand entries.
1128
8ddf6b2a
CZ		 11292016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1130
b99747ae
CZ		 1131 * arc-regs.h: Add a new subclass field. Add double assist
1132 accumulator register values.
1133 * arc-tbl.h: Use DPA subclass to mark the double assist
1134 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1135 * arc-opc.c (RSP): Define instead of SP.
1136 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1137
589a7d88
JW		 11382016-04-05 Jiong Wang <jiong.wang@arm.com>
1139
1140 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1141
0a191de9 11422016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1143
1144 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1145 NPS_R_SRC1.
1146
0a106562
AB		 11472016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1148
1149 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1150 issues. No functional changes.
1151
bd05ac5f
CZ		 11522016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1153
b99747ae
CZ		 1154 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1155 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1156 (RTT): Remove duplicate.
1157 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1158 (PCT_CONFIG*): Remove.
1159 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1160
9885948f
CZ		 11612016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1162
b99747ae 1163 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1164
f2dd8838
CZ		 11652016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1166
b99747ae
CZ		 1167 * arc-tbl.h (invld07): Remove.
1168 * arc-ext-tbl.h: New file.
1169 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1170 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1171
0d2f91fe
JK		 11722016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1173
1174 Fix -Wstack-usage warnings.
1175 * aarch64-dis.c (print_operands): Substitute size.
1176 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1177
a6b71f42
JM		 11782016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1179
1180 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1181 to get a proper diagnostic when an invalid ASR register is used.
1182
9780e045
NC		 11832016-03-22 Nick Clifton <nickc@redhat.com>
1184
1185 * configure: Regenerate.
1186
e23e8ebe
AB		 11872016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1188
1189 * arc-nps400-tbl.h: New file.
1190 * arc-opc.c: Add top level comment.
1191 (insert_nps_3bit_dst): New function.
1192 (extract_nps_3bit_dst): New function.
1193 (insert_nps_3bit_src2): New function.
1194 (extract_nps_3bit_src2): New function.
1195 (insert_nps_bitop_size): New function.
1196 (extract_nps_bitop_size): New function.
1197 (arc_flag_operands): Add nps400 entries.
1198 (arc_flag_classes): Add nps400 entries.
1199 (arc_operands): Add nps400 entries.
1200 (arc_opcodes): Add nps400 include.
1201
1ae8ab47
AB		 12022016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1203
1204 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1205 the new class enum values.
1206
8699fc3e
AB		 12072016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1208
1209 * arc-dis.c (print_insn_arc): Handle nps400.
1210
24740d83
AB		 12112016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1212
1213 * arc-opc.c (BASE): Delete.
1214
8678914f
NC		 12152016-03-18 Nick Clifton <nickc@redhat.com>
1216
1217 PR target/19721
1218 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1219 of MOV insn that aliases an ORR insn.
1220
cc933301
JW		 12212016-03-16 Jiong Wang <jiong.wang@arm.com>
1222
1223 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1224
f86f5863
TS		 12252016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1226
1227 * mcore-opc.h: Add const qualifiers.
1228 * microblaze-opc.h (struct op_code_struct): Likewise.
1229 * sh-opc.h: Likewise.
1230 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1231 (tic4x_print_op): Likewise.
1232
62de1c63
AM		 12332016-03-02 Alan Modra <amodra@gmail.com>
1234
d11698cd 1235 * or1k-desc.h: Regenerate.
62de1c63 1236 * fr30-ibld.c: Regenerate.
c697cf0b 1237 * rl78-decode.c: Regenerate.
62de1c63 1238
020efce5
NC		 12392016-03-01 Nick Clifton <nickc@redhat.com>
1240
1241 PR target/19747
1242 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1243
b0c11777
RL		 12442016-02-24 Renlin Li <renlin.li@arm.com>
1245
1246 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1247 (print_insn_coprocessor): Support fp16 instructions.
1248
3e309328
RL		 12492016-02-24 Renlin Li <renlin.li@arm.com>
1250
1251 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1252 vminnm, vrint(mpna).
1253
8afc7bea
RL		 12542016-02-24 Renlin Li <renlin.li@arm.com>
1255
1256 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1257 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1258
4fd7268a
L		 12592016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1260
1261 * i386-dis.c (print_insn): Parenthesize expression to prevent
1262 truncated addresses.
1263 (OP_J): Likewise.
1264
4670103e
CZ		 12652016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1266 Janek van Oirschot <jvanoirs@synopsys.com>
1267
b99747ae
CZ		 1268 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1269 variable.
4670103e 1270
c1d9289f
NC		 12712016-02-04 Nick Clifton <nickc@redhat.com>
1272
1273 PR target/19561
1274 * msp430-dis.c (print_insn_msp430): Add a special case for
1275 decoding an RRC instruction with the ZC bit set in the extension
1276 word.
1277
a143b004
AB		 12782016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1279
1280 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1281 * epiphany-ibld.c: Regenerate.
1282 * fr30-ibld.c: Regenerate.
1283 * frv-ibld.c: Regenerate.
1284 * ip2k-ibld.c: Regenerate.
1285 * iq2000-ibld.c: Regenerate.
1286 * lm32-ibld.c: Regenerate.
1287 * m32c-ibld.c: Regenerate.
1288 * m32r-ibld.c: Regenerate.
1289 * mep-ibld.c: Regenerate.
1290 * mt-ibld.c: Regenerate.
1291 * or1k-ibld.c: Regenerate.
1292 * xc16x-ibld.c: Regenerate.
1293 * xstormy16-ibld.c: Regenerate.
1294
b89807c6
AB		 12952016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1296
1297 * epiphany-dis.c: Regenerated from latest cpu files.
1298
d8c823c8
MM		 12992016-02-01 Michael McConville <mmcco@mykolab.com>
1300
1301 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1302 test bit.
1303
5bc5ae88
RL		 13042016-01-25 Renlin Li <renlin.li@arm.com>
1305
1306 * arm-dis.c (mapping_symbol_for_insn): New function.
1307 (find_ifthen_state): Call mapping_symbol_for_insn().
1308
0bff6e2d
MW		 13092016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1310
1311 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1312 of MSR UAO immediate operand.
1313
100b4f2e
MR		 13142016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1315
1316 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1317 instruction support.
1318
5c14705f
AM		 13192016-01-17 Alan Modra <amodra@gmail.com>
1320
1321 * configure: Regenerate.
1322
4d82fe66
NC		 13232016-01-14 Nick Clifton <nickc@redhat.com>
1324
1325 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1326 instructions that can support stack pointer operations.
1327 * rl78-decode.c: Regenerate.
1328 * rl78-dis.c: Fix display of stack pointer in MOVW based
1329 instructions.
1330
651657fa
MW		 13312016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1332
1333 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1334 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1335 erxtatus_el1 and erxaddr_el1.
1336
105bde57
MW		 13372016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1338
1339 * arm-dis.c (arm_opcodes): Add "esb".
1340 (thumb_opcodes): Likewise.
1341
afa8d405
PB		 13422016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1343
1344 * ppc-opc.c <xscmpnedp>: Delete.
1345 <xvcmpnedp>: Likewise.
1346 <xvcmpnedp.>: Likewise.
1347 <xvcmpnesp>: Likewise.
1348 <xvcmpnesp.>: Likewise.
1349
83c3256e
AS		 13502016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1351
1352 PR gas/13050
1353 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1354 addition to ISA_A.
1355
6f2750fe
AM		 13562016-01-01 Alan Modra <amodra@gmail.com>
1357
1358 Update year range in copyright notice of all files.
1359
3499769a
AM		 1360For older changes see ChangeLog-2015
1361\f
1362Copyright (C) 2016 Free Software Foundation, Inc.
1363
1364Copying and distribution of this file, with or without modification,
1365are permitted in any medium without royalty provided the copyright
1366notice and this notice are preserved.
1367
1368Local Variables:
1369mode: change-log
1370left-margin: 8
1371fill-column: 74
1372version-control: never
1373End:
GDB Binutils - Deliverables
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