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Fix buffer overrun in TIC30 disassembler.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
bbf9a0b5
NC		 12019-10-28 Nick Clifton <nickc@redhat.com>
2
3 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
4 operand buffer. Set value to 15 not 13.
5 (get_register_operand): Use OPERAND_BUFFER_LEN.
6 (get_indirect_operand): Likewise.
7 (print_two_operand): Likewise.
8 (print_three_operand): Likewise.
9 (print_oar_insn): Likewise.
10
d1e304bc
NC		 112019-10-28 Nick Clifton <nickc@redhat.com>
12
13 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
14 (bit_extract_simple): Likewise.
15 (bit_copy): Likewise.
16 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
17 index_offset array are not accessed.
18
dee33451
NC		 192019-10-28 Nick Clifton <nickc@redhat.com>
20
21 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
22 operand.
23
27cee81d
NC		 242019-10-25 Nick Clifton <nickc@redhat.com>
25
26 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
27 access to opcodes.op array element.
28
de6d8dc2
NC		 292019-10-23 Nick Clifton <nickc@redhat.com>
30
31 * rx-dis.c (get_register_name): Fix spelling typo in error
32 message.
33 (get_condition_name, get_flag_name, get_double_register_name)
34 (get_double_register_high_name, get_double_register_low_name)
35 (get_double_control_register_name, get_double_condition_name)
36 (get_opsize_name, get_size_name): Likewise.
37
6207ed28
NC		 382019-10-22 Nick Clifton <nickc@redhat.com>
39
40 * rx-dis.c (get_size_name): New function. Provides safe
41 access to name array.
42 (get_opsize_name): Likewise.
43 (print_insn_rx): Use the accessor functions.
44
12234dfd
NC		 452019-10-16 Nick Clifton <nickc@redhat.com>
46
47 * rx-dis.c (get_register_name): New function. Provides safe
48 access to name array.
49 (get_condition_name, get_flag_name, get_double_register_name)
50 (get_double_register_high_name, get_double_register_low_name)
51 (get_double_control_register_name, get_double_condition_name):
52 Likewise.
53 (print_insn_rx): Use the accessor functions.
54
1d378749
NC		 552019-10-09 Nick Clifton <nickc@redhat.com>
56
57 PR 25041
58 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
59 instructions.
60
d241b910
JB		 612019-10-07 Jan Beulich <jbeulich@suse.com>
62
63 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
64 (cmpsd): Likewise. Move EsSeg to other operand.
65 * opcodes/i386-tbl.h: Re-generate.
66
f5c5b7c1
AM		 672019-09-23 Alan Modra <amodra@gmail.com>
68
69 * m68k-dis.c: Include cpu-m68k.h
70
7beeaeb8
AM		 712019-09-23 Alan Modra <amodra@gmail.com>
72
73 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
74 "elf/mips.h" earlier.
75
3f9aad11
JB		 762018-09-20 Jan Beulich <jbeulich@suse.com>
77
78 PR gas/25012
79 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
80 with SReg operand.
81 * i386-tbl.h: Re-generate.
82
fd361982
AM		 832019-09-18 Alan Modra <amodra@gmail.com>
84
85 * arc-ext.c: Update throughout for bfd section macro changes.
86
e0b2a78c
SM		 872019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
88
89 * Makefile.in: Re-generate.
90 * configure: Re-generate.
91
7e9ad3a3
JW		 922019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
93
94 * riscv-opc.c (riscv_opcodes): Change subset field
95 to insn_class field for all instructions.
96 (riscv_insn_types): Likewise.
97
bb695960
PB		 982019-09-16 Phil Blundell <pb@pbcl.net>
99
100 * configure: Regenerated.
101
8063ab7e
MV		 1022019-09-10 Miod Vallat <miod@online.fr>
103
104 PR 24982
105 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
106
60391a25
PB		 1072019-09-09 Phil Blundell <pb@pbcl.net>
108
109 binutils 2.33 branch created.
110
f44b758d
NC		 1112019-09-03 Nick Clifton <nickc@redhat.com>
112
113 PR 24961
114 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
115 greater than zero before indexing via (bufcnt -1).
116
1e4b5e7d
NC		 1172019-09-03 Nick Clifton <nickc@redhat.com>
118
119 PR 24958
120 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
121 (MAX_SPEC_REG_NAME_LEN): Define.
122 (struct mmix_dis_info): Use defined constants for array lengths.
123 (get_reg_name): New function.
124 (get_sprec_reg_name): New function.
125 (print_insn_mmix): Use new functions.
126
c4a23bf8
SP		 1272019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
128
129 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
130 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
131 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
132
a051e2f3
KT		 1332019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
134
135 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
136 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
137 (aarch64_sys_reg_supported_p): Update checks for the above.
138
08132bdd
SP		 1392019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
140
141 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
142 cases MVE_SQRSHRL and MVE_UQRSHLL.
143 (print_insn_mve): Add case for specifier 'k' to check
144 specific bit of the instruction.
145
d88bdcb4
PA		 1462019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
147
148 PR 24854
149 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
150 encountering an unknown machine type.
151 (print_insn_arc): Handle arc_insn_length returning 0. In error
152 cases return -1 rather than calling abort.
153
bc750500
JB		 1542019-08-07 Jan Beulich <jbeulich@suse.com>
155
156 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
157 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
158 IgnoreSize.
159 * i386-tbl.h: Re-generate.
160
23d188c7
BW		 1612019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
162
163 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
164 instructions.
165
c0d6f62f
JW		 1662019-07-30 Mel Chen <mel.chen@sifive.com>
167
168 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
169 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
170
171 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
172 fscsr.
173
0f3f7167
CZ		 1742019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
175
176 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
177 and MPY class instructions.
178 (parse_option): Add nps400 option.
179 (print_arc_disassembler_options): Add nps400 info.
180
7e126ba3
CZ		 1812019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
182
183 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
184 (bspop): Likewise.
185 (modapp): Likewise.
186 * arc-opc.c (RAD_CHK): Add.
187 * arc-tbl.h: Regenerate.
188
a028026d
KT		 1892019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
190
191 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
192 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
193
ac79ff9e
NC		 1942019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
195
196 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
197 instructions as UNPREDICTABLE.
198
231097b0
JM		 1992019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
200
201 * bpf-desc.c: Regenerated.
202
1d942ae9
JB		 2032019-07-17 Jan Beulich <jbeulich@suse.com>
204
205 * i386-gen.c (static_assert): Define.
206 (main): Use it.
207 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
208 (Opcode_Modifier_Num): ... this.
209 (Mem): Delete.
210
dfd69174
JB		 2112019-07-16 Jan Beulich <jbeulich@suse.com>
212
213 * i386-gen.c (operand_types): Move RegMem ...
214 (opcode_modifiers): ... here.
215 * i386-opc.h (RegMem): Move to opcode modifer enum.
216 (union i386_operand_type): Move regmem field ...
217 (struct i386_opcode_modifier): ... here.
218 * i386-opc.tbl (RegMem): Define.
219 (mov, movq): Move RegMem on segment, control, debug, and test
220 register flavors.
221 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
222 to non-SSE2AVX flavor.
223 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
224 Move RegMem on register only flavors. Drop IgnoreSize from
225 legacy encoding flavors.
226 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
227 flavors.
228 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
229 register only flavors.
230 (vmovd): Move RegMem and drop IgnoreSize on register only
231 flavor. Change opcode and operand order to store form.
232 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
233
21df382b
JB		 2342019-07-16 Jan Beulich <jbeulich@suse.com>
235
236 * i386-gen.c (operand_type_init, operand_types): Replace SReg
237 entries.
238 * i386-opc.h (SReg2, SReg3): Replace by ...
239 (SReg): ... this.
240 (union i386_operand_type): Replace sreg fields.
241 * i386-opc.tbl (mov, ): Use SReg.
242 (push, pop): Likewies. Drop i386 and x86-64 specific segment
243 register flavors.
244 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
245 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
246
3719fd55
JM		 2472019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
248
249 * bpf-desc.c: Regenerate.
250 * bpf-opc.c: Likewise.
251 * bpf-opc.h: Likewise.
252
92434a14
JM		 2532019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
254
255 * bpf-desc.c: Regenerate.
256 * bpf-opc.c: Likewise.
257
43dd7626
HPN		 2582019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
259
260 * arm-dis.c (print_insn_coprocessor): Rename index to
261 index_operand.
262
98602811
JW		 2632019-07-05 Kito Cheng <kito.cheng@sifive.com>
264
265 * riscv-opc.c (riscv_insn_types): Add r4 type.
266
267 * riscv-opc.c (riscv_insn_types): Add b and j type.
268
269 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
270 format for sb type and correct s type.
271
01c1ee4a
RS		 2722019-07-02 Richard Sandiford <richard.sandiford@arm.com>
273
274 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
275 SVE FMOV alias of FCPY.
276
83adff69
RS		 2772019-07-02 Richard Sandiford <richard.sandiford@arm.com>
278
279 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
280 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
281
89418844
RS		 2822019-07-02 Richard Sandiford <richard.sandiford@arm.com>
283
284 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
285 registers in an instruction prefixed by MOVPRFX.
286
41be57ca
MM		 2872019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
288
289 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
290 sve_size_13 icode to account for variant behaviour of
291 pmull{t,b}.
292 * aarch64-dis-2.c: Regenerate.
293 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
294 sve_size_13 icode to account for variant behaviour of
295 pmull{t,b}.
296 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
297 (OP_SVE_VVV_Q_D): Add new qualifier.
298 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
299 (struct aarch64_opcode): Split pmull{t,b} into those requiring
300 AES and those not.
301
9d3bf266
JB		 3022019-07-01 Jan Beulich <jbeulich@suse.com>
303
304 * opcodes/i386-gen.c (operand_type_init): Remove
305 OPERAND_TYPE_VEC_IMM4 entry.
306 (operand_types): Remove Vec_Imm4.
307 * opcodes/i386-opc.h (Vec_Imm4): Delete.
308 (union i386_operand_type): Remove vec_imm4.
309 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
310 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
311
c3949f43
JB		 3122019-07-01 Jan Beulich <jbeulich@suse.com>
313
314 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
315 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
316 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
317 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
318 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
319 monitorx, mwaitx): Drop ImmExt from operand-less forms.
320 * i386-tbl.h: Re-generate.
321
5641ec01
JB		 3222019-07-01 Jan Beulich <jbeulich@suse.com>
323
324 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
325 register operands.
326 * i386-tbl.h: Re-generate.
327
79dec6b7
JB		 3282019-07-01 Jan Beulich <jbeulich@suse.com>
329
330 * i386-opc.tbl (C): New.
331 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
332 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
333 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
334 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
335 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
336 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
337 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
338 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
339 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
340 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
341 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
342 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
343 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
344 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
345 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
346 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
347 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
348 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
349 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
350 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
351 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
352 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
353 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
354 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
355 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
356 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
357 flavors.
358 * i386-tbl.h: Re-generate.
359
a0a1771e
JB		 3602019-07-01 Jan Beulich <jbeulich@suse.com>
361
362 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
363 register operands.
364 * i386-tbl.h: Re-generate.
365
cd546e7b
JB		 3662019-07-01 Jan Beulich <jbeulich@suse.com>
367
368 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
369 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
370 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
371 * i386-tbl.h: Re-generate.
372
e3bba3fc
JB		 3732019-07-01 Jan Beulich <jbeulich@suse.com>
374
375 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
376 Disp8MemShift from register only templates.
377 * i386-tbl.h: Re-generate.
378
36cc073e
JB		 3792019-07-01 Jan Beulich <jbeulich@suse.com>
380
381 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
382 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
383 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
384 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
385 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
386 EVEX_W_0F11_P_3_M_1): Delete.
387 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
388 EVEX_W_0F11_P_3): New.
389 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
390 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
391 MOD_EVEX_0F11_PREFIX_3 table entries.
392 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
393 PREFIX_EVEX_0F11 table entries.
394 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
395 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
396 EVEX_W_0F11_P_3_M_{0,1} table entries.
397
219920a7
JB		 3982019-07-01 Jan Beulich <jbeulich@suse.com>
399
400 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
401 Delete.
402
e395f487
L		 4032019-06-27 H.J. Lu <hongjiu.lu@intel.com>
404
405 PR binutils/24719
406 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
407 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
408 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
409 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
410 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
411 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
412 EVEX_LEN_0F38C7_R_6_P_2_W_1.
413 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
414 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
415 PREFIX_EVEX_0F38C6_REG_6 entries.
416 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
417 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
418 EVEX_W_0F38C7_R_6_P_2 entries.
419 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
420 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
421 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
422 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
423 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
424 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
425 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
426
2b7bcc87
JB		 4272019-06-27 Jan Beulich <jbeulich@suse.com>
428
429 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
430 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
431 VEX_LEN_0F2D_P_3): Delete.
432 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
433 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
434 (prefix_table): ... here.
435
c1dc7af5
JB		 4362019-06-27 Jan Beulich <jbeulich@suse.com>
437
438 * i386-dis.c (Iq): Delete.
439 (Id): New.
440 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
441 TBM insns.
442 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
443 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
444 (OP_E_memory): Also honor needindex when deciding whether an
445 address size prefix needs printing.
446 (OP_I): Remove handling of q_mode. Add handling of d_mode.
447
d7560e2d
JW		 4482019-06-26 Jim Wilson <jimw@sifive.com>
449
450 PR binutils/24739
451 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
452 Set info->display_endian to info->endian_code.
453
2c703856
JB		 4542019-06-25 Jan Beulich <jbeulich@suse.com>
455
456 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
457 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
458 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
459 OPERAND_TYPE_ACC64 entries.
460 * i386-init.h: Re-generate.
461
54fbadc0
JB		 4622019-06-25 Jan Beulich <jbeulich@suse.com>
463
464 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
465 Delete.
466 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
467 of dqa_mode.
468 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
469 entries here.
470 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
471 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
472
a280ab8e
JB		 4732019-06-25 Jan Beulich <jbeulich@suse.com>
474
475 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
476 variables.
477
e1a1babd
JB		 4782019-06-25 Jan Beulich <jbeulich@suse.com>
479
480 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
481 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
482 movnti.
d7560e2d 483 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 484 * i386-tbl.h: Re-generate.
485
b8364fa7
JB		 4862019-06-25 Jan Beulich <jbeulich@suse.com>
487
488 * i386-opc.tbl (and): Mark Imm8S form for optimization.
489 * i386-tbl.h: Re-generate.
490
ad692897
L		 4912019-06-21 H.J. Lu <hongjiu.lu@intel.com>
492
493 * i386-dis-evex.h: Break into ...
494 * i386-dis-evex-len.h: New file.
495 * i386-dis-evex-mod.h: Likewise.
496 * i386-dis-evex-prefix.h: Likewise.
497 * i386-dis-evex-reg.h: Likewise.
498 * i386-dis-evex-w.h: Likewise.
499 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
500 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
501 i386-dis-evex-mod.h.
502
f0a6222e
L		 5032019-06-19 H.J. Lu <hongjiu.lu@intel.com>
504
505 PR binutils/24700
506 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
507 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
508 EVEX_W_0F385B_P_2.
509 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
510 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
511 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
512 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
513 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
514 EVEX_LEN_0F385B_P_2_W_1.
515 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
516 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
517 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
518 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
519 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
520 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
521 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
522 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
523 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
524 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
525
6e1c90b7
L		 5262019-06-17 H.J. Lu <hongjiu.lu@intel.com>
527
528 PR binutils/24691
529 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
530 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
531 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
532 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
533 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
534 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
535 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
536 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
537 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
538 EVEX_LEN_0F3A43_P_2_W_1.
539 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
540 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
541 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
542 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
543 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
544 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
545 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
546 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
547 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
548 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
549 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
550 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
551
bcc5a6eb
NC		 5522019-06-14 Nick Clifton <nickc@redhat.com>
553
554 * po/fr.po; Updated French translation.
555
e4c4ac46
SH		 5562019-06-13 Stafford Horne <shorne@gmail.com>
557
558 * or1k-asm.c: Regenerated.
559 * or1k-desc.c: Regenerated.
560 * or1k-desc.h: Regenerated.
561 * or1k-dis.c: Regenerated.
562 * or1k-ibld.c: Regenerated.
563 * or1k-opc.c: Regenerated.
564 * or1k-opc.h: Regenerated.
565 * or1k-opinst.c: Regenerated.
566
a0e44ef5
PB		 5672019-06-12 Peter Bergner <bergner@linux.ibm.com>
568
569 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
570
12efd68d
L		 5712019-06-05 H.J. Lu <hongjiu.lu@intel.com>
572
573 PR binutils/24633
574 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
575 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
576 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
577 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
578 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
579 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
580 EVEX_LEN_0F3A1B_P_2_W_1.
581 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
582 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
583 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
584 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
585 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
586 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
587 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
588 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
589
63c6fc6c
L		 5902019-06-04 H.J. Lu <hongjiu.lu@intel.com>
591
592 PR binutils/24626
593 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
594 EVEX.vvvv when disassembling VEX and EVEX instructions.
595 (OP_VEX): Set vex.register_specifier to 0 after readding
596 vex.register_specifier.
597 (OP_Vex_2src_1): Likewise.
598 (OP_Vex_2src_2): Likewise.
599 (OP_LWP_E): Likewise.
600 (OP_EX_Vex): Don't check vex.register_specifier.
601 (OP_XMM_Vex): Likewise.
602
9186c494
L		 6032019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
604 Lili Cui <lili.cui@intel.com>
605
606 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
607 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
608 instructions.
609 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
610 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
611 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
612 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
613 (i386_cpu_flags): Add cpuavx512_vp2intersect.
614 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
615 * i386-init.h: Regenerated.
616 * i386-tbl.h: Likewise.
617
5d79adc4
L		 6182019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
619 Lili Cui <lili.cui@intel.com>
620
621 * doc/c-i386.texi: Document enqcmd.
622 * testsuite/gas/i386/enqcmd-intel.d: New file.
623 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
624 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
625 * testsuite/gas/i386/enqcmd.d: Likewise.
626 * testsuite/gas/i386/enqcmd.s: Likewise.
627 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
628 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
629 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
630 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
631 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
632 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
633 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
634 and x86-64-enqcmd.
635
a9d96ab9
AH		 6362019-06-04 Alan Hayward <alan.hayward@arm.com>
637
638 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
639
4f6d070a
AM		 6402019-06-03 Alan Modra <amodra@gmail.com>
641
642 * ppc-dis.c (prefix_opcd_indices): Correct size.
643
a2f4b66c
L		 6442019-05-28 H.J. Lu <hongjiu.lu@intel.com>
645
646 PR gas/24625
647 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
648 Disp8ShiftVL.
649 * i386-tbl.h: Regenerated.
650
405b5bd8
AM		 6512019-05-24 Alan Modra <amodra@gmail.com>
652
653 * po/POTFILES.in: Regenerate.
654
8acf1435
PB		 6552019-05-24 Peter Bergner <bergner@linux.ibm.com>
656 Alan Modra <amodra@gmail.com>
657
658 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
659 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
660 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
661 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
662 XTOP>): Define and add entries.
663 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
664 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
665 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
666 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
667
dd7efa79
PB		 6682019-05-24 Peter Bergner <bergner@linux.ibm.com>
669 Alan Modra <amodra@gmail.com>
670
671 * ppc-dis.c (ppc_opts): Add "future" entry.
672 (PREFIX_OPCD_SEGS): Define.
673 (prefix_opcd_indices): New array.
674 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
675 (lookup_prefix): New function.
676 (print_insn_powerpc): Handle 64-bit prefix instructions.
677 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
678 (PMRR, POWERXX): Define.
679 (prefix_opcodes): New instruction table.
680 (prefix_num_opcodes): New constant.
681
79472b45
JM		 6822019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
683
684 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
685 * configure: Regenerated.
686 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
687 and cpu/bpf.opc.
688 (HFILES): Add bpf-desc.h and bpf-opc.h.
689 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
690 bpf-ibld.c and bpf-opc.c.
691 (BPF_DEPS): Define.
692 * Makefile.in: Regenerated.
693 * disassemble.c (ARCH_bpf): Define.
694 (disassembler): Add case for bfd_arch_bpf.
695 (disassemble_init_for_target): Likewise.
696 (enum epbf_isa_attr): Define.
697 * disassemble.h: extern print_insn_bpf.
698 * bpf-asm.c: Generated.
699 * bpf-opc.h: Likewise.
700 * bpf-opc.c: Likewise.
701 * bpf-ibld.c: Likewise.
702 * bpf-dis.c: Likewise.
703 * bpf-desc.h: Likewise.
704 * bpf-desc.c: Likewise.
705
ba6cd17f
SD		 7062019-05-21 Sudakshina Das <sudi.das@arm.com>
707
708 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
709 and VMSR with the new operands.
710
e39c1607
SD		 7112019-05-21 Sudakshina Das <sudi.das@arm.com>
712
713 * arm-dis.c (enum mve_instructions): New enum
714 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
715 and cneg.
716 (mve_opcodes): New instructions as above.
717 (is_mve_encoding_conflict): Add cases for csinc, csinv,
718 csneg and csel.
719 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
720
23d00a41
SD		 7212019-05-21 Sudakshina Das <sudi.das@arm.com>
722
723 * arm-dis.c (emun mve_instructions): Updated for new instructions.
724 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
725 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
726 uqshl, urshrl and urshr.
727 (is_mve_okay_in_it): Add new instructions to TRUE list.
728 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
729 (print_insn_mve): Updated to accept new %j,
730 %<bitfield>m and %<bitfield>n patterns.
731
cd4797ee
FS		 7322019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
733
734 * mips-opc.c (mips_builtin_opcodes): Change source register
735 constraint for DAUI.
736
999b073b
NC		 7372019-05-20 Nick Clifton <nickc@redhat.com>
738
739 * po/fr.po: Updated French translation.
740
14b456f2
AV		 7412019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
742 Michael Collison <michael.collison@arm.com>
743
744 * arm-dis.c (thumb32_opcodes): Add new instructions.
745 (enum mve_instructions): Likewise.
746 (enum mve_undefined): Add new reasons.
747 (is_mve_encoding_conflict): Handle new instructions.
748 (is_mve_undefined): Likewise.
749 (is_mve_unpredictable): Likewise.
750 (print_mve_undefined): Likewise.
751 (print_mve_size): Likewise.
752
f49bb598
AV		 7532019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
754 Michael Collison <michael.collison@arm.com>
755
756 * arm-dis.c (thumb32_opcodes): Add new instructions.
757 (enum mve_instructions): Likewise.
758 (is_mve_encoding_conflict): Handle new instructions.
759 (is_mve_undefined): Likewise.
760 (is_mve_unpredictable): Likewise.
761 (print_mve_size): Likewise.
762
56858bea
AV		 7632019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
764 Michael Collison <michael.collison@arm.com>
765
766 * arm-dis.c (thumb32_opcodes): Add new instructions.
767 (enum mve_instructions): Likewise.
768 (is_mve_encoding_conflict): Likewise.
769 (is_mve_unpredictable): Likewise.
770 (print_mve_size): Likewise.
771
e523f101
AV		 7722019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
773 Michael Collison <michael.collison@arm.com>
774
775 * arm-dis.c (thumb32_opcodes): Add new instructions.
776 (enum mve_instructions): Likewise.
777 (is_mve_encoding_conflict): Handle new instructions.
778 (is_mve_undefined): Likewise.
779 (is_mve_unpredictable): Likewise.
780 (print_mve_size): Likewise.
781
66dcaa5d
AV		 7822019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
783 Michael Collison <michael.collison@arm.com>
784
785 * arm-dis.c (thumb32_opcodes): Add new instructions.
786 (enum mve_instructions): Likewise.
787 (is_mve_encoding_conflict): Handle new instructions.
788 (is_mve_undefined): Likewise.
789 (is_mve_unpredictable): Likewise.
790 (print_mve_size): Likewise.
791 (print_insn_mve): Likewise.
792
d052b9b7
AV		 7932019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
794 Michael Collison <michael.collison@arm.com>
795
796 * arm-dis.c (thumb32_opcodes): Add new instructions.
797 (print_insn_thumb32): Handle new instructions.
798
ed63aa17
AV		 7992019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
800 Michael Collison <michael.collison@arm.com>
801
802 * arm-dis.c (enum mve_instructions): Add new instructions.
803 (enum mve_undefined): Add new reasons.
804 (is_mve_encoding_conflict): Handle new instructions.
805 (is_mve_undefined): Likewise.
806 (is_mve_unpredictable): Likewise.
807 (print_mve_undefined): Likewise.
808 (print_mve_size): Likewise.
809 (print_mve_shift_n): Likewise.
810 (print_insn_mve): Likewise.
811
897b9bbc
AV		 8122019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
813 Michael Collison <michael.collison@arm.com>
814
815 * arm-dis.c (enum mve_instructions): Add new instructions.
816 (is_mve_encoding_conflict): Handle new instructions.
817 (is_mve_unpredictable): Likewise.
818 (print_mve_rotate): Likewise.
819 (print_mve_size): Likewise.
820 (print_insn_mve): Likewise.
821
1c8f2df8
AV		 8222019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
823 Michael Collison <michael.collison@arm.com>
824
825 * arm-dis.c (enum mve_instructions): Add new instructions.
826 (is_mve_encoding_conflict): Handle new instructions.
827 (is_mve_unpredictable): Likewise.
828 (print_mve_size): Likewise.
829 (print_insn_mve): Likewise.
830
d3b63143
AV		 8312019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
832 Michael Collison <michael.collison@arm.com>
833
834 * arm-dis.c (enum mve_instructions): Add new instructions.
835 (enum mve_undefined): Add new reasons.
836 (is_mve_encoding_conflict): Handle new instructions.
837 (is_mve_undefined): Likewise.
838 (is_mve_unpredictable): Likewise.
839 (print_mve_undefined): Likewise.
840 (print_mve_size): Likewise.
841 (print_insn_mve): Likewise.
842
14925797
AV		 8432019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
844 Michael Collison <michael.collison@arm.com>
845
846 * arm-dis.c (enum mve_instructions): Add new instructions.
847 (is_mve_encoding_conflict): Handle new instructions.
848 (is_mve_undefined): Likewise.
849 (is_mve_unpredictable): Likewise.
850 (print_mve_size): Likewise.
851 (print_insn_mve): Likewise.
852
c507f10b
AV		 8532019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
854 Michael Collison <michael.collison@arm.com>
855
856 * arm-dis.c (enum mve_instructions): Add new instructions.
857 (enum mve_unpredictable): Add new reasons.
858 (enum mve_undefined): Likewise.
859 (is_mve_okay_in_it): Handle new isntructions.
860 (is_mve_encoding_conflict): Likewise.
861 (is_mve_undefined): Likewise.
862 (is_mve_unpredictable): Likewise.
863 (print_mve_vmov_index): Likewise.
864 (print_simd_imm8): Likewise.
865 (print_mve_undefined): Likewise.
866 (print_mve_unpredictable): Likewise.
867 (print_mve_size): Likewise.
868 (print_insn_mve): Likewise.
869
bf0b396d
AV		 8702019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
871 Michael Collison <michael.collison@arm.com>
872
873 * arm-dis.c (enum mve_instructions): Add new instructions.
874 (enum mve_unpredictable): Add new reasons.
875 (enum mve_undefined): Likewise.
876 (is_mve_encoding_conflict): Handle new instructions.
877 (is_mve_undefined): Likewise.
878 (is_mve_unpredictable): Likewise.
879 (print_mve_undefined): Likewise.
880 (print_mve_unpredictable): Likewise.
881 (print_mve_rounding_mode): Likewise.
882 (print_mve_vcvt_size): Likewise.
883 (print_mve_size): Likewise.
884 (print_insn_mve): Likewise.
885
ef1576a1
AV		 8862019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
887 Michael Collison <michael.collison@arm.com>
888
889 * arm-dis.c (enum mve_instructions): Add new instructions.
890 (enum mve_unpredictable): Add new reasons.
891 (enum mve_undefined): Likewise.
892 (is_mve_undefined): Handle new instructions.
893 (is_mve_unpredictable): Likewise.
894 (print_mve_undefined): Likewise.
895 (print_mve_unpredictable): Likewise.
896 (print_mve_size): Likewise.
897 (print_insn_mve): Likewise.
898
aef6d006
AV		 8992019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
900 Michael Collison <michael.collison@arm.com>
901
902 * arm-dis.c (enum mve_instructions): Add new instructions.
903 (enum mve_undefined): Add new reasons.
904 (insns): Add new instructions.
905 (is_mve_encoding_conflict):
906 (print_mve_vld_str_addr): New print function.
907 (is_mve_undefined): Handle new instructions.
908 (is_mve_unpredictable): Likewise.
909 (print_mve_undefined): Likewise.
910 (print_mve_size): Likewise.
911 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
912 (print_insn_mve): Handle new operands.
913
04d54ace
AV		 9142019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
915 Michael Collison <michael.collison@arm.com>
916
917 * arm-dis.c (enum mve_instructions): Add new instructions.
918 (enum mve_unpredictable): Add new reasons.
919 (is_mve_encoding_conflict): Handle new instructions.
920 (is_mve_unpredictable): Likewise.
921 (mve_opcodes): Add new instructions.
922 (print_mve_unpredictable): Handle new reasons.
923 (print_mve_register_blocks): New print function.
924 (print_mve_size): Handle new instructions.
925 (print_insn_mve): Likewise.
926
9743db03
AV		 9272019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
928 Michael Collison <michael.collison@arm.com>
929
930 * arm-dis.c (enum mve_instructions): Add new instructions.
931 (enum mve_unpredictable): Add new reasons.
932 (enum mve_undefined): Likewise.
933 (is_mve_encoding_conflict): Handle new instructions.
934 (is_mve_undefined): Likewise.
935 (is_mve_unpredictable): Likewise.
936 (coprocessor_opcodes): Move NEON VDUP from here...
937 (neon_opcodes): ... to here.
938 (mve_opcodes): Add new instructions.
939 (print_mve_undefined): Handle new reasons.
940 (print_mve_unpredictable): Likewise.
941 (print_mve_size): Handle new instructions.
942 (print_insn_neon): Handle vdup.
943 (print_insn_mve): Handle new operands.
944
143275ea
AV		 9452019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
946 Michael Collison <michael.collison@arm.com>
947
948 * arm-dis.c (enum mve_instructions): Add new instructions.
949 (enum mve_unpredictable): Add new values.
950 (mve_opcodes): Add new instructions.
951 (vec_condnames): New array with vector conditions.
952 (mve_predicatenames): New array with predicate suffixes.
953 (mve_vec_sizename): New array with vector sizes.
954 (enum vpt_pred_state): New enum with vector predication states.
955 (struct vpt_block): New struct type for vpt blocks.
956 (vpt_block_state): Global struct to keep track of state.
957 (mve_extract_pred_mask): New helper function.
958 (num_instructions_vpt_block): Likewise.
959 (mark_outside_vpt_block): Likewise.
960 (mark_inside_vpt_block): Likewise.
961 (invert_next_predicate_state): Likewise.
962 (update_next_predicate_state): Likewise.
963 (update_vpt_block_state): Likewise.
964 (is_vpt_instruction): Likewise.
965 (is_mve_encoding_conflict): Add entries for new instructions.
966 (is_mve_unpredictable): Likewise.
967 (print_mve_unpredictable): Handle new cases.
968 (print_instruction_predicate): Likewise.
969 (print_mve_size): New function.
970 (print_vec_condition): New function.
971 (print_insn_mve): Handle vpt blocks and new print operands.
972
f08d8ce3
AV		 9732019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
974
975 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
976 8, 14 and 15 for Armv8.1-M Mainline.
977
73cd51e5
AV		 9782019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
979 Michael Collison <michael.collison@arm.com>
980
981 * arm-dis.c (enum mve_instructions): New enum.
982 (enum mve_unpredictable): Likewise.
983 (enum mve_undefined): Likewise.
984 (struct mopcode32): New struct.
985 (is_mve_okay_in_it): New function.
986 (is_mve_architecture): Likewise.
987 (arm_decode_field): Likewise.
988 (arm_decode_field_multiple): Likewise.
989 (is_mve_encoding_conflict): Likewise.
990 (is_mve_undefined): Likewise.
991 (is_mve_unpredictable): Likewise.
992 (print_mve_undefined): Likewise.
993 (print_mve_unpredictable): Likewise.
994 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
995 (print_insn_mve): New function.
996 (print_insn_thumb32): Handle MVE architecture.
997 (select_arm_features): Force thumb for Armv8.1-m Mainline.
998
3076e594
NC		 9992019-05-10 Nick Clifton <nickc@redhat.com>
1000
1001 PR 24538
1002 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1003 end of the table prematurely.
1004
387e7624
FS		 10052019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1006
1007 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1008 macros for R6.
1009
0067be51
AM		 10102019-05-11 Alan Modra <amodra@gmail.com>
1011
1012 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1013 when -Mraw is in effect.
1014
42e6288f
MM		 10152019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1016
1017 * aarch64-dis-2.c: Regenerate.
1018 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1019 (OP_SVE_BBB): New variant set.
1020 (OP_SVE_DDDD): New variant set.
1021 (OP_SVE_HHH): New variant set.
1022 (OP_SVE_HHHU): New variant set.
1023 (OP_SVE_SSS): New variant set.
1024 (OP_SVE_SSSU): New variant set.
1025 (OP_SVE_SHH): New variant set.
1026 (OP_SVE_SBBU): New variant set.
1027 (OP_SVE_DSS): New variant set.
1028 (OP_SVE_DHHU): New variant set.
1029 (OP_SVE_VMV_HSD_BHS): New variant set.
1030 (OP_SVE_VVU_HSD_BHS): New variant set.
1031 (OP_SVE_VVVU_SD_BH): New variant set.
1032 (OP_SVE_VVVU_BHSD): New variant set.
1033 (OP_SVE_VVV_QHD_DBS): New variant set.
1034 (OP_SVE_VVV_HSD_BHS): New variant set.
1035 (OP_SVE_VVV_HSD_BHS2): New variant set.
1036 (OP_SVE_VVV_BHS_HSD): New variant set.
1037 (OP_SVE_VV_BHS_HSD): New variant set.
1038 (OP_SVE_VVV_SD): New variant set.
1039 (OP_SVE_VVU_BHS_HSD): New variant set.
1040 (OP_SVE_VZVV_SD): New variant set.
1041 (OP_SVE_VZVV_BH): New variant set.
1042 (OP_SVE_VZV_SD): New variant set.
1043 (aarch64_opcode_table): Add sve2 instructions.
1044
28ed815a
MM		 10452019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1046
1047 * aarch64-asm-2.c: Regenerated.
1048 * aarch64-dis-2.c: Regenerated.
1049 * aarch64-opc-2.c: Regenerated.
1050 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1051 for SVE_SHLIMM_UNPRED_22.
1052 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1053 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1054 operand.
1055
fd1dc4a0
MM		 10562019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1057
1058 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1059 sve_size_tsz_bhs iclass encode.
1060 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1061 sve_size_tsz_bhs iclass decode.
1062
31e36ab3
MM		 10632019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1064
1065 * aarch64-asm-2.c: Regenerated.
1066 * aarch64-dis-2.c: Regenerated.
1067 * aarch64-opc-2.c: Regenerated.
1068 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1069 for SVE_Zm4_11_INDEX.
1070 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1071 (fields): Handle SVE_i2h field.
1072 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1073 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1074
1be5f94f
MM		 10752019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1076
1077 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1078 sve_shift_tsz_bhsd iclass encode.
1079 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1080 sve_shift_tsz_bhsd iclass decode.
1081
3c17238b
MM		 10822019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1083
1084 * aarch64-asm-2.c: Regenerated.
1085 * aarch64-dis-2.c: Regenerated.
1086 * aarch64-opc-2.c: Regenerated.
1087 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1088 (aarch64_encode_variant_using_iclass): Handle
1089 sve_shift_tsz_hsd iclass encode.
1090 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1091 sve_shift_tsz_hsd iclass decode.
1092 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1093 for SVE_SHRIMM_UNPRED_22.
1094 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1095 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1096 operand.
1097
cd50a87a
MM		 10982019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1099
1100 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1101 sve_size_013 iclass encode.
1102 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1103 sve_size_013 iclass decode.
1104
3c705960
MM		 11052019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1106
1107 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1108 sve_size_bh iclass encode.
1109 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1110 sve_size_bh iclass decode.
1111
0a57e14f
MM		 11122019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1113
1114 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1115 sve_size_sd2 iclass encode.
1116 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1117 sve_size_sd2 iclass decode.
1118 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1119 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1120
c469c864
MM		 11212019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1122
1123 * aarch64-asm-2.c: Regenerated.
1124 * aarch64-dis-2.c: Regenerated.
1125 * aarch64-opc-2.c: Regenerated.
1126 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1127 for SVE_ADDR_ZX.
1128 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1129 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1130
116adc27
MM		 11312019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1132
1133 * aarch64-asm-2.c: Regenerated.
1134 * aarch64-dis-2.c: Regenerated.
1135 * aarch64-opc-2.c: Regenerated.
1136 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1137 for SVE_Zm3_11_INDEX.
1138 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1139 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1140 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1141 fields.
1142 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1143
3bd82c86
MM		 11442019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1145
1146 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1147 sve_size_hsd2 iclass encode.
1148 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1149 sve_size_hsd2 iclass decode.
1150 * aarch64-opc.c (fields): Handle SVE_size field.
1151 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1152
adccc507
MM		 11532019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1154
1155 * aarch64-asm-2.c: Regenerated.
1156 * aarch64-dis-2.c: Regenerated.
1157 * aarch64-opc-2.c: Regenerated.
1158 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1159 for SVE_IMM_ROT3.
1160 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1161 (fields): Handle SVE_rot3 field.
1162 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1163 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1164
5cd99750
MM		 11652019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1166
1167 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1168 instructions.
1169
7ce2460a
MM		 11702019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1171
1172 * aarch64-tbl.h
1173 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1174 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1175 aarch64_feature_sve2bitperm): New feature sets.
1176 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1177 for feature set addresses.
1178 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1179 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1180
41cee089
FS		 11812019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1182 Faraz Shahbazker <fshahbazker@wavecomp.com>
1183
1184 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1185 argument and set ASE_EVA_R6 appropriately.
1186 (set_default_mips_dis_options): Pass ISA to above.
1187 (parse_mips_dis_option): Likewise.
1188 * mips-opc.c (EVAR6): New macro.
1189 (mips_builtin_opcodes): Add llwpe, scwpe.
1190
b83b4b13
SD		 11912019-05-01 Sudakshina Das <sudi.das@arm.com>
1192
1193 * aarch64-asm-2.c: Regenerated.
1194 * aarch64-dis-2.c: Regenerated.
1195 * aarch64-opc-2.c: Regenerated.
1196 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1197 AARCH64_OPND_TME_UIMM16.
1198 (aarch64_print_operand): Likewise.
1199 * aarch64-tbl.h (QL_IMM_NIL): New.
1200 (TME): New.
1201 (_TME_INSN): New.
1202 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1203
4a90ce95
JD		 12042019-04-29 John Darrington <john@darrington.wattle.id.au>
1205
1206 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1207
a45328b9
AB		 12082019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1209 Faraz Shahbazker <fshahbazker@wavecomp.com>
1210
1211 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1212
d10be0cb
JD		 12132019-04-24 John Darrington <john@darrington.wattle.id.au>
1214
1215 * s12z-opc.h: Add extern "C" bracketing to help
1216 users who wish to use this interface in c++ code.
1217
a679f24e
JD		 12182019-04-24 John Darrington <john@darrington.wattle.id.au>
1219
1220 * s12z-opc.c (bm_decode): Handle bit map operations with the
1221 "reserved0" mode.
1222
32c36c3c
AV		 12232019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1224
1225 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1226 specifier. Add entries for VLDR and VSTR of system registers.
1227 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1228 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1229 of %J and %K format specifier.
1230
efd6b359
AV		 12312019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1232
1233 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1234 Add new entries for VSCCLRM instruction.
1235 (print_insn_coprocessor): Handle new %C format control code.
1236
6b0dd094
AV		 12372019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1238
1239 * arm-dis.c (enum isa): New enum.
1240 (struct sopcode32): New structure.
1241 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1242 set isa field of all current entries to ANY.
1243 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1244 Only match an entry if its isa field allows the current mode.
1245
4b5a202f
AV		 12462019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1247
1248 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1249 CLRM.
1250 (print_insn_thumb32): Add logic to print %n CLRM register list.
1251
60f993ce
AV		 12522019-04-15 Sudakshina Das <sudi.das@arm.com>
1253
1254 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1255 and %Q patterns.
1256
f6b2b12d
AV		 12572019-04-15 Sudakshina Das <sudi.das@arm.com>
1258
1259 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1260 (print_insn_thumb32): Edit the switch case for %Z.
1261
1889da70
AV		 12622019-04-15 Sudakshina Das <sudi.das@arm.com>
1263
1264 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1265
65d1bc05
AV		 12662019-04-15 Sudakshina Das <sudi.das@arm.com>
1267
1268 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1269
1caf72a5
AV		 12702019-04-15 Sudakshina Das <sudi.das@arm.com>
1271
1272 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1273
f1c7f421
AV		 12742019-04-15 Sudakshina Das <sudi.das@arm.com>
1275
1276 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1277 Arm register with r13 and r15 unpredictable.
1278 (thumb32_opcodes): New instructions for bfx and bflx.
1279
4389b29a
AV		 12802019-04-15 Sudakshina Das <sudi.das@arm.com>
1281
1282 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1283
e5d6e09e
AV		 12842019-04-15 Sudakshina Das <sudi.das@arm.com>
1285
1286 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1287
e12437dc
AV		 12882019-04-15 Sudakshina Das <sudi.das@arm.com>
1289
1290 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1291
031254f2
AV		 12922019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1293
1294 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1295
e5a557ac
JD		 12962019-04-12 John Darrington <john@darrington.wattle.id.au>
1297
1298 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1299 "optr". ("operator" is a reserved word in c++).
1300
bd7ceb8d
SD		 13012019-04-11 Sudakshina Das <sudi.das@arm.com>
1302
1303 * aarch64-opc.c (aarch64_print_operand): Add case for
1304 AARCH64_OPND_Rt_SP.
1305 (verify_constraints): Likewise.
1306 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1307 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1308 to accept Rt|SP as first operand.
1309 (AARCH64_OPERANDS): Add new Rt_SP.
1310 * aarch64-asm-2.c: Regenerated.
1311 * aarch64-dis-2.c: Regenerated.
1312 * aarch64-opc-2.c: Regenerated.
1313
e54010f1
SD		 13142019-04-11 Sudakshina Das <sudi.das@arm.com>
1315
1316 * aarch64-asm-2.c: Regenerated.
1317 * aarch64-dis-2.c: Likewise.
1318 * aarch64-opc-2.c: Likewise.
1319 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1320
7e96e219
RS		 13212019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1322
1323 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1324
6f2791d5
L		 13252019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1326
1327 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1328 * i386-init.h: Regenerated.
1329
e392bad3
AM		 13302019-04-07 Alan Modra <amodra@gmail.com>
1331
1332 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1333 op_separator to control printing of spaces, comma and parens
1334 rather than need_comma, need_paren and spaces vars.
1335
dffaa15c
AM		 13362019-04-07 Alan Modra <amodra@gmail.com>
1337
1338 PR 24421
1339 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1340 (print_insn_neon, print_insn_arm): Likewise.
1341
d6aab7a1
XG		 13422019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1343
1344 * i386-dis-evex.h (evex_table): Updated to support BF16
1345 instructions.
1346 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1347 and EVEX_W_0F3872_P_3.
1348 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1349 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1350 * i386-opc.h (enum): Add CpuAVX512_BF16.
1351 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1352 * i386-opc.tbl: Add AVX512 BF16 instructions.
1353 * i386-init.h: Regenerated.
1354 * i386-tbl.h: Likewise.
1355
66e85460
AM		 13562019-04-05 Alan Modra <amodra@gmail.com>
1357
1358 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1359 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1360 to favour printing of "-" branch hint when using the "y" bit.
1361 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1362
c2b1c275
AM		 13632019-04-05 Alan Modra <amodra@gmail.com>
1364
1365 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1366 opcode until first operand is output.
1367
aae9718e
PB		 13682019-04-04 Peter Bergner <bergner@linux.ibm.com>
1369
1370 PR gas/24349
1371 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1372 (valid_bo_post_v2): Add support for 'at' branch hints.
1373 (insert_bo): Only error on branch on ctr.
1374 (get_bo_hint_mask): New function.
1375 (insert_boe): Add new 'branch_taken' formal argument. Add support
1376 for inserting 'at' branch hints.
1377 (extract_boe): Add new 'branch_taken' formal argument. Add support
1378 for extracting 'at' branch hints.
1379 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1380 (BOE): Delete operand.
1381 (BOM, BOP): New operands.
1382 (RM): Update value.
1383 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1384 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1385 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1386 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1387 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1388 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1389 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1390 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1391 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1392 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1393 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1394 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1395 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1396 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1397 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1398 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1399 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1400 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1401 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1402 bttarl+>: New extended mnemonics.
1403
96a86c01
AM		 14042019-03-28 Alan Modra <amodra@gmail.com>
1405
1406 PR 24390
1407 * ppc-opc.c (BTF): Define.
1408 (powerpc_opcodes): Use for mtfsb*.
1409 * ppc-dis.c (print_insn_powerpc): Print fields with both
1410 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1411
796d6298
TC		 14122019-03-25 Tamar Christina <tamar.christina@arm.com>
1413
1414 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1415 (mapping_symbol_for_insn): Implement new algorithm.
1416 (print_insn): Remove duplicate code.
1417
60df3720
TC		 14182019-03-25 Tamar Christina <tamar.christina@arm.com>
1419
1420 * aarch64-dis.c (print_insn_aarch64):
1421 Implement override.
1422
51457761
TC		 14232019-03-25 Tamar Christina <tamar.christina@arm.com>
1424
1425 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1426 order.
1427
53b2f36b
TC		 14282019-03-25 Tamar Christina <tamar.christina@arm.com>
1429
1430 * aarch64-dis.c (last_stop_offset): New.
1431 (print_insn_aarch64): Use stop_offset.
1432
89199bb5
L		 14332019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1434
1435 PR gas/24359
1436 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1437 CPU_ANY_AVX2_FLAGS.
1438 * i386-init.h: Regenerated.
1439
97ed31ae
L		 14402019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1441
1442 PR gas/24348
1443 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1444 vmovdqu16, vmovdqu32 and vmovdqu64.
1445 * i386-tbl.h: Regenerated.
1446
0919bfe9
AK		 14472019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1448
1449 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1450 from vstrszb, vstrszh, and vstrszf.
1451
14522019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1453
1454 * s390-opc.txt: Add instruction descriptions.
1455
21820ebe
JW		 14562019-02-08 Jim Wilson <jimw@sifive.com>
1457
1458 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1459 <bne>: Likewise.
1460
f7dd2fb2
TC		 14612019-02-07 Tamar Christina <tamar.christina@arm.com>
1462
1463 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1464
6456d318
TC		 14652019-02-07 Tamar Christina <tamar.christina@arm.com>
1466
1467 PR binutils/23212
1468 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1469 * aarch64-opc.c (verify_elem_sd): New.
1470 (fields): Add FLD_sz entr.
1471 * aarch64-tbl.h (_SIMD_INSN): New.
1472 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1473 fmulx scalar and vector by element isns.
1474
4a83b610
NC		 14752019-02-07 Nick Clifton <nickc@redhat.com>
1476
1477 * po/sv.po: Updated Swedish translation.
1478
fc60b8c8
AK		 14792019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1480
1481 * s390-mkopc.c (main): Accept arch13 as cpu string.
1482 * s390-opc.c: Add new instruction formats and instruction opcode
1483 masks.
1484 * s390-opc.txt: Add new arch13 instructions.
1485
e10620d3
TC		 14862019-01-25 Sudakshina Das <sudi.das@arm.com>
1487
1488 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1489 (aarch64_opcode): Change encoding for stg, stzg
1490 st2g and st2zg.
1491 * aarch64-asm-2.c: Regenerated.
1492 * aarch64-dis-2.c: Regenerated.
1493 * aarch64-opc-2.c: Regenerated.
1494
20a4ca55
SD		 14952019-01-25 Sudakshina Das <sudi.das@arm.com>
1496
1497 * aarch64-asm-2.c: Regenerated.
1498 * aarch64-dis-2.c: Likewise.
1499 * aarch64-opc-2.c: Likewise.
1500 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1501
550fd7bf
SD		 15022019-01-25 Sudakshina Das <sudi.das@arm.com>
1503 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1504
1505 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1506 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1507 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1508 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1509 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1510 case for ldstgv_indexed.
1511 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1512 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1513 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1514 * aarch64-asm-2.c: Regenerated.
1515 * aarch64-dis-2.c: Regenerated.
1516 * aarch64-opc-2.c: Regenerated.
1517
d9938630
NC		 15182019-01-23 Nick Clifton <nickc@redhat.com>
1519
1520 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1521
375cd423
NC		 15222019-01-21 Nick Clifton <nickc@redhat.com>
1523
1524 * po/de.po: Updated German translation.
1525 * po/uk.po: Updated Ukranian translation.
1526
57299f48
CX		 15272019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1528 * mips-dis.c (mips_arch_choices): Fix typo in
1529 gs464, gs464e and gs264e descriptors.
1530
f48dfe41
NC		 15312019-01-19 Nick Clifton <nickc@redhat.com>
1532
1533 * configure: Regenerate.
1534 * po/opcodes.pot: Regenerate.
1535
f974f26c
NC		 15362018-06-24 Nick Clifton <nickc@redhat.com>
1537
1538 2.32 branch created.
1539
39f286cd
JD		 15402019-01-09 John Darrington <john@darrington.wattle.id.au>
1541
448b8ca8
JD		 1542 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1543 if it is null.
1544 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 1545 zero.
1546
3107326d
AP		 15472019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1548
1549 * configure: Regenerate.
1550
7e9ca91e
AM		 15512019-01-07 Alan Modra <amodra@gmail.com>
1552
1553 * configure: Regenerate.
1554 * po/POTFILES.in: Regenerate.
1555
ef1ad42b
JD		 15562019-01-03 John Darrington <john@darrington.wattle.id.au>
1557
1558 * s12z-opc.c: New file.
1559 * s12z-opc.h: New file.
1560 * s12z-dis.c: Removed all code not directly related to display
1561 of instructions. Used the interface provided by the new files
1562 instead.
1563 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 1564 * Makefile.in: Regenerate.
ef1ad42b 1565 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 1566 * configure: Regenerate.
ef1ad42b 1567
82704155
AM		 15682019-01-01 Alan Modra <amodra@gmail.com>
1569
1570 Update year range in copyright notice of all files.
1571
d5c04e1b 1572For older changes see ChangeLog-2018
3499769a 1573\f
d5c04e1b 1574Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 1575
1576Copying and distribution of this file, with or without modification,
1577are permitted in any medium without royalty provided the copyright
1578notice and this notice are preserved.
1579
1580Local Variables:
1581mode: change-log
1582left-margin: 8
1583fill-column: 74
1584version-control: never
1585End:
GDB Binutils - Deliverables
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