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[AArch64][SVE 02/32] Avoid hard-coded limit in indented_print
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
bd11d5d8
RS		 12016-09-21 Richard Sandiford <richard.sandiford@arm.com>
2
3 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
4
f807f43d
CZ		 52016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
6
7 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
8
fd486b63
PB		 92016-09-14 Peter Bergner <bergner@vnet.ibm.com>
10
11 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
12 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
13 xor3>: Delete mnemonics.
14 <cp_abort>: Rename mnemonic from ...
15 <cpabort>: ...to this.
16 <setb>: Change to a X form instruction.
17 <sync>: Change to 1 operand form.
18 <copy>: Delete mnemonic.
19 <copy_first>: Rename mnemonic from ...
20 <copy>: ...to this.
21 <paste, paste.>: Delete mnemonics.
22 <paste_last>: Rename mnemonic from ...
23 <paste.>: ...to this.
24
dce08442
AK		 252016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
26
27 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
28
952c3f51
AK		 292016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
30
31 * s390-mkopc.c (main): Support alternate arch strings.
32
8b71537b
PS		 332016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
34
35 * s390-opc.txt: Fix kmctr instruction type.
36
5b64d091
L		 372016-09-07 H.J. Lu <hongjiu.lu@intel.com>
38
39 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
40 * i386-init.h: Regenerated.
41
7763838e
CM		 422016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
43
44 * opcodes/arc-dis.c (print_insn_arc): Changed.
45
1b8b6532
JM		 462016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
47
48 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
49 camellia_fl.
50
1a336194
TP		 512016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
52
53 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
54 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
55 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
56
6b40c462
L		 572016-08-24 H.J. Lu <hongjiu.lu@intel.com>
58
59 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
60 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
61 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
62 PREFIX_MOD_3_0FAE_REG_4.
63 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
64 PREFIX_MOD_3_0FAE_REG_4.
65 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
66 (cpu_flags): Add CpuPTWRITE.
67 * i386-opc.h (CpuPTWRITE): New.
68 (i386_cpu_flags): Add cpuptwrite.
69 * i386-opc.tbl: Add ptwrite instruction.
70 * i386-init.h: Regenerated.
71 * i386-tbl.h: Likewise.
72
ab548d2d
AK		 732016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
74
75 * arc-dis.h: Wrap around in extern "C".
76
344bde0a
RS		 772016-08-23 Richard Sandiford <richard.sandiford@arm.com>
78
79 * aarch64-tbl.h (V8_2_INSN): New macro.
80 (aarch64_opcode_table): Use it.
81
5ce912d8
RS		 822016-08-23 Richard Sandiford <richard.sandiford@arm.com>
83
84 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
85 CORE_INSN, __FP_INSN and SIMD_INSN.
86
9d30b0bd
RS		 872016-08-23 Richard Sandiford <richard.sandiford@arm.com>
88
89 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
90 (aarch64_opcode_table): Update uses accordingly.
91
dfdaec14
AJ		 922016-07-25 Andrew Jenner <andrew@codesourcery.com>
93 Kwok Cheung Yeung <kcy@codesourcery.com>
94
95 opcodes/
96 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
97 'e_cmplwi' to 'e_cmpli' instead.
98 (OPVUPRT, OPVUPRT_MASK): Define.
99 (powerpc_opcodes): Add E200Z4 insns.
100 (vle_opcodes): Add context save/restore insns.
101
7bd374a4
MR		 1022016-07-27 Maciej W. Rozycki <macro@imgtec.com>
103
104 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
105 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
106 "j".
107
db18dbab
GM		 1082016-07-27 Graham Markall <graham.markall@embecosm.com>
109
110 * arc-nps400-tbl.h: Change block comments to GNU format.
111 * arc-dis.c: Add new globals addrtypenames,
112 addrtypenames_max, and addtypeunknown.
113 (get_addrtype): New function.
114 (print_insn_arc): Print colons and address types when
115 required.
116 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
117 define insert and extract functions for all address types.
118 (arc_operands): Add operands for colon and all address
119 types.
120 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
121 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
122 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
123 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
124 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
125 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
126
fecd57f9
L		 1272016-07-21 H.J. Lu <hongjiu.lu@intel.com>
128
129 * configure: Regenerated.
130
37fd5ef3
CZ		 1312016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
132
133 * arc-dis.c (skipclass): New structure.
134 (decodelist): New variable.
135 (is_compatible_p): New function.
136 (new_element): Likewise.
137 (skip_class_p): Likewise.
138 (find_format_from_table): Use skip_class_p function.
139 (find_format): Decode first the extension instructions.
140 (print_insn_arc): Select either ARCEM or ARCHS based on elf
141 e_flags.
142 (parse_option): New function.
143 (parse_disassembler_options): Likewise.
144 (print_arc_disassembler_options): Likewise.
145 (print_insn_arc): Use parse_disassembler_options function. Proper
146 select ARCv2 cpu variant.
147 * disassemble.c (disassembler_usage): Add ARC disassembler
148 options.
149
92281a5b
MR		 1502016-07-13 Maciej W. Rozycki <macro@imgtec.com>
151
152 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
153 annotation from the "nal" entry and reorder it beyond "bltzal".
154
6e7ced37
JM		 1552016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
156
157 * sparc-opc.c (ldtxa): New macro.
158 (sparc_opcodes): Use the macro defined above to add entries for
159 the LDTXA instructions.
160 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
161 instruction.
162
2f831b9a 1632016-07-07 James Bowman <james.bowman@ftdichip.com>
164
165 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
166 and "jmpc".
167
c07315e0
JB		 1682016-07-01 Jan Beulich <jbeulich@suse.com>
169
170 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
171 (movzb): Adjust to cover all permitted suffixes.
172 (movzw): New.
173 * i386-tbl.h: Re-generate.
174
9243100a
JB		 1752016-07-01 Jan Beulich <jbeulich@suse.com>
176
177 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
178 (lgdt): Remove Tbyte from non-64-bit variant.
179 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
180 xsaves64, xsavec64): Remove Disp16.
181 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
182 Remove Disp32S from non-64-bit variants. Remove Disp16 from
183 64-bit variants.
184 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
185 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
186 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
187 64-bit variants.
188 * i386-tbl.h: Re-generate.
189
8325cc63
JB		 1902016-07-01 Jan Beulich <jbeulich@suse.com>
191
192 * i386-opc.tbl (xlat): Remove RepPrefixOk.
193 * i386-tbl.h: Re-generate.
194
838441e4
YQ		 1952016-06-30 Yao Qi <yao.qi@linaro.org>
196
197 * arm-dis.c (print_insn): Fix typo in comment.
198
dab26bf4
RS		 1992016-06-28 Richard Sandiford <richard.sandiford@arm.com>
200
201 * aarch64-opc.c (operand_general_constraint_met_p): Check the
202 range of ldst_elemlist operands.
203 (print_register_list): Use PRIi64 to print the index.
204 (aarch64_print_operand): Likewise.
205
5703197e
TS		 2062016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
207
208 * mcore-opc.h: Remove sentinal.
209 * mcore-dis.c (print_insn_mcore): Adjust.
210
ce440d63
GM		 2112016-06-23 Graham Markall <graham.markall@embecosm.com>
212
213 * arc-opc.c: Correct description of availability of NPS400
214 features.
215
6fd3a02d
PB		 2162016-06-22 Peter Bergner <bergner@vnet.ibm.com>
217
218 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
219 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
220 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
221 xor3>: New mnemonics.
222 <setb>: Change to a VX form instruction.
223 (insert_sh6): Add support for rldixor.
224 (extract_sh6): Likewise.
225
6b477896
TS		 2262016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
227
228 * arc-ext.h: Wrap in extern C.
229
bdd582db
GM		 2302016-06-21 Graham Markall <graham.markall@embecosm.com>
231
232 * arc-dis.c (arc_insn_length): Add comment on instruction length.
233 Use same method for determining instruction length on ARC700 and
234 NPS-400.
235 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
236 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
237 with the NPS400 subclass.
238 * arc-opc.c: Likewise.
239
96074adc
JM		 2402016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
241
242 * sparc-opc.c (rdasr): New macro.
243 (wrasr): Likewise.
244 (rdpr): Likewise.
245 (wrpr): Likewise.
246 (rdhpr): Likewise.
247 (wrhpr): Likewise.
248 (sparc_opcodes): Use the macros above to fix and expand the
249 definition of read/write instructions from/to
250 asr/privileged/hyperprivileged instructions.
251 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
252 %hva_mask_nz. Prefer softint_set and softint_clear over
253 set_softint and clear_softint.
254 (print_insn_sparc): Support %ver in Rd.
255
7a10c22f
JM		 2562016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
257
258 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
259 architecture according to the hardware capabilities they require.
260
4f26fb3a
JM		 2612016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
262
263 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
264 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
265 bfd_mach_sparc_v9{c,d,e,v,m}.
266 * sparc-opc.c (MASK_V9C): Define.
267 (MASK_V9D): Likewise.
268 (MASK_V9E): Likewise.
269 (MASK_V9V): Likewise.
270 (MASK_V9M): Likewise.
271 (v6): Add MASK_V9{C,D,E,V,M}.
272 (v6notlet): Likewise.
273 (v7): Likewise.
274 (v8): Likewise.
275 (v9): Likewise.
276 (v9andleon): Likewise.
277 (v9a): Likewise.
278 (v9b): Likewise.
279 (v9c): Define.
280 (v9d): Likewise.
281 (v9e): Likewise.
282 (v9v): Likewise.
283 (v9m): Likewise.
284 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
285
3ee6e4fb
NC		 2862016-06-15 Nick Clifton <nickc@redhat.com>
287
288 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
289 constants to match expected behaviour.
290 (nds32_parse_opcode): Likewise. Also for whitespace.
291
02f3be19
AB		 2922016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
293
294 * arc-opc.c (extract_rhv1): Extract value from insn.
295
6f9f37ed 2962016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 297
298 * arc-nps400-tbl.h: Add ldbit instruction.
299 * arc-opc.c: Add flag classes required for ldbit.
300
6f9f37ed 3012016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 302
303 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
304 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
305 support the above instructions.
306
6f9f37ed 3072016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 308
309 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
310 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
311 csma, cbba, zncv, and hofs.
312 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
313 support the above instructions.
314
3152016-06-06 Graham Markall <graham.markall@embecosm.com>
316
317 * arc-nps400-tbl.h: Add andab and orab instructions.
318
3192016-06-06 Graham Markall <graham.markall@embecosm.com>
320
321 * arc-nps400-tbl.h: Add addl-like instructions.
322
3232016-06-06 Graham Markall <graham.markall@embecosm.com>
324
325 * arc-nps400-tbl.h: Add mxb and imxb instructions.
326
3272016-06-06 Graham Markall <graham.markall@embecosm.com>
328
329 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
330 instructions.
331
b2cc3f6f
AK		 3322016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
333
334 * s390-dis.c (option_use_insn_len_bits_p): New file scope
335 variable.
336 (init_disasm): Handle new command line option "insnlength".
337 (print_s390_disassembler_options): Mention new option in help
338 output.
339 (print_insn_s390): Use the encoded insn length when dumping
340 unknown instructions.
341
1857fe72
DC		 3422016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
343
344 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
345 to the address and set as symbol address for LDS/ STS immediate operands.
346
14b57c7c
AM		 3472016-06-07 Alan Modra <amodra@gmail.com>
348
349 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
350 cpu for "vle" to e500.
351 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
352 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
353 (PPCNONE): Delete, substitute throughout.
354 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
355 except for major opcode 4 and 31.
356 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
357
4d1464f2
MW		 3582016-06-07 Matthew Wahab <matthew.wahab@arm.com>
359
360 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
361 ARM_EXT_RAS in relevant entries.
362
026122a6
PB		 3632016-06-03 Peter Bergner <bergner@vnet.ibm.com>
364
365 PR binutils/20196
366 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
367 opcodes for E6500.
368
07f5af7d
L		 3692016-06-03 H.J. Lu <hongjiu.lu@intel.com>
370
371 PR binutis/18386
372 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
373 (indir_v_mode): New.
374 Add comments for '&'.
375 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
376 (putop): Handle '&'.
377 (intel_operand_size): Handle indir_v_mode.
378 (OP_E_register): Likewise.
379 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
380 64-bit indirect call/jmp for AMD64.
381 * i386-tbl.h: Regenerated
382
4eb6f892
AB		 3832016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
384
385 * arc-dis.c (struct arc_operand_iterator): New structure.
386 (find_format_from_table): All the old content from find_format,
387 with some minor adjustments, and parameter renaming.
388 (find_format_long_instructions): New function.
389 (find_format): Rewritten.
390 (arc_insn_length): Add LSB parameter.
391 (extract_operand_value): New function.
392 (operand_iterator_next): New function.
393 (print_insn_arc): Use new functions to find opcode, and iterator
394 over operands.
395 * arc-opc.c (insert_nps_3bit_dst_short): New function.
396 (extract_nps_3bit_dst_short): New function.
397 (insert_nps_3bit_src2_short): New function.
398 (extract_nps_3bit_src2_short): New function.
399 (insert_nps_bitop1_size): New function.
400 (extract_nps_bitop1_size): New function.
401 (insert_nps_bitop2_size): New function.
402 (extract_nps_bitop2_size): New function.
403 (insert_nps_bitop_mod4_msb): New function.
404 (extract_nps_bitop_mod4_msb): New function.
405 (insert_nps_bitop_mod4_lsb): New function.
406 (extract_nps_bitop_mod4_lsb): New function.
407 (insert_nps_bitop_dst_pos3_pos4): New function.
408 (extract_nps_bitop_dst_pos3_pos4): New function.
409 (insert_nps_bitop_ins_ext): New function.
410 (extract_nps_bitop_ins_ext): New function.
411 (arc_operands): Add new operands.
412 (arc_long_opcodes): New global array.
413 (arc_num_long_opcodes): New global.
414 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
415
1fe0971e
TS		 4162016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
417
418 * nds32-asm.h: Add extern "C".
419 * sh-opc.h: Likewise.
420
315f180f
GM		 4212016-06-01 Graham Markall <graham.markall@embecosm.com>
422
423 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
424 0,b,limm to the rflt instruction.
425
a2b5fccc
TS		 4262016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
427
428 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
429 constant.
430
0cbd0046
L		 4312016-05-29 H.J. Lu <hongjiu.lu@intel.com>
432
433 PR gas/20145
434 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
435 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
436 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
437 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
438 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
439 * i386-init.h: Regenerated.
440
1848e567
L		 4412016-05-27 H.J. Lu <hongjiu.lu@intel.com>
442
443 PR gas/20145
444 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
445 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
446 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
447 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
448 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
449 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
450 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
451 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
452 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
453 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
454 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
455 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
456 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
457 CpuRegMask for AVX512.
458 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
459 and CpuRegMask.
460 (set_bitfield_from_cpu_flag_init): New function.
461 (set_bitfield): Remove const on f. Call
462 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
463 * i386-opc.h (CpuRegMMX): New.
464 (CpuRegXMM): Likewise.
465 (CpuRegYMM): Likewise.
466 (CpuRegZMM): Likewise.
467 (CpuRegMask): Likewise.
468 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
469 and cpuregmask.
470 * i386-init.h: Regenerated.
471 * i386-tbl.h: Likewise.
472
e92bae62
L		 4732016-05-27 H.J. Lu <hongjiu.lu@intel.com>
474
475 PR gas/20154
476 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
477 (opcode_modifiers): Add AMD64 and Intel64.
478 (main): Properly verify CpuMax.
479 * i386-opc.h (CpuAMD64): Removed.
480 (CpuIntel64): Likewise.
481 (CpuMax): Set to CpuNo64.
482 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
483 (AMD64): New.
484 (Intel64): Likewise.
485 (i386_opcode_modifier): Add amd64 and intel64.
486 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
487 on call and jmp.
488 * i386-init.h: Regenerated.
489 * i386-tbl.h: Likewise.
490
e89c5eaa
L		 4912016-05-27 H.J. Lu <hongjiu.lu@intel.com>
492
493 PR gas/20154
494 * i386-gen.c (main): Fail if CpuMax is incorrect.
495 * i386-opc.h (CpuMax): Set to CpuIntel64.
496 * i386-tbl.h: Regenerated.
497
77d66e7b
NC		 4982016-05-27 Nick Clifton <nickc@redhat.com>
499
500 PR target/20150
501 * msp430-dis.c (msp430dis_read_two_bytes): New function.
502 (msp430dis_opcode_unsigned): New function.
503 (msp430dis_opcode_signed): New function.
504 (msp430_singleoperand): Use the new opcode reading functions.
505 Only disassenmble bytes if they were successfully read.
506 (msp430_doubleoperand): Likewise.
507 (msp430_branchinstr): Likewise.
508 (msp430x_callx_instr): Likewise.
509 (print_insn_msp430): Check that it is safe to read bytes before
510 attempting disassembly. Use the new opcode reading functions.
511
19dfcc89
PB		 5122016-05-26 Peter Bergner <bergner@vnet.ibm.com>
513
514 * ppc-opc.c (CY): New define. Document it.
515 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
516
f3ad7637
L		 5172016-05-25 H.J. Lu <hongjiu.lu@intel.com>
518
519 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
520 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
521 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
522 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
523 CPU_ANY_AVX_FLAGS.
524 * i386-init.h: Regenerated.
525
f1360d58
L		 5262016-05-25 H.J. Lu <hongjiu.lu@intel.com>
527
528 PR gas/20141
529 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
530 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
531 * i386-init.h: Regenerated.
532
293f5f65
L		 5332016-05-25 H.J. Lu <hongjiu.lu@intel.com>
534
535 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
536 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
537 * i386-init.h: Regenerated.
538
d9eca1df
CZ		 5392016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
540
541 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
542 information.
543 (print_insn_arc): Set insn_type information.
544 * arc-opc.c (C_CC): Add F_CLASS_COND.
545 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
546 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
547 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
548 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
549 (brne, brne_s, jeq_s, jne_s): Likewise.
550
87789e08
CZ		 5512016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
552
553 * arc-tbl.h (neg): New instruction variant.
554
c810e0b8
CZ		 5552016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
556
557 * arc-dis.c (find_format, find_format, get_auxreg)
558 (print_insn_arc): Changed.
559 * arc-ext.h (INSERT_XOP): Likewise.
560
3d207518
TS		 5612016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
562
563 * tic54x-dis.c (sprint_mmr): Adjust.
564 * tic54x-opc.c: Likewise.
565
514e58b7
AM		 5662016-05-19 Alan Modra <amodra@gmail.com>
567
568 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
569
e43de63c
AM		 5702016-05-19 Alan Modra <amodra@gmail.com>
571
572 * ppc-opc.c: Formatting.
573 (NSISIGNOPT): Define.
574 (powerpc_opcodes <subis>): Use NSISIGNOPT.
575
1401d2fe
MR		 5762016-05-18 Maciej W. Rozycki <macro@imgtec.com>
577
578 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
579 replacing references to `micromips_ase' throughout.
580 (_print_insn_mips): Don't use file-level microMIPS annotation to
581 determine the disassembly mode with the symbol table.
582
1178da44
PB		 5832016-05-13 Peter Bergner <bergner@vnet.ibm.com>
584
585 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
586
8f4f9071
MF		 5872016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
588
589 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
590 mips64r6.
591 * mips-opc.c (D34): New macro.
592 (mips_builtin_opcodes): Define bposge32c for DSPr3.
593
8bc52696
AF		 5942016-05-10 Alexander Fomin <alexander.fomin@intel.com>
595
596 * i386-dis.c (prefix_table): Add RDPID instruction.
597 * i386-gen.c (cpu_flag_init): Add RDPID flag.
598 (cpu_flags): Add RDPID bitfield.
599 * i386-opc.h (enum): Add RDPID element.
600 (i386_cpu_flags): Add RDPID field.
601 * i386-opc.tbl: Add RDPID instruction.
602 * i386-init.h: Regenerate.
603 * i386-tbl.h: Regenerate.
604
39d911fc
TP		 6052016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
606
607 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
608 branch type of a symbol.
609 (print_insn): Likewise.
610
16a1fa25
TP		 6112016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
612
613 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
614 Mainline Security Extensions instructions.
615 (thumb_opcodes): Add entries for narrow ARMv8-M Security
616 Extensions instructions.
617 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
618 instructions.
619 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
620 special registers.
621
d751b79e
JM		 6222016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
623
624 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
625
945e0f82
CZ		 6262016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
627
628 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
629 (arcExtMap_genOpcode): Likewise.
630 * arc-opc.c (arg_32bit_rc): Define new variable.
631 (arg_32bit_u6): Likewise.
632 (arg_32bit_limm): Likewise.
633
20f55f38
SN		 6342016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
635
636 * aarch64-gen.c (VERIFIER): Define.
637 * aarch64-opc.c (VERIFIER): Define.
638 (verify_ldpsw): Use static linkage.
639 * aarch64-opc.h (verify_ldpsw): Remove.
640 * aarch64-tbl.h: Use VERIFIER for verifiers.
641
4bd13cde
NC		 6422016-04-28 Nick Clifton <nickc@redhat.com>
643
644 PR target/19722
645 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
646 * aarch64-opc.c (verify_ldpsw): New function.
647 * aarch64-opc.h (verify_ldpsw): New prototype.
648 * aarch64-tbl.h: Add initialiser for verifier field.
649 (LDPSW): Set verifier to verify_ldpsw.
650
c0f92bf9
L		 6512016-04-23 H.J. Lu <hongjiu.lu@intel.com>
652
653 PR binutils/19983
654 PR binutils/19984
655 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
656 smaller than address size.
657
e6c7cdec
TS		 6582016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
659
660 * alpha-dis.c: Regenerate.
661 * crx-dis.c: Likewise.
662 * disassemble.c: Likewise.
663 * epiphany-opc.c: Likewise.
664 * fr30-opc.c: Likewise.
665 * frv-opc.c: Likewise.
666 * ip2k-opc.c: Likewise.
667 * iq2000-opc.c: Likewise.
668 * lm32-opc.c: Likewise.
669 * lm32-opinst.c: Likewise.
670 * m32c-opc.c: Likewise.
671 * m32r-opc.c: Likewise.
672 * m32r-opinst.c: Likewise.
673 * mep-opc.c: Likewise.
674 * mt-opc.c: Likewise.
675 * or1k-opc.c: Likewise.
676 * or1k-opinst.c: Likewise.
677 * tic80-opc.c: Likewise.
678 * xc16x-opc.c: Likewise.
679 * xstormy16-opc.c: Likewise.
680
537aefaf
AB		 6812016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
682
683 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
684 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
685 calcsd, and calcxd instructions.
686 * arc-opc.c (insert_nps_bitop_size): Delete.
687 (extract_nps_bitop_size): Delete.
688 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
689 (extract_nps_qcmp_m3): Define.
690 (extract_nps_qcmp_m2): Define.
691 (extract_nps_qcmp_m1): Define.
692 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
693 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
694 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
695 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
696 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
697 NPS_QCMP_M3.
698
c8f785f2
AB		 6992016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
700
701 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
702
6fd8e7c2
L		 7032016-04-15 H.J. Lu <hongjiu.lu@intel.com>
704
705 * Makefile.in: Regenerated with automake 1.11.6.
706 * aclocal.m4: Likewise.
707
4b0c052e
AB		 7082016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
709
710 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
711 instructions.
712 * arc-opc.c (insert_nps_cmem_uimm16): New function.
713 (extract_nps_cmem_uimm16): New function.
714 (arc_operands): Add NPS_XLDST_UIMM16 operand.
715
cb040366
AB		 7162016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
717
718 * arc-dis.c (arc_insn_length): New function.
719 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
720 (find_format): Change insnLen parameter to unsigned.
721
accc0180
NC		 7222016-04-13 Nick Clifton <nickc@redhat.com>
723
724 PR target/19937
725 * v850-opc.c (v850_opcodes): Correct masks for long versions of
726 the LD.B and LD.BU instructions.
727
f36e33da
CZ		 7282016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
729
730 * arc-dis.c (find_format): Check for extension flags.
731 (print_flags): New function.
732 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
733 .extAuxRegister.
734 * arc-ext.c (arcExtMap_coreRegName): Use
735 LAST_EXTENSION_CORE_REGISTER.
736 (arcExtMap_coreReadWrite): Likewise.
737 (dump_ARC_extmap): Update printing.
738 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
739 (arc_aux_regs): Add cpu field.
740 * arc-regs.h: Add cpu field, lower case name aux registers.
741
1c2e355e
CZ		 7422016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
743
744 * arc-tbl.h: Add rtsc, sleep with no arguments.
745
b99747ae
CZ		 7462016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
747
748 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
749 Initialize.
750 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
751 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
752 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
753 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
754 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
755 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
756 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
757 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
758 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
759 (arc_opcode arc_opcodes): Null terminate the array.
760 (arc_num_opcodes): Remove.
761 * arc-ext.h (INSERT_XOP): Define.
762 (extInstruction_t): Likewise.
763 (arcExtMap_instName): Delete.
764 (arcExtMap_insn): New function.
765 (arcExtMap_genOpcode): Likewise.
766 * arc-ext.c (ExtInstruction): Remove.
767 (create_map): Zero initialize instruction fields.
768 (arcExtMap_instName): Remove.
769 (arcExtMap_insn): New function.
770 (dump_ARC_extmap): More info while debuging.
771 (arcExtMap_genOpcode): New function.
772 * arc-dis.c (find_format): New function.
773 (print_insn_arc): Use find_format.
774 (arc_get_disassembler): Enable dump_ARC_extmap only when
775 debugging.
776
92708cec
MR		 7772016-04-11 Maciej W. Rozycki <macro@imgtec.com>
778
779 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
780 instruction bits out.
781
a42a4f84
AB		 7822016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
783
784 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
785 * arc-opc.c (arc_flag_operands): Add new flags.
786 (arc_flag_classes): Add new classes.
787
1328504b
AB		 7882016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
789
790 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
791
820f03ff
AB		 7922016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
793
794 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
795 encode1, rflt, crc16, and crc32 instructions.
796 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
797 (arc_flag_classes): Add C_NPS_R.
798 (insert_nps_bitop_size_2b): New function.
799 (extract_nps_bitop_size_2b): Likewise.
800 (insert_nps_bitop_uimm8): Likewise.
801 (extract_nps_bitop_uimm8): Likewise.
802 (arc_operands): Add new operand entries.
803
8ddf6b2a
CZ		 8042016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
805
b99747ae
CZ		 806 * arc-regs.h: Add a new subclass field. Add double assist
807 accumulator register values.
808 * arc-tbl.h: Use DPA subclass to mark the double assist
809 instructions. Use DPX/SPX subclas to mark the FPX instructions.
810 * arc-opc.c (RSP): Define instead of SP.
811 (arc_aux_regs): Add the subclass field.
8ddf6b2a 812
589a7d88
JW		 8132016-04-05 Jiong Wang <jiong.wang@arm.com>
814
815 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
816
0a191de9 8172016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 818
819 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
820 NPS_R_SRC1.
821
0a106562
AB		 8222016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
823
824 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
825 issues. No functional changes.
826
bd05ac5f
CZ		 8272016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
828
b99747ae
CZ		 829 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
830 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
831 (RTT): Remove duplicate.
832 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
833 (PCT_CONFIG*): Remove.
834 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 835
9885948f
CZ		 8362016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
837
b99747ae 838 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 839
f2dd8838
CZ		 8402016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
841
b99747ae
CZ		 842 * arc-tbl.h (invld07): Remove.
843 * arc-ext-tbl.h: New file.
844 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
845 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 846
0d2f91fe
JK		 8472016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
848
849 Fix -Wstack-usage warnings.
850 * aarch64-dis.c (print_operands): Substitute size.
851 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
852
a6b71f42
JM		 8532016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
854
855 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
856 to get a proper diagnostic when an invalid ASR register is used.
857
9780e045
NC		 8582016-03-22 Nick Clifton <nickc@redhat.com>
859
860 * configure: Regenerate.
861
e23e8ebe
AB		 8622016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
863
864 * arc-nps400-tbl.h: New file.
865 * arc-opc.c: Add top level comment.
866 (insert_nps_3bit_dst): New function.
867 (extract_nps_3bit_dst): New function.
868 (insert_nps_3bit_src2): New function.
869 (extract_nps_3bit_src2): New function.
870 (insert_nps_bitop_size): New function.
871 (extract_nps_bitop_size): New function.
872 (arc_flag_operands): Add nps400 entries.
873 (arc_flag_classes): Add nps400 entries.
874 (arc_operands): Add nps400 entries.
875 (arc_opcodes): Add nps400 include.
876
1ae8ab47
AB		 8772016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
878
879 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
880 the new class enum values.
881
8699fc3e
AB		 8822016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
883
884 * arc-dis.c (print_insn_arc): Handle nps400.
885
24740d83
AB		 8862016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
887
888 * arc-opc.c (BASE): Delete.
889
8678914f
NC		 8902016-03-18 Nick Clifton <nickc@redhat.com>
891
892 PR target/19721
893 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
894 of MOV insn that aliases an ORR insn.
895
cc933301
JW		 8962016-03-16 Jiong Wang <jiong.wang@arm.com>
897
898 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
899
f86f5863
TS		 9002016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
901
902 * mcore-opc.h: Add const qualifiers.
903 * microblaze-opc.h (struct op_code_struct): Likewise.
904 * sh-opc.h: Likewise.
905 * tic4x-dis.c (tic4x_print_indirect): Likewise.
906 (tic4x_print_op): Likewise.
907
62de1c63
AM		 9082016-03-02 Alan Modra <amodra@gmail.com>
909
d11698cd 910 * or1k-desc.h: Regenerate.
62de1c63 911 * fr30-ibld.c: Regenerate.
c697cf0b 912 * rl78-decode.c: Regenerate.
62de1c63 913
020efce5
NC		 9142016-03-01 Nick Clifton <nickc@redhat.com>
915
916 PR target/19747
917 * rl78-dis.c (print_insn_rl78_common): Fix typo.
918
b0c11777
RL		 9192016-02-24 Renlin Li <renlin.li@arm.com>
920
921 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
922 (print_insn_coprocessor): Support fp16 instructions.
923
3e309328
RL		 9242016-02-24 Renlin Li <renlin.li@arm.com>
925
926 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
927 vminnm, vrint(mpna).
928
8afc7bea
RL		 9292016-02-24 Renlin Li <renlin.li@arm.com>
930
931 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
932 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
933
4fd7268a
L		 9342016-02-15 H.J. Lu <hongjiu.lu@intel.com>
935
936 * i386-dis.c (print_insn): Parenthesize expression to prevent
937 truncated addresses.
938 (OP_J): Likewise.
939
4670103e
CZ		 9402016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
941 Janek van Oirschot <jvanoirs@synopsys.com>
942
b99747ae
CZ		 943 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
944 variable.
4670103e 945
c1d9289f
NC		 9462016-02-04 Nick Clifton <nickc@redhat.com>
947
948 PR target/19561
949 * msp430-dis.c (print_insn_msp430): Add a special case for
950 decoding an RRC instruction with the ZC bit set in the extension
951 word.
952
a143b004
AB		 9532016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
954
955 * cgen-ibld.in (insert_normal): Rework calculation of shift.
956 * epiphany-ibld.c: Regenerate.
957 * fr30-ibld.c: Regenerate.
958 * frv-ibld.c: Regenerate.
959 * ip2k-ibld.c: Regenerate.
960 * iq2000-ibld.c: Regenerate.
961 * lm32-ibld.c: Regenerate.
962 * m32c-ibld.c: Regenerate.
963 * m32r-ibld.c: Regenerate.
964 * mep-ibld.c: Regenerate.
965 * mt-ibld.c: Regenerate.
966 * or1k-ibld.c: Regenerate.
967 * xc16x-ibld.c: Regenerate.
968 * xstormy16-ibld.c: Regenerate.
969
b89807c6
AB		 9702016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
971
972 * epiphany-dis.c: Regenerated from latest cpu files.
973
d8c823c8
MM		 9742016-02-01 Michael McConville <mmcco@mykolab.com>
975
976 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
977 test bit.
978
5bc5ae88
RL		 9792016-01-25 Renlin Li <renlin.li@arm.com>
980
981 * arm-dis.c (mapping_symbol_for_insn): New function.
982 (find_ifthen_state): Call mapping_symbol_for_insn().
983
0bff6e2d
MW		 9842016-01-20 Matthew Wahab <matthew.wahab@arm.com>
985
986 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
987 of MSR UAO immediate operand.
988
100b4f2e
MR		 9892016-01-18 Maciej W. Rozycki <macro@imgtec.com>
990
991 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
992 instruction support.
993
5c14705f
AM		 9942016-01-17 Alan Modra <amodra@gmail.com>
995
996 * configure: Regenerate.
997
4d82fe66
NC		 9982016-01-14 Nick Clifton <nickc@redhat.com>
999
1000 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1001 instructions that can support stack pointer operations.
1002 * rl78-decode.c: Regenerate.
1003 * rl78-dis.c: Fix display of stack pointer in MOVW based
1004 instructions.
1005
651657fa
MW		 10062016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1007
1008 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1009 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1010 erxtatus_el1 and erxaddr_el1.
1011
105bde57
MW		 10122016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1013
1014 * arm-dis.c (arm_opcodes): Add "esb".
1015 (thumb_opcodes): Likewise.
1016
afa8d405
PB		 10172016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1018
1019 * ppc-opc.c <xscmpnedp>: Delete.
1020 <xvcmpnedp>: Likewise.
1021 <xvcmpnedp.>: Likewise.
1022 <xvcmpnesp>: Likewise.
1023 <xvcmpnesp.>: Likewise.
1024
83c3256e
AS		 10252016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1026
1027 PR gas/13050
1028 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1029 addition to ISA_A.
1030
6f2750fe
AM		 10312016-01-01 Alan Modra <amodra@gmail.com>
1032
1033 Update year range in copyright notice of all files.
1034
3499769a
AM		 1035For older changes see ChangeLog-2015
1036\f
1037Copyright (C) 2016 Free Software Foundation, Inc.
1038
1039Copying and distribution of this file, with or without modification,
1040are permitted in any medium without royalty provided the copyright
1041notice and this notice are preserved.
1042
1043Local Variables:
1044mode: change-log
1045left-margin: 8
1046fill-column: 74
1047version-control: never
1048End:
GDB Binutils - Deliverables
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