[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2019-05-01  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
	* aarch64-opc.c (operand_general_constraint_met_p): Add case for
	AARCH64_OPND_TME_UIMM16.
	(aarch64_print_operand): Likewise.
	* aarch64-tbl.h (QL_IMM_NIL): New.
	(TME): New.
	(_TME_INSN): New.
	(struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.

2019-04-29  John Darrington  <john@darrington.wattle.id.au>

        * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.

2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
	    Faraz Shahbazker  <fshahbazker@wavecomp.com>

	* mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.

2019-04-24  John Darrington  <john@darrington.wattle.id.au>

        * s12z-opc.h: Add extern "C" bracketing to help
	users who wish to use this interface in c++ code.

2019-04-24  John Darrington  <john@darrington.wattle.id.au>

	* s12z-opc.c (bm_decode): Handle bit map operations with the
	"reserved0" mode.

2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* arm-dis.c (coprocessor_opcodes): Document new %J and %K format
	specifier.  Add entries for VLDR and VSTR of system registers.
	(print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
	coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
	of %J and %K format specifier.

2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* arm-dis.c (coprocessor_opcodes): Document new %C format control code.
	Add new entries for VSCCLRM instruction.
	(print_insn_coprocessor): Handle new %C format control code.

2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* arm-dis.c (enum isa): New enum.
	(struct sopcode32): New structure.
	(coprocessor_opcodes): change type of entries to struct sopcode32 and
	set isa field of all current entries to ANY.
	(print_insn_coprocessor): Change type of insn to struct sopcode32.
	Only match an entry if its isa field allows the current mode.

2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
	CLRM.
	(print_insn_thumb32): Add logic to print %n CLRM register list.

2019-04-15  Sudakshina Das  <sudi.das@arm.com>

	* arm-dis.c (print_insn_thumb32): Updated to accept new %P
	and %Q patterns.

2019-04-15  Sudakshina Das  <sudi.das@arm.com>

	* arm-dis.c (thumb32_opcodes): New instruction bfcsel.
	(print_insn_thumb32): Edit the switch case for %Z.

2019-04-15  Sudakshina Das  <sudi.das@arm.com>

	* arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.

2019-04-15  Sudakshina Das  <sudi.das@arm.com>

	* arm-dis.c (thumb32_opcodes): New instruction bfl.

2019-04-15  Sudakshina Das  <sudi.das@arm.com>

	* arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.

2019-04-15  Sudakshina Das  <sudi.das@arm.com>

	* arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
	Arm register with r13 and r15 unpredictable.
	(thumb32_opcodes): New instructions for bfx and bflx.

2019-04-15  Sudakshina Das  <sudi.das@arm.com>

	* arm-dis.c (thumb32_opcodes): New instructions for bf.

2019-04-15  Sudakshina Das  <sudi.das@arm.com>

	* arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.

2019-04-15  Sudakshina Das  <sudi.das@arm.com>

	* arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.

2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.

2019-04-12  John Darrington <john@darrington.wattle.id.au>

	s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
	"optr". ("operator" is a reserved word in c++).

2019-04-11  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-opc.c (aarch64_print_operand): Add case for
	AARCH64_OPND_Rt_SP.
	(verify_constraints): Likewise.
	* aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
	(struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
	to accept Rt|SP as first operand.
	(AARCH64_OPERANDS): Add new Rt_SP.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.

2019-04-11  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.
	* aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.

2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>

	* mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.

2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Consolidate AVX512 BF16 entries.
	* i386-init.h: Regenerated.

2019-04-07  Alan Modra  <amodra@gmail.com>

	* ppc-dis.c (print_insn_powerpc): Use a tiny state machine
	op_separator to control printing of spaces, comma and parens
	rather than need_comma, need_paren and spaces vars.

2019-04-07  Alan Modra  <amodra@gmail.com>

	PR 24421
	* arm-dis.c (print_insn_coprocessor): Correct bracket placement.
	(print_insn_neon, print_insn_arm): Likewise.

2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>

	* i386-dis-evex.h (evex_table): Updated to support BF16
	instructions.
	* i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
	and EVEX_W_0F3872_P_3.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
	(cpu_flags): Add bitfield for CpuAVX512_BF16.
	* i386-opc.h (enum): Add CpuAVX512_BF16.
	(i386_cpu_flags): Add bitfield for cpuavx512_bf16.
	* i386-opc.tbl: Add AVX512 BF16 instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2019-04-05  Alan Modra  <amodra@gmail.com>

	* ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
	(powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
	to favour printing of "-" branch hint when using the "y" bit.
	Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.

2019-04-05  Alan Modra  <amodra@gmail.com>

	* ppc-dis.c (print_insn_powerpc): Delay printing spaces after
	opcode until first operand is output.

2019-04-04  Peter Bergner  <bergner@linux.ibm.com>

	PR gas/24349
	* ppc-opc.c (valid_bo_pre_v2): Add comments.
	(valid_bo_post_v2): Add support for 'at' branch hints.
	(insert_bo): Only error on branch on ctr.
	(get_bo_hint_mask): New function.
	(insert_boe): Add new 'branch_taken' formal argument.  Add support
	for inserting 'at' branch hints.
	(extract_boe): Add new 'branch_taken' formal argument.  Add support
	for extracting 'at' branch hints.
	(insert_bom, extract_bom, insert_bop, extract_bop): New functions.
	(BOE): Delete operand.
	(BOM, BOP): New operands.
	(RM): Update value.
	(XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
	(powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
	bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
	(powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
	bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
	<bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
	bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
	bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
	bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
	bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
	bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
	bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
	bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
	beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
	bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
	buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
	bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
	bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
	bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
	bttarl+>: New extended mnemonics.

2019-03-28  Alan Modra  <amodra@gmail.com>

	PR 24390
	* ppc-opc.c (BTF): Define.
	(powerpc_opcodes): Use for mtfsb*.
	* ppc-dis.c (print_insn_powerpc): Print fields with both
	PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.

2019-03-25  Tamar Christina  <tamar.christina@arm.com>

	* arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
	(mapping_symbol_for_insn): Implement new algorithm.
	(print_insn): Remove duplicate code.

2019-03-25  Tamar Christina  <tamar.christina@arm.com>

	* aarch64-dis.c (print_insn_aarch64):
	Implement override.

2019-03-25  Tamar Christina  <tamar.christina@arm.com>

	* aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
	order.

2019-03-25  Tamar Christina  <tamar.christina@arm.com>

	* aarch64-dis.c (last_stop_offset): New.
	(print_insn_aarch64): Use stop_offset.

2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/24359
	* i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
	CPU_ANY_AVX2_FLAGS.
	* i386-init.h: Regenerated.

2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/24348
	* i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
	vmovdqu16, vmovdqu32 and vmovdqu64.
	* i386-tbl.h: Regenerated.

2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>

	* s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
	from vstrszb, vstrszh, and vstrszf.

2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>

	* s390-opc.txt: Add instruction descriptions.

2019-02-08  Jim Wilson  <jimw@sifive.com>

	* riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
	<bne>: Likewise.

2019-02-07  Tamar Christina  <tamar.christina@arm.com>

	* arm-dis.c (arm_opcodes): Redefine hlt to armv1.

2019-02-07  Tamar Christina  <tamar.christina@arm.com>

	PR binutils/23212
	* aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
	* aarch64-opc.c (verify_elem_sd): New.
	(fields): Add FLD_sz entr.
	* aarch64-tbl.h (_SIMD_INSN): New.
	(aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
	fmulx scalar and vector by element isns.

2019-02-07  Nick Clifton  <nickc@redhat.com>

	* po/sv.po: Updated Swedish translation.

2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>

	* s390-mkopc.c (main): Accept arch13 as cpu string.
	* s390-opc.c: Add new instruction formats and instruction opcode
	masks.
	* s390-opc.txt: Add new arch13 instructions.

2019-01-25  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-tbl.h (QL_LDST_AT): Update macro.
	(aarch64_opcode): Change encoding for stg, stzg
	st2g and st2zg.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.

2019-01-25  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.
	* aarch64-tbl.h (aarch64_opcode): Add new stzgm.

2019-01-25  Sudakshina Das  <sudi.das@arm.com>
	    Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	* aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
	* aarch64-asm.h (ins_addr_simple_2): Likeiwse.
	* aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
	* aarch64-dis.h (ext_addr_simple_2): Likewise.
	* aarch64-opc.c (operand_general_constraint_met_p): Remove
	case for ldstgv_indexed.
	(aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
	* aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
	(AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.

2019-01-23  Nick Clifton  <nickc@redhat.com>

	* po/pt_BR.po: Updated Brazilian Portuguese translation.

2019-01-21  Nick Clifton  <nickc@redhat.com>

	* po/de.po: Updated German translation.
	* po/uk.po: Updated Ukranian translation.

2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
	* mips-dis.c (mips_arch_choices): Fix typo in
	gs464, gs464e and gs264e descriptors.

2019-01-19  Nick Clifton  <nickc@redhat.com>

	* configure: Regenerate.
	* po/opcodes.pot: Regenerate.

2018-06-24  Nick Clifton  <nickc@redhat.com>

	2.32 branch created.

2019-01-09  John Darrington <john@darrington.wattle.id.au>

	* s12z-dis.c (print_insn_s12z):  Do not dereference an operand
	if it is null.
	-dis.c (opr_emit_disassembly): Do not omit an index if it is
	zero.

2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>

	* configure: Regenerate.

2019-01-07  Alan Modra  <amodra@gmail.com>

	* configure: Regenerate.
	* po/POTFILES.in: Regenerate.

2019-01-03  John Darrington <john@darrington.wattle.id.au>

	* s12z-opc.c: New file.
	* s12z-opc.h: New file.
	* s12z-dis.c: Removed all code not directly related to display
	of instructions.  Used the interface provided by the new files
	instead.
	* Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
	* Makefile.in: Regenerate.
	* configure.ac (bfd_s12z_arch): Correct the dependencies.
	* configure: Regenerate.

2019-01-01  Alan Modra  <amodra@gmail.com>

	Update year range in copyright notice of all files.

For older changes see ChangeLog-2018
\f
Copyright (C) 2019 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
b83b4b13 SD	1	2019-05-01 Sudakshina Das <sudi.das@arm.com>
	2
	3	* aarch64-asm-2.c: Regenerated.
	4	* aarch64-dis-2.c: Regenerated.
	5	* aarch64-opc-2.c: Regenerated.
	6	* aarch64-opc.c (operand_general_constraint_met_p): Add case for
	7	AARCH64_OPND_TME_UIMM16.
	8	(aarch64_print_operand): Likewise.
	9	* aarch64-tbl.h (QL_IMM_NIL): New.
	10	(TME): New.
	11	(_TME_INSN): New.
	12	(struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
	13
4a90ce95 JD	14	2019-04-29 John Darrington <john@darrington.wattle.id.au>
	15
	16	* s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
	17
a45328b9 AB	18	2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
	19	Faraz Shahbazker <fshahbazker@wavecomp.com>
	20
	21	* mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
	22
d10be0cb JD	23	2019-04-24 John Darrington <john@darrington.wattle.id.au>
	24
	25	* s12z-opc.h: Add extern "C" bracketing to help
	26	users who wish to use this interface in c++ code.
	27
a679f24e JD	28	2019-04-24 John Darrington <john@darrington.wattle.id.au>
	29
	30	* s12z-opc.c (bm_decode): Handle bit map operations with the
	31	"reserved0" mode.
	32
32c36c3c AV	33	2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
	34
	35	* arm-dis.c (coprocessor_opcodes): Document new %J and %K format
	36	specifier. Add entries for VLDR and VSTR of system registers.
	37	(print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
	38	coprocessor instructions on Armv8.1-M Mainline targets. Add handling
	39	of %J and %K format specifier.
	40
efd6b359 AV	41	2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
	42
	43	* arm-dis.c (coprocessor_opcodes): Document new %C format control code.
	44	Add new entries for VSCCLRM instruction.
	45	(print_insn_coprocessor): Handle new %C format control code.
	46
6b0dd094 AV	47	2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
	48
	49	* arm-dis.c (enum isa): New enum.
	50	(struct sopcode32): New structure.
	51	(coprocessor_opcodes): change type of entries to struct sopcode32 and
	52	set isa field of all current entries to ANY.
	53	(print_insn_coprocessor): Change type of insn to struct sopcode32.
	54	Only match an entry if its isa field allows the current mode.
	55
4b5a202f AV	56	2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
	57
	58	* arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
	59	CLRM.
	60	(print_insn_thumb32): Add logic to print %n CLRM register list.
	61
60f993ce AV	62	2019-04-15 Sudakshina Das <sudi.das@arm.com>
	63
	64	* arm-dis.c (print_insn_thumb32): Updated to accept new %P
	65	and %Q patterns.
	66
f6b2b12d AV	67	2019-04-15 Sudakshina Das <sudi.das@arm.com>
	68
	69	* arm-dis.c (thumb32_opcodes): New instruction bfcsel.
	70	(print_insn_thumb32): Edit the switch case for %Z.
	71
1889da70 AV	72	2019-04-15 Sudakshina Das <sudi.das@arm.com>
	73
	74	* arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
	75
65d1bc05 AV	76	2019-04-15 Sudakshina Das <sudi.das@arm.com>
	77
	78	* arm-dis.c (thumb32_opcodes): New instruction bfl.
	79
1caf72a5 AV	80	2019-04-15 Sudakshina Das <sudi.das@arm.com>
	81
	82	* arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
	83
f1c7f421 AV	84	2019-04-15 Sudakshina Das <sudi.das@arm.com>
	85
	86	* arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
	87	Arm register with r13 and r15 unpredictable.
	88	(thumb32_opcodes): New instructions for bfx and bflx.
	89
4389b29a AV	90	2019-04-15 Sudakshina Das <sudi.das@arm.com>
	91
	92	* arm-dis.c (thumb32_opcodes): New instructions for bf.
	93
e5d6e09e AV	94	2019-04-15 Sudakshina Das <sudi.das@arm.com>
	95
	96	* arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
	97
e12437dc AV	98	2019-04-15 Sudakshina Das <sudi.das@arm.com>
	99
	100	* arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
	101
031254f2 AV	102	2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
	103
	104	* arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
	105
e5a557ac JD	106	2019-04-12 John Darrington <john@darrington.wattle.id.au>
	107
	108	s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
	109	"optr". ("operator" is a reserved word in c++).
	110
bd7ceb8d SD	111	2019-04-11 Sudakshina Das <sudi.das@arm.com>
	112
	113	* aarch64-opc.c (aarch64_print_operand): Add case for
	114	AARCH64_OPND_Rt_SP.
	115	(verify_constraints): Likewise.
	116	* aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
	117	(struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
	118	to accept Rt\|SP as first operand.
	119	(AARCH64_OPERANDS): Add new Rt_SP.
	120	* aarch64-asm-2.c: Regenerated.
	121	* aarch64-dis-2.c: Regenerated.
	122	* aarch64-opc-2.c: Regenerated.
	123
e54010f1 SD	124	2019-04-11 Sudakshina Das <sudi.das@arm.com>
	125
	126	* aarch64-asm-2.c: Regenerated.
	127	* aarch64-dis-2.c: Likewise.
	128	* aarch64-opc-2.c: Likewise.
	129	* aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
	130
7e96e219 RS	131	2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
	132
	133	* mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
	134
6f2791d5 L	135	2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
	136
	137	* i386-opc.tbl: Consolidate AVX512 BF16 entries.
	138	* i386-init.h: Regenerated.
	139
e392bad3 AM	140	2019-04-07 Alan Modra <amodra@gmail.com>
	141
	142	* ppc-dis.c (print_insn_powerpc): Use a tiny state machine
	143	op_separator to control printing of spaces, comma and parens
	144	rather than need_comma, need_paren and spaces vars.
	145
dffaa15c AM	146	2019-04-07 Alan Modra <amodra@gmail.com>
	147
	148	PR 24421
	149	* arm-dis.c (print_insn_coprocessor): Correct bracket placement.
	150	(print_insn_neon, print_insn_arm): Likewise.
	151
d6aab7a1 XG	152	2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
	153
	154	* i386-dis-evex.h (evex_table): Updated to support BF16
	155	instructions.
	156	* i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
	157	and EVEX_W_0F3872_P_3.
	158	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
	159	(cpu_flags): Add bitfield for CpuAVX512_BF16.
	160	* i386-opc.h (enum): Add CpuAVX512_BF16.
	161	(i386_cpu_flags): Add bitfield for cpuavx512_bf16.
	162	* i386-opc.tbl: Add AVX512 BF16 instructions.
	163	* i386-init.h: Regenerated.
	164	* i386-tbl.h: Likewise.
	165
66e85460 AM	166	2019-04-05 Alan Modra <amodra@gmail.com>
	167
	168	* ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
	169	(powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
	170	to favour printing of "-" branch hint when using the "y" bit.
	171	Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
	172
c2b1c275 AM	173	2019-04-05 Alan Modra <amodra@gmail.com>
	174
	175	* ppc-dis.c (print_insn_powerpc): Delay printing spaces after
	176	opcode until first operand is output.
	177
aae9718e PB	178	2019-04-04 Peter Bergner <bergner@linux.ibm.com>
	179
	180	PR gas/24349
	181	* ppc-opc.c (valid_bo_pre_v2): Add comments.
	182	(valid_bo_post_v2): Add support for 'at' branch hints.
	183	(insert_bo): Only error on branch on ctr.
	184	(get_bo_hint_mask): New function.
	185	(insert_boe): Add new 'branch_taken' formal argument. Add support
	186	for inserting 'at' branch hints.
	187	(extract_boe): Add new 'branch_taken' formal argument. Add support
	188	for extracting 'at' branch hints.
	189	(insert_bom, extract_bom, insert_bop, extract_bop): New functions.
	190	(BOE): Delete operand.
	191	(BOM, BOP): New operands.
	192	(RM): Update value.
	193	(XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
	194	(powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
	195	bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
	196	(powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
	197	bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
	198	<bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
	199	bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
	200	bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
	201	bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
	202	bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
	203	bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
	204	bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
	205	bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
	206	beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
	207	bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
	208	buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
	209	bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
	210	bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
	211	bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
	212	bttarl+>: New extended mnemonics.
	213
96a86c01 AM	214	2019-03-28 Alan Modra <amodra@gmail.com>
	215
	216	PR 24390
	217	* ppc-opc.c (BTF): Define.
	218	(powerpc_opcodes): Use for mtfsb*.
	219	* ppc-dis.c (print_insn_powerpc): Print fields with both
	220	PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
	221
796d6298 TC	222	2019-03-25 Tamar Christina <tamar.christina@arm.com>
	223
	224	* arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
	225	(mapping_symbol_for_insn): Implement new algorithm.
	226	(print_insn): Remove duplicate code.
	227
60df3720 TC	228	2019-03-25 Tamar Christina <tamar.christina@arm.com>
	229
	230	* aarch64-dis.c (print_insn_aarch64):
	231	Implement override.
	232
51457761 TC	233	2019-03-25 Tamar Christina <tamar.christina@arm.com>
	234
	235	* aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
	236	order.
	237
53b2f36b TC	238	2019-03-25 Tamar Christina <tamar.christina@arm.com>
	239
	240	* aarch64-dis.c (last_stop_offset): New.
	241	(print_insn_aarch64): Use stop_offset.
	242
89199bb5 L	243	2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
	244
	245	PR gas/24359
	246	* i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
	247	CPU_ANY_AVX2_FLAGS.
	248	* i386-init.h: Regenerated.
	249
97ed31ae L	250	2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
	251
	252	PR gas/24348
	253	* i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
	254	vmovdqu16, vmovdqu32 and vmovdqu64.
	255	* i386-tbl.h: Regenerated.
	256
0919bfe9 AK	257	2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
	258
	259	* s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
	260	from vstrszb, vstrszh, and vstrszf.
	261
	262	2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
	263
	264	* s390-opc.txt: Add instruction descriptions.
	265
21820ebe JW	266	2019-02-08 Jim Wilson <jimw@sifive.com>
	267
	268	* riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
	269	<bne>: Likewise.
	270
f7dd2fb2 TC	271	2019-02-07 Tamar Christina <tamar.christina@arm.com>
	272
	273	* arm-dis.c (arm_opcodes): Redefine hlt to armv1.
	274
6456d318 TC	275	2019-02-07 Tamar Christina <tamar.christina@arm.com>
	276
	277	PR binutils/23212
	278	* aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
	279	* aarch64-opc.c (verify_elem_sd): New.
	280	(fields): Add FLD_sz entr.
	281	* aarch64-tbl.h (_SIMD_INSN): New.
	282	(aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
	283	fmulx scalar and vector by element isns.
	284
4a83b610 NC	285	2019-02-07 Nick Clifton <nickc@redhat.com>
	286
	287	* po/sv.po: Updated Swedish translation.
	288
fc60b8c8 AK	289	2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
	290
	291	* s390-mkopc.c (main): Accept arch13 as cpu string.
	292	* s390-opc.c: Add new instruction formats and instruction opcode
	293	masks.
	294	* s390-opc.txt: Add new arch13 instructions.
	295
e10620d3 TC	296	2019-01-25 Sudakshina Das <sudi.das@arm.com>
	297
	298	* aarch64-tbl.h (QL_LDST_AT): Update macro.
	299	(aarch64_opcode): Change encoding for stg, stzg
	300	st2g and st2zg.
	301	* aarch64-asm-2.c: Regenerated.
	302	* aarch64-dis-2.c: Regenerated.
	303	* aarch64-opc-2.c: Regenerated.
	304
20a4ca55 SD	305	2019-01-25 Sudakshina Das <sudi.das@arm.com>
	306
	307	* aarch64-asm-2.c: Regenerated.
	308	* aarch64-dis-2.c: Likewise.
	309	* aarch64-opc-2.c: Likewise.
	310	* aarch64-tbl.h (aarch64_opcode): Add new stzgm.
	311
550fd7bf SD	312	2019-01-25 Sudakshina Das <sudi.das@arm.com>
	313	Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
	314
	315	* aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
	316	* aarch64-asm.h (ins_addr_simple_2): Likeiwse.
	317	* aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
	318	* aarch64-dis.h (ext_addr_simple_2): Likewise.
	319	* aarch64-opc.c (operand_general_constraint_met_p): Remove
	320	case for ldstgv_indexed.
	321	(aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
	322	* aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
	323	(AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
	324	* aarch64-asm-2.c: Regenerated.
	325	* aarch64-dis-2.c: Regenerated.
	326	* aarch64-opc-2.c: Regenerated.
	327
d9938630 NC	328	2019-01-23 Nick Clifton <nickc@redhat.com>
	329
	330	* po/pt_BR.po: Updated Brazilian Portuguese translation.
	331
375cd423 NC	332	2019-01-21 Nick Clifton <nickc@redhat.com>
	333
	334	* po/de.po: Updated German translation.
	335	* po/uk.po: Updated Ukranian translation.
	336
57299f48 CX	337	2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
	338	* mips-dis.c (mips_arch_choices): Fix typo in
	339	gs464, gs464e and gs264e descriptors.
	340
f48dfe41 NC	341	2019-01-19 Nick Clifton <nickc@redhat.com>
	342
	343	* configure: Regenerate.
	344	* po/opcodes.pot: Regenerate.
	345
f974f26c NC	346	2018-06-24 Nick Clifton <nickc@redhat.com>
	347
	348	2.32 branch created.
	349
39f286cd JD	350	2019-01-09 John Darrington <john@darrington.wattle.id.au>
39f286cd JD	351
448b8ca8 JD	352	* s12z-dis.c (print_insn_s12z): Do not dereference an operand
	353	if it is null.
	354	-dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd JD	355	zero.
39f286cd JD	356
3107326d AP	357	2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
	358
	359	* configure: Regenerate.
	360
7e9ca91e AM	361	2019-01-07 Alan Modra <amodra@gmail.com>
	362
	363	* configure: Regenerate.
	364	* po/POTFILES.in: Regenerate.
	365
ef1ad42b JD	366	2019-01-03 John Darrington <john@darrington.wattle.id.au>
	367
	368	* s12z-opc.c: New file.
	369	* s12z-opc.h: New file.
	370	* s12z-dis.c: Removed all code not directly related to display
	371	of instructions. Used the interface provided by the new files
	372	instead.
	373	* Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e	374	* Makefile.in: Regenerate.
ef1ad42b	375	* configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e	376	* configure: Regenerate.
ef1ad42b	377
82704155 AM	378	2019-01-01 Alan Modra <amodra@gmail.com>
	379
	380	Update year range in copyright notice of all files.
	381
d5c04e1b	382	For older changes see ChangeLog-2018
3499769a	383	\f
d5c04e1b	384	Copyright (C) 2019 Free Software Foundation, Inc.
3499769a AM	385
	386	Copying and distribution of this file, with or without modification,
	387	are permitted in any medium without royalty provided the copyright
	388	notice and this notice are preserved.
	389
	390	Local Variables:
	391	mode: change-log
	392	left-margin: 8
	393	fill-column: 74
	394	version-control: never
	395	End: