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[PATCH 44/57][Arm][OBJDUMP] Add support for MVE instructions: vcvt and vrint
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
bf0b396d
AV		 12019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2 Michael Collison <michael.collison@arm.com>
3
4 * arm-dis.c (enum mve_instructions): Add new instructions.
5 (enum mve_unpredictable): Add new reasons.
6 (enum mve_undefined): Likewise.
7 (is_mve_encoding_conflict): Handle new instructions.
8 (is_mve_undefined): Likewise.
9 (is_mve_unpredictable): Likewise.
10 (print_mve_undefined): Likewise.
11 (print_mve_unpredictable): Likewise.
12 (print_mve_rounding_mode): Likewise.
13 (print_mve_vcvt_size): Likewise.
14 (print_mve_size): Likewise.
15 (print_insn_mve): Likewise.
16
ef1576a1
AV		 172019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
18 Michael Collison <michael.collison@arm.com>
19
20 * arm-dis.c (enum mve_instructions): Add new instructions.
21 (enum mve_unpredictable): Add new reasons.
22 (enum mve_undefined): Likewise.
23 (is_mve_undefined): Handle new instructions.
24 (is_mve_unpredictable): Likewise.
25 (print_mve_undefined): Likewise.
26 (print_mve_unpredictable): Likewise.
27 (print_mve_size): Likewise.
28 (print_insn_mve): Likewise.
29
aef6d006
AV		 302019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
31 Michael Collison <michael.collison@arm.com>
32
33 * arm-dis.c (enum mve_instructions): Add new instructions.
34 (enum mve_undefined): Add new reasons.
35 (insns): Add new instructions.
36 (is_mve_encoding_conflict):
37 (print_mve_vld_str_addr): New print function.
38 (is_mve_undefined): Handle new instructions.
39 (is_mve_unpredictable): Likewise.
40 (print_mve_undefined): Likewise.
41 (print_mve_size): Likewise.
42 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
43 (print_insn_mve): Handle new operands.
44
04d54ace
AV		 452019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
46 Michael Collison <michael.collison@arm.com>
47
48 * arm-dis.c (enum mve_instructions): Add new instructions.
49 (enum mve_unpredictable): Add new reasons.
50 (is_mve_encoding_conflict): Handle new instructions.
51 (is_mve_unpredictable): Likewise.
52 (mve_opcodes): Add new instructions.
53 (print_mve_unpredictable): Handle new reasons.
54 (print_mve_register_blocks): New print function.
55 (print_mve_size): Handle new instructions.
56 (print_insn_mve): Likewise.
57
9743db03
AV		 582019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
59 Michael Collison <michael.collison@arm.com>
60
61 * arm-dis.c (enum mve_instructions): Add new instructions.
62 (enum mve_unpredictable): Add new reasons.
63 (enum mve_undefined): Likewise.
64 (is_mve_encoding_conflict): Handle new instructions.
65 (is_mve_undefined): Likewise.
66 (is_mve_unpredictable): Likewise.
67 (coprocessor_opcodes): Move NEON VDUP from here...
68 (neon_opcodes): ... to here.
69 (mve_opcodes): Add new instructions.
70 (print_mve_undefined): Handle new reasons.
71 (print_mve_unpredictable): Likewise.
72 (print_mve_size): Handle new instructions.
73 (print_insn_neon): Handle vdup.
74 (print_insn_mve): Handle new operands.
75
143275ea
AV		 762019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
77 Michael Collison <michael.collison@arm.com>
78
79 * arm-dis.c (enum mve_instructions): Add new instructions.
80 (enum mve_unpredictable): Add new values.
81 (mve_opcodes): Add new instructions.
82 (vec_condnames): New array with vector conditions.
83 (mve_predicatenames): New array with predicate suffixes.
84 (mve_vec_sizename): New array with vector sizes.
85 (enum vpt_pred_state): New enum with vector predication states.
86 (struct vpt_block): New struct type for vpt blocks.
87 (vpt_block_state): Global struct to keep track of state.
88 (mve_extract_pred_mask): New helper function.
89 (num_instructions_vpt_block): Likewise.
90 (mark_outside_vpt_block): Likewise.
91 (mark_inside_vpt_block): Likewise.
92 (invert_next_predicate_state): Likewise.
93 (update_next_predicate_state): Likewise.
94 (update_vpt_block_state): Likewise.
95 (is_vpt_instruction): Likewise.
96 (is_mve_encoding_conflict): Add entries for new instructions.
97 (is_mve_unpredictable): Likewise.
98 (print_mve_unpredictable): Handle new cases.
99 (print_instruction_predicate): Likewise.
100 (print_mve_size): New function.
101 (print_vec_condition): New function.
102 (print_insn_mve): Handle vpt blocks and new print operands.
103
f08d8ce3
AV		 1042019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
105
106 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
107 8, 14 and 15 for Armv8.1-M Mainline.
108
73cd51e5
AV		 1092019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
110 Michael Collison <michael.collison@arm.com>
111
112 * arm-dis.c (enum mve_instructions): New enum.
113 (enum mve_unpredictable): Likewise.
114 (enum mve_undefined): Likewise.
115 (struct mopcode32): New struct.
116 (is_mve_okay_in_it): New function.
117 (is_mve_architecture): Likewise.
118 (arm_decode_field): Likewise.
119 (arm_decode_field_multiple): Likewise.
120 (is_mve_encoding_conflict): Likewise.
121 (is_mve_undefined): Likewise.
122 (is_mve_unpredictable): Likewise.
123 (print_mve_undefined): Likewise.
124 (print_mve_unpredictable): Likewise.
125 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
126 (print_insn_mve): New function.
127 (print_insn_thumb32): Handle MVE architecture.
128 (select_arm_features): Force thumb for Armv8.1-m Mainline.
129
3076e594
NC		 1302019-05-10 Nick Clifton <nickc@redhat.com>
131
132 PR 24538
133 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
134 end of the table prematurely.
135
387e7624
FS		 1362019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
137
138 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
139 macros for R6.
140
0067be51
AM		 1412019-05-11 Alan Modra <amodra@gmail.com>
142
143 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
144 when -Mraw is in effect.
145
42e6288f
MM		 1462019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
147
148 * aarch64-dis-2.c: Regenerate.
149 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
150 (OP_SVE_BBB): New variant set.
151 (OP_SVE_DDDD): New variant set.
152 (OP_SVE_HHH): New variant set.
153 (OP_SVE_HHHU): New variant set.
154 (OP_SVE_SSS): New variant set.
155 (OP_SVE_SSSU): New variant set.
156 (OP_SVE_SHH): New variant set.
157 (OP_SVE_SBBU): New variant set.
158 (OP_SVE_DSS): New variant set.
159 (OP_SVE_DHHU): New variant set.
160 (OP_SVE_VMV_HSD_BHS): New variant set.
161 (OP_SVE_VVU_HSD_BHS): New variant set.
162 (OP_SVE_VVVU_SD_BH): New variant set.
163 (OP_SVE_VVVU_BHSD): New variant set.
164 (OP_SVE_VVV_QHD_DBS): New variant set.
165 (OP_SVE_VVV_HSD_BHS): New variant set.
166 (OP_SVE_VVV_HSD_BHS2): New variant set.
167 (OP_SVE_VVV_BHS_HSD): New variant set.
168 (OP_SVE_VV_BHS_HSD): New variant set.
169 (OP_SVE_VVV_SD): New variant set.
170 (OP_SVE_VVU_BHS_HSD): New variant set.
171 (OP_SVE_VZVV_SD): New variant set.
172 (OP_SVE_VZVV_BH): New variant set.
173 (OP_SVE_VZV_SD): New variant set.
174 (aarch64_opcode_table): Add sve2 instructions.
175
28ed815a
MM		 1762019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
177
178 * aarch64-asm-2.c: Regenerated.
179 * aarch64-dis-2.c: Regenerated.
180 * aarch64-opc-2.c: Regenerated.
181 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
182 for SVE_SHLIMM_UNPRED_22.
183 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
184 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
185 operand.
186
fd1dc4a0
MM		 1872019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
188
189 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
190 sve_size_tsz_bhs iclass encode.
191 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
192 sve_size_tsz_bhs iclass decode.
193
31e36ab3
MM		 1942019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
195
196 * aarch64-asm-2.c: Regenerated.
197 * aarch64-dis-2.c: Regenerated.
198 * aarch64-opc-2.c: Regenerated.
199 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
200 for SVE_Zm4_11_INDEX.
201 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
202 (fields): Handle SVE_i2h field.
203 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
204 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
205
1be5f94f
MM		 2062019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
207
208 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
209 sve_shift_tsz_bhsd iclass encode.
210 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
211 sve_shift_tsz_bhsd iclass decode.
212
3c17238b
MM		 2132019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
214
215 * aarch64-asm-2.c: Regenerated.
216 * aarch64-dis-2.c: Regenerated.
217 * aarch64-opc-2.c: Regenerated.
218 * aarch64-asm.c (aarch64_ins_sve_shrimm):
219 (aarch64_encode_variant_using_iclass): Handle
220 sve_shift_tsz_hsd iclass encode.
221 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
222 sve_shift_tsz_hsd iclass decode.
223 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
224 for SVE_SHRIMM_UNPRED_22.
225 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
226 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
227 operand.
228
cd50a87a
MM		 2292019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
230
231 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
232 sve_size_013 iclass encode.
233 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
234 sve_size_013 iclass decode.
235
3c705960
MM		 2362019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
237
238 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
239 sve_size_bh iclass encode.
240 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
241 sve_size_bh iclass decode.
242
0a57e14f
MM		 2432019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
244
245 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
246 sve_size_sd2 iclass encode.
247 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
248 sve_size_sd2 iclass decode.
249 * aarch64-opc.c (fields): Handle SVE_sz2 field.
250 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
251
c469c864
MM		 2522019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
253
254 * aarch64-asm-2.c: Regenerated.
255 * aarch64-dis-2.c: Regenerated.
256 * aarch64-opc-2.c: Regenerated.
257 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
258 for SVE_ADDR_ZX.
259 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
260 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
261
116adc27
MM		 2622019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
263
264 * aarch64-asm-2.c: Regenerated.
265 * aarch64-dis-2.c: Regenerated.
266 * aarch64-opc-2.c: Regenerated.
267 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
268 for SVE_Zm3_11_INDEX.
269 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
270 (fields): Handle SVE_i3l and SVE_i3h2 fields.
271 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
272 fields.
273 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
274
3bd82c86
MM		 2752019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
276
277 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
278 sve_size_hsd2 iclass encode.
279 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
280 sve_size_hsd2 iclass decode.
281 * aarch64-opc.c (fields): Handle SVE_size field.
282 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
283
adccc507
MM		 2842019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
285
286 * aarch64-asm-2.c: Regenerated.
287 * aarch64-dis-2.c: Regenerated.
288 * aarch64-opc-2.c: Regenerated.
289 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
290 for SVE_IMM_ROT3.
291 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
292 (fields): Handle SVE_rot3 field.
293 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
294 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
295
5cd99750
MM		 2962019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
297
298 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
299 instructions.
300
7ce2460a
MM		 3012019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
302
303 * aarch64-tbl.h
304 (aarch64_feature_sve2, aarch64_feature_sve2aes,
305 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
306 aarch64_feature_sve2bitperm): New feature sets.
307 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
308 for feature set addresses.
309 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
310 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
311
41cee089
FS		 3122019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
313 Faraz Shahbazker <fshahbazker@wavecomp.com>
314
315 * mips-dis.c (mips_calculate_combination_ases): Add ISA
316 argument and set ASE_EVA_R6 appropriately.
317 (set_default_mips_dis_options): Pass ISA to above.
318 (parse_mips_dis_option): Likewise.
319 * mips-opc.c (EVAR6): New macro.
320 (mips_builtin_opcodes): Add llwpe, scwpe.
321
b83b4b13
SD		 3222019-05-01 Sudakshina Das <sudi.das@arm.com>
323
324 * aarch64-asm-2.c: Regenerated.
325 * aarch64-dis-2.c: Regenerated.
326 * aarch64-opc-2.c: Regenerated.
327 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
328 AARCH64_OPND_TME_UIMM16.
329 (aarch64_print_operand): Likewise.
330 * aarch64-tbl.h (QL_IMM_NIL): New.
331 (TME): New.
332 (_TME_INSN): New.
333 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
334
4a90ce95
JD		 3352019-04-29 John Darrington <john@darrington.wattle.id.au>
336
337 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
338
a45328b9
AB		 3392019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
340 Faraz Shahbazker <fshahbazker@wavecomp.com>
341
342 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
343
d10be0cb
JD		 3442019-04-24 John Darrington <john@darrington.wattle.id.au>
345
346 * s12z-opc.h: Add extern "C" bracketing to help
347 users who wish to use this interface in c++ code.
348
a679f24e
JD		 3492019-04-24 John Darrington <john@darrington.wattle.id.au>
350
351 * s12z-opc.c (bm_decode): Handle bit map operations with the
352 "reserved0" mode.
353
32c36c3c
AV		 3542019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
355
356 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
357 specifier. Add entries for VLDR and VSTR of system registers.
358 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
359 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
360 of %J and %K format specifier.
361
efd6b359
AV		 3622019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
363
364 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
365 Add new entries for VSCCLRM instruction.
366 (print_insn_coprocessor): Handle new %C format control code.
367
6b0dd094
AV		 3682019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
369
370 * arm-dis.c (enum isa): New enum.
371 (struct sopcode32): New structure.
372 (coprocessor_opcodes): change type of entries to struct sopcode32 and
373 set isa field of all current entries to ANY.
374 (print_insn_coprocessor): Change type of insn to struct sopcode32.
375 Only match an entry if its isa field allows the current mode.
376
4b5a202f
AV		 3772019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
378
379 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
380 CLRM.
381 (print_insn_thumb32): Add logic to print %n CLRM register list.
382
60f993ce
AV		 3832019-04-15 Sudakshina Das <sudi.das@arm.com>
384
385 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
386 and %Q patterns.
387
f6b2b12d
AV		 3882019-04-15 Sudakshina Das <sudi.das@arm.com>
389
390 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
391 (print_insn_thumb32): Edit the switch case for %Z.
392
1889da70
AV		 3932019-04-15 Sudakshina Das <sudi.das@arm.com>
394
395 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
396
65d1bc05
AV		 3972019-04-15 Sudakshina Das <sudi.das@arm.com>
398
399 * arm-dis.c (thumb32_opcodes): New instruction bfl.
400
1caf72a5
AV		 4012019-04-15 Sudakshina Das <sudi.das@arm.com>
402
403 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
404
f1c7f421
AV		 4052019-04-15 Sudakshina Das <sudi.das@arm.com>
406
407 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
408 Arm register with r13 and r15 unpredictable.
409 (thumb32_opcodes): New instructions for bfx and bflx.
410
4389b29a
AV		 4112019-04-15 Sudakshina Das <sudi.das@arm.com>
412
413 * arm-dis.c (thumb32_opcodes): New instructions for bf.
414
e5d6e09e
AV		 4152019-04-15 Sudakshina Das <sudi.das@arm.com>
416
417 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
418
e12437dc
AV		 4192019-04-15 Sudakshina Das <sudi.das@arm.com>
420
421 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
422
031254f2
AV		 4232019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
424
425 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
426
e5a557ac
JD		 4272019-04-12 John Darrington <john@darrington.wattle.id.au>
428
429 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
430 "optr". ("operator" is a reserved word in c++).
431
bd7ceb8d
SD		 4322019-04-11 Sudakshina Das <sudi.das@arm.com>
433
434 * aarch64-opc.c (aarch64_print_operand): Add case for
435 AARCH64_OPND_Rt_SP.
436 (verify_constraints): Likewise.
437 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
438 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
439 to accept Rt|SP as first operand.
440 (AARCH64_OPERANDS): Add new Rt_SP.
441 * aarch64-asm-2.c: Regenerated.
442 * aarch64-dis-2.c: Regenerated.
443 * aarch64-opc-2.c: Regenerated.
444
e54010f1
SD		 4452019-04-11 Sudakshina Das <sudi.das@arm.com>
446
447 * aarch64-asm-2.c: Regenerated.
448 * aarch64-dis-2.c: Likewise.
449 * aarch64-opc-2.c: Likewise.
450 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
451
7e96e219
RS		 4522019-04-09 Robert Suchanek <robert.suchanek@mips.com>
453
454 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
455
6f2791d5
L		 4562019-04-08 H.J. Lu <hongjiu.lu@intel.com>
457
458 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
459 * i386-init.h: Regenerated.
460
e392bad3
AM		 4612019-04-07 Alan Modra <amodra@gmail.com>
462
463 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
464 op_separator to control printing of spaces, comma and parens
465 rather than need_comma, need_paren and spaces vars.
466
dffaa15c
AM		 4672019-04-07 Alan Modra <amodra@gmail.com>
468
469 PR 24421
470 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
471 (print_insn_neon, print_insn_arm): Likewise.
472
d6aab7a1
XG		 4732019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
474
475 * i386-dis-evex.h (evex_table): Updated to support BF16
476 instructions.
477 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
478 and EVEX_W_0F3872_P_3.
479 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
480 (cpu_flags): Add bitfield for CpuAVX512_BF16.
481 * i386-opc.h (enum): Add CpuAVX512_BF16.
482 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
483 * i386-opc.tbl: Add AVX512 BF16 instructions.
484 * i386-init.h: Regenerated.
485 * i386-tbl.h: Likewise.
486
66e85460
AM		 4872019-04-05 Alan Modra <amodra@gmail.com>
488
489 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
490 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
491 to favour printing of "-" branch hint when using the "y" bit.
492 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
493
c2b1c275
AM		 4942019-04-05 Alan Modra <amodra@gmail.com>
495
496 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
497 opcode until first operand is output.
498
aae9718e
PB		 4992019-04-04 Peter Bergner <bergner@linux.ibm.com>
500
501 PR gas/24349
502 * ppc-opc.c (valid_bo_pre_v2): Add comments.
503 (valid_bo_post_v2): Add support for 'at' branch hints.
504 (insert_bo): Only error on branch on ctr.
505 (get_bo_hint_mask): New function.
506 (insert_boe): Add new 'branch_taken' formal argument. Add support
507 for inserting 'at' branch hints.
508 (extract_boe): Add new 'branch_taken' formal argument. Add support
509 for extracting 'at' branch hints.
510 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
511 (BOE): Delete operand.
512 (BOM, BOP): New operands.
513 (RM): Update value.
514 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
515 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
516 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
517 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
518 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
519 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
520 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
521 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
522 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
523 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
524 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
525 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
526 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
527 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
528 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
529 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
530 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
531 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
532 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
533 bttarl+>: New extended mnemonics.
534
96a86c01
AM		 5352019-03-28 Alan Modra <amodra@gmail.com>
536
537 PR 24390
538 * ppc-opc.c (BTF): Define.
539 (powerpc_opcodes): Use for mtfsb*.
540 * ppc-dis.c (print_insn_powerpc): Print fields with both
541 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
542
796d6298
TC		 5432019-03-25 Tamar Christina <tamar.christina@arm.com>
544
545 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
546 (mapping_symbol_for_insn): Implement new algorithm.
547 (print_insn): Remove duplicate code.
548
60df3720
TC		 5492019-03-25 Tamar Christina <tamar.christina@arm.com>
550
551 * aarch64-dis.c (print_insn_aarch64):
552 Implement override.
553
51457761
TC		 5542019-03-25 Tamar Christina <tamar.christina@arm.com>
555
556 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
557 order.
558
53b2f36b
TC		 5592019-03-25 Tamar Christina <tamar.christina@arm.com>
560
561 * aarch64-dis.c (last_stop_offset): New.
562 (print_insn_aarch64): Use stop_offset.
563
89199bb5
L		 5642019-03-19 H.J. Lu <hongjiu.lu@intel.com>
565
566 PR gas/24359
567 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
568 CPU_ANY_AVX2_FLAGS.
569 * i386-init.h: Regenerated.
570
97ed31ae
L		 5712019-03-18 H.J. Lu <hongjiu.lu@intel.com>
572
573 PR gas/24348
574 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
575 vmovdqu16, vmovdqu32 and vmovdqu64.
576 * i386-tbl.h: Regenerated.
577
0919bfe9
AK		 5782019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
579
580 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
581 from vstrszb, vstrszh, and vstrszf.
582
5832019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
584
585 * s390-opc.txt: Add instruction descriptions.
586
21820ebe
JW		 5872019-02-08 Jim Wilson <jimw@sifive.com>
588
589 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
590 <bne>: Likewise.
591
f7dd2fb2
TC		 5922019-02-07 Tamar Christina <tamar.christina@arm.com>
593
594 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
595
6456d318
TC		 5962019-02-07 Tamar Christina <tamar.christina@arm.com>
597
598 PR binutils/23212
599 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
600 * aarch64-opc.c (verify_elem_sd): New.
601 (fields): Add FLD_sz entr.
602 * aarch64-tbl.h (_SIMD_INSN): New.
603 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
604 fmulx scalar and vector by element isns.
605
4a83b610
NC		 6062019-02-07 Nick Clifton <nickc@redhat.com>
607
608 * po/sv.po: Updated Swedish translation.
609
fc60b8c8
AK		 6102019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
611
612 * s390-mkopc.c (main): Accept arch13 as cpu string.
613 * s390-opc.c: Add new instruction formats and instruction opcode
614 masks.
615 * s390-opc.txt: Add new arch13 instructions.
616
e10620d3
TC		 6172019-01-25 Sudakshina Das <sudi.das@arm.com>
618
619 * aarch64-tbl.h (QL_LDST_AT): Update macro.
620 (aarch64_opcode): Change encoding for stg, stzg
621 st2g and st2zg.
622 * aarch64-asm-2.c: Regenerated.
623 * aarch64-dis-2.c: Regenerated.
624 * aarch64-opc-2.c: Regenerated.
625
20a4ca55
SD		 6262019-01-25 Sudakshina Das <sudi.das@arm.com>
627
628 * aarch64-asm-2.c: Regenerated.
629 * aarch64-dis-2.c: Likewise.
630 * aarch64-opc-2.c: Likewise.
631 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
632
550fd7bf
SD		 6332019-01-25 Sudakshina Das <sudi.das@arm.com>
634 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
635
636 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
637 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
638 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
639 * aarch64-dis.h (ext_addr_simple_2): Likewise.
640 * aarch64-opc.c (operand_general_constraint_met_p): Remove
641 case for ldstgv_indexed.
642 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
643 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
644 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
645 * aarch64-asm-2.c: Regenerated.
646 * aarch64-dis-2.c: Regenerated.
647 * aarch64-opc-2.c: Regenerated.
648
d9938630
NC		 6492019-01-23 Nick Clifton <nickc@redhat.com>
650
651 * po/pt_BR.po: Updated Brazilian Portuguese translation.
652
375cd423
NC		 6532019-01-21 Nick Clifton <nickc@redhat.com>
654
655 * po/de.po: Updated German translation.
656 * po/uk.po: Updated Ukranian translation.
657
57299f48
CX		 6582019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
659 * mips-dis.c (mips_arch_choices): Fix typo in
660 gs464, gs464e and gs264e descriptors.
661
f48dfe41
NC		 6622019-01-19 Nick Clifton <nickc@redhat.com>
663
664 * configure: Regenerate.
665 * po/opcodes.pot: Regenerate.
666
f974f26c
NC		 6672018-06-24 Nick Clifton <nickc@redhat.com>
668
669 2.32 branch created.
670
39f286cd
JD		 6712019-01-09 John Darrington <john@darrington.wattle.id.au>
672
448b8ca8
JD		 673 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
674 if it is null.
675 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 676 zero.
677
3107326d
AP		 6782019-01-09 Andrew Paprocki <andrew@ishiboo.com>
679
680 * configure: Regenerate.
681
7e9ca91e
AM		 6822019-01-07 Alan Modra <amodra@gmail.com>
683
684 * configure: Regenerate.
685 * po/POTFILES.in: Regenerate.
686
ef1ad42b
JD		 6872019-01-03 John Darrington <john@darrington.wattle.id.au>
688
689 * s12z-opc.c: New file.
690 * s12z-opc.h: New file.
691 * s12z-dis.c: Removed all code not directly related to display
692 of instructions. Used the interface provided by the new files
693 instead.
694 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 695 * Makefile.in: Regenerate.
ef1ad42b 696 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 697 * configure: Regenerate.
ef1ad42b 698
82704155
AM		 6992019-01-01 Alan Modra <amodra@gmail.com>
700
701 Update year range in copyright notice of all files.
702
d5c04e1b 703For older changes see ChangeLog-2018
3499769a 704\f
d5c04e1b 705Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 706
707Copying and distribution of this file, with or without modification,
708are permitted in any medium without royalty provided the copyright
709notice and this notice are preserved.
710
711Local Variables:
712mode: change-log
713left-margin: 8
714fill-column: 74
715version-control: never
716End:
GDB Binutils - Deliverables
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