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Handle function aliases better (PR gdb/19487, errno printing)
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
cc4a945a
JW		 12017-08-09 Jiong Wang <jiong.wang@arm.com>
2
3 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
4 register operands in CRC instructions.
5 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
6 comments.
7
b28b8b5e
L		 82017-08-07 H.J. Lu <hongjiu.lu@intel.com>
9
10 * disassemble.c (disassembler): Mark big and mach with
11 ATTRIBUTE_UNUSED.
12
e347efc3
MR		 132017-08-07 Maciej W. Rozycki <macro@imgtec.com>
14
15 * disassemble.c (disassembler): Remove arch/mach/endian
16 assertions.
17
7cbc739c
NC		 182017-07-25 Nick Clifton <nickc@redhat.com>
19
20 PR 21739
21 * arc-opc.c (insert_rhv2): Use lower case first letter in error
22 message.
23 (insert_r0): Likewise.
24 (insert_r1): Likewise.
25 (insert_r2): Likewise.
26 (insert_r3): Likewise.
27 (insert_sp): Likewise.
28 (insert_gp): Likewise.
29 (insert_pcl): Likewise.
30 (insert_blink): Likewise.
31 (insert_ilink1): Likewise.
32 (insert_ilink2): Likewise.
33 (insert_ras): Likewise.
34 (insert_rbs): Likewise.
35 (insert_rcs): Likewise.
36 (insert_simm3s): Likewise.
37 (insert_rrange): Likewise.
38 (insert_r13el): Likewise.
39 (insert_fpel): Likewise.
40 (insert_blinkel): Likewise.
41 (insert_pclel): Likewise.
42 (insert_nps_bitop_size_2b): Likewise.
43 (insert_nps_imm_offset): Likewise.
44 (insert_nps_imm_entry): Likewise.
45 (insert_nps_size_16bit): Likewise.
46 (insert_nps_##NAME##_pos): Likewise.
47 (insert_nps_##NAME): Likewise.
48 (insert_nps_bitop_ins_ext): Likewise.
49 (insert_nps_##NAME): Likewise.
50 (insert_nps_min_hofs): Likewise.
51 (insert_nps_##NAME): Likewise.
52 (insert_nps_rbdouble_64): Likewise.
53 (insert_nps_misc_imm_offset): Likewise.
54 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
55 option description.
56
7684e580
JW		 572017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
58 Jiong Wang <jiong.wang@arm.com>
59
60 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
61 correct the print.
62 * aarch64-dis-2.c: Regenerated.
63
47826cdb
AK		 642017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
65
66 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
67 table.
68
2d2dbad0
NC		 692017-07-20 Nick Clifton <nickc@redhat.com>
70
71 * po/de.po: Updated German translation.
72
70b448ba 732017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
74
75 * arc-regs.h (sec_stat): New aux register.
76 (aux_kernel_sp): Likewise.
77 (aux_sec_u_sp): Likewise.
78 (aux_sec_k_sp): Likewise.
79 (sec_vecbase_build): Likewise.
80 (nsc_table_top): Likewise.
81 (nsc_table_base): Likewise.
82 (ersec_stat): Likewise.
83 (aux_sec_except): Likewise.
84
7179e0e6
CZ		 852017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
86
87 * arc-opc.c (extract_uimm12_20): New function.
88 (UIMM12_20): New operand.
89 (SIMM3_5_S): Adjust.
90 * arc-tbl.h (sjli): Add new instruction.
91
684d5a10
JEM		 922017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
93 John Eric Martin <John.Martin@emmicro-us.com>
94
95 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
96 (UIMM3_23): Adjust accordingly.
97 * arc-regs.h: Add/correct jli_base register.
98 * arc-tbl.h (jli_s): Likewise.
99
de194d85
YC		 1002017-07-18 Nick Clifton <nickc@redhat.com>
101
102 PR 21775
103 * aarch64-opc.c: Fix spelling typos.
104 * i386-dis.c: Likewise.
105
0f6329bd
RB		 1062017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
107
108 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
109 max_addr_offset and octets variables to size_t.
110
429d795d
AM		 1112017-07-12 Alan Modra <amodra@gmail.com>
112
113 * po/da.po: Update from translationproject.org/latest/opcodes/.
114 * po/de.po: Likewise.
115 * po/es.po: Likewise.
116 * po/fi.po: Likewise.
117 * po/fr.po: Likewise.
118 * po/id.po: Likewise.
119 * po/it.po: Likewise.
120 * po/nl.po: Likewise.
121 * po/pt_BR.po: Likewise.
122 * po/ro.po: Likewise.
123 * po/sv.po: Likewise.
124 * po/tr.po: Likewise.
125 * po/uk.po: Likewise.
126 * po/vi.po: Likewise.
127 * po/zh_CN.po: Likewise.
128
4162bb66
AM		 1292017-07-11 Yao Qi <yao.qi@linaro.org>
130 Alan Modra <amodra@gmail.com>
131
132 * cgen.sh: Mark generated files read-only.
133 * epiphany-asm.c: Regenerate.
134 * epiphany-desc.c: Regenerate.
135 * epiphany-desc.h: Regenerate.
136 * epiphany-dis.c: Regenerate.
137 * epiphany-ibld.c: Regenerate.
138 * epiphany-opc.c: Regenerate.
139 * epiphany-opc.h: Regenerate.
140 * fr30-asm.c: Regenerate.
141 * fr30-desc.c: Regenerate.
142 * fr30-desc.h: Regenerate.
143 * fr30-dis.c: Regenerate.
144 * fr30-ibld.c: Regenerate.
145 * fr30-opc.c: Regenerate.
146 * fr30-opc.h: Regenerate.
147 * frv-asm.c: Regenerate.
148 * frv-desc.c: Regenerate.
149 * frv-desc.h: Regenerate.
150 * frv-dis.c: Regenerate.
151 * frv-ibld.c: Regenerate.
152 * frv-opc.c: Regenerate.
153 * frv-opc.h: Regenerate.
154 * ip2k-asm.c: Regenerate.
155 * ip2k-desc.c: Regenerate.
156 * ip2k-desc.h: Regenerate.
157 * ip2k-dis.c: Regenerate.
158 * ip2k-ibld.c: Regenerate.
159 * ip2k-opc.c: Regenerate.
160 * ip2k-opc.h: Regenerate.
161 * iq2000-asm.c: Regenerate.
162 * iq2000-desc.c: Regenerate.
163 * iq2000-desc.h: Regenerate.
164 * iq2000-dis.c: Regenerate.
165 * iq2000-ibld.c: Regenerate.
166 * iq2000-opc.c: Regenerate.
167 * iq2000-opc.h: Regenerate.
168 * lm32-asm.c: Regenerate.
169 * lm32-desc.c: Regenerate.
170 * lm32-desc.h: Regenerate.
171 * lm32-dis.c: Regenerate.
172 * lm32-ibld.c: Regenerate.
173 * lm32-opc.c: Regenerate.
174 * lm32-opc.h: Regenerate.
175 * lm32-opinst.c: Regenerate.
176 * m32c-asm.c: Regenerate.
177 * m32c-desc.c: Regenerate.
178 * m32c-desc.h: Regenerate.
179 * m32c-dis.c: Regenerate.
180 * m32c-ibld.c: Regenerate.
181 * m32c-opc.c: Regenerate.
182 * m32c-opc.h: Regenerate.
183 * m32r-asm.c: Regenerate.
184 * m32r-desc.c: Regenerate.
185 * m32r-desc.h: Regenerate.
186 * m32r-dis.c: Regenerate.
187 * m32r-ibld.c: Regenerate.
188 * m32r-opc.c: Regenerate.
189 * m32r-opc.h: Regenerate.
190 * m32r-opinst.c: Regenerate.
191 * mep-asm.c: Regenerate.
192 * mep-desc.c: Regenerate.
193 * mep-desc.h: Regenerate.
194 * mep-dis.c: Regenerate.
195 * mep-ibld.c: Regenerate.
196 * mep-opc.c: Regenerate.
197 * mep-opc.h: Regenerate.
198 * mt-asm.c: Regenerate.
199 * mt-desc.c: Regenerate.
200 * mt-desc.h: Regenerate.
201 * mt-dis.c: Regenerate.
202 * mt-ibld.c: Regenerate.
203 * mt-opc.c: Regenerate.
204 * mt-opc.h: Regenerate.
205 * or1k-asm.c: Regenerate.
206 * or1k-desc.c: Regenerate.
207 * or1k-desc.h: Regenerate.
208 * or1k-dis.c: Regenerate.
209 * or1k-ibld.c: Regenerate.
210 * or1k-opc.c: Regenerate.
211 * or1k-opc.h: Regenerate.
212 * or1k-opinst.c: Regenerate.
213 * xc16x-asm.c: Regenerate.
214 * xc16x-desc.c: Regenerate.
215 * xc16x-desc.h: Regenerate.
216 * xc16x-dis.c: Regenerate.
217 * xc16x-ibld.c: Regenerate.
218 * xc16x-opc.c: Regenerate.
219 * xc16x-opc.h: Regenerate.
220 * xstormy16-asm.c: Regenerate.
221 * xstormy16-desc.c: Regenerate.
222 * xstormy16-desc.h: Regenerate.
223 * xstormy16-dis.c: Regenerate.
224 * xstormy16-ibld.c: Regenerate.
225 * xstormy16-opc.c: Regenerate.
226 * xstormy16-opc.h: Regenerate.
227
7639175c
AM		 2282017-07-07 Alan Modra <amodra@gmail.com>
229
230 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
231 * m32c-dis.c: Regenerate.
232 * mep-dis.c: Regenerate.
233
e4bdd679
BP		 2342017-07-05 Borislav Petkov <bp@suse.de>
235
236 * i386-dis.c: Enable ModRM.reg /6 aliases.
237
60c96dbf
RR		 2382017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
239
240 * opcodes/arm-dis.c: Support MVFR2 in disassembly
241 with vmrs and vmsr.
242
0d702cfe
TG		 2432017-07-04 Tristan Gingold <gingold@adacore.com>
244
245 * configure: Regenerate.
246
15e6ed8c
TG		 2472017-07-03 Tristan Gingold <gingold@adacore.com>
248
249 * po/opcodes.pot: Regenerate.
250
b1d3c886
MR		 2512017-06-30 Maciej W. Rozycki <macro@imgtec.com>
252
253 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
254 entries to the MSA ASE instruction block.
255
909b4e3d
MR		 2562017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
257 Maciej W. Rozycki <macro@imgtec.com>
258
259 * micromips-opc.c (XPA, XPAVZ): New macros.
260 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
261 "mthgc0".
262
f5b2fd52
MR		 2632017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
264 Maciej W. Rozycki <macro@imgtec.com>
265
266 * micromips-opc.c (I36): New macro.
267 (micromips_opcodes): Add "eretnc".
268
9785fc2a
MR		 2692017-06-30 Maciej W. Rozycki <macro@imgtec.com>
270 Andrew Bennett <andrew.bennett@imgtec.com>
271
272 * mips-dis.c (mips_calculate_combination_ases): Handle the
273 ASE_XPA_VIRT flag.
274 (parse_mips_ase_option): New function.
275 (parse_mips_dis_option): Factor out ASE option handling to the
276 new function. Call `mips_calculate_combination_ases'.
277 * mips-opc.c (XPAVZ): New macro.
278 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
279 "mfhgc0", "mthc0" and "mthgc0".
280
60804c53
MR		 2812017-06-29 Maciej W. Rozycki <macro@imgtec.com>
282
283 * mips-dis.c (mips_calculate_combination_ases): New function.
284 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
285 calculation to the new function.
286 (set_default_mips_dis_options): Call the new function.
287
2e74f9dd
AK		 2882017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
289
290 * arc-dis.c (parse_disassembler_options): Use
291 FOR_EACH_DISASSEMBLER_OPTION.
292
e1e94c49
AK		 2932017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
294
295 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
296 disassembler option strings.
297 (parse_cpu_option): Likewise.
298
65a55fbb
TC		 2992017-06-28 Tamar Christina <tamar.christina@arm.com>
300
301 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
302 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
303 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
304 (aarch64_feature_dotprod, DOT_INSN): New.
305 (udot, sdot): New.
306 * aarch64-dis-2.c: Regenerated.
307
c604a79a
JW		 3082017-06-28 Jiong Wang <jiong.wang@arm.com>
309
310 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
311
38bf472a
MR		 3122017-06-28 Maciej W. Rozycki <macro@imgtec.com>
313 Matthew Fortune <matthew.fortune@imgtec.com>
4151f684 314 Andrew Bennett <andrew.bennett@imgtec.com>
38bf472a
MR		 315
316 * mips-formats.h (INT_BIAS): New macro.
317 (INT_ADJ): Redefine in INT_BIAS terms.
318 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
319 (mips_print_save_restore): New function.
320 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
321 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
322 call.
323 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
324 (print_mips16_insn_arg): Call `mips_print_save_restore' for
325 OP_SAVE_RESTORE_LIST handling, factored out from here.
326 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
327 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
328 (mips_builtin_opcodes): Add "restore" and "save" entries.
329 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
330 (IAMR2): New macro.
331 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
332
9bdfdbf9
AW		 3332017-06-23 Andrew Waterman <andrew@sifive.com>
334
335 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
336 alias; do not mark SLTI instruction as an alias.
337
2234eee6
L		 3382017-06-21 H.J. Lu <hongjiu.lu@intel.com>
339
340 * i386-dis.c (RM_0FAE_REG_5): Removed.
341 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
342 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
343 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
344 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
345 PREFIX_MOD_3_0F01_REG_5_RM_0.
346 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
347 PREFIX_MOD_3_0FAE_REG_5.
348 (mod_table): Update MOD_0FAE_REG_5.
349 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
350 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
351 * i386-tbl.h: Regenerated.
352
c2f76402
L		 3532017-06-21 H.J. Lu <hongjiu.lu@intel.com>
354
355 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
356 * i386-opc.tbl: Likewise.
357 * i386-tbl.h: Regenerated.
358
9fef80d6
L		 3592017-06-21 H.J. Lu <hongjiu.lu@intel.com>
360
361 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
362 and "jmp{&|}".
363 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
364 prefix.
365
0f6d864d
NC		 3662017-06-19 Nick Clifton <nickc@redhat.com>
367
368 PR binutils/21614
369 * score-dis.c (score_opcodes): Add sentinel.
370
e197589b
AM		 3712017-06-16 Alan Modra <amodra@gmail.com>
372
373 * rx-decode.c: Regenerate.
374
0d96e4df
L		 3752017-06-15 H.J. Lu <hongjiu.lu@intel.com>
376
377 PR binutils/21594
378 * i386-dis.c (OP_E_register): Check valid bnd register.
379 (OP_G): Likewise.
380
cd3ea7c6
NC		 3812017-06-15 Nick Clifton <nickc@redhat.com>
382
383 PR binutils/21595
384 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
385 range value.
386
63323b5b
NC		 3872017-06-15 Nick Clifton <nickc@redhat.com>
388
389 PR binutils/21588
390 * rl78-decode.opc (OP_BUF_LEN): Define.
391 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
392 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
393 array.
394 * rl78-decode.c: Regenerate.
395
08c7881b
NC		 3962017-06-15 Nick Clifton <nickc@redhat.com>
397
398 PR binutils/21586
399 * bfin-dis.c (gregs): Clip index to prevent overflow.
400 (regs): Likewise.
401 (regs_lo): Likewise.
402 (regs_hi): Likewise.
403
e64519d1
NC		 4042017-06-14 Nick Clifton <nickc@redhat.com>
405
406 PR binutils/21576
407 * score7-dis.c (score_opcodes): Add sentinel.
408
6394c606
YQ		 4092017-06-14 Yao Qi <yao.qi@linaro.org>
410
411 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
412 * arm-dis.c: Likewise.
413 * ia64-dis.c: Likewise.
414 * mips-dis.c: Likewise.
415 * spu-dis.c: Likewise.
416 * disassemble.h (print_insn_aarch64): New declaration, moved from
417 include/dis-asm.h.
418 (print_insn_big_arm, print_insn_big_mips): Likewise.
419 (print_insn_i386, print_insn_ia64): Likewise.
420 (print_insn_little_arm, print_insn_little_mips): Likewise.
421
db5fa770
NC		 4222017-06-14 Nick Clifton <nickc@redhat.com>
423
424 PR binutils/21587
425 * rx-decode.opc: Include libiberty.h
426 (GET_SCALE): New macro - validates access to SCALE array.
427 (GET_PSCALE): New macro - validates access to PSCALE array.
428 (DIs, SIs, S2Is, rx_disp): Use new macros.
429 * rx-decode.c: Regenerate.
430
05c966f3
AV		 4312017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
432
433 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
434
10045478
AK		 4352017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
436
437 * arc-dis.c (enforced_isa_mask): Declare.
438 (cpu_types): Likewise.
439 (parse_cpu_option): New function.
440 (parse_disassembler_options): Use it.
441 (print_insn_arc): Use enforced_isa_mask.
442 (print_arc_disassembler_options): Document new options.
443
88c1242d
YQ		 4442017-05-24 Yao Qi <yao.qi@linaro.org>
445
446 * alpha-dis.c: Include disassemble.h, don't include
447 dis-asm.h.
448 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
449 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
450 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
451 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
452 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
453 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
454 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
455 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
456 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
457 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
458 * moxie-dis.c, msp430-dis.c, mt-dis.c:
459 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
460 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
461 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
462 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
463 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
464 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
465 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
466 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
467 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
468 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
469 * z80-dis.c, z8k-dis.c: Likewise.
470 * disassemble.h: New file.
471
ab20fa4a
YQ		 4722017-05-24 Yao Qi <yao.qi@linaro.org>
473
474 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
475 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
476
003ca0fd
YQ		 4772017-05-24 Yao Qi <yao.qi@linaro.org>
478
479 * disassemble.c (disassembler): Add arguments a, big and mach.
480 Use them.
481
04ef582a
L		 4822017-05-22 H.J. Lu <hongjiu.lu@intel.com>
483
484 * i386-dis.c (NOTRACK_Fixup): New.
485 (NOTRACK): Likewise.
486 (NOTRACK_PREFIX): Likewise.
487 (last_active_prefix): Likewise.
488 (reg_table): Use NOTRACK on indirect call and jmp.
489 (ckprefix): Set last_active_prefix.
490 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
491 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
492 * i386-opc.h (NoTrackPrefixOk): New.
493 (i386_opcode_modifier): Add notrackprefixok.
494 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
495 Add notrack.
496 * i386-tbl.h: Regenerated.
497
64517994
JM		 4982017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
499
500 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
501 (X_IMM2): Define.
502 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
503 bfd_mach_sparc_v9m8.
504 (print_insn_sparc): Handle new operand types.
505 * sparc-opc.c (MASK_M8): Define.
506 (v6): Add MASK_M8.
507 (v6notlet): Likewise.
508 (v7): Likewise.
509 (v8): Likewise.
510 (v9): Likewise.
511 (v9a): Likewise.
512 (v9b): Likewise.
513 (v9c): Likewise.
514 (v9d): Likewise.
515 (v9e): Likewise.
516 (v9v): Likewise.
517 (v9m): Likewise.
518 (v9andleon): Likewise.
519 (m8): Define.
520 (HWS_VM8): Define.
521 (HWS2_VM8): Likewise.
522 (sparc_opcode_archs): Add entry for "m8".
523 (sparc_opcodes): Add OSA2017 and M8 instructions
524 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
525 fpx{ll,ra,rl}64x,
526 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
527 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
528 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
529 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
530 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
531 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
532 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
533 ASI_CORE_SELECT_COMMIT_NHT.
534
535b785f
AM		 5352017-05-18 Alan Modra <amodra@gmail.com>
536
537 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
538 * aarch64-dis.c: Likewise.
539 * aarch64-gen.c: Likewise.
540 * aarch64-opc.c: Likewise.
541
25499ac7
MR		 5422017-05-15 Maciej W. Rozycki <macro@imgtec.com>
543 Matthew Fortune <matthew.fortune@imgtec.com>
544
545 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
546 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
547 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
548 (print_insn_arg) <OP_REG28>: Add handler.
549 (validate_insn_args) <OP_REG28>: Handle.
550 (print_mips16_insn_arg): Handle MIPS16 instructions that require
551 32-bit encoding and 9-bit immediates.
552 (print_insn_mips16): Handle MIPS16 instructions that require
553 32-bit encoding and MFC0/MTC0 operand decoding.
554 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
555 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
556 (RD_C0, WR_C0, E2, E2MT): New macros.
557 (mips16_opcodes): Add entries for MIPS16e2 instructions:
558 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
559 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
560 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
561 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
562 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
563 instructions, "swl", "swr", "sync" and its "sync_acquire",
564 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
565 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
566 regular/extended entries for original MIPS16 ISA revision
567 instructions whose extended forms are subdecoded in the MIPS16e2
568 ISA revision: "li", "sll" and "srl".
569
fdfb4752
MR		 5702017-05-15 Maciej W. Rozycki <macro@imgtec.com>
571
572 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
573 reference in CP0 move operand decoding.
574
a4f89915
MR		 5752017-05-12 Maciej W. Rozycki <macro@imgtec.com>
576
577 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
578 type to hexadecimal.
579 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
580
99e2d67a
MR		 5812017-05-11 Maciej W. Rozycki <macro@imgtec.com>
582
583 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
584 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
585 "sync_rmb" and "sync_wmb" as aliases.
586 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
587 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
588
53a346d8
CZ		 5892017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
590
591 * arc-dis.c (parse_option): Update quarkse_em option..
592 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
593 QUARKSE1.
594 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
595
f91d48de
KC		 5962017-05-03 Kito Cheng <kito.cheng@gmail.com>
597
598 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
599
43e379d7
MC		 6002017-05-01 Michael Clark <michaeljclark@mac.com>
601
602 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
603 register.
604
a4ddc54e
MR		 6052017-05-02 Maciej W. Rozycki <macro@imgtec.com>
606
607 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
608 and branches and not synthetic data instructions.
609
fe50e98c
BE		 6102017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
611
612 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
613
126124cc
CZ		 6142017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
615
616 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
617 * arc-opc.c (insert_r13el): New function.
618 (R13_EL): Define.
619 * arc-tbl.h: Add new enter/leave variants.
620
be6a24d8
CZ		 6212017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
622
623 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
624
0348fd79
MR		 6252017-04-25 Maciej W. Rozycki <macro@imgtec.com>
626
627 * mips-dis.c (print_mips_disassembler_options): Add
628 `no-aliases'.
629
6e3d1f07
MR		 6302017-04-25 Maciej W. Rozycki <macro@imgtec.com>
631
632 * mips16-opc.c (AL): New macro.
633 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
634 of "ld" and "lw" as aliases.
635
957f6b39
TC		 6362017-04-24 Tamar Christina <tamar.christina@arm.com>
637
638 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
639 arguments.
640
a8cc8a54
AM		 6412017-04-22 Alexander Fedotov <alfedotov@gmail.com>
642 Alan Modra <amodra@gmail.com>
643
644 * ppc-opc.c (ELEV): Define.
645 (vle_opcodes): Add se_rfgi and e_sc.
646 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
647 for E200Z4.
648
3ab87b68
JM		 6492017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
650
651 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
652
792f174f
NC		 6532017-04-21 Nick Clifton <nickc@redhat.com>
654
655 PR binutils/21380
656 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
657 LD3R and LD4R.
658
42742084
AM		 6592017-04-13 Alan Modra <amodra@gmail.com>
660
661 * epiphany-desc.c: Regenerate.
662 * fr30-desc.c: Regenerate.
663 * frv-desc.c: Regenerate.
664 * ip2k-desc.c: Regenerate.
665 * iq2000-desc.c: Regenerate.
666 * lm32-desc.c: Regenerate.
667 * m32c-desc.c: Regenerate.
668 * m32r-desc.c: Regenerate.
669 * mep-desc.c: Regenerate.
670 * mt-desc.c: Regenerate.
671 * or1k-desc.c: Regenerate.
672 * xc16x-desc.c: Regenerate.
673 * xstormy16-desc.c: Regenerate.
674
9a85b496
AM		 6752017-04-11 Alan Modra <amodra@gmail.com>
676
ef85eab0 677 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 678 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
679 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 680 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
681 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 682 (PPCVSX2): Define as PPC_OPCODE_POWER8.
683 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 684 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 685 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 686
62adc510
AM		 6872017-04-10 Alan Modra <amodra@gmail.com>
688
689 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
690 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
691 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
692 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
693
aa808707
PC		 6942017-04-09 Pip Cet <pipcet@gmail.com>
695
696 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
697 appropriate floating-point precision directly.
698
ac8f0f72
AM		 6992017-04-07 Alan Modra <amodra@gmail.com>
700
701 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
702 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
703 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
704 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
705 vector instructions with E6500 not PPCVEC2.
706
62ecb94c
PC		 7072017-04-06 Pip Cet <pipcet@gmail.com>
708
709 * Makefile.am: Add wasm32-dis.c.
710 * configure.ac: Add wasm32-dis.c to wasm32 target.
711 * disassemble.c: Add wasm32 disassembler code.
712 * wasm32-dis.c: New file.
713 * Makefile.in: Regenerate.
714 * configure: Regenerate.
715 * po/POTFILES.in: Regenerate.
716 * po/opcodes.pot: Regenerate.
717
f995bbe8
PA		 7182017-04-05 Pedro Alves <palves@redhat.com>
719
720 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
721 * arm-dis.c (parse_arm_disassembler_options): Constify.
722 * ppc-dis.c (powerpc_init_dialect): Constify local.
723 * vax-dis.c (parse_disassembler_options): Constify.
724
b5292032
PD		 7252017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
726
727 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
728 RISCV_GP_SYMBOL.
729
f96bd6c2
PC		 7302017-03-30 Pip Cet <pipcet@gmail.com>
731
732 * configure.ac: Add (empty) bfd_wasm32_arch target.
733 * configure: Regenerate
734 * po/opcodes.pot: Regenerate.
735
f7c514a3
JM		 7362017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
737
738 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
739 OSA2015.
740 * opcodes/sparc-opc.c (asi_table): New ASIs.
741
52be03fd
AM		 7422017-03-29 Alan Modra <amodra@gmail.com>
743
744 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
745 "raw" option.
746 (lookup_powerpc): Don't special case -1 dialect. Handle
747 PPC_OPCODE_RAW.
748 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
749 lookup_powerpc call, pass it on second.
750
9b753937
AM		 7512017-03-27 Alan Modra <amodra@gmail.com>
752
753 PR 21303
754 * ppc-dis.c (struct ppc_mopt): Comment.
755 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
756
c0c31e91
RZ		 7572017-03-27 Rinat Zelig <rinat@mellanox.com>
758
759 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
760 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
761 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
762 (insert_nps_misc_imm_offset): New function.
763 (extract_nps_misc imm_offset): New function.
764 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
765 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
766
2253c8f0
AK		 7672017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
768
769 * s390-mkopc.c (main): Remove vx2 check.
770 * s390-opc.txt: Remove vx2 instruction flags.
771
645d3342
RZ		 7722017-03-21 Rinat Zelig <rinat@mellanox.com>
773
774 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
775 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
776 (insert_nps_imm_offset): New function.
777 (extract_nps_imm_offset): New function.
778 (insert_nps_imm_entry): New function.
779 (extract_nps_imm_entry): New function.
780
4b94dd2d
AM		 7812017-03-17 Alan Modra <amodra@gmail.com>
782
783 PR 21248
784 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
785 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
786 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
787
b416fe87
KC		 7882017-03-14 Kito Cheng <kito.cheng@gmail.com>
789
790 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
791 <c.andi>: Likewise.
792 <c.addiw> Likewise.
793
03b039a5
KC		 7942017-03-14 Kito Cheng <kito.cheng@gmail.com>
795
796 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
797
2c232b83
AW		 7982017-03-13 Andrew Waterman <andrew@sifive.com>
799
800 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
801 <srl> Likewise.
802 <srai> Likewise.
803 <sra> Likewise.
804
86fa6981
L		 8052017-03-09 H.J. Lu <hongjiu.lu@intel.com>
806
807 * i386-gen.c (opcode_modifiers): Replace S with Load.
808 * i386-opc.h (S): Removed.
809 (Load): New.
810 (i386_opcode_modifier): Replace s with load.
811 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
812 and {evex}. Replace S with Load.
813 * i386-tbl.h: Regenerated.
814
c1fe188b
L		 8152017-03-09 H.J. Lu <hongjiu.lu@intel.com>
816
817 * i386-opc.tbl: Use CpuCET on rdsspq.
818 * i386-tbl.h: Regenerated.
819
4b8b687e
PB		 8202017-03-08 Peter Bergner <bergner@vnet.ibm.com>
821
822 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
823 <vsx>: Do not use PPC_OPCODE_VSX3;
824
1437d063
PB		 8252017-03-08 Peter Bergner <bergner@vnet.ibm.com>
826
827 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
828
603555e5
L		 8292017-03-06 H.J. Lu <hongjiu.lu@intel.com>
830
831 * i386-dis.c (REG_0F1E_MOD_3): New enum.
832 (MOD_0F1E_PREFIX_1): Likewise.
833 (MOD_0F38F5_PREFIX_2): Likewise.
834 (MOD_0F38F6_PREFIX_0): Likewise.
835 (RM_0F1E_MOD_3_REG_7): Likewise.
836 (PREFIX_MOD_0_0F01_REG_5): Likewise.
837 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
838 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
839 (PREFIX_0F1E): Likewise.
840 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
841 (PREFIX_0F38F5): Likewise.
842 (dis386_twobyte): Use PREFIX_0F1E.
843 (reg_table): Add REG_0F1E_MOD_3.
844 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
845 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
846 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
847 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
848 (three_byte_table): Use PREFIX_0F38F5.
849 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
850 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
851 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
852 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
853 PREFIX_MOD_3_0F01_REG_5_RM_2.
854 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
855 (cpu_flags): Add CpuCET.
856 * i386-opc.h (CpuCET): New enum.
857 (CpuUnused): Commented out.
858 (i386_cpu_flags): Add cpucet.
859 * i386-opc.tbl: Add Intel CET instructions.
860 * i386-init.h: Regenerated.
861 * i386-tbl.h: Likewise.
862
73f07bff
AM		 8632017-03-06 Alan Modra <amodra@gmail.com>
864
865 PR 21124
866 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
867 (extract_raq, extract_ras, extract_rbx): New functions.
868 (powerpc_operands): Use opposite corresponding insert function.
869 (Q_MASK): Define.
870 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
871 register restriction.
872
65b48a81
PB		 8732017-02-28 Peter Bergner <bergner@vnet.ibm.com>
874
875 * disassemble.c Include "safe-ctype.h".
876 (disassemble_init_for_target): Handle s390 init.
877 (remove_whitespace_and_extra_commas): New function.
878 (disassembler_options_cmp): Likewise.
879 * arm-dis.c: Include "libiberty.h".
880 (NUM_ELEM): Delete.
881 (regnames): Use long disassembler style names.
882 Add force-thumb and no-force-thumb options.
883 (NUM_ARM_REGNAMES): Rename from this...
884 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
885 (get_arm_regname_num_options): Delete.
886 (set_arm_regname_option): Likewise.
887 (get_arm_regnames): Likewise.
888 (parse_disassembler_options): Likewise.
889 (parse_arm_disassembler_option): Rename from this...
890 (parse_arm_disassembler_options): ...to this. Make static.
891 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
892 (print_insn): Use parse_arm_disassembler_options.
893 (disassembler_options_arm): New function.
894 (print_arm_disassembler_options): Handle updated regnames.
895 * ppc-dis.c: Include "libiberty.h".
896 (ppc_opts): Add "32" and "64" entries.
897 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
898 (powerpc_init_dialect): Add break to switch statement.
899 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
900 (disassembler_options_powerpc): New function.
901 (print_ppc_disassembler_options): Use ARRAY_SIZE.
902 Remove printing of "32" and "64".
903 * s390-dis.c: Include "libiberty.h".
904 (init_flag): Remove unneeded variable.
905 (struct s390_options_t): New structure type.
906 (options): New structure.
907 (init_disasm): Rename from this...
908 (disassemble_init_s390): ...to this. Add initializations for
909 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
910 (print_insn_s390): Delete call to init_disasm.
911 (disassembler_options_s390): New function.
912 (print_s390_disassembler_options): Print using information from
913 struct 'options'.
914 * po/opcodes.pot: Regenerate.
915
15c7c1d8
JB		 9162017-02-28 Jan Beulich <jbeulich@suse.com>
917
918 * i386-dis.c (PCMPESTR_Fixup): New.
919 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
920 (prefix_table): Use PCMPESTR_Fixup.
921 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
922 PCMPESTR_Fixup.
923 (vex_w_table): Delete VPCMPESTR{I,M} entries.
924 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
925 Split 64-bit and non-64-bit variants.
926 * opcodes/i386-tbl.h: Re-generate.
927
582e12bf
RS		 9282017-02-24 Richard Sandiford <richard.sandiford@arm.com>
929
930 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
931 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
932 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
933 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
934 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
935 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
936 (OP_SVE_V_HSD): New macros.
937 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
938 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
939 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
940 (aarch64_opcode_table): Add new SVE instructions.
941 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
942 for rotation operands. Add new SVE operands.
943 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
944 (ins_sve_quad_index): Likewise.
945 (ins_imm_rotate): Split into...
946 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
947 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
948 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
949 functions.
950 (aarch64_ins_sve_addr_ri_s4): New function.
951 (aarch64_ins_sve_quad_index): Likewise.
952 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
953 * aarch64-asm-2.c: Regenerate.
954 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
955 (ext_sve_quad_index): Likewise.
956 (ext_imm_rotate): Split into...
957 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
958 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
959 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
960 functions.
961 (aarch64_ext_sve_addr_ri_s4): New function.
962 (aarch64_ext_sve_quad_index): Likewise.
963 (aarch64_ext_sve_index): Allow quad indices.
964 (do_misc_decoding): Likewise.
965 * aarch64-dis-2.c: Regenerate.
966 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
967 aarch64_field_kinds.
968 (OPD_F_OD_MASK): Widen by one bit.
969 (OPD_F_NO_ZR): Bump accordingly.
970 (get_operand_field_width): New function.
971 * aarch64-opc.c (fields): Add new SVE fields.
972 (operand_general_constraint_met_p): Handle new SVE operands.
973 (aarch64_print_operand): Likewise.
974 * aarch64-opc-2.c: Regenerate.
975
f482d304
RS		 9762017-02-24 Richard Sandiford <richard.sandiford@arm.com>
977
978 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
979 (aarch64_feature_compnum): ...this.
980 (SIMD_V8_3): Replace with...
981 (COMPNUM): ...this.
982 (CNUM_INSN): New macro.
983 (aarch64_opcode_table): Use it for the complex number instructions.
984
7db2c588
JB		 9852017-02-24 Jan Beulich <jbeulich@suse.com>
986
987 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
988
1e9d41d4
SL		 9892017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
990
991 Add support for associating SPARC ASIs with an architecture level.
992 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
993 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
994 decoding of SPARC ASIs.
995
53c4d625
JB		 9962017-02-23 Jan Beulich <jbeulich@suse.com>
997
998 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
999 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1000
11648de5
JB		 10012017-02-21 Jan Beulich <jbeulich@suse.com>
1002
1003 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1004 1 (instead of to itself). Correct typo.
1005
f98d33be
AW		 10062017-02-14 Andrew Waterman <andrew@sifive.com>
1007
1008 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1009 pseudoinstructions.
1010
773fb663
RS		 10112017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1012
1013 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1014 (aarch64_sys_reg_supported_p): Handle them.
1015
cc07cda6
CZ		 10162017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1017
1018 * arc-opc.c (UIMM6_20R): Define.
1019 (SIMM12_20): Use above.
1020 (SIMM12_20R): Define.
1021 (SIMM3_5_S): Use above.
1022 (UIMM7_A32_11R_S): Define.
1023 (UIMM7_9_S): Use above.
1024 (UIMM3_13R_S): Define.
1025 (SIMM11_A32_7_S): Use above.
1026 (SIMM9_8R): Define.
1027 (UIMM10_A32_8_S): Use above.
1028 (UIMM8_8R_S): Define.
1029 (W6): Use above.
1030 (arc_relax_opcodes): Use all above defines.
1031
66a5a740
VG		 10322017-02-15 Vineet Gupta <vgupta@synopsys.com>
1033
1034 * arc-regs.h: Distinguish some of the registers different on
1035 ARC700 and HS38 cpus.
1036
7e0de605
AM		 10372017-02-14 Alan Modra <amodra@gmail.com>
1038
1039 PR 21118
1040 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1041 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1042
54064fdb
AM		 10432017-02-11 Stafford Horne <shorne@gmail.com>
1044 Alan Modra <amodra@gmail.com>
1045
1046 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1047 Use insn_bytes_value and insn_int_value directly instead. Don't
1048 free allocated memory until function exit.
1049
dce75bf9
NP		 10502017-02-10 Nicholas Piggin <npiggin@gmail.com>
1051
1052 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1053
1b7e3d2f
NC		 10542017-02-03 Nick Clifton <nickc@redhat.com>
1055
1056 PR 21096
1057 * aarch64-opc.c (print_register_list): Ensure that the register
1058 list index will fir into the tb buffer.
1059 (print_register_offset_address): Likewise.
1060 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1061
8ec5cf65
AD		 10622017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1063
1064 PR 21056
1065 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1066 instructions when the previous fetch packet ends with a 32-bit
1067 instruction.
1068
a1aa5e81
DD		 10692017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1070
1071 * pru-opc.c: Remove vague reference to a future GDB port.
1072
add3afb2
NC		 10732017-01-20 Nick Clifton <nickc@redhat.com>
1074
1075 * po/ga.po: Updated Irish translation.
1076
c13a63b0
SN		 10772017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1078
1079 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1080
9608051a
YQ		 10812017-01-13 Yao Qi <yao.qi@linaro.org>
1082
1083 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1084 if FETCH_DATA returns 0.
1085 (m68k_scan_mask): Likewise.
1086 (print_insn_m68k): Update code to handle -1 return value.
1087
f622ea96
YQ		 10882017-01-13 Yao Qi <yao.qi@linaro.org>
1089
1090 * m68k-dis.c (enum print_insn_arg_error): New.
1091 (NEXTBYTE): Replace -3 with
1092 PRINT_INSN_ARG_MEMORY_ERROR.
1093 (NEXTULONG): Likewise.
1094 (NEXTSINGLE): Likewise.
1095 (NEXTDOUBLE): Likewise.
1096 (NEXTDOUBLE): Likewise.
1097 (NEXTPACKED): Likewise.
1098 (FETCH_ARG): Likewise.
1099 (FETCH_DATA): Update comments.
1100 (print_insn_arg): Update comments. Replace magic numbers with
1101 enum.
1102 (match_insn_m68k): Likewise.
1103
620214f7
IT		 11042017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1105
1106 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1107 * i386-dis-evex.h (evex_table): Updated.
1108 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1109 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1110 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1111 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1112 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1113 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1114 * i386-init.h: Regenerate.
1115 * i386-tbl.h: Ditto.
1116
d95014a2
YQ		 11172017-01-12 Yao Qi <yao.qi@linaro.org>
1118
1119 * msp430-dis.c (msp430_singleoperand): Return -1 if
1120 msp430dis_opcode_signed returns false.
1121 (msp430_doubleoperand): Likewise.
1122 (msp430_branchinstr): Return -1 if
1123 msp430dis_opcode_unsigned returns false.
1124 (msp430x_calla_instr): Likewise.
1125 (print_insn_msp430): Likewise.
1126
0ae60c3e
NC		 11272017-01-05 Nick Clifton <nickc@redhat.com>
1128
1129 PR 20946
1130 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1131 could not be matched.
1132 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1133 NULL.
1134
d74d4880
SN		 11352017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1136
1137 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1138 (aarch64_opcode_table): Use RCPC_INSN.
1139
cc917fd9
KC		 11402017-01-03 Kito Cheng <kito.cheng@gmail.com>
1141
1142 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1143 extension.
1144 * riscv-opcodes/all-opcodes: Likewise.
1145
b52d3cfc
DP		 11462017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1147
1148 * riscv-dis.c (print_insn_args): Add fall through comment.
1149
f90c58d5
NC		 11502017-01-03 Nick Clifton <nickc@redhat.com>
1151
1152 * po/sr.po: New Serbian translation.
1153 * configure.ac (ALL_LINGUAS): Add sr.
1154 * configure: Regenerate.
1155
f47b0d4a
AM		 11562017-01-02 Alan Modra <amodra@gmail.com>
1157
1158 * epiphany-desc.h: Regenerate.
1159 * epiphany-opc.h: Regenerate.
1160 * fr30-desc.h: Regenerate.
1161 * fr30-opc.h: Regenerate.
1162 * frv-desc.h: Regenerate.
1163 * frv-opc.h: Regenerate.
1164 * ip2k-desc.h: Regenerate.
1165 * ip2k-opc.h: Regenerate.
1166 * iq2000-desc.h: Regenerate.
1167 * iq2000-opc.h: Regenerate.
1168 * lm32-desc.h: Regenerate.
1169 * lm32-opc.h: Regenerate.
1170 * m32c-desc.h: Regenerate.
1171 * m32c-opc.h: Regenerate.
1172 * m32r-desc.h: Regenerate.
1173 * m32r-opc.h: Regenerate.
1174 * mep-desc.h: Regenerate.
1175 * mep-opc.h: Regenerate.
1176 * mt-desc.h: Regenerate.
1177 * mt-opc.h: Regenerate.
1178 * or1k-desc.h: Regenerate.
1179 * or1k-opc.h: Regenerate.
1180 * xc16x-desc.h: Regenerate.
1181 * xc16x-opc.h: Regenerate.
1182 * xstormy16-desc.h: Regenerate.
1183 * xstormy16-opc.h: Regenerate.
1184
2571583a
AM		 11852017-01-02 Alan Modra <amodra@gmail.com>
1186
1187 Update year range in copyright notice of all files.
1188
5c1ad6b5 1189For older changes see ChangeLog-2016
3499769a 1190\f
5c1ad6b5 1191Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 1192
1193Copying and distribution of this file, with or without modification,
1194are permitted in any medium without royalty provided the copyright
1195notice and this notice are preserved.
1196
1197Local Variables:
1198mode: change-log
1199left-margin: 8
1200fill-column: 74
1201version-control: never
1202End:
GDB Binutils - Deliverables
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