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Add scm_t_dynwind_flags casts
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
485f23cf
AK		 12015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
2
3 * s390-opc.c: Fix comment.
4 * s390-opc.txt: Change instruction type for troo, trot, trto, and
5 trtt to RRF_U0RER since the second parameter does not need to be a
6 register pair.
7
3f94e60d
NC		 82015-10-08 Nick Clifton <nickc@redhat.com>
9
10 * arc-dis.c (print_insn_arc): Initiallise insn array.
11
875880c6
YQ		 122015-10-07 Yao Qi <yao.qi@linaro.org>
13
14 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
15 'name' rather than 'template'.
16 * aarch64-opc.c (aarch64_print_operand): Likewise.
17
886a2506
NC		 182015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
19
20 * arc-dis.c: Revamped file for ARC support
21 * arc-dis.h: Likewise.
22 * arc-ext.c: Likewise.
23 * arc-ext.h: Likewise.
24 * arc-opc.c: Likewise.
25 * arc-fxi.h: New file.
26 * arc-regs.h: Likewise.
27 * arc-tbl.h: Likewise.
28
36f4aab1
YQ		 292015-10-02 Yao Qi <yao.qi@linaro.org>
30
31 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
32 argument insn type to aarch64_insn. Rename to ...
33 (aarch64_decode_insn): ... it.
34 (print_insn_aarch64_word): Caller updated.
35
7232d389
YQ		 362015-10-02 Yao Qi <yao.qi@linaro.org>
37
38 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
39 (print_insn_aarch64_word): Caller updated.
40
7ecc513a
DV		 412015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
42
43 * s390-mkopc.c (main): Parse htm and vx flag.
44 * s390-opc.txt: Mark instructions from the hardware transactional
45 memory and vector facilities with the "htm"/"vx" flag.
46
b08b78e7
NC		 472015-09-28 Nick Clifton <nickc@redhat.com>
48
49 * po/de.po: Updated German translation.
50
36f7a941
TR		 512015-09-28 Tom Rix <tom@bumblecow.com>
52
53 * ppc-opc.c (PPC500): Mark some opcodes as invalid
54
b6518b38
NC		 552015-09-23 Nick Clifton <nickc@redhat.com>
56
57 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
58 function.
59 * tic30-dis.c (print_branch): Likewise.
60 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
61 value before left shifting.
62 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
63 * hppa-dis.c (print_insn_hppa): Likewise.
64 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
65 array.
66 * msp430-dis.c (msp430_singleoperand): Likewise.
67 (msp430_doubleoperand): Likewise.
68 (print_insn_msp430): Likewise.
69 * nds32-asm.c (parse_operand): Likewise.
70 * sh-opc.h (MASK): Likewise.
71 * v850-dis.c (get_operand_value): Likewise.
72
f04265ec
NC		 732015-09-22 Nick Clifton <nickc@redhat.com>
74
75 * rx-decode.opc (bwl): Use RX_Bad_Size.
76 (sbwl): Likewise.
77 (ubwl): Likewise. Rename to ubw.
78 (uBWL): Rename to uBW.
79 Replace all references to uBWL with uBW.
80 * rx-decode.c: Regenerate.
81 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
82 (opsize_names): Likewise.
83 (print_insn_rx): Detect and report RX_Bad_Size.
84
6dca4fd1
AB		 852015-09-22 Anton Blanchard <anton@samba.org>
86
87 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
88
38074311
JM		 892015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
90
91 * sparc-dis.c (print_insn_sparc): Handle the privileged register
92 %pmcdper.
93
5f40e14d
JS		 942015-08-24 Jan Stancek <jstancek@redhat.com>
95
96 * i386-dis.c (print_insn): Fix decoding of three byte operands.
97
ab4e4ed5
AF		 982015-08-21 Alexander Fomin <alexander.fomin@intel.com>
99
100 PR binutils/18257
101 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
102 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
103 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
104 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
105 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
106 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
107 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
108 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
109 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
110 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
111 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
112 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
113 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
114 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
115 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
116 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
117 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
118 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
119 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
120 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
121 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
122 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
123 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
124 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
125 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
126 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
127 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
128 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
129 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
130 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
131 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
132 (vex_w_table): Replace terminals with MOD_TABLE entries for
133 most of mask instructions.
134
919b75f7
AM		 1352015-08-17 Alan Modra <amodra@gmail.com>
136
137 * cgen.sh: Trim trailing space from cgen output.
138 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
139 (print_dis_table): Likewise.
140 * opc2c.c (dump_lines): Likewise.
141 (orig_filename): Warning fix.
142 * ia64-asmtab.c: Regenerate.
143
4ab90a7a
AV		 1442015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
145
146 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
147 and higher with ARM instruction set will now mark the 26-bit
148 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
149 (arm_opcodes): Fix for unpredictable nop being recognized as a
150 teq.
151
40fc1451
SD		 1522015-08-12 Simon Dardis <simon.dardis@imgtec.com>
153
154 * micromips-opc.c (micromips_opcodes): Re-order table so that move
155 based on 'or' is first.
156 * mips-opc.c (mips_builtin_opcodes): Ditto.
157
922c5db5
NC		 1582015-08-11 Nick Clifton <nickc@redhat.com>
159
160 PR 18800
161 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
162 instruction.
163
75fb7498
RS		 1642015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
165
166 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
167
36aed29d
AP		 1682015-08-07 Amit Pawar <Amit.Pawar@amd.com>
169
170 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
171 * i386-init.h: Regenerated.
172
a8484f96
L		 1732015-07-30 H.J. Lu <hongjiu.lu@intel.com>
174
175 PR binutils/13571
176 * i386-dis.c (MOD_0FC3): New.
177 (PREFIX_0FC3): Renamed to ...
178 (PREFIX_MOD_0_0FC3): This.
179 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
180 (prefix_table): Replace Ma with Ev on movntiS.
181 (mod_table): Add MOD_0FC3.
182
37a42ee9
L		 1832015-07-27 H.J. Lu <hongjiu.lu@intel.com>
184
185 * configure: Regenerated.
186
070fe95d
AM		 1872015-07-23 Alan Modra <amodra@gmail.com>
188
189 PR 18708
190 * i386-dis.c (get64): Avoid signed integer overflow.
191
20c2a615
L		 1922015-07-22 Alexander Fomin <alexander.fomin@intel.com>
193
194 PR binutils/18631
195 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
196 "EXEvexHalfBcstXmmq" for the second operand.
197 (EVEX_W_0F79_P_2): Likewise.
198 (EVEX_W_0F7A_P_2): Likewise.
199 (EVEX_W_0F7B_P_2): Likewise.
200
6f1c2142
AM		 2012015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
202
203 * arm-dis.c (print_insn_coprocessor): Added support for quarter
204 float bitfield format.
205 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
206 quarter float bitfield format.
207
8a643cc3
L		 2082015-07-14 H.J. Lu <hongjiu.lu@intel.com>
209
210 * configure: Regenerated.
211
ef5a96d5
AM		 2122015-07-03 Alan Modra <amodra@gmail.com>
213
214 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
215 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
216 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
217
c8c8175b
SL		 2182015-07-01 Sandra Loosemore <sandra@codesourcery.com>
219 Cesar Philippidis <cesar@codesourcery.com>
220
221 * nios2-dis.c (nios2_extract_opcode): New.
222 (nios2_disassembler_state): New.
223 (nios2_find_opcode_hash): Use mach parameter to select correct
224 disassembler state.
225 (nios2_print_insn_arg): Extend to support new R2 argument letters
226 and formats.
227 (print_insn_nios2): Check for 16-bit instruction at end of memory.
228 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
229 (NIOS2_NUM_OPCODES): Rename to...
230 (NIOS2_NUM_R1_OPCODES): This.
231 (nios2_r2_opcodes): New.
232 (NIOS2_NUM_R2_OPCODES): New.
233 (nios2_num_r2_opcodes): New.
234 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
235 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
236 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
237 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
238 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
239
9916071f
AP		 2402015-06-30 Amit Pawar <Amit.Pawar@amd.com>
241
242 * i386-dis.c (OP_Mwaitx): New.
243 (rm_table): Add monitorx/mwaitx.
244 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
245 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
246 (operand_type_init): Add CpuMWAITX.
247 * i386-opc.h (CpuMWAITX): New.
248 (i386_cpu_flags): Add cpumwaitx.
249 * i386-opc.tbl: Add monitorx and mwaitx.
250 * i386-init.h: Regenerated.
251 * i386-tbl.h: Likewise.
252
7b934113
PB		 2532015-06-22 Peter Bergner <bergner@vnet.ibm.com>
254
255 * ppc-opc.c (insert_ls): Test for invalid LS operands.
256 (insert_esync): New function.
257 (LS, WC): Use insert_ls.
258 (ESYNC): Use insert_esync.
259
bdc4de1b
NC		 2602015-06-22 Nick Clifton <nickc@redhat.com>
261
262 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
263 requested region lies beyond it.
264 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
265 looking for 32-bit insns.
266 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
267 data.
268 * sh-dis.c (print_insn_sh): Likewise.
269 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
270 blocks of instructions.
271 * vax-dis.c (print_insn_vax): Check that the requested address
272 does not clash with the stop_vma.
273
11a0cf2e
PB		 2742015-06-19 Peter Bergner <bergner@vnet.ibm.com>
275
070fe95d 276 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 277 * ppc-opc.c (FXM4): Add non-zero optional value.
278 (TBR): Likewise.
279 (SXL): Likewise.
280 (insert_fxm): Handle new default operand value.
281 (extract_fxm): Likewise.
282 (insert_tbr): Likewise.
283 (extract_tbr): Likewise.
284
bdfa8b95
MW		 2852015-06-16 Matthew Wahab <matthew.wahab@arm.com>
286
287 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
288
24b4cf66
SN		 2892015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
290
291 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
292
99a2c561
PB		 2932015-06-12 Peter Bergner <bergner@vnet.ibm.com>
294
295 * ppc-opc.c: Add comment accidentally removed by old commit.
296 (MTMSRD_L): Delete.
297
40f77f82
AM		 2982015-06-04 Peter Bergner <bergner@vnet.ibm.com>
299
300 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
301
13be46a2
NC		 3022015-06-04 Nick Clifton <nickc@redhat.com>
303
304 PR 18474
305 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
306
ddfded2f
MW		 3072015-06-02 Matthew Wahab <matthew.wahab@arm.com>
308
309 * arm-dis.c (arm_opcodes): Add "setpan".
310 (thumb_opcodes): Add "setpan".
311
1af1dd51
MW		 3122015-06-02 Matthew Wahab <matthew.wahab@arm.com>
313
314 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
315 macros.
316
9e1f0fa7
MW		 3172015-06-02 Matthew Wahab <matthew.wahab@arm.com>
318
319 * aarch64-tbl.h (aarch64_feature_rdma): New.
320 (RDMA): New.
321 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
322 * aarch64-asm-2.c: Regenerate.
323 * aarch64-dis-2.c: Regenerate.
324 * aarch64-opc-2.c: Regenerate.
325
290806fd
MW		 3262015-06-02 Matthew Wahab <matthew.wahab@arm.com>
327
328 * aarch64-tbl.h (aarch64_feature_lor): New.
329 (LOR): New.
330 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
331 "stllrb", "stllrh".
332 * aarch64-asm-2.c: Regenerate.
333 * aarch64-dis-2.c: Regenerate.
334 * aarch64-opc-2.c: Regenerate.
335
f21cce2c
MW		 3362015-06-01 Matthew Wahab <matthew.wahab@arm.com>
337
338 * aarch64-opc.c (F_ARCHEXT): New.
339 (aarch64_sys_regs): Add "pan".
340 (aarch64_sys_reg_supported_p): New.
341 (aarch64_pstatefields): Add "pan".
342 (aarch64_pstatefield_supported_p): New.
343
d194d186
JB		 3442015-06-01 Jan Beulich <jbeulich@suse.com>
345
346 * i386-tbl.h: Regenerate.
347
3a8547d2
JB		 3482015-06-01 Jan Beulich <jbeulich@suse.com>
349
350 * i386-dis.c (print_insn): Swap rounding mode specifier and
351 general purpose register in Intel mode.
352
015c54d5
JB		 3532015-06-01 Jan Beulich <jbeulich@suse.com>
354
355 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
356 * i386-tbl.h: Regenerate.
357
071f0063
L		 3582015-05-18 H.J. Lu <hongjiu.lu@intel.com>
359
360 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
361 * i386-init.h: Regenerated.
362
5db04b09
L		 3632015-05-15 H.J. Lu <hongjiu.lu@intel.com>
364
365 PR binutis/18386
366 * i386-dis.c: Add comments for '@'.
367 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
368 (enum x86_64_isa): New.
369 (isa64): Likewise.
370 (print_i386_disassembler_options): Add amd64 and intel64.
371 (print_insn): Handle amd64 and intel64.
372 (putop): Handle '@'.
373 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
374 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
375 * i386-opc.h (AMD64): New.
376 (CpuIntel64): Likewise.
377 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
378 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
379 Mark direct call/jmp without Disp16|Disp32 as Intel64.
380 * i386-init.h: Regenerated.
381 * i386-tbl.h: Likewise.
382
4bc0608a
PB		 3832015-05-14 Peter Bergner <bergner@vnet.ibm.com>
384
385 * ppc-opc.c (IH) New define.
386 (powerpc_opcodes) <wait>: Do not enable for POWER7.
387 <tlbie>: Add RS operand for POWER7.
388 <slbia>: Add IH operand for POWER6.
389
70cead07
L		 3902015-05-11 H.J. Lu <hongjiu.lu@intel.com>
391
392 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
393 direct branch.
394 (jmp): Likewise.
395 * i386-tbl.h: Regenerated.
396
7b6d09fb
L		 3972015-05-11 H.J. Lu <hongjiu.lu@intel.com>
398
399 * configure.ac: Support bfd_iamcu_arch.
400 * disassemble.c (disassembler): Support bfd_iamcu_arch.
401 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
402 CPU_IAMCU_COMPAT_FLAGS.
403 (cpu_flags): Add CpuIAMCU.
404 * i386-opc.h (CpuIAMCU): New.
405 (i386_cpu_flags): Add cpuiamcu.
406 * configure: Regenerated.
407 * i386-init.h: Likewise.
408 * i386-tbl.h: Likewise.
409
31955f99
L		 4102015-05-08 H.J. Lu <hongjiu.lu@intel.com>
411
412 PR binutis/18386
413 * i386-dis.c (X86_64_E8): New.
414 (X86_64_E9): Likewise.
415 Update comments on 'T', 'U', 'V'. Add comments for '^'.
416 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
417 (x86_64_table): Add X86_64_E8 and X86_64_E9.
418 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
419 (putop): Handle '^'.
420 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
421 REX_W.
422
0952813b
DD		 4232015-04-30 DJ Delorie <dj@redhat.com>
424
425 * disassemble.c (disassembler): Choose suitable disassembler based
426 on E_ABI.
427 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
428 it to decode mul/div insns.
429 * rl78-decode.c: Regenerate.
430 * rl78-dis.c (print_insn_rl78): Rename to...
431 (print_insn_rl78_common): ...this, take ISA parameter.
432 (print_insn_rl78): New.
433 (print_insn_rl78_g10): New.
434 (print_insn_rl78_g13): New.
435 (print_insn_rl78_g14): New.
436 (rl78_get_disassembler): New.
437
f9d3ecaa
NC		 4382015-04-29 Nick Clifton <nickc@redhat.com>
439
440 * po/fr.po: Updated French translation.
441
4fff86c5
PB		 4422015-04-27 Peter Bergner <bergner@vnet.ibm.com>
443
444 * ppc-opc.c (DCBT_EO): New define.
445 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
446 <lharx>: Likewise.
447 <stbcx.>: Likewise.
448 <sthcx.>: Likewise.
449 <waitrsv>: Do not enable for POWER7 and later.
450 <waitimpl>: Likewise.
451 <dcbt>: Default to the two operand form of the instruction for all
452 "old" cpus. For "new" cpus, use the operand ordering that matches
453 whether the cpu is server or embedded.
454 <dcbtst>: Likewise.
455
3b78cfe1
AK		 4562015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
457
458 * s390-opc.c: New instruction type VV0UU2.
459 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
460 and WFC.
461
04d824a4
JB		 4622015-04-23 Jan Beulich <jbeulich@suse.com>
463
464 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
465 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
466 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
467 (vfpclasspd, vfpclassps): Add %XZ.
468
09708981
L		 4692015-04-15 H.J. Lu <hongjiu.lu@intel.com>
470
471 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
472 (PREFIX_UD_REPZ): Likewise.
473 (PREFIX_UD_REPNZ): Likewise.
474 (PREFIX_UD_DATA): Likewise.
475 (PREFIX_UD_ADDR): Likewise.
476 (PREFIX_UD_LOCK): Likewise.
477
3888916d
L		 4782015-04-15 H.J. Lu <hongjiu.lu@intel.com>
479
480 * i386-dis.c (prefix_requirement): Removed.
481 (print_insn): Don't set prefix_requirement. Check
482 dp->prefix_requirement instead of prefix_requirement.
483
f24bcbaa
L		 4842015-04-15 H.J. Lu <hongjiu.lu@intel.com>
485
486 PR binutils/17898
487 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
488 (PREFIX_MOD_0_0FC7_REG_6): This.
489 (PREFIX_MOD_3_0FC7_REG_6): New.
490 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
491 (prefix_table): Replace PREFIX_0FC7_REG_6 with
492 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
493 PREFIX_MOD_3_0FC7_REG_7.
494 (mod_table): Replace PREFIX_0FC7_REG_6 with
495 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
496 PREFIX_MOD_3_0FC7_REG_7.
497
507bd325
L		 4982015-04-15 H.J. Lu <hongjiu.lu@intel.com>
499
500 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
501 (PREFIX_MANDATORY_REPNZ): Likewise.
502 (PREFIX_MANDATORY_DATA): Likewise.
503 (PREFIX_MANDATORY_ADDR): Likewise.
504 (PREFIX_MANDATORY_LOCK): Likewise.
505 (PREFIX_MANDATORY): Likewise.
506 (PREFIX_UD_SHIFT): Set to 8
507 (PREFIX_UD_REPZ): Updated.
508 (PREFIX_UD_REPNZ): Likewise.
509 (PREFIX_UD_DATA): Likewise.
510 (PREFIX_UD_ADDR): Likewise.
511 (PREFIX_UD_LOCK): Likewise.
512 (PREFIX_IGNORED_SHIFT): New.
513 (PREFIX_IGNORED_REPZ): Likewise.
514 (PREFIX_IGNORED_REPNZ): Likewise.
515 (PREFIX_IGNORED_DATA): Likewise.
516 (PREFIX_IGNORED_ADDR): Likewise.
517 (PREFIX_IGNORED_LOCK): Likewise.
518 (PREFIX_OPCODE): Likewise.
519 (PREFIX_IGNORED): Likewise.
520 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
521 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
522 (three_byte_table): Likewise.
523 (mod_table): Likewise.
524 (mandatory_prefix): Renamed to ...
525 (prefix_requirement): This.
526 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
527 Update PREFIX_90 entry.
528 (get_valid_dis386): Check prefix_requirement to see if a prefix
529 should be ignored.
530 (print_insn): Replace mandatory_prefix with prefix_requirement.
531
f0fba320
RL		 5322015-04-15 Renlin Li <renlin.li@arm.com>
533
534 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
535 use it for ssat and ssat16.
536 (print_insn_thumb32): Add handle case for 'D' control code.
537
bf890a93
IT		 5382015-04-06 Ilya Tocar <ilya.tocar@intel.com>
539 H.J. Lu <hongjiu.lu@intel.com>
540
541 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
542 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
543 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
544 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
545 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
546 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
547 Fill prefix_requirement field.
548 (struct dis386): Add prefix_requirement field.
549 (dis386): Fill prefix_requirement field.
550 (dis386_twobyte): Ditto.
551 (twobyte_has_mandatory_prefix_: Remove.
552 (reg_table): Fill prefix_requirement field.
553 (prefix_table): Ditto.
554 (x86_64_table): Ditto.
555 (three_byte_table): Ditto.
556 (xop_table): Ditto.
557 (vex_table): Ditto.
558 (vex_len_table): Ditto.
559 (vex_w_table): Ditto.
560 (mod_table): Ditto.
561 (bad_opcode): Ditto.
562 (print_insn): Use prefix_requirement.
563 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
564 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
565 (float_reg): Ditto.
566
2f783c1f
MF		 5672015-03-30 Mike Frysinger <vapier@gentoo.org>
568
569 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
570
b9d94d62
L		 5712015-03-29 H.J. Lu <hongjiu.lu@intel.com>
572
573 * Makefile.in: Regenerated.
574
27c49e9a
AB		 5752015-03-25 Anton Blanchard <anton@samba.org>
576
577 * ppc-dis.c (disassemble_init_powerpc): Only initialise
578 powerpc_opcd_indices and vle_opcd_indices once.
579
c4e676f1
AB		 5802015-03-25 Anton Blanchard <anton@samba.org>
581
582 * ppc-opc.c (powerpc_opcodes): Add slbfee.
583
823d2571
TG		 5842015-03-24 Terry Guo <terry.guo@arm.com>
585
586 * arm-dis.c (opcode32): Updated to use new arm feature struct.
587 (opcode16): Likewise.
588 (coprocessor_opcodes): Replace bit with feature struct.
589 (neon_opcodes): Likewise.
590 (arm_opcodes): Likewise.
591 (thumb_opcodes): Likewise.
592 (thumb32_opcodes): Likewise.
593 (print_insn_coprocessor): Likewise.
594 (print_insn_arm): Likewise.
595 (select_arm_features): Follow new feature struct.
596
029f3522
GG		 5972015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
598
599 * i386-dis.c (rm_table): Add clzero.
600 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
601 Add CPU_CLZERO_FLAGS.
602 (cpu_flags): Add CpuCLZERO.
603 * i386-opc.h: Add CpuCLZERO.
604 * i386-opc.tbl: Add clzero.
605 * i386-init.h: Re-generated.
606 * i386-tbl.h: Re-generated.
607
6914869a
AB		 6082015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
609
610 * mips-opc.c (decode_mips_operand): Fix constraint issues
611 with u and y operands.
612
21e20815
AB		 6132015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
614
615 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
616
6b1d7593
AK		 6172015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
618
619 * s390-opc.c: Add new IBM z13 instructions.
620 * s390-opc.txt: Likewise.
621
c8f89a34
JW		 6222015-03-10 Renlin Li <renlin.li@arm.com>
623
624 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
625 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
626 related alias.
627 * aarch64-asm-2.c: Regenerate.
628 * aarch64-dis-2.c: Likewise.
629 * aarch64-opc-2.c: Likewise.
630
d8282f0e
JW		 6312015-03-03 Jiong Wang <jiong.wang@arm.com>
632
633 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
634
ac994365
OE		 6352015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
636
637 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
638 arch_sh_up.
639 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
640 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
641
fd63f640
V		 6422015-02-23 Vinay <Vinay.G@kpit.com>
643
644 * rl78-decode.opc (MOV): Added space between two operands for
645 'mov' instruction in index addressing mode.
646 * rl78-decode.c: Regenerate.
647
f63c1776
PA		 6482015-02-19 Pedro Alves <palves@redhat.com>
649
650 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
651
07774fcc
PA		 6522015-02-10 Pedro Alves <palves@redhat.com>
653 Tom Tromey <tromey@redhat.com>
654
655 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
656 microblaze_and, microblaze_xor.
657 * microblaze-opc.h (opcodes): Adjust.
658
3f8107ab
AM		 6592015-01-28 James Bowman <james.bowman@ftdichip.com>
660
661 * Makefile.am: Add FT32 files.
662 * configure.ac: Handle FT32.
663 * disassemble.c (disassembler): Call print_insn_ft32.
664 * ft32-dis.c: New file.
665 * ft32-opc.c: New file.
666 * Makefile.in: Regenerate.
667 * configure: Regenerate.
668 * po/POTFILES.in: Regenerate.
669
e5fe4957
KLC		 6702015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
671
672 * nds32-asm.c (keyword_sr): Add new system registers.
673
1e2e8c52
AK		 6742015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
675
676 * s390-dis.c (s390_extract_operand): Support vector register
677 operands.
678 (s390_print_insn_with_opcode): Support new operands types and add
679 new handling of optional operands.
680 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
681 and include opcode/s390.h instead.
682 (struct op_struct): New field `flags'.
683 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
684 (dumpTable): Dump flags.
685 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
686 string.
687 * s390-opc.c: Add new operands types, instruction formats, and
688 instruction masks.
689 (s390_opformats): Add new formats for .insn.
690 * s390-opc.txt: Add new instructions.
691
b90efa5b 6922015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 693
b90efa5b 694 Update year range in copyright notice of all files.
bffb6004 695
b90efa5b 696For older changes see ChangeLog-2014
252b5132 697\f
b90efa5b 698Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 699
700Copying and distribution of this file, with or without modification,
701are permitted in any medium without royalty provided the copyright
702notice and this notice are preserved.
703
252b5132 704Local Variables:
2f6d2f85
NC		 705mode: change-log
706left-margin: 8
707fill-column: 74
252b5132
RH		 708version-control: never
709End:
GDB Binutils - Deliverables
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