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1437d063
PB		 12017-03-08 Peter Bergner <bergner@vnet.ibm.com>
2
3 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
4
603555e5
L		 52017-03-06 H.J. Lu <hongjiu.lu@intel.com>
6
7 * i386-dis.c (REG_0F1E_MOD_3): New enum.
8 (MOD_0F1E_PREFIX_1): Likewise.
9 (MOD_0F38F5_PREFIX_2): Likewise.
10 (MOD_0F38F6_PREFIX_0): Likewise.
11 (RM_0F1E_MOD_3_REG_7): Likewise.
12 (PREFIX_MOD_0_0F01_REG_5): Likewise.
13 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
14 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
15 (PREFIX_0F1E): Likewise.
16 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
17 (PREFIX_0F38F5): Likewise.
18 (dis386_twobyte): Use PREFIX_0F1E.
19 (reg_table): Add REG_0F1E_MOD_3.
20 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
21 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
22 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
23 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
24 (three_byte_table): Use PREFIX_0F38F5.
25 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
26 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
27 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
28 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
29 PREFIX_MOD_3_0F01_REG_5_RM_2.
30 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
31 (cpu_flags): Add CpuCET.
32 * i386-opc.h (CpuCET): New enum.
33 (CpuUnused): Commented out.
34 (i386_cpu_flags): Add cpucet.
35 * i386-opc.tbl: Add Intel CET instructions.
36 * i386-init.h: Regenerated.
37 * i386-tbl.h: Likewise.
38
73f07bff
AM		 392017-03-06 Alan Modra <amodra@gmail.com>
40
41 PR 21124
42 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
43 (extract_raq, extract_ras, extract_rbx): New functions.
44 (powerpc_operands): Use opposite corresponding insert function.
45 (Q_MASK): Define.
46 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
47 register restriction.
48
65b48a81
PB		 492017-02-28 Peter Bergner <bergner@vnet.ibm.com>
50
51 * disassemble.c Include "safe-ctype.h".
52 (disassemble_init_for_target): Handle s390 init.
53 (remove_whitespace_and_extra_commas): New function.
54 (disassembler_options_cmp): Likewise.
55 * arm-dis.c: Include "libiberty.h".
56 (NUM_ELEM): Delete.
57 (regnames): Use long disassembler style names.
58 Add force-thumb and no-force-thumb options.
59 (NUM_ARM_REGNAMES): Rename from this...
60 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
61 (get_arm_regname_num_options): Delete.
62 (set_arm_regname_option): Likewise.
63 (get_arm_regnames): Likewise.
64 (parse_disassembler_options): Likewise.
65 (parse_arm_disassembler_option): Rename from this...
66 (parse_arm_disassembler_options): ...to this. Make static.
67 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
68 (print_insn): Use parse_arm_disassembler_options.
69 (disassembler_options_arm): New function.
70 (print_arm_disassembler_options): Handle updated regnames.
71 * ppc-dis.c: Include "libiberty.h".
72 (ppc_opts): Add "32" and "64" entries.
73 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
74 (powerpc_init_dialect): Add break to switch statement.
75 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
76 (disassembler_options_powerpc): New function.
77 (print_ppc_disassembler_options): Use ARRAY_SIZE.
78 Remove printing of "32" and "64".
79 * s390-dis.c: Include "libiberty.h".
80 (init_flag): Remove unneeded variable.
81 (struct s390_options_t): New structure type.
82 (options): New structure.
83 (init_disasm): Rename from this...
84 (disassemble_init_s390): ...to this. Add initializations for
85 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
86 (print_insn_s390): Delete call to init_disasm.
87 (disassembler_options_s390): New function.
88 (print_s390_disassembler_options): Print using information from
89 struct 'options'.
90 * po/opcodes.pot: Regenerate.
91
15c7c1d8
JB		 922017-02-28 Jan Beulich <jbeulich@suse.com>
93
94 * i386-dis.c (PCMPESTR_Fixup): New.
95 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
96 (prefix_table): Use PCMPESTR_Fixup.
97 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
98 PCMPESTR_Fixup.
99 (vex_w_table): Delete VPCMPESTR{I,M} entries.
100 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
101 Split 64-bit and non-64-bit variants.
102 * opcodes/i386-tbl.h: Re-generate.
103
582e12bf
RS		 1042017-02-24 Richard Sandiford <richard.sandiford@arm.com>
105
106 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
107 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
108 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
109 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
110 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
111 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
112 (OP_SVE_V_HSD): New macros.
113 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
114 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
115 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
116 (aarch64_opcode_table): Add new SVE instructions.
117 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
118 for rotation operands. Add new SVE operands.
119 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
120 (ins_sve_quad_index): Likewise.
121 (ins_imm_rotate): Split into...
122 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
123 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
124 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
125 functions.
126 (aarch64_ins_sve_addr_ri_s4): New function.
127 (aarch64_ins_sve_quad_index): Likewise.
128 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
129 * aarch64-asm-2.c: Regenerate.
130 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
131 (ext_sve_quad_index): Likewise.
132 (ext_imm_rotate): Split into...
133 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
134 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
135 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
136 functions.
137 (aarch64_ext_sve_addr_ri_s4): New function.
138 (aarch64_ext_sve_quad_index): Likewise.
139 (aarch64_ext_sve_index): Allow quad indices.
140 (do_misc_decoding): Likewise.
141 * aarch64-dis-2.c: Regenerate.
142 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
143 aarch64_field_kinds.
144 (OPD_F_OD_MASK): Widen by one bit.
145 (OPD_F_NO_ZR): Bump accordingly.
146 (get_operand_field_width): New function.
147 * aarch64-opc.c (fields): Add new SVE fields.
148 (operand_general_constraint_met_p): Handle new SVE operands.
149 (aarch64_print_operand): Likewise.
150 * aarch64-opc-2.c: Regenerate.
151
f482d304
RS		 1522017-02-24 Richard Sandiford <richard.sandiford@arm.com>
153
154 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
155 (aarch64_feature_compnum): ...this.
156 (SIMD_V8_3): Replace with...
157 (COMPNUM): ...this.
158 (CNUM_INSN): New macro.
159 (aarch64_opcode_table): Use it for the complex number instructions.
160
7db2c588
JB		 1612017-02-24 Jan Beulich <jbeulich@suse.com>
162
163 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
164
1e9d41d4
SL		 1652017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
166
167 Add support for associating SPARC ASIs with an architecture level.
168 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
169 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
170 decoding of SPARC ASIs.
171
53c4d625
JB		 1722017-02-23 Jan Beulich <jbeulich@suse.com>
173
174 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
175 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
176
11648de5
JB		 1772017-02-21 Jan Beulich <jbeulich@suse.com>
178
179 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
180 1 (instead of to itself). Correct typo.
181
f98d33be
AW		 1822017-02-14 Andrew Waterman <andrew@sifive.com>
183
184 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
185 pseudoinstructions.
186
773fb663
RS		 1872017-02-15 Richard Sandiford <richard.sandiford@arm.com>
188
189 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
190 (aarch64_sys_reg_supported_p): Handle them.
191
cc07cda6
CZ		 1922017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
193
194 * arc-opc.c (UIMM6_20R): Define.
195 (SIMM12_20): Use above.
196 (SIMM12_20R): Define.
197 (SIMM3_5_S): Use above.
198 (UIMM7_A32_11R_S): Define.
199 (UIMM7_9_S): Use above.
200 (UIMM3_13R_S): Define.
201 (SIMM11_A32_7_S): Use above.
202 (SIMM9_8R): Define.
203 (UIMM10_A32_8_S): Use above.
204 (UIMM8_8R_S): Define.
205 (W6): Use above.
206 (arc_relax_opcodes): Use all above defines.
207
66a5a740
VG		 2082017-02-15 Vineet Gupta <vgupta@synopsys.com>
209
210 * arc-regs.h: Distinguish some of the registers different on
211 ARC700 and HS38 cpus.
212
7e0de605
AM		 2132017-02-14 Alan Modra <amodra@gmail.com>
214
215 PR 21118
216 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
217 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
218
54064fdb
AM		 2192017-02-11 Stafford Horne <shorne@gmail.com>
220 Alan Modra <amodra@gmail.com>
221
222 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
223 Use insn_bytes_value and insn_int_value directly instead. Don't
224 free allocated memory until function exit.
225
dce75bf9
NP		 2262017-02-10 Nicholas Piggin <npiggin@gmail.com>
227
228 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
229
1b7e3d2f
NC		 2302017-02-03 Nick Clifton <nickc@redhat.com>
231
232 PR 21096
233 * aarch64-opc.c (print_register_list): Ensure that the register
234 list index will fir into the tb buffer.
235 (print_register_offset_address): Likewise.
236 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
237
8ec5cf65
AD		 2382017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
239
240 PR 21056
241 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
242 instructions when the previous fetch packet ends with a 32-bit
243 instruction.
244
a1aa5e81
DD		 2452017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
246
247 * pru-opc.c: Remove vague reference to a future GDB port.
248
add3afb2
NC		 2492017-01-20 Nick Clifton <nickc@redhat.com>
250
251 * po/ga.po: Updated Irish translation.
252
c13a63b0
SN		 2532017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
254
255 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
256
9608051a
YQ		 2572017-01-13 Yao Qi <yao.qi@linaro.org>
258
259 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
260 if FETCH_DATA returns 0.
261 (m68k_scan_mask): Likewise.
262 (print_insn_m68k): Update code to handle -1 return value.
263
f622ea96
YQ		 2642017-01-13 Yao Qi <yao.qi@linaro.org>
265
266 * m68k-dis.c (enum print_insn_arg_error): New.
267 (NEXTBYTE): Replace -3 with
268 PRINT_INSN_ARG_MEMORY_ERROR.
269 (NEXTULONG): Likewise.
270 (NEXTSINGLE): Likewise.
271 (NEXTDOUBLE): Likewise.
272 (NEXTDOUBLE): Likewise.
273 (NEXTPACKED): Likewise.
274 (FETCH_ARG): Likewise.
275 (FETCH_DATA): Update comments.
276 (print_insn_arg): Update comments. Replace magic numbers with
277 enum.
278 (match_insn_m68k): Likewise.
279
620214f7
IT		 2802017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
281
282 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
283 * i386-dis-evex.h (evex_table): Updated.
284 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
285 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
286 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
287 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
288 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
289 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
290 * i386-init.h: Regenerate.
291 * i386-tbl.h: Ditto.
292
d95014a2
YQ		 2932017-01-12 Yao Qi <yao.qi@linaro.org>
294
295 * msp430-dis.c (msp430_singleoperand): Return -1 if
296 msp430dis_opcode_signed returns false.
297 (msp430_doubleoperand): Likewise.
298 (msp430_branchinstr): Return -1 if
299 msp430dis_opcode_unsigned returns false.
300 (msp430x_calla_instr): Likewise.
301 (print_insn_msp430): Likewise.
302
0ae60c3e
NC		 3032017-01-05 Nick Clifton <nickc@redhat.com>
304
305 PR 20946
306 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
307 could not be matched.
308 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
309 NULL.
310
d74d4880
SN		 3112017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
312
313 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
314 (aarch64_opcode_table): Use RCPC_INSN.
315
cc917fd9
KC		 3162017-01-03 Kito Cheng <kito.cheng@gmail.com>
317
318 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
319 extension.
320 * riscv-opcodes/all-opcodes: Likewise.
321
b52d3cfc
DP		 3222017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
323
324 * riscv-dis.c (print_insn_args): Add fall through comment.
325
f90c58d5
NC		 3262017-01-03 Nick Clifton <nickc@redhat.com>
327
328 * po/sr.po: New Serbian translation.
329 * configure.ac (ALL_LINGUAS): Add sr.
330 * configure: Regenerate.
331
f47b0d4a
AM		 3322017-01-02 Alan Modra <amodra@gmail.com>
333
334 * epiphany-desc.h: Regenerate.
335 * epiphany-opc.h: Regenerate.
336 * fr30-desc.h: Regenerate.
337 * fr30-opc.h: Regenerate.
338 * frv-desc.h: Regenerate.
339 * frv-opc.h: Regenerate.
340 * ip2k-desc.h: Regenerate.
341 * ip2k-opc.h: Regenerate.
342 * iq2000-desc.h: Regenerate.
343 * iq2000-opc.h: Regenerate.
344 * lm32-desc.h: Regenerate.
345 * lm32-opc.h: Regenerate.
346 * m32c-desc.h: Regenerate.
347 * m32c-opc.h: Regenerate.
348 * m32r-desc.h: Regenerate.
349 * m32r-opc.h: Regenerate.
350 * mep-desc.h: Regenerate.
351 * mep-opc.h: Regenerate.
352 * mt-desc.h: Regenerate.
353 * mt-opc.h: Regenerate.
354 * or1k-desc.h: Regenerate.
355 * or1k-opc.h: Regenerate.
356 * xc16x-desc.h: Regenerate.
357 * xc16x-opc.h: Regenerate.
358 * xstormy16-desc.h: Regenerate.
359 * xstormy16-opc.h: Regenerate.
360
2571583a
AM		 3612017-01-02 Alan Modra <amodra@gmail.com>
362
363 Update year range in copyright notice of all files.
364
5c1ad6b5 365For older changes see ChangeLog-2016
3499769a 366\f
5c1ad6b5 367Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 368
369Copying and distribution of this file, with or without modification,
370are permitted in any medium without royalty provided the copyright
371notice and this notice are preserved.
372
373Local Variables:
374mode: change-log
375left-margin: 8
376fill-column: 74
377version-control: never
378End:
GDB Binutils - Deliverables
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