Fix parseing functions to return an error message if the parse failed
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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12006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
2
3 * xc16x-asm.c: Regenerate.
4 * xc16x-dis.c: Regenerate.
5 * xc16x-ibld.c: Regenerate.
6
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72006-02-27 Carlos O'Donell <carlos@codesourcery.com>
8
9 * po/Make-in: Add html target.
10
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112006-02-27 H.J. Lu <hongjiu.lu@intel.com>
12
13 * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
14 Intel Merom New Instructions.
15 (THREE_BYTE_0): Likewise.
16 (THREE_BYTE_1): Likewise.
17 (three_byte_table): Likewise.
18 (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
19 THREE_BYTE_1 for entry 0x3a.
20 (twobyte_has_modrm): Updated.
21 (twobyte_uses_SSE_prefix): Likewise.
22 (print_insn): Handle 3-byte opcodes used by Intel Merom New
23 Instructions.
24
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252006-02-24 David S. Miller <davem@sunset.davemloft.net>
26
27 * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
28 (v9_hpriv_reg_names): New table.
29 (print_insn_sparc): Allow values up to 16 for '?' and '!'.
30 New cases '$' and '%' for read/write hyperprivileged register.
31 * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
32 window handling and rdhpr/wrhpr instructions.
33
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342006-02-24 DJ Delorie <dj@redhat.com>
35
36 * m32c-desc.c: Regenerate with linker relaxation attributes.
37 * m32c-desc.h: Likewise.
38 * m32c-dis.c: Likewise.
39 * m32c-opc.c: Likewise.
40
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412006-02-24 Paul Brook <paul@codesourcery.com>
42
43 * arm-dis.c (arm_opcodes): Add V7 instructions.
44 (thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
45 (print_arm_address): New function.
46 (print_insn_arm): Use it. Add 'P' and 'U' cases.
47 (psr_name): New function.
48 (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
49
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502006-02-23 H.J. Lu <hongjiu.lu@intel.com>
51
52 * ia64-opc-i.c (bXc): New.
53 (mXc): Likewise.
54 (OpX2TaTbYaXcC): Likewise.
55 (TF). Likewise.
56 (TFCM). Likewise.
57 (ia64_opcodes_i): Add instructions for tf.
58
59 * ia64-opc.h (IMMU5b): New.
60
61 * ia64-asmtab.c: Regenerated.
62
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632006-02-23 H.J. Lu <hongjiu.lu@intel.com>
64
65 * ia64-gen.c: Update copyright years.
66 * ia64-opc-b.c: Likewise.
67
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682006-02-22 H.J. Lu <hongjiu.lu@intel.com>
69
70 * ia64-gen.c (lookup_regindex): Handle ".vm".
71 (print_dependency_table): Handle '\"'.
72
73 * ia64-ic.tbl: Updated from SDM 2.2.
74 * ia64-raw.tbl: Likewise.
75 * ia64-waw.tbl: Likewise.
76 * ia64-asmtab.c: Regenerated.
77
78 * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
79
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802006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
81 Anil Paranjape <anilp1@kpitcummins.com>
82 Shilin Shakti <shilins@kpitcummins.com>
83
84 * xc16x-desc.h: New file
85 * xc16x-desc.c: New file
86 * xc16x-opc.h: New file
87 * xc16x-opc.c: New file
88 * xc16x-ibld.c: New file
89 * xc16x-asm.c: New file
90 * xc16x-dis.c: New file
91 * Makefile.am: Entries for xc16x
92 * Makefile.in: Regenerate
93 * cofigure.in: Add xc16x target information.
94 * configure: Regenerate.
95 * disassemble.c: Add xc16x target information.
96
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972006-02-11 H.J. Lu <hongjiu.lu@intel.com>
98
99 * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
100 moves.
101
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1022006-02-11 H.J. Lu <hongjiu.lu@intel.com>
103
104 * i386-dis.c ('Z'): Add a new macro.
105 (dis386_twobyte): Use "movZ" for control register moves.
106
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1072006-02-10 Nick Clifton <nickc@redhat.com>
108
109 * iq2000-asm.c: Regenerate.
110
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1112006-02-07 Nathan Sidwell <nathan@codesourcery.com>
112
113 * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
114
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1152006-01-26 David Ung <davidu@mips.com>
116
117 * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
118 ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
119 floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
120 nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
121 rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
122
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1232006-01-18 Arnold Metselaar <arnoldm@sourceware.org>
124
125 * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
126 ld_d_r, pref_xd_cb): Use signed char to hold data to be
127 disassembled.
128 * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
129 buffer overflows when disassembling instructions like
130 ld (ix+123),0x23
131 * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
132 operand, if the offset is negative.
133
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1342006-01-17 Arnold Metselaar <arnoldm@sourceware.org>
135
136 * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
137 unsigned char to hold data to be disassembled.
138
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1392006-01-17 Andreas Schwab <schwab@suse.de>
140
141 PR binutils/1486
142 * disassemble.c (disassemble_init_for_target): Set
143 disassembler_needs_relocs for bfd_arch_arm.
144
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1452006-01-16 Paul Brook <paul@codesourcery.com>
146
e88d958a 147 * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
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148 f?add?, and f?sub? instructions.
149
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1502006-01-16 Nick Clifton <nickc@redhat.com>
151
152 * po/zh_CN.po: New Chinese (simplified) translation.
153 * configure.in (ALL_LINGUAS): Add "zh_CH".
154 * configure: Regenerate.
155
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1562006-01-05 Paul Brook <paul@codesourcery.com>
157
158 * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
159
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1602006-01-06 DJ Delorie <dj@redhat.com>
161
162 * m32c-desc.c: Regenerate.
163 * m32c-opc.c: Regenerate.
164 * m32c-opc.h: Regenerate.
165
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1662006-01-03 DJ Delorie <dj@redhat.com>
167
168 * cgen-ibld.in (extract_normal): Avoid memory range errors.
169 * m32c-ibld.c: Regenerated.
170
e88d958a 171For older changes see ChangeLog-2005
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172\f
173Local Variables:
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174mode: change-log
175left-margin: 8
176fill-column: 74
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177version-control: never
178End:
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