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Set TYPE_LENGTH on a variant part
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
43135d3b
JW		 12018-08-30 Kito Cheng <kito@andestech.com>
2
3 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
4 riscv_opcode.xlen_requirement.
5 * riscv-opc.c (riscv_opcodes): Update for struct change.
6
df28970f
MA		 72018-08-29 Martin Aberg <maberg@gaisler.com>
8
9 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
10 psr (PWRPSR) instruction.
11
9108bc33
CX		 122018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
13
14 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
15
bd782c07
CX		 162018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
17
18 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
19
ac8cb70f
CX		 202018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
21
22 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
23 loongson3a as an alias of gs464 for compatibility.
24 * mips-opc.c (mips_opcodes): Change Comments.
25
a693765e
CX		 262018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
27
28 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
29 option.
30 (print_mips_disassembler_options): Document -M loongson-ext.
31 * mips-opc.c (LEXT2): New macro.
32 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
33
bdc6c06e
CX		 342018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
35
36 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
37 descriptors.
38 (parse_mips_ase_option): Handle -M loongson-ext option.
39 (print_mips_disassembler_options): Document -M loongson-ext.
40 * mips-opc.c (IL3A): Delete.
41 * mips-opc.c (LEXT): New macro.
42 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
43 instructions.
44
716c08de
CX		 452018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
46
47 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
48 descriptors.
49 (parse_mips_ase_option): Handle -M loongson-cam option.
50 (print_mips_disassembler_options): Document -M loongson-cam.
51 * mips-opc.c (LCAM): New macro.
52 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
53 instructions.
54
9cf7e568
AM		 552018-08-21 Alan Modra <amodra@gmail.com>
56
57 * ppc-dis.c (operand_value_powerpc): Init "invalid".
58 (skip_optional_operands): Count optional operands, and update
59 ppc_optional_operand_value call.
60 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
61 (extract_vlensi): Likewise.
62 (extract_fxm): Return default value for missing optional operand.
63 (extract_ls, extract_raq, extract_tbr): Likewise.
64 (insert_sxl, extract_sxl): New functions.
65 (insert_esync, extract_esync): Remove Power9 handling and simplify.
66 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
67 flag and extra entry.
68 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
69 extract_sxl.
70
d203b41a 712018-08-20 Alan Modra <amodra@gmail.com>
f4107842 72
d203b41a 73 * sh-opc.h (MASK): Simplify.
f4107842 74
08a8fe2f 752018-08-18 John Darrington <john@darrington.wattle.id.au>
7ba3ba91 76
d203b41a
AM		 77 * s12z-dis.c (bm_decode): Deal with cases where the mode is
78 BM_RESERVED0 or BM_RESERVED1
08a8fe2f 79 (bm_rel_decode, bm_n_bytes): Ditto.
d203b41a 80
08a8fe2f 812018-08-18 John Darrington <john@darrington.wattle.id.au>
d203b41a
AM		 82
83 * s12z.h: Delete.
7ba3ba91 84
1bc60e56
L		 852018-08-14 H.J. Lu <hongjiu.lu@intel.com>
86
87 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
88 address with the addr32 prefix and without base nor index
89 registers.
90
d871f3f4
L		 912018-08-11 H.J. Lu <hongjiu.lu@intel.com>
92
93 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
94 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
95 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
96 (cpu_flags): Add CpuCMOV and CpuFXSR.
97 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
98 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
99 * i386-init.h: Regenerated.
100 * i386-tbl.h: Likewise.
101
b6523c37 1022018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
103
104 * arc-regs.h: Update auxiliary registers.
105
e968fc9b
JB		 1062018-08-06 Jan Beulich <jbeulich@suse.com>
107
108 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
109 (RegIP, RegIZ): Define.
110 * i386-reg.tbl: Adjust comments.
111 (rip): Use Qword instead of BaseIndex. Use RegIP.
112 (eip): Use Dword instead of BaseIndex. Use RegIP.
113 (riz): Add Qword. Use RegIZ.
114 (eiz): Add Dword. Use RegIZ.
115 * i386-tbl.h: Re-generate.
116
dbf8be89
JB		 1172018-08-03 Jan Beulich <jbeulich@suse.com>
118
119 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
120 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
121 vpmovzxdq, vpmovzxwd): Remove NoRex64.
122 * i386-tbl.h: Re-generate.
123
c48dadc9
JB		 1242018-08-03 Jan Beulich <jbeulich@suse.com>
125
126 * i386-gen.c (operand_types): Remove Mem field.
127 * i386-opc.h (union i386_operand_type): Remove mem field.
128 * i386-init.h, i386-tbl.h: Re-generate.
129
cb86a42a
AM		 1302018-08-01 Alan Modra <amodra@gmail.com>
131
132 * po/POTFILES.in: Regenerate.
133
07cc0450
NC		 1342018-07-31 Nick Clifton <nickc@redhat.com>
135
136 * po/sv.po: Updated Swedish translation.
137
1424ad86
JB		 1382018-07-31 Jan Beulich <jbeulich@suse.com>
139
140 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
141 * i386-init.h, i386-tbl.h: Re-generate.
142
ae2387fe
JB		 1432018-07-31 Jan Beulich <jbeulich@suse.com>
144
145 * i386-opc.h (ZEROING_MASKING) Rename to ...
146 (DYNAMIC_MASKING): ... this. Adjust comment.
147 * i386-opc.tbl (MaskingMorZ): Define.
148 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
149 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
150 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
151 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
152 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
153 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
154 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
155 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
156 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
157
6ff00b5e
JB		 1582018-07-31 Jan Beulich <jbeulich@suse.com>
159
160 * i386-opc.tbl: Use element rather than vector size for AVX512*
161 scatter/gather insns.
162 * i386-tbl.h: Re-generate.
163
e951d5ca
JB		 1642018-07-31 Jan Beulich <jbeulich@suse.com>
165
166 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
167 (cpu_flags): Drop CpuVREX.
168 * i386-opc.h (CpuVREX): Delete.
169 (union i386_cpu_flags): Remove cpuvrex.
170 * i386-init.h, i386-tbl.h: Re-generate.
171
eb41b248
JW		 1722018-07-30 Jim Wilson <jimw@sifive.com>
173
174 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
175 fields.
176 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
177
b8891f8d
AJ		 1782018-07-30 Andrew Jenner <andrew@codesourcery.com>
179
180 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
181 * Makefile.in: Regenerated.
182 * configure.ac: Add C-SKY.
183 * configure: Regenerated.
184 * csky-dis.c: New file.
185 * csky-opc.h: New file.
186 * disassemble.c (ARCH_csky): Define.
187 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
188 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
189
16065af1
AM		 1902018-07-27 Alan Modra <amodra@gmail.com>
191
192 * ppc-opc.c (insert_sprbat): Correct function parameter and
193 return type.
194 (extract_sprbat): Likewise, variable too.
195
fa758a70
AC		 1962018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
197 Alan Modra <amodra@gmail.com>
198
199 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
200 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
201 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
202 support disjointed BAT.
203 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
204 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
205 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
206
4a1b91ea
L		 2072018-07-25 H.J. Lu <hongjiu.lu@intel.com>
208 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
209
210 * i386-gen.c (adjust_broadcast_modifier): New function.
211 (process_i386_opcode_modifier): Add an argument for operands.
212 Adjust the Broadcast value based on operands.
213 (output_i386_opcode): Pass operand_types to
214 process_i386_opcode_modifier.
215 (process_i386_opcodes): Pass NULL as operands to
216 process_i386_opcode_modifier.
217 * i386-opc.h (BYTE_BROADCAST): New.
218 (WORD_BROADCAST): Likewise.
219 (DWORD_BROADCAST): Likewise.
220 (QWORD_BROADCAST): Likewise.
221 (i386_opcode_modifier): Expand broadcast to 3 bits.
222 * i386-tbl.h: Regenerated.
223
67ce483b
AM		 2242018-07-24 Alan Modra <amodra@gmail.com>
225
226 PR 23430
227 * or1k-desc.h: Regenerate.
228
4174bfff
JB		 2292018-07-24 Jan Beulich <jbeulich@suse.com>
230
231 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
232 vcvtusi2ss, and vcvtusi2sd.
233 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
234 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
235 * i386-tbl.h: Re-generate.
236
04e65276
CZ		 2372018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
238
239 * arc-opc.c (extract_w6): Fix extending the sign.
240
47e6f81c
CZ		 2412018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
242
243 * arc-tbl.h (vewt): Allow it for ARC EM family.
244
bb71536f
AM		 2452018-07-23 Alan Modra <amodra@gmail.com>
246
247 PR 23419
248 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
249 opcode variants for mtspr/mfspr encodings.
250
8095d2f7
CX		 2512018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
252 Maciej W. Rozycki <macro@mips.com>
253
254 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
255 loongson3a descriptors.
256 (parse_mips_ase_option): Handle -M loongson-mmi option.
257 (print_mips_disassembler_options): Document -M loongson-mmi.
258 * mips-opc.c (LMMI): New macro.
259 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
260 instructions.
261
5f32791e
JB		 2622018-07-19 Jan Beulich <jbeulich@suse.com>
263
264 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
265 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
266 IgnoreSize and [XYZ]MMword where applicable.
267 * i386-tbl.h: Re-generate.
268
625cbd7a
JB		 2692018-07-19 Jan Beulich <jbeulich@suse.com>
270
271 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
272 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
273 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
274 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
275 * i386-tbl.h: Re-generate.
276
86b15c32
JB		 2772018-07-19 Jan Beulich <jbeulich@suse.com>
278
279 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
280 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
281 VPCLMULQDQ templates into their respective AVX512VL counterparts
282 where possible, using Disp8ShiftVL and CheckRegSize instead of
283 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
284 * i386-tbl.h: Re-generate.
285
cf769ed5
JB		 2862018-07-19 Jan Beulich <jbeulich@suse.com>
287
288 * i386-opc.tbl: Fold AVX512DQ templates into their respective
289 AVX512VL counterparts where possible, using Disp8ShiftVL and
290 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
291 IgnoreSize) as appropriate.
292 * i386-tbl.h: Re-generate.
293
8282b7ad
JB		 2942018-07-19 Jan Beulich <jbeulich@suse.com>
295
296 * i386-opc.tbl: Fold AVX512BW templates into their respective
297 AVX512VL counterparts where possible, using Disp8ShiftVL and
298 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
299 IgnoreSize) as appropriate.
300 * i386-tbl.h: Re-generate.
301
755908cc
JB		 3022018-07-19 Jan Beulich <jbeulich@suse.com>
303
304 * i386-opc.tbl: Fold AVX512CD templates into their respective
305 AVX512VL counterparts where possible, using Disp8ShiftVL and
306 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
307 IgnoreSize) as appropriate.
308 * i386-tbl.h: Re-generate.
309
7091c612
JB		 3102018-07-19 Jan Beulich <jbeulich@suse.com>
311
312 * i386-opc.h (DISP8_SHIFT_VL): New.
313 * i386-opc.tbl (Disp8ShiftVL): Define.
314 (various): Fold AVX512VL templates into their respective
315 AVX512F counterparts where possible, using Disp8ShiftVL and
316 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
317 IgnoreSize) as appropriate.
318 * i386-tbl.h: Re-generate.
319
c30be56e
JB		 3202018-07-19 Jan Beulich <jbeulich@suse.com>
321
322 * Makefile.am: Change dependencies and rule for
323 $(srcdir)/i386-init.h.
324 * Makefile.in: Re-generate.
325 * i386-gen.c (process_i386_opcodes): New local variable
326 "marker". Drop opening of input file. Recognize marker and line
327 number directives.
328 * i386-opc.tbl (OPCODE_I386_H): Define.
329 (i386-opc.h): Include it.
330 (None): Undefine.
331
11a322db
L		 3322018-07-18 H.J. Lu <hongjiu.lu@intel.com>
333
334 PR gas/23418
335 * i386-opc.h (Byte): Update comments.
336 (Word): Likewise.
337 (Dword): Likewise.
338 (Fword): Likewise.
339 (Qword): Likewise.
340 (Tbyte): Likewise.
341 (Xmmword): Likewise.
342 (Ymmword): Likewise.
343 (Zmmword): Likewise.
344 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
345 vcvttps2uqq.
346 * i386-tbl.h: Regenerated.
347
cde3679e
NC		 3482018-07-12 Sudakshina Das <sudi.das@arm.com>
349
350 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
351 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
352 * aarch64-asm-2.c: Regenerate.
353 * aarch64-dis-2.c: Regenerate.
354 * aarch64-opc-2.c: Regenerate.
355
45a28947
TC		 3562018-07-12 Tamar Christina <tamar.christina@arm.com>
357
358 PR binutils/23192
359 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
360 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
361 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
362 sqdmulh, sqrdmulh): Use Em16.
363
c597cc3d
SD		 3642018-07-11 Sudakshina Das <sudi.das@arm.com>
365
366 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
367 csdb together with them.
368 (thumb32_opcodes): Likewise.
369
a79eaed6
JB		 3702018-07-11 Jan Beulich <jbeulich@suse.com>
371
372 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
373 requiring 32-bit registers as operands 2 and 3. Improve
374 comments.
375 (mwait, mwaitx): Fold templates. Improve comments.
376 OPERAND_TYPE_INOUTPORTREG.
377 * i386-tbl.h: Re-generate.
378
2fb5be8d
JB		 3792018-07-11 Jan Beulich <jbeulich@suse.com>
380
381 * i386-gen.c (operand_type_init): Remove
382 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
383 OPERAND_TYPE_INOUTPORTREG.
384 * i386-init.h: Re-generate.
385
7f5cad30
JB		 3862018-07-11 Jan Beulich <jbeulich@suse.com>
387
388 * i386-opc.tbl (wrssd, wrussd): Add Dword.
389 (wrssq, wrussq): Add Qword.
390 * i386-tbl.h: Re-generate.
391
f0a85b07
JB		 3922018-07-11 Jan Beulich <jbeulich@suse.com>
393
394 * i386-opc.h: Rename OTMax to OTNum.
395 (OTNumOfUints): Adjust calculation.
396 (OTUnused): Directly alias to OTNum.
397
9dcb0ba4
MR		 3982018-07-09 Maciej W. Rozycki <macro@mips.com>
399
400 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
401 `reg_xys'.
402 (lea_reg_xys): Likewise.
403 (print_insn_loop_primitive): Rename `reg' local variable to
404 `reg_dxy'.
405
f311ba7e
TC		 4062018-07-06 Tamar Christina <tamar.christina@arm.com>
407
408 PR binutils/23242
409 * aarch64-tbl.h (ldarh): Fix disassembly mask.
410
cba05feb
TC		 4112018-07-06 Tamar Christina <tamar.christina@arm.com>
412
413 PR binutils/23369
414 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
415 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
416
471b9d15
MR		 4172018-07-02 Maciej W. Rozycki <macro@mips.com>
418
419 PR tdep/8282
420 * mips-dis.c (mips_option_arg_t): New enumeration.
421 (mips_options): New variable.
422 (disassembler_options_mips): New function.
423 (print_mips_disassembler_options): Reimplement in terms of
424 `disassembler_options_mips'.
425 * arm-dis.c (disassembler_options_arm): Adapt to using the
426 `disasm_options_and_args_t' structure.
427 * ppc-dis.c (disassembler_options_powerpc): Likewise.
428 * s390-dis.c (disassembler_options_s390): Likewise.
429
c0c468d5
TP		 4302018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
431
432 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
433 expected result.
434 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
435 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
436 * testsuite/ld-arm/tls-longplt.d: Likewise.
437
369c9167
TC		 4382018-06-29 Tamar Christina <tamar.christina@arm.com>
439
440 PR binutils/23192
441 * aarch64-asm-2.c: Regenerate.
442 * aarch64-dis-2.c: Likewise.
443 * aarch64-opc-2.c: Likewise.
444 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
445 * aarch64-opc.c (operand_general_constraint_met_p,
446 aarch64_print_operand): Likewise.
447 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
448 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
449 fmlal2, fmlsl2.
450 (AARCH64_OPERANDS): Add Em2.
451
30aa1306
NC		 4522018-06-26 Nick Clifton <nickc@redhat.com>
453
454 * po/uk.po: Updated Ukranian translation.
455 * po/de.po: Updated German translation.
456 * po/pt_BR.po: Updated Brazilian Portuguese translation.
457
eca4b721
NC		 4582018-06-26 Nick Clifton <nickc@redhat.com>
459
460 * nfp-dis.c: Fix spelling mistake.
461
71300e2c
NC		 4622018-06-24 Nick Clifton <nickc@redhat.com>
463
464 * configure: Regenerate.
465 * po/opcodes.pot: Regenerate.
466
719d8288
NC		 4672018-06-24 Nick Clifton <nickc@redhat.com>
468
469 2.31 branch created.
470
514cd3a0
TC		 4712018-06-19 Tamar Christina <tamar.christina@arm.com>
472
473 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
474 * aarch64-asm-2.c: Regenerate.
475 * aarch64-dis-2.c: Likewise.
476
385e4d0f
MR		 4772018-06-21 Maciej W. Rozycki <macro@mips.com>
478
479 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
480 `-M ginv' option description.
481
160d1b3d
SH		 4822018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
483
484 PR gas/23305
485 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
486 la and lla.
487
d0ac1c44
SM		 4882018-06-19 Simon Marchi <simon.marchi@ericsson.com>
489
490 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
491 * configure.ac: Remove AC_PREREQ.
492 * Makefile.in: Re-generate.
493 * aclocal.m4: Re-generate.
494 * configure: Re-generate.
495
6f20c942
FS		 4962018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
497
498 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
499 mips64r6 descriptors.
500 (parse_mips_ase_option): Handle -Mginv option.
501 (print_mips_disassembler_options): Document -Mginv.
502 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
503 (GINV): New macro.
504 (mips_opcodes): Define ginvi and ginvt.
505
730c3174
SE		 5062018-06-13 Scott Egerton <scott.egerton@imgtec.com>
507 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
508
509 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
510 * mips-opc.c (CRC, CRC64): New macros.
511 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
512 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
513 crc32cd for CRC64.
514
cb366992
EB		 5152018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
516
517 PR 20319
518 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
519 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
520
ce72cd46
AM		 5212018-06-06 Alan Modra <amodra@gmail.com>
522
523 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
524 setjmp. Move init for some other vars later too.
525
4b8e28c7
MF		 5262018-06-04 Max Filippov <jcmvbkbc@gmail.com>
527
528 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
529 (dis_private): Add new fields for property section tracking.
530 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
531 (xtensa_instruction_fits): New functions.
532 (fetch_data): Bump minimal fetch size to 4.
533 (print_insn_xtensa): Make struct dis_private static.
534 Load and prepare property table on section change.
535 Don't disassemble literals. Don't disassemble instructions that
536 cross property table boundaries.
537
55e99962
L		 5382018-06-01 H.J. Lu <hongjiu.lu@intel.com>
539
540 * configure: Regenerated.
541
733bd0ab
JB		 5422018-06-01 Jan Beulich <jbeulich@suse.com>
543
544 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
545 * i386-tbl.h: Re-generate.
546
dfd27d41
JB		 5472018-06-01 Jan Beulich <jbeulich@suse.com>
548
549 * i386-opc.tbl (sldt, str): Add NoRex64.
550 * i386-tbl.h: Re-generate.
551
64795710
JB		 5522018-06-01 Jan Beulich <jbeulich@suse.com>
553
554 * i386-opc.tbl (invpcid): Add Oword.
555 * i386-tbl.h: Re-generate.
556
030157d8
AM		 5572018-06-01 Alan Modra <amodra@gmail.com>
558
559 * sysdep.h (_bfd_error_handler): Don't declare.
560 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
561 * rl78-decode.opc: Likewise.
562 * msp430-decode.c: Regenerate.
563 * rl78-decode.c: Regenerate.
564
a9660a6f
AP		 5652018-05-30 Amit Pawar <Amit.Pawar@amd.com>
566
567 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
568 * i386-init.h : Regenerated.
569
277eb7f6
AM		 5702018-05-25 Alan Modra <amodra@gmail.com>
571
572 * Makefile.in: Regenerate.
573 * po/POTFILES.in: Regenerate.
574
98553ad3
PB		 5752018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
576
577 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
578 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
579 (insert_bab, extract_bab, insert_btab, extract_btab,
580 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
581 (BAT, BBA VBA RBS XB6S): Delete macros.
582 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
583 (BB, BD, RBX, XC6): Update for new macros.
584 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
585 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
586 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
587 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
588
7b4ae824
JD		 5892018-05-18 John Darrington <john@darrington.wattle.id.au>
590
591 * Makefile.am: Add support for s12z architecture.
592 * configure.ac: Likewise.
593 * disassemble.c: Likewise.
594 * disassemble.h: Likewise.
595 * Makefile.in: Regenerate.
596 * configure: Regenerate.
597 * s12z-dis.c: New file.
598 * s12z.h: New file.
599
29e0f0a1
AM		 6002018-05-18 Alan Modra <amodra@gmail.com>
601
602 * nfp-dis.c: Don't #include libbfd.h.
603 (init_nfp3200_priv): Use bfd_get_section_contents.
604 (nit_nfp6000_mecsr_sec): Likewise.
605
809276d2
NC		 6062018-05-17 Nick Clifton <nickc@redhat.com>
607
608 * po/zh_CN.po: Updated simplified Chinese translation.
609
ff329288
TC		 6102018-05-16 Tamar Christina <tamar.christina@arm.com>
611
612 PR binutils/23109
613 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
614 * aarch64-dis-2.c: Regenerate.
615
f9830ec1
TC		 6162018-05-15 Tamar Christina <tamar.christina@arm.com>
617
618 PR binutils/21446
619 * aarch64-asm.c (opintl.h): Include.
620 (aarch64_ins_sysreg): Enforce read/write constraints.
621 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
622 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
623 (F_REG_READ, F_REG_WRITE): New.
624 * aarch64-opc.c (aarch64_print_operand): Generate notes for
625 AARCH64_OPND_SYSREG.
626 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
627 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
628 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
629 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
630 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
631 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
632 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
633 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
634 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
635 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
636 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
637 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
638 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
639 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
640 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
641 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
642 msr (F_SYS_WRITE), mrs (F_SYS_READ).
643
7d02540a
TC		 6442018-05-15 Tamar Christina <tamar.christina@arm.com>
645
646 PR binutils/21446
647 * aarch64-dis.c (no_notes: New.
648 (parse_aarch64_dis_option): Support notes.
649 (aarch64_decode_insn, print_operands): Likewise.
650 (print_aarch64_disassembler_options): Document notes.
651 * aarch64-opc.c (aarch64_print_operand): Support notes.
652
561a72d4
TC		 6532018-05-15 Tamar Christina <tamar.christina@arm.com>
654
655 PR binutils/21446
656 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
657 and take error struct.
658 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
659 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
660 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
661 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
662 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
663 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
664 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
665 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
666 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
667 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
668 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
669 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
670 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
671 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
672 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
673 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
674 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
675 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
676 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
677 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
678 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
679 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
680 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
681 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
682 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
683 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
684 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
685 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
686 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
687 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
688 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
689 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
690 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
691 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
692 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
693 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
694 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
695 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
696 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
697 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
698 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
699 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
700 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
701 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
702 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
703 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
704 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
705 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
706 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
707 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
708 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
709 (determine_disassembling_preference, aarch64_decode_insn,
710 print_insn_aarch64_word, print_insn_data): Take errors struct.
711 (print_insn_aarch64): Use errors.
712 * aarch64-asm-2.c: Regenerate.
713 * aarch64-dis-2.c: Regenerate.
714 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
715 boolean in aarch64_insert_operan.
716 (print_operand_extractor): Likewise.
717 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
718
1678bd35
FT		 7192018-05-15 Francois H. Theron <francois.theron@netronome.com>
720
721 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
722
06cfb1c8
L		 7232018-05-09 H.J. Lu <hongjiu.lu@intel.com>
724
725 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
726
84f9f8c3
AM		 7272018-05-09 Sebastian Rasmussen <sebras@gmail.com>
728
729 * cr16-opc.c (cr16_instruction): Comment typo fix.
730 * hppa-dis.c (print_insn_hppa): Likewise.
731
e6f372ba
JW		 7322018-05-08 Jim Wilson <jimw@sifive.com>
733
734 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
735 (match_c_slli64, match_srxi_as_c_srxi): New.
736 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
737 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
738 <c.slli, c.srli, c.srai>: Use match_s_slli.
739 <c.slli64, c.srli64, c.srai64>: New.
740
f413a913
AM		 7412018-05-08 Alan Modra <amodra@gmail.com>
742
743 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
744 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
745 partition opcode space for index lookup.
746
a87a6478
PB		 7472018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
748
749 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
750 <insn_length>: ...with this. Update usage.
751 Remove duplicate call to *info->memory_error_func.
752
c0a30a9f
L		 7532018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
754 H.J. Lu <hongjiu.lu@intel.com>
755
756 * i386-dis.c (Gva): New.
757 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
758 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
759 (prefix_table): New instructions (see prefix above).
760 (mod_table): New instructions (see prefix above).
761 (OP_G): Handle va_mode.
762 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
763 CPU_MOVDIR64B_FLAGS.
764 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
765 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
766 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
767 * i386-opc.tbl: Add movidir{i,64b}.
768 * i386-init.h: Regenerated.
769 * i386-tbl.h: Likewise.
770
75c0a438
L		 7712018-05-07 H.J. Lu <hongjiu.lu@intel.com>
772
773 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
774 AddrPrefixOpReg.
775 * i386-opc.h (AddrPrefixOp0): Renamed to ...
776 (AddrPrefixOpReg): This.
777 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
778 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
779
2ceb7719
PB		 7802018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
781
782 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
783 (vle_num_opcodes): Likewise.
784 (spe2_num_opcodes): Likewise.
785 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
786 initialization loop.
787 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
788 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
789 only once.
790
b3ac5c6c
TC		 7912018-05-01 Tamar Christina <tamar.christina@arm.com>
792
793 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
794
fe944acf
FT		 7952018-04-30 Francois H. Theron <francois.theron@netronome.com>
796
797 Makefile.am: Added nfp-dis.c.
798 configure.ac: Added bfd_nfp_arch.
799 disassemble.h: Added print_insn_nfp prototype.
800 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
801 nfp-dis.c: New, for NFP support.
802 po/POTFILES.in: Added nfp-dis.c to the list.
803 Makefile.in: Regenerate.
804 configure: Regenerate.
805
e2195274
JB		 8062018-04-26 Jan Beulich <jbeulich@suse.com>
807
808 * i386-opc.tbl: Fold various non-memory operand AVX512VL
809 templates into their base ones.
810 * i386-tlb.h: Re-generate.
811
59ef5df4
JB		 8122018-04-26 Jan Beulich <jbeulich@suse.com>
813
814 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
815 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
816 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
817 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
818 * i386-init.h: Re-generate.
819
6e041cf4
JB		 8202018-04-26 Jan Beulich <jbeulich@suse.com>
821
822 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
823 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
824 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
825 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
826 comment.
827 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
828 and CpuRegMask.
829 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
830 CpuRegMask: Delete.
831 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
832 cpuregzmm, and cpuregmask.
833 * i386-init.h: Re-generate.
834 * i386-tbl.h: Re-generate.
835
0e0eea78
JB		 8362018-04-26 Jan Beulich <jbeulich@suse.com>
837
838 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
839 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
840 * i386-init.h: Re-generate.
841
2f1bada2
JB		 8422018-04-26 Jan Beulich <jbeulich@suse.com>
843
844 * i386-gen.c (VexImmExt): Delete.
845 * i386-opc.h (VexImmExt, veximmext): Delete.
846 * i386-opc.tbl: Drop all VexImmExt uses.
847 * i386-tlb.h: Re-generate.
848
bacd1457
JB		 8492018-04-25 Jan Beulich <jbeulich@suse.com>
850
851 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
852 register-only forms.
853 * i386-tlb.h: Re-generate.
854
10bba94b
TC		 8552018-04-25 Tamar Christina <tamar.christina@arm.com>
856
857 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
858
c48935d7
IT		 8592018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
860
861 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
862 PREFIX_0F1C.
863 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
864 (cpu_flags): Add CpuCLDEMOTE.
865 * i386-init.h: Regenerate.
866 * i386-opc.h (enum): Add CpuCLDEMOTE,
867 (i386_cpu_flags): Add cpucldemote.
868 * i386-opc.tbl: Add cldemote.
869 * i386-tbl.h: Regenerate.
870
211dc24b
AM		 8712018-04-16 Alan Modra <amodra@gmail.com>
872
873 * Makefile.am: Remove sh5 and sh64 support.
874 * configure.ac: Likewise.
875 * disassemble.c: Likewise.
876 * disassemble.h: Likewise.
877 * sh-dis.c: Likewise.
878 * sh64-dis.c: Delete.
879 * sh64-opc.c: Delete.
880 * sh64-opc.h: Delete.
881 * Makefile.in: Regenerate.
882 * configure: Regenerate.
883 * po/POTFILES.in: Regenerate.
884
a9a4b302
AM		 8852018-04-16 Alan Modra <amodra@gmail.com>
886
887 * Makefile.am: Remove w65 support.
888 * configure.ac: Likewise.
889 * disassemble.c: Likewise.
890 * disassemble.h: Likewise.
891 * w65-dis.c: Delete.
892 * w65-opc.h: Delete.
893 * Makefile.in: Regenerate.
894 * configure: Regenerate.
895 * po/POTFILES.in: Regenerate.
896
04cb01fd
AM		 8972018-04-16 Alan Modra <amodra@gmail.com>
898
899 * configure.ac: Remove we32k support.
900 * configure: Regenerate.
901
c2bf1eec
AM		 9022018-04-16 Alan Modra <amodra@gmail.com>
903
904 * Makefile.am: Remove m88k support.
905 * configure.ac: Likewise.
906 * disassemble.c: Likewise.
907 * disassemble.h: Likewise.
908 * m88k-dis.c: Delete.
909 * Makefile.in: Regenerate.
910 * configure: Regenerate.
911 * po/POTFILES.in: Regenerate.
912
6793974d
AM		 9132018-04-16 Alan Modra <amodra@gmail.com>
914
915 * Makefile.am: Remove i370 support.
916 * configure.ac: Likewise.
917 * disassemble.c: Likewise.
918 * disassemble.h: Likewise.
919 * i370-dis.c: Delete.
920 * i370-opc.c: Delete.
921 * Makefile.in: Regenerate.
922 * configure: Regenerate.
923 * po/POTFILES.in: Regenerate.
924
e82aa794
AM		 9252018-04-16 Alan Modra <amodra@gmail.com>
926
927 * Makefile.am: Remove h8500 support.
928 * configure.ac: Likewise.
929 * disassemble.c: Likewise.
930 * disassemble.h: Likewise.
931 * h8500-dis.c: Delete.
932 * h8500-opc.h: Delete.
933 * Makefile.in: Regenerate.
934 * configure: Regenerate.
935 * po/POTFILES.in: Regenerate.
936
fceadf09
AM		 9372018-04-16 Alan Modra <amodra@gmail.com>
938
939 * configure.ac: Remove tahoe support.
940 * configure: Regenerate.
941
ae1d3843
L		 9422018-04-15 H.J. Lu <hongjiu.lu@intel.com>
943
944 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
945 umwait.
946 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
947 64-bit mode.
948 * i386-tbl.h: Regenerated.
949
de89d0a3
IT		 9502018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
951
952 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
953 PREFIX_MOD_1_0FAE_REG_6.
954 (va_mode): New.
955 (OP_E_register): Use va_mode.
956 * i386-dis-evex.h (prefix_table):
957 New instructions (see prefixes above).
958 * i386-gen.c (cpu_flag_init): Add WAITPKG.
959 (cpu_flags): Likewise.
960 * i386-opc.h (enum): Likewise.
961 (i386_cpu_flags): Likewise.
962 * i386-opc.tbl: Add umonitor, umwait, tpause.
963 * i386-init.h: Regenerate.
964 * i386-tbl.h: Likewise.
965
a8eb42a8
AM		 9662018-04-11 Alan Modra <amodra@gmail.com>
967
968 * opcodes/i860-dis.c: Delete.
969 * opcodes/i960-dis.c: Delete.
970 * Makefile.am: Remove i860 and i960 support.
971 * configure.ac: Likewise.
972 * disassemble.c: Likewise.
973 * disassemble.h: Likewise.
974 * Makefile.in: Regenerate.
975 * configure: Regenerate.
976 * po/POTFILES.in: Regenerate.
977
caf0678c
L		 9782018-04-04 H.J. Lu <hongjiu.lu@intel.com>
979
980 PR binutils/23025
981 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
982 to 0.
983 (print_insn): Clear vex instead of vex.evex.
984
4fb0d2b9
NC		 9852018-04-04 Nick Clifton <nickc@redhat.com>
986
987 * po/es.po: Updated Spanish translation.
988
c39e5b26
JB		 9892018-03-28 Jan Beulich <jbeulich@suse.com>
990
991 * i386-gen.c (opcode_modifiers): Delete VecESize.
992 * i386-opc.h (VecESize): Delete.
993 (struct i386_opcode_modifier): Delete vecesize.
994 * i386-opc.tbl: Drop VecESize.
995 * i386-tlb.h: Re-generate.
996
8e6e0792
JB		 9972018-03-28 Jan Beulich <jbeulich@suse.com>
998
999 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1000 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1001 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1002 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1003 * i386-tlb.h: Re-generate.
1004
9f123b91
JB		 10052018-03-28 Jan Beulich <jbeulich@suse.com>
1006
1007 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1008 Fold AVX512 forms
1009 * i386-tlb.h: Re-generate.
1010
9646c87b
JB		 10112018-03-28 Jan Beulich <jbeulich@suse.com>
1012
1013 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1014 (vex_len_table): Drop Y for vcvt*2si.
1015 (putop): Replace plain 'Y' handling by abort().
1016
c8d59609
NC		 10172018-03-28 Nick Clifton <nickc@redhat.com>
1018
1019 PR 22988
1020 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1021 instructions with only a base address register.
1022 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1023 handle AARHC64_OPND_SVE_ADDR_R.
1024 (aarch64_print_operand): Likewise.
1025 * aarch64-asm-2.c: Regenerate.
1026 * aarch64_dis-2.c: Regenerate.
1027 * aarch64-opc-2.c: Regenerate.
1028
b8c169f3
JB		 10292018-03-22 Jan Beulich <jbeulich@suse.com>
1030
1031 * i386-opc.tbl: Drop VecESize from register only insn forms and
1032 memory forms not allowing broadcast.
1033 * i386-tlb.h: Re-generate.
1034
96bc132a
JB		 10352018-03-22 Jan Beulich <jbeulich@suse.com>
1036
1037 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1038 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1039 sha256*): Drop Disp<N>.
1040
9f79e886
JB		 10412018-03-22 Jan Beulich <jbeulich@suse.com>
1042
1043 * i386-dis.c (EbndS, bnd_swap_mode): New.
1044 (prefix_table): Use EbndS.
1045 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1046 * i386-opc.tbl (bndmov): Move misplaced Load.
1047 * i386-tlb.h: Re-generate.
1048
d6793fa1
JB		 10492018-03-22 Jan Beulich <jbeulich@suse.com>
1050
1051 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1052 templates allowing memory operands and folded ones for register
1053 only flavors.
1054 * i386-tlb.h: Re-generate.
1055
f7768225
JB		 10562018-03-22 Jan Beulich <jbeulich@suse.com>
1057
1058 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1059 256-bit templates. Drop redundant leftover Disp<N>.
1060 * i386-tlb.h: Re-generate.
1061
0e35537d
JW		 10622018-03-14 Kito Cheng <kito.cheng@gmail.com>
1063
1064 * riscv-opc.c (riscv_insn_types): New.
1065
b4a3689a
NC		 10662018-03-13 Nick Clifton <nickc@redhat.com>
1067
1068 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1069
d3d50934
L		 10702018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1071
1072 * i386-opc.tbl: Add Optimize to clr.
1073 * i386-tbl.h: Regenerated.
1074
bd5dea88
L		 10752018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1076
1077 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1078 * i386-opc.h (OldGcc): Removed.
1079 (i386_opcode_modifier): Remove oldgcc.
1080 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1081 instructions for old (<= 2.8.1) versions of gcc.
1082 * i386-tbl.h: Regenerated.
1083
e771e7c9
JB		 10842018-03-08 Jan Beulich <jbeulich@suse.com>
1085
1086 * i386-opc.h (EVEXDYN): New.
1087 * i386-opc.tbl: Fold various AVX512VL templates.
1088 * i386-tlb.h: Re-generate.
1089
ed438a93
JB		 10902018-03-08 Jan Beulich <jbeulich@suse.com>
1091
1092 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1093 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1094 vpexpandd, vpexpandq): Fold AFX512VF templates.
1095 * i386-tlb.h: Re-generate.
1096
454172a9
JB		 10972018-03-08 Jan Beulich <jbeulich@suse.com>
1098
1099 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1100 Fold 128- and 256-bit VEX-encoded templates.
1101 * i386-tlb.h: Re-generate.
1102
36824150
JB		 11032018-03-08 Jan Beulich <jbeulich@suse.com>
1104
1105 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1106 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1107 vpexpandd, vpexpandq): Fold AVX512F templates.
1108 * i386-tlb.h: Re-generate.
1109
e7f5c0a9
JB		 11102018-03-08 Jan Beulich <jbeulich@suse.com>
1111
1112 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1113 64-bit templates. Drop Disp<N>.
1114 * i386-tlb.h: Re-generate.
1115
25a4277f
JB		 11162018-03-08 Jan Beulich <jbeulich@suse.com>
1117
1118 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1119 and 256-bit templates.
1120 * i386-tlb.h: Re-generate.
1121
d2224064
JB		 11222018-03-08 Jan Beulich <jbeulich@suse.com>
1123
1124 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1125 * i386-tlb.h: Re-generate.
1126
1b193f0b
JB		 11272018-03-08 Jan Beulich <jbeulich@suse.com>
1128
1129 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1130 Drop NoAVX.
1131 * i386-tlb.h: Re-generate.
1132
f2f6a710
JB		 11332018-03-08 Jan Beulich <jbeulich@suse.com>
1134
1135 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1136 * i386-tlb.h: Re-generate.
1137
38e314eb
JB		 11382018-03-08 Jan Beulich <jbeulich@suse.com>
1139
1140 * i386-gen.c (opcode_modifiers): Delete FloatD.
1141 * i386-opc.h (FloatD): Delete.
1142 (struct i386_opcode_modifier): Delete floatd.
1143 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1144 FloatD by D.
1145 * i386-tlb.h: Re-generate.
1146
d53e6b98
JB		 11472018-03-08 Jan Beulich <jbeulich@suse.com>
1148
1149 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1150
2907c2f5
JB		 11512018-03-08 Jan Beulich <jbeulich@suse.com>
1152
1153 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1154 * i386-tlb.h: Re-generate.
1155
73053c1f
JB		 11562018-03-08 Jan Beulich <jbeulich@suse.com>
1157
1158 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1159 forms.
1160 * i386-tlb.h: Re-generate.
1161
52fe4420
AM		 11622018-03-07 Alan Modra <amodra@gmail.com>
1163
1164 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1165 bfd_arch_rs6000.
1166 * disassemble.h (print_insn_rs6000): Delete.
1167 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1168 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1169 (print_insn_rs6000): Delete.
1170
a6743a54
AM		 11712018-03-03 Alan Modra <amodra@gmail.com>
1172
1173 * sysdep.h (opcodes_error_handler): Define.
1174 (_bfd_error_handler): Declare.
1175 * Makefile.am: Remove stray #.
1176 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1177 EDIT" comment.
1178 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1179 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1180 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1181 opcodes_error_handler to print errors. Standardize error messages.
1182 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1183 and include opintl.h.
1184 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1185 * i386-gen.c: Standardize error messages.
1186 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1187 * Makefile.in: Regenerate.
1188 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1189 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1190 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1191 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1192 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1193 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1194 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1195 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1196 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1197 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1198 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1199 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1200 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1201
8305403a
L		 12022018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1203
1204 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1205 vpsub[bwdq] instructions.
1206 * i386-tbl.h: Regenerated.
1207
e184813f
AM		 12082018-03-01 Alan Modra <amodra@gmail.com>
1209
1210 * configure.ac (ALL_LINGUAS): Sort.
1211 * configure: Regenerate.
1212
5b616bef
TP		 12132018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1214
1215 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1216 macro by assignements.
1217
b6f8c7c4
L		 12182018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1219
1220 PR gas/22871
1221 * i386-gen.c (opcode_modifiers): Add Optimize.
1222 * i386-opc.h (Optimize): New enum.
1223 (i386_opcode_modifier): Add optimize.
1224 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1225 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1226 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1227 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1228 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1229 vpxord and vpxorq.
1230 * i386-tbl.h: Regenerated.
1231
e95b887f
AM		 12322018-02-26 Alan Modra <amodra@gmail.com>
1233
1234 * crx-dis.c (getregliststring): Allocate a large enough buffer
1235 to silence false positive gcc8 warning.
1236
0bccfb29
JW		 12372018-02-22 Shea Levy <shea@shealevy.com>
1238
1239 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1240
6b6b6807
L		 12412018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1242
1243 * i386-opc.tbl: Add {rex},
1244 * i386-tbl.h: Regenerated.
1245
75f31665
MR		 12462018-02-20 Maciej W. Rozycki <macro@mips.com>
1247
1248 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1249 (mips16_opcodes): Replace `M' with `m' for "restore".
1250
e207bc53
TP		 12512018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1252
1253 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1254
87993319
MR		 12552018-02-13 Maciej W. Rozycki <macro@mips.com>
1256
1257 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1258 variable to `function_index'.
1259
68d20676
NC		 12602018-02-13 Nick Clifton <nickc@redhat.com>
1261
1262 PR 22823
1263 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1264 about truncation of printing.
1265
d2159fdc
HW		 12662018-02-12 Henry Wong <henry@stuffedcow.net>
1267
1268 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1269
f174ef9f
NC		 12702018-02-05 Nick Clifton <nickc@redhat.com>
1271
1272 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1273
be3a8dca
IT		 12742018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1275
1276 * i386-dis.c (enum): Add pconfig.
1277 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1278 (cpu_flags): Add CpuPCONFIG.
1279 * i386-opc.h (enum): Add CpuPCONFIG.
1280 (i386_cpu_flags): Add cpupconfig.
1281 * i386-opc.tbl: Add PCONFIG instruction.
1282 * i386-init.h: Regenerate.
1283 * i386-tbl.h: Likewise.
1284
3233d7d0
IT		 12852018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1286
1287 * i386-dis.c (enum): Add PREFIX_0F09.
1288 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1289 (cpu_flags): Add CpuWBNOINVD.
1290 * i386-opc.h (enum): Add CpuWBNOINVD.
1291 (i386_cpu_flags): Add cpuwbnoinvd.
1292 * i386-opc.tbl: Add WBNOINVD instruction.
1293 * i386-init.h: Regenerate.
1294 * i386-tbl.h: Likewise.
1295
e925c834
JW		 12962018-01-17 Jim Wilson <jimw@sifive.com>
1297
1298 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1299
d777820b
IT		 13002018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1301
1302 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1303 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1304 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1305 (cpu_flags): Add CpuIBT, CpuSHSTK.
1306 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1307 (i386_cpu_flags): Add cpuibt, cpushstk.
1308 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1309 * i386-init.h: Regenerate.
1310 * i386-tbl.h: Likewise.
1311
f6efed01
NC		 13122018-01-16 Nick Clifton <nickc@redhat.com>
1313
1314 * po/pt_BR.po: Updated Brazilian Portugese translation.
1315 * po/de.po: Updated German translation.
1316
2721d702
JW		 13172018-01-15 Jim Wilson <jimw@sifive.com>
1318
1319 * riscv-opc.c (match_c_nop): New.
1320 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1321
616dcb87
NC		 13222018-01-15 Nick Clifton <nickc@redhat.com>
1323
1324 * po/uk.po: Updated Ukranian translation.
1325
3957a496
NC		 13262018-01-13 Nick Clifton <nickc@redhat.com>
1327
1328 * po/opcodes.pot: Regenerated.
1329
769c7ea5
NC		 13302018-01-13 Nick Clifton <nickc@redhat.com>
1331
1332 * configure: Regenerate.
1333
faf766e3
NC		 13342018-01-13 Nick Clifton <nickc@redhat.com>
1335
1336 2.30 branch created.
1337
888a89da
IT		 13382018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1339
1340 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1341 * i386-tbl.h: Regenerate.
1342
cbda583a
JB		 13432018-01-10 Jan Beulich <jbeulich@suse.com>
1344
1345 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1346 * i386-tbl.h: Re-generate.
1347
c9e92278
JB		 13482018-01-10 Jan Beulich <jbeulich@suse.com>
1349
1350 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1351 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1352 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1353 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1354 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1355 Disp8MemShift of AVX512VL forms.
1356 * i386-tbl.h: Re-generate.
1357
35fd2b2b
JW		 13582018-01-09 Jim Wilson <jimw@sifive.com>
1359
1360 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1361 then the hi_addr value is zero.
1362
91d8b670
JG		 13632018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1364
1365 * arm-dis.c (arm_opcodes): Add csdb.
1366 (thumb32_opcodes): Add csdb.
1367
be2e7d95
JG		 13682018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1369
1370 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1371 * aarch64-asm-2.c: Regenerate.
1372 * aarch64-dis-2.c: Regenerate.
1373 * aarch64-opc-2.c: Regenerate.
1374
704a705d
L		 13752018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1376
1377 PR gas/22681
1378 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1379 Remove AVX512 vmovd with 64-bit operands.
1380 * i386-tbl.h: Regenerated.
1381
35eeb78f
JW		 13822018-01-05 Jim Wilson <jimw@sifive.com>
1383
1384 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1385 jalr.
1386
219d1afa
AM		 13872018-01-03 Alan Modra <amodra@gmail.com>
1388
1389 Update year range in copyright notice of all files.
1390
1508bbf5
JB		 13912018-01-02 Jan Beulich <jbeulich@suse.com>
1392
1393 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1394 and OPERAND_TYPE_REGZMM entries.
1395
1e563868 1396For older changes see ChangeLog-2017
3499769a 1397\f
1e563868 1398Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 1399
1400Copying and distribution of this file, with or without modification,
1401are permitted in any medium without royalty provided the copyright
1402notice and this notice are preserved.
1403
1404Local Variables:
1405mode: change-log
1406left-margin: 8
1407fill-column: 74
1408version-control: never
1409End:
GDB Binutils - Deliverables
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