projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Fix earlier ChangeLog entry to give Igor credit, add testcases.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
64c11183
MR		 12016-12-09 Maciej W. Rozycki <macro@imgtec.com>
2
3 * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
4
f17ecb4b
MR		 52016-12-09 Maciej W. Rozycki <macro@imgtec.com>
6
7 * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
8 than UINT.
9
55af4784
MR		 102016-12-09 Maciej W. Rozycki <macro@imgtec.com>
11
12 * mips-dis.c (print_insn_mips16): Use a tab rather than a space
13 to separate `extend' and its uninterpreted argument output.
14 Separate hexadecimal halves of undecoded extended instructions
15 output.
16
39f66f3a
MR		 172016-12-08 Maciej W. Rozycki <macro@imgtec.com>
18
19 * mips-dis.c (print_mips16_insn_arg): Remove extraneous
20 indentation space across.
21
860b03a8
MR		 222016-12-08 Maciej W. Rozycki <macro@imgtec.com>
23
24 * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
25 adjustment for PC-relative operations following MIPS16e compact
26 jumps or undefined RR/J(AL)R(C) encodings.
27
329d01f7
MR		 282016-12-08 Maciej W. Rozycki <macro@imgtec.com>
29
30 * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
31 variable to `reglane_index'.
32
3a2488dd
LM		 332016-12-08 Luis Machado <lgustavo@codesourcery.com>
34
35 * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
36
5f5c6e03
MR		 372016-12-07 Maciej W. Rozycki <macro@imgtec.com>
38
39 * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
40
343fa690
MR		 412016-12-07 Maciej W. Rozycki <macro@imgtec.com>
42
43 * mips16-opc.c (mips16_opcodes): Update comment naming structure
44 members.
45
6725647c
MR		 462016-12-07 Maciej W. Rozycki <macro@imgtec.com>
47
48 * mips-dis.c (print_mips_disassembler_options): Reformat output.
49
c28eeff2
SN		 502016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
51
52 * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
53 (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
54
49e8a725
SN		 552016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
56
57 * arm-dis.c (coprocessor_opcodes): Add vjcvt.
58
a37a2806
NC		 592016-12-01 Nick Clifton <nickc@redhat.com>
60
61 PR binutils/20893
62 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
63 opcode designator.
64
abe7c33b
CZ		 652016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
66
67 * arc-opc.c (insert_ra_chk): New function.
68 (insert_rb_chk): Likewise.
69 (insert_rad): Update text error message.
70 (insert_rcd): Likewise.
71 (insert_rhv2): Likewise.
72 (insert_r0): Likewise.
73 (insert_r1): Likewise.
74 (insert_r2): Likewise.
75 (insert_r3): Likewise.
76 (insert_sp): Likewise.
77 (insert_gp): Likewise.
78 (insert_pcl): Likewise.
79 (insert_blink): Likewise.
80 (insert_ilink1): Likewise.
81 (insert_ilink2): Likewise.
82 (insert_ras): Likewise.
83 (insert_rbs): Likewise.
84 (insert_rcs): Likewise.
85 (insert_simm3s): Likewise.
86 (insert_rrange): Likewise.
87 (insert_fpel): Likewise.
88 (insert_blinkel): Likewise.
89 (insert_pcel): Likewise.
90 (insert_nps_3bit_dst): Likewise.
91 (insert_nps_3bit_dst_short): Likewise.
92 (insert_nps_3bit_src2_short): Likewise.
93 (insert_nps_bitop_size_2b): Likewise.
94 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
95 (RA_CHK): Define.
96 (RB): Adjust.
97 (RB_CHK): Define.
98 (RC): Adjust.
99 * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
100 * arc-tbl.h (div, divu): All instructions are DIVREM class.
101 Change first insn argument to check for LP_COUNT usage.
102 (rem): Likewise.
103 (ld, ldd): All instructions are LOAD class. Change first insn
104 argument to check for LP_COUNT usage.
105 (st, std): All instructions are STORE class.
106 (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
107 Change first insn argument to check for LP_COUNT usage.
108 (mov): All instructions are MOVE class. Change first insn
109 argument to check for LP_COUNT usage.
110
ee881e5d
CZ		 1112016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
112
113 * arc-dis.c (is_compatible_p): Remove function.
114 (skip_this_opcode): Don't add any decoding class to decode list.
115 Remove warning.
116 (find_format_from_table): Go through all opcodes, and warn if we
117 use a guessed mnemonic.
118
abfcb414
AP		 1192016-11-28 Ramiro Polla <ramiro@hex-rays.com>
120 Amit Pawar <amit.pawar@amd.com>
121
122 PR binutils/20637
123 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
124 instructions.
125
96fe4562
AM		 1262016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
127
128 * configure: Regenerate.
129
6884417a
JM		 1302016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
131
132 * sparc-opc.c (HWS_V8): Definition moved from
133 gas/config/tc-sparc.c.
134 (HWS_V9): Likewise.
135 (HWS_VA): Likewise.
136 (HWS_VB): Likewise.
137 (HWS_VC): Likewise.
138 (HWS_VD): Likewise.
139 (HWS_VE): Likewise.
140 (HWS_VV): Likewise.
141 (HWS_VM): Likewise.
142 (HWS2_VM): Likewise.
143 (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
144 existing entries.
145
c4b943d7
CZ		 1462016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
147
148 * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
149 instructions.
150
c2c4ff8d
SN		 1512016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
152
153 * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
154 (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
155 (aarch64_opcode_table): Add fcmla and fcadd.
156 (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
157 * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
158 * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
159 * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
160 * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
161 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
162 * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
163 (operand_general_constraint_met_p): Rotate and index range check.
164 (aarch64_print_operand): Handle rotate operand.
165 * aarch64-asm-2.c: Regenerate.
166 * aarch64-dis-2.c: Likewise.
167 * aarch64-opc-2.c: Likewise.
168
28617675
SN		 1692016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
170
171 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
172 * aarch64-asm-2.c: Regenerate.
173 * aarch64-dis-2.c: Regenerate.
174 * aarch64-opc-2.c: Regenerate.
175
ccfc90a3
SN		 1762016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
177
178 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
179 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
180 * aarch64-asm-2.c: Regenerate.
181 * aarch64-dis-2.c: Regenerate.
182 * aarch64-opc-2.c: Regenerate.
183
3f06e550
SN		 1842016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
185
186 * aarch64-tbl.h (QL_X1NIL): New.
187 (arch64_opcode_table): Add ldraa, ldrab.
188 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
189 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
190 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
191 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
192 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
193 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
194 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
195 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
196 (aarch64_print_operand): Likewise.
197 * aarch64-asm-2.c: Regenerate.
198 * aarch64-dis-2.c: Regenerate.
199 * aarch64-opc-2.c: Regenerate.
200
74f5402d
SN		 2012016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
202
203 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
204 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
205 * aarch64-asm-2.c: Regenerate.
206 * aarch64-dis-2.c: Regenerate.
207 * aarch64-opc-2.c: Regenerate.
208
c84364ec
SN		 2092016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
210
211 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
212 (AARCH64_OPERANDS): Add Rm_SP.
213 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
214 * aarch64-asm-2.c: Regenerate.
215 * aarch64-dis-2.c: Regenerate.
216 * aarch64-opc-2.c: Regenerate.
217
a2cfc830
SN		 2182016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
219
220 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
221 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
222 autdzb, xpaci, xpacd.
223 * aarch64-asm-2.c: Regenerate.
224 * aarch64-dis-2.c: Regenerate.
225 * aarch64-opc-2.c: Regenerate.
226
b0bfa7b5
SN		 2272016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
228
229 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
230 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
231 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
232 (aarch64_sys_reg_supported_p): Add feature test for new registers.
233
8787d804
SN		 2342016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
235
236 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
237 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
238 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
239 autibsp.
240 * aarch64-asm-2.c: Regenerate.
241 * aarch64-dis-2.c: Regenerate.
242
3d731f69
SN		 2432016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
244
245 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
246
60227d64
L		 2472016-11-09 H.J. Lu <hongjiu.lu@intel.com>
248
249 PR binutils/20799
250 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
251 * i386-dis.c (EdqwS): Removed.
252 (dqw_swap_mode): Likewise.
253 (intel_operand_size): Don't check dqw_swap_mode.
254 (OP_E_register): Likewise.
255 (OP_E_memory): Likewise.
256 (OP_G): Likewise.
257 (OP_EX): Likewise.
258 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
259 * i386-tbl.h: Regerated.
260
7efeed17
L		 2612016-11-09 H.J. Lu <hongjiu.lu@intel.com>
262
263 * i386-opc.tbl: Merge AVX512F vmovq.
1032d6eb 264 * i386-tbl.h: Regerated.
7efeed17 265
1f334aeb
L		 2662016-11-08 H.J. Lu <hongjiu.lu@intel.com>
267
268 PR binutils/20701
269 * i386-dis.c (THREE_BYTE_0F7A): Removed.
270 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
271 (three_byte_table): Remove THREE_BYTE_0F7A.
272
48c97fa1
L		 2732016-11-07 H.J. Lu <hongjiu.lu@intel.com>
274
275 PR binutils/20775
276 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
277 (FGRPd9_4): Replace 1 with 2.
278 (FGRPd9_5): Replace 2 with 3.
279 (FGRPd9_6): Replace 3 with 4.
280 (FGRPd9_7): Replace 4 with 5.
281 (FGRPda_5): Replace 5 with 6.
282 (FGRPdb_4): Replace 6 with 7.
283 (FGRPde_3): Replace 7 with 8.
284 (FGRPdf_4): Replace 8 with 9.
285 (fgrps): Add an entry for Bad_Opcode.
286
b437d035
AB		 2872016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
288
289 * arc-opc.c (arc_flag_operands): Add F_DI14.
290 (arc_flag_classes): Add C_DI14.
291 * arc-nps400-tbl.h: Add new exc instructions.
292
5a736821
GM		 2932016-11-03 Graham Markall <graham.markall@embecosm.com>
294
295 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
296 major opcode 0xa.
297 * arc-nps-400-tbl.h: Add dcmac instruction.
298 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
299 (insert_nps_rbdouble_64): Added.
300 (extract_nps_rbdouble_64): Added.
301 (insert_nps_proto_size): Added.
302 (extract_nps_proto_size): Added.
303
bdfe53e3
AB		 3042016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
305
306 * arc-dis.c (struct arc_operand_iterator): Remove all fields
307 relating to long instruction processing, add new limm field.
308 (OPCODE): Rename to...
309 (OPCODE_32BIT_INSN): ...this.
310 (OPCODE_AC): Delete.
311 (skip_this_opcode): Handle different instruction lengths, update
312 macro name.
313 (special_flag_p): Update parameter type.
314 (find_format_from_table): Update for more instruction lengths.
315 (find_format_long_instructions): Delete.
316 (find_format): Update for more instruction lengths.
317 (arc_insn_length): Likewise.
318 (extract_operand_value): Update for more instruction lengths.
319 (operand_iterator_next): Remove code relating to long
320 instructions.
321 (arc_opcode_to_insn_type): New function.
322 (print_insn_arc):Update for more instructions lengths.
323 * arc-ext.c (extInstruction_t): Change argument type.
324 * arc-ext.h (extInstruction_t): Change argument type.
325 * arc-fxi.h: Change type unsigned to unsigned long long
326 extensively throughout.
327 * arc-nps400-tbl.h: Add long instructions taken from
328 arc_long_opcodes table in arc-opc.c.
329 * arc-opc.c: Update parameter types on insert/extract handlers.
330 (arc_long_opcodes): Delete.
331 (arc_num_long_opcodes): Delete.
332 (arc_opcode_len): Update for more instruction lengths.
333
90f61cce
GM		 3342016-11-03 Graham Markall <graham.markall@embecosm.com>
335
336 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
337
06fe285f
GM		 3382016-11-03 Graham Markall <graham.markall@embecosm.com>
339
340 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
341 with arc_opcode_len.
342 (find_format_long_instructions): Likewise.
343 * arc-opc.c (arc_opcode_len): New function.
344
ecf64ec6
AB		 3452016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
346
347 * arc-nps400-tbl.h: Fix some instruction masks.
348
d039fef3
L		 3492016-11-03 H.J. Lu <hongjiu.lu@intel.com>
350
351 * i386-dis.c (REG_82): Removed.
352 (X86_64_82_REG_0): Likewise.
353 (X86_64_82_REG_1): Likewise.
354 (X86_64_82_REG_2): Likewise.
355 (X86_64_82_REG_3): Likewise.
356 (X86_64_82_REG_4): Likewise.
357 (X86_64_82_REG_5): Likewise.
358 (X86_64_82_REG_6): Likewise.
359 (X86_64_82_REG_7): Likewise.
360 (X86_64_82): New.
361 (dis386): Use X86_64_82 instead of REG_82.
362 (reg_table): Remove REG_82.
363 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
364 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
365 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
366 X86_64_82_REG_7.
367
8b89fe14
L		 3682016-11-03 H.J. Lu <hongjiu.lu@intel.com>
369
370 PR binutils/20754
371 * i386-dis.c (REG_82): New.
372 (X86_64_82_REG_0): Likewise.
373 (X86_64_82_REG_1): Likewise.
374 (X86_64_82_REG_2): Likewise.
375 (X86_64_82_REG_3): Likewise.
376 (X86_64_82_REG_4): Likewise.
377 (X86_64_82_REG_5): Likewise.
378 (X86_64_82_REG_6): Likewise.
379 (X86_64_82_REG_7): Likewise.
380 (dis386): Use REG_82.
381 (reg_table): Add REG_82.
382 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
383 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
384 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
385
7148c369
L		 3862016-11-03 H.J. Lu <hongjiu.lu@intel.com>
387
388 * i386-dis.c (REG_82): Renamed to ...
389 (REG_83): This.
390 (dis386): Updated.
391 (reg_table): Likewise.
392
47acf0bd
IT		 3932016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
394
395 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
396 * i386-dis-evex.h (evex_table): Updated.
397 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
398 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
399 (cpu_flags): Add CpuAVX512_4VNNIW.
400 * i386-opc.h (enum): (AVX512_4VNNIW): New.
401 (i386_cpu_flags): Add cpuavx512_4vnniw.
402 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
403 * i386-init.h: Regenerate.
404 * i386-tbl.h: Ditto.
405
920d2ddc
IT		 4062016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
407
408 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
409 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
410 * i386-dis-evex.h (evex_table): Updated.
411 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
412 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
413 (cpu_flags): Add CpuAVX512_4FMAPS.
414 (opcode_modifiers): Add ImplicitQuadGroup modifier.
415 * i386-opc.h (AVX512_4FMAP): New.
416 (i386_cpu_flags): Add cpuavx512_4fmaps.
417 (ImplicitQuadGroup): New.
418 (i386_opcode_modifier): Add implicitquadgroup.
419 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
420 * i386-init.h: Regenerate.
421 * i386-tbl.h: Ditto.
422
e23eba97
NC		 4232016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
424 Andrew Waterman <andrew@sifive.com>
425
426 Add support for RISC-V architecture.
427 * configure.ac: Add entry for bfd_riscv_arch.
428 * configure: Regenerate.
429 * disassemble.c (disassembler): Add support for riscv.
430 (disassembler_usage): Likewise.
431 * riscv-dis.c: New file.
432 * riscv-opc.c: New file.
433
b5cefcca
L		 4342016-10-21 H.J. Lu <hongjiu.lu@intel.com>
435
436 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
437 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
438 (rm_table): Update the RM_0FAE_REG_7 entry.
439 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
440 (cpu_flags): Remove CpuPCOMMIT.
441 * i386-opc.h (CpuPCOMMIT): Removed.
442 (i386_cpu_flags): Remove cpupcommit.
443 * i386-opc.tbl: Remove pcommit.
444 * i386-init.h: Regenerated.
445 * i386-tbl.h: Likewise.
446
9889cbb1
L		 4472016-10-20 H.J. Lu <hongjiu.lu@intel.com>
448
449 PR binutis/20705
450 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
451 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
452 32-bit mode. Don't check vex.register_specifier in 32-bit
453 mode.
454 (OP_VEX): Check for invalid mask registers.
455
28596323
L		 4562016-10-18 H.J. Lu <hongjiu.lu@intel.com>
457
458 PR binutis/20699
459 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
460 sizeflag.
461
da8d7d66
L		 4622016-10-18 H.J. Lu <hongjiu.lu@intel.com>
463
464 PR binutis/20704
465 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
466
eaf02703
MR		 4672016-10-18 Maciej W. Rozycki <macro@imgtec.com>
468
469 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
470 local variable to `index_regno'.
471
decf5bd1
CM		 4722016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
473
474 * arc-tbl.h: Removed any "inv.+" instructions from the table.
475
e5b06ef0
CZ		 4762016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
477
478 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
479 usage on ISA basis.
480
93562a34
JW		 4812016-10-11 Jiong Wang <jiong.wang@arm.com>
482
483 PR target/20666
484 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
485
362c0c4d
JW		 4862016-10-07 Jiong Wang <jiong.wang@arm.com>
487
488 PR target/20667
489 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
490 available.
491
1047201f
AM		 4922016-10-07 Alan Modra <amodra@gmail.com>
493
494 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
495
1a0670f3
AM		 4962016-10-06 Alan Modra <amodra@gmail.com>
497
498 * aarch64-opc.c: Spell fall through comments consistently.
499 * i386-dis.c: Likewise.
500 * aarch64-dis.c: Add missing fall through comments.
501 * aarch64-opc.c: Likewise.
502 * arc-dis.c: Likewise.
503 * arm-dis.c: Likewise.
504 * i386-dis.c: Likewise.
505 * m68k-dis.c: Likewise.
506 * mep-asm.c: Likewise.
507 * ns32k-dis.c: Likewise.
508 * sh-dis.c: Likewise.
509 * tic4x-dis.c: Likewise.
510 * tic6x-dis.c: Likewise.
511 * vax-dis.c: Likewise.
512
2b804145
AM		 5132016-10-06 Alan Modra <amodra@gmail.com>
514
515 * arc-ext.c (create_map): Add missing break.
516 * msp430-decode.opc (encode_as): Likewise.
517 * msp430-decode.c: Regenerate.
518
616ec358
AM		 5192016-10-06 Alan Modra <amodra@gmail.com>
520
521 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
522 * crx-dis.c (print_insn_crx): Likewise.
523
72da393d
L		 5242016-09-30 H.J. Lu <hongjiu.lu@intel.com>
525
526 PR binutils/20657
527 * i386-dis.c (putop): Don't assign alt twice.
528
744ce302
JW		 5292016-09-29 Jiong Wang <jiong.wang@arm.com>
530
531 PR target/20553
532 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
533
a5721ba2
AM		 5342016-09-29 Alan Modra <amodra@gmail.com>
535
536 * ppc-opc.c (L): Make compulsory.
537 (LOPT): New, optional form of L.
538 (HTM_R): Define as LOPT.
539 (L0, L1): Delete.
540 (L32OPT): New, optional for 32-bit L.
541 (L2OPT): New, 2-bit L for dcbf.
542 (SVC_LEC): Update.
543 (L2): Define.
544 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
545 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
546 <dcbf>: Use L2OPT.
547 <tlbiel, tlbie>: Use LOPT.
548 <wclr, wclrall>: Use L2.
549
c5da1932
VZ		 5502016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
551
552 * Makefile.in: Regenerate.
553 * configure: Likewise.
554
2b848ebd
CZ		 5552016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
556
557 * arc-ext-tbl.h (EXTINSN2OPF): Define.
558 (EXTINSN2OP): Use EXTINSN2OPF.
559 (bspeekm, bspop, modapp): New extension instructions.
560 * arc-opc.c (F_DNZ_ND): Define.
561 (F_DNZ_D): Likewise.
562 (F_SIZEB1): Changed.
563 (C_DNZ_D): Define.
564 (C_HARD): Changed.
565 * arc-tbl.h (dbnz): New instruction.
566 (prealloc): Allow it for ARC EM.
567 (xbfu): Likewise.
568
ad43e107
RS		 5692016-09-21 Richard Sandiford <richard.sandiford@arm.com>
570
571 * aarch64-opc.c (print_immediate_offset_address): Print spaces
572 after commas in addresses.
573 (aarch64_print_operand): Likewise.
574
ab3b8fcf
RS		 5752016-09-21 Richard Sandiford <richard.sandiford@arm.com>
576
577 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
578 rather than "should be" or "expected to be" in error messages.
579
bb7eff52
RS		 5802016-09-21 Richard Sandiford <richard.sandiford@arm.com>
581
582 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
583 (print_mnemonic_name): ...here.
584 (print_comment): New function.
585 (print_aarch64_insn): Call it.
586 * aarch64-opc.c (aarch64_conds): Add SVE names.
587 (aarch64_print_operand): Print alternative condition names in
588 a comment.
589
c0890d26
RS		 5902016-09-21 Richard Sandiford <richard.sandiford@arm.com>
591
592 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
593 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
594 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
595 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
596 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
597 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
598 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
599 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
600 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
601 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
602 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
603 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
604 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
605 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
606 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
607 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
608 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
609 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
610 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
611 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
612 (OP_SVE_XWU, OP_SVE_XXU): New macros.
613 (aarch64_feature_sve): New variable.
614 (SVE): New macro.
615 (_SVE_INSN): Likewise.
616 (aarch64_opcode_table): Add SVE instructions.
617 * aarch64-opc.h (extract_fields): Declare.
618 * aarch64-opc-2.c: Regenerate.
619 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
620 * aarch64-asm-2.c: Regenerate.
621 * aarch64-dis.c (extract_fields): Make global.
622 (do_misc_decoding): Handle the new SVE aarch64_ops.
623 * aarch64-dis-2.c: Regenerate.
624
116b6019
RS		 6252016-09-21 Richard Sandiford <richard.sandiford@arm.com>
626
627 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
628 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
629 aarch64_field_kinds.
630 * aarch64-opc.c (fields): Add corresponding entries.
631 * aarch64-asm.c (aarch64_get_variant): New function.
632 (aarch64_encode_variant_using_iclass): Likewise.
633 (aarch64_opcode_encode): Call it.
634 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
635 (aarch64_opcode_decode): Call it.
636
047cd301
RS		 6372016-09-21 Richard Sandiford <richard.sandiford@arm.com>
638
639 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
640 and FP register operands.
641 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
642 (FLD_SVE_Vn): New aarch64_field_kinds.
643 * aarch64-opc.c (fields): Add corresponding entries.
644 (aarch64_print_operand): Handle the new SVE core and FP register
645 operands.
646 * aarch64-opc-2.c: Regenerate.
647 * aarch64-asm-2.c: Likewise.
648 * aarch64-dis-2.c: Likewise.
649
165d4950
RS		 6502016-09-21 Richard Sandiford <richard.sandiford@arm.com>
651
652 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
653 immediate operands.
654 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
655 * aarch64-opc.c (fields): Add corresponding entry.
656 (operand_general_constraint_met_p): Handle the new SVE FP immediate
657 operands.
658 (aarch64_print_operand): Likewise.
659 * aarch64-opc-2.c: Regenerate.
660 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
661 (ins_sve_float_zero_one): New inserters.
662 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
663 (aarch64_ins_sve_float_half_two): Likewise.
664 (aarch64_ins_sve_float_zero_one): Likewise.
665 * aarch64-asm-2.c: Regenerate.
666 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
667 (ext_sve_float_zero_one): New extractors.
668 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
669 (aarch64_ext_sve_float_half_two): Likewise.
670 (aarch64_ext_sve_float_zero_one): Likewise.
671 * aarch64-dis-2.c: Regenerate.
672
e950b345
RS		 6732016-09-21 Richard Sandiford <richard.sandiford@arm.com>
674
675 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
676 integer immediate operands.
677 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
678 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
679 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
680 * aarch64-opc.c (fields): Add corresponding entries.
681 (operand_general_constraint_met_p): Handle the new SVE integer
682 immediate operands.
683 (aarch64_print_operand): Likewise.
684 (aarch64_sve_dupm_mov_immediate_p): New function.
685 * aarch64-opc-2.c: Regenerate.
686 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
687 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
688 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
689 (aarch64_ins_limm): ...here.
690 (aarch64_ins_inv_limm): New function.
691 (aarch64_ins_sve_aimm): Likewise.
692 (aarch64_ins_sve_asimm): Likewise.
693 (aarch64_ins_sve_limm_mov): Likewise.
694 (aarch64_ins_sve_shlimm): Likewise.
695 (aarch64_ins_sve_shrimm): Likewise.
696 * aarch64-asm-2.c: Regenerate.
697 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
698 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
699 * aarch64-dis.c (decode_limm): New function, split out from...
700 (aarch64_ext_limm): ...here.
701 (aarch64_ext_inv_limm): New function.
702 (decode_sve_aimm): Likewise.
703 (aarch64_ext_sve_aimm): Likewise.
704 (aarch64_ext_sve_asimm): Likewise.
705 (aarch64_ext_sve_limm_mov): Likewise.
706 (aarch64_top_bit): Likewise.
707 (aarch64_ext_sve_shlimm): Likewise.
708 (aarch64_ext_sve_shrimm): Likewise.
709 * aarch64-dis-2.c: Regenerate.
710
98907a70
RS		 7112016-09-21 Richard Sandiford <richard.sandiford@arm.com>
712
713 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
714 operands.
715 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
716 the AARCH64_MOD_MUL_VL entry.
717 (value_aligned_p): Cope with non-power-of-two alignments.
718 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
719 (print_immediate_offset_address): Likewise.
720 (aarch64_print_operand): Likewise.
721 * aarch64-opc-2.c: Regenerate.
722 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
723 (ins_sve_addr_ri_s9xvl): New inserters.
724 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
725 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
726 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
727 * aarch64-asm-2.c: Regenerate.
728 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
729 (ext_sve_addr_ri_s9xvl): New extractors.
730 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
731 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
732 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
733 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
734 * aarch64-dis-2.c: Regenerate.
735
4df068de
RS		 7362016-09-21 Richard Sandiford <richard.sandiford@arm.com>
737
738 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
739 address operands.
740 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
741 (FLD_SVE_xs_22): New aarch64_field_kinds.
742 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
743 (get_operand_specific_data): New function.
744 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
745 FLD_SVE_xs_14 and FLD_SVE_xs_22.
746 (operand_general_constraint_met_p): Handle the new SVE address
747 operands.
748 (sve_reg): New array.
749 (get_addr_sve_reg_name): New function.
750 (aarch64_print_operand): Handle the new SVE address operands.
751 * aarch64-opc-2.c: Regenerate.
752 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
753 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
754 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
755 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
756 (aarch64_ins_sve_addr_rr_lsl): Likewise.
757 (aarch64_ins_sve_addr_rz_xtw): Likewise.
758 (aarch64_ins_sve_addr_zi_u5): Likewise.
759 (aarch64_ins_sve_addr_zz): Likewise.
760 (aarch64_ins_sve_addr_zz_lsl): Likewise.
761 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
762 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
763 * aarch64-asm-2.c: Regenerate.
764 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
765 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
766 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
767 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
768 (aarch64_ext_sve_addr_ri_u6): Likewise.
769 (aarch64_ext_sve_addr_rr_lsl): Likewise.
770 (aarch64_ext_sve_addr_rz_xtw): Likewise.
771 (aarch64_ext_sve_addr_zi_u5): Likewise.
772 (aarch64_ext_sve_addr_zz): Likewise.
773 (aarch64_ext_sve_addr_zz_lsl): Likewise.
774 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
775 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
776 * aarch64-dis-2.c: Regenerate.
777
2442d846
RS		 7782016-09-21 Richard Sandiford <richard.sandiford@arm.com>
779
780 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
781 AARCH64_OPND_SVE_PATTERN_SCALED.
782 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
783 * aarch64-opc.c (fields): Add a corresponding entry.
784 (set_multiplier_out_of_range_error): New function.
785 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
786 (operand_general_constraint_met_p): Handle
787 AARCH64_OPND_SVE_PATTERN_SCALED.
788 (print_register_offset_address): Use PRIi64 to print the
789 shift amount.
790 (aarch64_print_operand): Likewise. Handle
791 AARCH64_OPND_SVE_PATTERN_SCALED.
792 * aarch64-opc-2.c: Regenerate.
793 * aarch64-asm.h (ins_sve_scale): New inserter.
794 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
795 * aarch64-asm-2.c: Regenerate.
796 * aarch64-dis.h (ext_sve_scale): New inserter.
797 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
798 * aarch64-dis-2.c: Regenerate.
799
245d2e3f
RS		 8002016-09-21 Richard Sandiford <richard.sandiford@arm.com>
801
802 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
803 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
804 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
805 (FLD_SVE_prfop): Likewise.
806 * aarch64-opc.c: Include libiberty.h.
807 (aarch64_sve_pattern_array): New variable.
808 (aarch64_sve_prfop_array): Likewise.
809 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
810 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
811 AARCH64_OPND_SVE_PRFOP.
812 * aarch64-asm-2.c: Regenerate.
813 * aarch64-dis-2.c: Likewise.
814 * aarch64-opc-2.c: Likewise.
815
d50c751e
RS		 8162016-09-21 Richard Sandiford <richard.sandiford@arm.com>
817
818 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
819 AARCH64_OPND_QLF_P_[ZM].
820 (aarch64_print_operand): Print /z and /m where appropriate.
821
f11ad6bc
RS		 8222016-09-21 Richard Sandiford <richard.sandiford@arm.com>
823
824 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
825 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
826 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
827 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
828 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
829 * aarch64-opc.c (fields): Add corresponding entries here.
830 (operand_general_constraint_met_p): Check that SVE register lists
831 have the correct length. Check the ranges of SVE index registers.
832 Check for cases where p8-p15 are used in 3-bit predicate fields.
833 (aarch64_print_operand): Handle the new SVE operands.
834 * aarch64-opc-2.c: Regenerate.
835 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
836 * aarch64-asm.c (aarch64_ins_sve_index): New function.
837 (aarch64_ins_sve_reglist): Likewise.
838 * aarch64-asm-2.c: Regenerate.
839 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
840 * aarch64-dis.c (aarch64_ext_sve_index): New function.
841 (aarch64_ext_sve_reglist): Likewise.
842 * aarch64-dis-2.c: Regenerate.
843
0c608d6b
RS		 8442016-09-21 Richard Sandiford <richard.sandiford@arm.com>
845
846 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
847 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
848 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
849 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
850 tied operands.
851
01dbfe4c
RS		 8522016-09-21 Richard Sandiford <richard.sandiford@arm.com>
853
854 * aarch64-opc.c (get_offset_int_reg_name): New function.
855 (print_immediate_offset_address): Likewise.
856 (print_register_offset_address): Take the base and offset
857 registers as parameters.
858 (aarch64_print_operand): Update caller accordingly. Use
859 print_immediate_offset_address.
860
72e9f319
RS		 8612016-09-21 Richard Sandiford <richard.sandiford@arm.com>
862
863 * aarch64-opc.c (BANK): New macro.
864 (R32, R64): Take a register number as argument
865 (int_reg): Use BANK.
866
8a7f0c1b
RS		 8672016-09-21 Richard Sandiford <richard.sandiford@arm.com>
868
869 * aarch64-opc.c (print_register_list): Add a prefix parameter.
870 (aarch64_print_operand): Update accordingly.
871
aa2aa4c6
RS		 8722016-09-21 Richard Sandiford <richard.sandiford@arm.com>
873
874 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
875 for FPIMM.
876 * aarch64-asm.h (ins_fpimm): New inserter.
877 * aarch64-asm.c (aarch64_ins_fpimm): New function.
878 * aarch64-asm-2.c: Regenerate.
879 * aarch64-dis.h (ext_fpimm): New extractor.
880 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
881 (aarch64_ext_fpimm): New function.
882 * aarch64-dis-2.c: Regenerate.
883
b5464a68
RS		 8842016-09-21 Richard Sandiford <richard.sandiford@arm.com>
885
886 * aarch64-asm.c: Include libiberty.h.
887 (insert_fields): New function.
888 (aarch64_ins_imm): Use it.
889 * aarch64-dis.c (extract_fields): New function.
890 (aarch64_ext_imm): Use it.
891
42408347
RS		 8922016-09-21 Richard Sandiford <richard.sandiford@arm.com>
893
894 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
895 with an esize parameter.
896 (operand_general_constraint_met_p): Update accordingly.
897 Fix misindented code.
898 * aarch64-asm.c (aarch64_ins_limm): Update call to
899 aarch64_logical_immediate_p.
900
4989adac
RS		 9012016-09-21 Richard Sandiford <richard.sandiford@arm.com>
902
903 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
904
bd11d5d8
RS		 9052016-09-21 Richard Sandiford <richard.sandiford@arm.com>
906
907 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
908
f807f43d
CZ		 9092016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
910
911 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
912
fd486b63
PB		 9132016-09-14 Peter Bergner <bergner@vnet.ibm.com>
914
915 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
916 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
917 xor3>: Delete mnemonics.
918 <cp_abort>: Rename mnemonic from ...
919 <cpabort>: ...to this.
920 <setb>: Change to a X form instruction.
921 <sync>: Change to 1 operand form.
922 <copy>: Delete mnemonic.
923 <copy_first>: Rename mnemonic from ...
924 <copy>: ...to this.
925 <paste, paste.>: Delete mnemonics.
926 <paste_last>: Rename mnemonic from ...
927 <paste.>: ...to this.
928
dce08442
AK		 9292016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
930
931 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
932
952c3f51
AK		 9332016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
934
935 * s390-mkopc.c (main): Support alternate arch strings.
936
8b71537b
PS		 9372016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
938
939 * s390-opc.txt: Fix kmctr instruction type.
940
5b64d091
L		 9412016-09-07 H.J. Lu <hongjiu.lu@intel.com>
942
943 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
944 * i386-init.h: Regenerated.
945
7763838e
CM		 9462016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
947
948 * opcodes/arc-dis.c (print_insn_arc): Changed.
949
1b8b6532
JM		 9502016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
951
952 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
953 camellia_fl.
954
1a336194
TP		 9552016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
956
957 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
958 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
959 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
960
6b40c462
L		 9612016-08-24 H.J. Lu <hongjiu.lu@intel.com>
962
963 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
964 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
965 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
966 PREFIX_MOD_3_0FAE_REG_4.
967 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
968 PREFIX_MOD_3_0FAE_REG_4.
969 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
970 (cpu_flags): Add CpuPTWRITE.
971 * i386-opc.h (CpuPTWRITE): New.
972 (i386_cpu_flags): Add cpuptwrite.
973 * i386-opc.tbl: Add ptwrite instruction.
974 * i386-init.h: Regenerated.
975 * i386-tbl.h: Likewise.
976
ab548d2d
AK		 9772016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
978
979 * arc-dis.h: Wrap around in extern "C".
980
344bde0a
RS		 9812016-08-23 Richard Sandiford <richard.sandiford@arm.com>
982
983 * aarch64-tbl.h (V8_2_INSN): New macro.
984 (aarch64_opcode_table): Use it.
985
5ce912d8
RS		 9862016-08-23 Richard Sandiford <richard.sandiford@arm.com>
987
988 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
989 CORE_INSN, __FP_INSN and SIMD_INSN.
990
9d30b0bd
RS		 9912016-08-23 Richard Sandiford <richard.sandiford@arm.com>
992
993 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
994 (aarch64_opcode_table): Update uses accordingly.
995
dfdaec14
AJ		 9962016-07-25 Andrew Jenner <andrew@codesourcery.com>
997 Kwok Cheung Yeung <kcy@codesourcery.com>
998
999 opcodes/
1000 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1001 'e_cmplwi' to 'e_cmpli' instead.
1002 (OPVUPRT, OPVUPRT_MASK): Define.
1003 (powerpc_opcodes): Add E200Z4 insns.
1004 (vle_opcodes): Add context save/restore insns.
1005
7bd374a4
MR		 10062016-07-27 Maciej W. Rozycki <macro@imgtec.com>
1007
1008 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1009 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1010 "j".
1011
db18dbab
GM		 10122016-07-27 Graham Markall <graham.markall@embecosm.com>
1013
1014 * arc-nps400-tbl.h: Change block comments to GNU format.
1015 * arc-dis.c: Add new globals addrtypenames,
1016 addrtypenames_max, and addtypeunknown.
1017 (get_addrtype): New function.
1018 (print_insn_arc): Print colons and address types when
1019 required.
1020 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1021 define insert and extract functions for all address types.
1022 (arc_operands): Add operands for colon and all address
1023 types.
1024 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1025 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1026 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1027 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1028 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1029 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1030
fecd57f9
L		 10312016-07-21 H.J. Lu <hongjiu.lu@intel.com>
1032
1033 * configure: Regenerated.
1034
37fd5ef3
CZ		 10352016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
1036
1037 * arc-dis.c (skipclass): New structure.
1038 (decodelist): New variable.
1039 (is_compatible_p): New function.
1040 (new_element): Likewise.
1041 (skip_class_p): Likewise.
1042 (find_format_from_table): Use skip_class_p function.
1043 (find_format): Decode first the extension instructions.
1044 (print_insn_arc): Select either ARCEM or ARCHS based on elf
1045 e_flags.
1046 (parse_option): New function.
1047 (parse_disassembler_options): Likewise.
1048 (print_arc_disassembler_options): Likewise.
1049 (print_insn_arc): Use parse_disassembler_options function. Proper
1050 select ARCv2 cpu variant.
1051 * disassemble.c (disassembler_usage): Add ARC disassembler
1052 options.
1053
92281a5b
MR		 10542016-07-13 Maciej W. Rozycki <macro@imgtec.com>
1055
1056 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1057 annotation from the "nal" entry and reorder it beyond "bltzal".
1058
6e7ced37
JM		 10592016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
1060
1061 * sparc-opc.c (ldtxa): New macro.
1062 (sparc_opcodes): Use the macro defined above to add entries for
1063 the LDTXA instructions.
1064 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1065 instruction.
1066
2f831b9a 10672016-07-07 James Bowman <james.bowman@ftdichip.com>
1068
1069 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1070 and "jmpc".
1071
c07315e0
JB		 10722016-07-01 Jan Beulich <jbeulich@suse.com>
1073
1074 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1075 (movzb): Adjust to cover all permitted suffixes.
1076 (movzw): New.
1077 * i386-tbl.h: Re-generate.
1078
9243100a
JB		 10792016-07-01 Jan Beulich <jbeulich@suse.com>
1080
1081 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1082 (lgdt): Remove Tbyte from non-64-bit variant.
1083 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1084 xsaves64, xsavec64): Remove Disp16.
1085 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1086 Remove Disp32S from non-64-bit variants. Remove Disp16 from
1087 64-bit variants.
1088 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1089 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1090 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1091 64-bit variants.
1092 * i386-tbl.h: Re-generate.
1093
8325cc63
JB		 10942016-07-01 Jan Beulich <jbeulich@suse.com>
1095
1096 * i386-opc.tbl (xlat): Remove RepPrefixOk.
1097 * i386-tbl.h: Re-generate.
1098
838441e4
YQ		 10992016-06-30 Yao Qi <yao.qi@linaro.org>
1100
1101 * arm-dis.c (print_insn): Fix typo in comment.
1102
dab26bf4
RS		 11032016-06-28 Richard Sandiford <richard.sandiford@arm.com>
1104
1105 * aarch64-opc.c (operand_general_constraint_met_p): Check the
1106 range of ldst_elemlist operands.
1107 (print_register_list): Use PRIi64 to print the index.
1108 (aarch64_print_operand): Likewise.
1109
5703197e
TS		 11102016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1111
1112 * mcore-opc.h: Remove sentinal.
1113 * mcore-dis.c (print_insn_mcore): Adjust.
1114
ce440d63
GM		 11152016-06-23 Graham Markall <graham.markall@embecosm.com>
1116
1117 * arc-opc.c: Correct description of availability of NPS400
1118 features.
1119
6fd3a02d
PB		 11202016-06-22 Peter Bergner <bergner@vnet.ibm.com>
1121
1122 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1123 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1124 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1125 xor3>: New mnemonics.
1126 <setb>: Change to a VX form instruction.
1127 (insert_sh6): Add support for rldixor.
1128 (extract_sh6): Likewise.
1129
6b477896
TS		 11302016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1131
1132 * arc-ext.h: Wrap in extern C.
1133
bdd582db
GM		 11342016-06-21 Graham Markall <graham.markall@embecosm.com>
1135
1136 * arc-dis.c (arc_insn_length): Add comment on instruction length.
1137 Use same method for determining instruction length on ARC700 and
1138 NPS-400.
1139 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1140 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1141 with the NPS400 subclass.
1142 * arc-opc.c: Likewise.
1143
96074adc
JM		 11442016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1145
1146 * sparc-opc.c (rdasr): New macro.
1147 (wrasr): Likewise.
1148 (rdpr): Likewise.
1149 (wrpr): Likewise.
1150 (rdhpr): Likewise.
1151 (wrhpr): Likewise.
1152 (sparc_opcodes): Use the macros above to fix and expand the
1153 definition of read/write instructions from/to
1154 asr/privileged/hyperprivileged instructions.
1155 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1156 %hva_mask_nz. Prefer softint_set and softint_clear over
1157 set_softint and clear_softint.
1158 (print_insn_sparc): Support %ver in Rd.
1159
7a10c22f
JM		 11602016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1161
1162 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1163 architecture according to the hardware capabilities they require.
1164
4f26fb3a
JM		 11652016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1166
1167 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1168 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1169 bfd_mach_sparc_v9{c,d,e,v,m}.
1170 * sparc-opc.c (MASK_V9C): Define.
1171 (MASK_V9D): Likewise.
1172 (MASK_V9E): Likewise.
1173 (MASK_V9V): Likewise.
1174 (MASK_V9M): Likewise.
1175 (v6): Add MASK_V9{C,D,E,V,M}.
1176 (v6notlet): Likewise.
1177 (v7): Likewise.
1178 (v8): Likewise.
1179 (v9): Likewise.
1180 (v9andleon): Likewise.
1181 (v9a): Likewise.
1182 (v9b): Likewise.
1183 (v9c): Define.
1184 (v9d): Likewise.
1185 (v9e): Likewise.
1186 (v9v): Likewise.
1187 (v9m): Likewise.
1188 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1189
3ee6e4fb
NC		 11902016-06-15 Nick Clifton <nickc@redhat.com>
1191
1192 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1193 constants to match expected behaviour.
1194 (nds32_parse_opcode): Likewise. Also for whitespace.
1195
02f3be19
AB		 11962016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1197
1198 * arc-opc.c (extract_rhv1): Extract value from insn.
1199
6f9f37ed 12002016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 1201
1202 * arc-nps400-tbl.h: Add ldbit instruction.
1203 * arc-opc.c: Add flag classes required for ldbit.
1204
6f9f37ed 12052016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 1206
1207 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1208 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1209 support the above instructions.
1210
6f9f37ed 12112016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 1212
1213 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1214 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1215 csma, cbba, zncv, and hofs.
1216 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1217 support the above instructions.
1218
12192016-06-06 Graham Markall <graham.markall@embecosm.com>
1220
1221 * arc-nps400-tbl.h: Add andab and orab instructions.
1222
12232016-06-06 Graham Markall <graham.markall@embecosm.com>
1224
1225 * arc-nps400-tbl.h: Add addl-like instructions.
1226
12272016-06-06 Graham Markall <graham.markall@embecosm.com>
1228
1229 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1230
12312016-06-06 Graham Markall <graham.markall@embecosm.com>
1232
1233 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1234 instructions.
1235
b2cc3f6f
AK		 12362016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1237
1238 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1239 variable.
1240 (init_disasm): Handle new command line option "insnlength".
1241 (print_s390_disassembler_options): Mention new option in help
1242 output.
1243 (print_insn_s390): Use the encoded insn length when dumping
1244 unknown instructions.
1245
1857fe72
DC		 12462016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1247
1248 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1249 to the address and set as symbol address for LDS/ STS immediate operands.
1250
14b57c7c
AM		 12512016-06-07 Alan Modra <amodra@gmail.com>
1252
1253 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1254 cpu for "vle" to e500.
1255 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1256 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1257 (PPCNONE): Delete, substitute throughout.
1258 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1259 except for major opcode 4 and 31.
1260 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1261
4d1464f2
MW		 12622016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1263
1264 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1265 ARM_EXT_RAS in relevant entries.
1266
026122a6
PB		 12672016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1268
1269 PR binutils/20196
1270 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1271 opcodes for E6500.
1272
07f5af7d
L		 12732016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1274
1275 PR binutis/18386
1276 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1277 (indir_v_mode): New.
1278 Add comments for '&'.
1279 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1280 (putop): Handle '&'.
1281 (intel_operand_size): Handle indir_v_mode.
1282 (OP_E_register): Likewise.
1283 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1284 64-bit indirect call/jmp for AMD64.
1285 * i386-tbl.h: Regenerated
1286
4eb6f892
AB		 12872016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1288
1289 * arc-dis.c (struct arc_operand_iterator): New structure.
1290 (find_format_from_table): All the old content from find_format,
1291 with some minor adjustments, and parameter renaming.
1292 (find_format_long_instructions): New function.
1293 (find_format): Rewritten.
1294 (arc_insn_length): Add LSB parameter.
1295 (extract_operand_value): New function.
1296 (operand_iterator_next): New function.
1297 (print_insn_arc): Use new functions to find opcode, and iterator
1298 over operands.
1299 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1300 (extract_nps_3bit_dst_short): New function.
1301 (insert_nps_3bit_src2_short): New function.
1302 (extract_nps_3bit_src2_short): New function.
1303 (insert_nps_bitop1_size): New function.
1304 (extract_nps_bitop1_size): New function.
1305 (insert_nps_bitop2_size): New function.
1306 (extract_nps_bitop2_size): New function.
1307 (insert_nps_bitop_mod4_msb): New function.
1308 (extract_nps_bitop_mod4_msb): New function.
1309 (insert_nps_bitop_mod4_lsb): New function.
1310 (extract_nps_bitop_mod4_lsb): New function.
1311 (insert_nps_bitop_dst_pos3_pos4): New function.
1312 (extract_nps_bitop_dst_pos3_pos4): New function.
1313 (insert_nps_bitop_ins_ext): New function.
1314 (extract_nps_bitop_ins_ext): New function.
1315 (arc_operands): Add new operands.
1316 (arc_long_opcodes): New global array.
1317 (arc_num_long_opcodes): New global.
1318 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1319
1fe0971e
TS		 13202016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1321
1322 * nds32-asm.h: Add extern "C".
1323 * sh-opc.h: Likewise.
1324
315f180f
GM		 13252016-06-01 Graham Markall <graham.markall@embecosm.com>
1326
1327 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1328 0,b,limm to the rflt instruction.
1329
a2b5fccc
TS		 13302016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1331
1332 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1333 constant.
1334
0cbd0046
L		 13352016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1336
1337 PR gas/20145
1338 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1339 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1340 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1341 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1342 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1343 * i386-init.h: Regenerated.
1344
1848e567
L		 13452016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1346
1347 PR gas/20145
1348 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1349 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1350 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1351 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1352 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1353 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1354 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1355 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1356 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1357 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1358 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1359 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1360 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1361 CpuRegMask for AVX512.
1362 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1363 and CpuRegMask.
1364 (set_bitfield_from_cpu_flag_init): New function.
1365 (set_bitfield): Remove const on f. Call
1366 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1367 * i386-opc.h (CpuRegMMX): New.
1368 (CpuRegXMM): Likewise.
1369 (CpuRegYMM): Likewise.
1370 (CpuRegZMM): Likewise.
1371 (CpuRegMask): Likewise.
1372 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1373 and cpuregmask.
1374 * i386-init.h: Regenerated.
1375 * i386-tbl.h: Likewise.
1376
e92bae62
L		 13772016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1378
1379 PR gas/20154
1380 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1381 (opcode_modifiers): Add AMD64 and Intel64.
1382 (main): Properly verify CpuMax.
1383 * i386-opc.h (CpuAMD64): Removed.
1384 (CpuIntel64): Likewise.
1385 (CpuMax): Set to CpuNo64.
1386 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1387 (AMD64): New.
1388 (Intel64): Likewise.
1389 (i386_opcode_modifier): Add amd64 and intel64.
1390 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1391 on call and jmp.
1392 * i386-init.h: Regenerated.
1393 * i386-tbl.h: Likewise.
1394
e89c5eaa
L		 13952016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1396
1397 PR gas/20154
1398 * i386-gen.c (main): Fail if CpuMax is incorrect.
1399 * i386-opc.h (CpuMax): Set to CpuIntel64.
1400 * i386-tbl.h: Regenerated.
1401
77d66e7b
NC		 14022016-05-27 Nick Clifton <nickc@redhat.com>
1403
1404 PR target/20150
1405 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1406 (msp430dis_opcode_unsigned): New function.
1407 (msp430dis_opcode_signed): New function.
1408 (msp430_singleoperand): Use the new opcode reading functions.
1409 Only disassenmble bytes if they were successfully read.
1410 (msp430_doubleoperand): Likewise.
1411 (msp430_branchinstr): Likewise.
1412 (msp430x_callx_instr): Likewise.
1413 (print_insn_msp430): Check that it is safe to read bytes before
1414 attempting disassembly. Use the new opcode reading functions.
1415
19dfcc89
PB		 14162016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1417
1418 * ppc-opc.c (CY): New define. Document it.
1419 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1420
f3ad7637
L		 14212016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1422
1423 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1424 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1425 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1426 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1427 CPU_ANY_AVX_FLAGS.
1428 * i386-init.h: Regenerated.
1429
f1360d58
L		 14302016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1431
1432 PR gas/20141
1433 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1434 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1435 * i386-init.h: Regenerated.
1436
293f5f65
L		 14372016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1438
1439 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1440 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1441 * i386-init.h: Regenerated.
1442
d9eca1df
CZ		 14432016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1444
1445 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1446 information.
1447 (print_insn_arc): Set insn_type information.
1448 * arc-opc.c (C_CC): Add F_CLASS_COND.
1449 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1450 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1451 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1452 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1453 (brne, brne_s, jeq_s, jne_s): Likewise.
1454
87789e08
CZ		 14552016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1456
1457 * arc-tbl.h (neg): New instruction variant.
1458
c810e0b8
CZ		 14592016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1460
1461 * arc-dis.c (find_format, find_format, get_auxreg)
1462 (print_insn_arc): Changed.
1463 * arc-ext.h (INSERT_XOP): Likewise.
1464
3d207518
TS		 14652016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1466
1467 * tic54x-dis.c (sprint_mmr): Adjust.
1468 * tic54x-opc.c: Likewise.
1469
514e58b7
AM		 14702016-05-19 Alan Modra <amodra@gmail.com>
1471
1472 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1473
e43de63c
AM		 14742016-05-19 Alan Modra <amodra@gmail.com>
1475
1476 * ppc-opc.c: Formatting.
1477 (NSISIGNOPT): Define.
1478 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1479
1401d2fe
MR		 14802016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1481
1482 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1483 replacing references to `micromips_ase' throughout.
1484 (_print_insn_mips): Don't use file-level microMIPS annotation to
1485 determine the disassembly mode with the symbol table.
1486
1178da44
PB		 14872016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1488
1489 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1490
8f4f9071
MF		 14912016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1492
1493 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1494 mips64r6.
1495 * mips-opc.c (D34): New macro.
1496 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1497
8bc52696
AF		 14982016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1499
1500 * i386-dis.c (prefix_table): Add RDPID instruction.
1501 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1502 (cpu_flags): Add RDPID bitfield.
1503 * i386-opc.h (enum): Add RDPID element.
1504 (i386_cpu_flags): Add RDPID field.
1505 * i386-opc.tbl: Add RDPID instruction.
1506 * i386-init.h: Regenerate.
1507 * i386-tbl.h: Regenerate.
1508
39d911fc
TP		 15092016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1510
1511 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1512 branch type of a symbol.
1513 (print_insn): Likewise.
1514
16a1fa25
TP		 15152016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1516
1517 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1518 Mainline Security Extensions instructions.
1519 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1520 Extensions instructions.
1521 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1522 instructions.
1523 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1524 special registers.
1525
d751b79e
JM		 15262016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1527
1528 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1529
945e0f82
CZ		 15302016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1531
1532 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1533 (arcExtMap_genOpcode): Likewise.
1534 * arc-opc.c (arg_32bit_rc): Define new variable.
1535 (arg_32bit_u6): Likewise.
1536 (arg_32bit_limm): Likewise.
1537
20f55f38
SN		 15382016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1539
1540 * aarch64-gen.c (VERIFIER): Define.
1541 * aarch64-opc.c (VERIFIER): Define.
1542 (verify_ldpsw): Use static linkage.
1543 * aarch64-opc.h (verify_ldpsw): Remove.
1544 * aarch64-tbl.h: Use VERIFIER for verifiers.
1545
4bd13cde
NC		 15462016-04-28 Nick Clifton <nickc@redhat.com>
1547
1548 PR target/19722
1549 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1550 * aarch64-opc.c (verify_ldpsw): New function.
1551 * aarch64-opc.h (verify_ldpsw): New prototype.
1552 * aarch64-tbl.h: Add initialiser for verifier field.
1553 (LDPSW): Set verifier to verify_ldpsw.
1554
c0f92bf9
L		 15552016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1556
1557 PR binutils/19983
1558 PR binutils/19984
1559 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1560 smaller than address size.
1561
e6c7cdec
TS		 15622016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1563
1564 * alpha-dis.c: Regenerate.
1565 * crx-dis.c: Likewise.
1566 * disassemble.c: Likewise.
1567 * epiphany-opc.c: Likewise.
1568 * fr30-opc.c: Likewise.
1569 * frv-opc.c: Likewise.
1570 * ip2k-opc.c: Likewise.
1571 * iq2000-opc.c: Likewise.
1572 * lm32-opc.c: Likewise.
1573 * lm32-opinst.c: Likewise.
1574 * m32c-opc.c: Likewise.
1575 * m32r-opc.c: Likewise.
1576 * m32r-opinst.c: Likewise.
1577 * mep-opc.c: Likewise.
1578 * mt-opc.c: Likewise.
1579 * or1k-opc.c: Likewise.
1580 * or1k-opinst.c: Likewise.
1581 * tic80-opc.c: Likewise.
1582 * xc16x-opc.c: Likewise.
1583 * xstormy16-opc.c: Likewise.
1584
537aefaf
AB		 15852016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1586
1587 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1588 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1589 calcsd, and calcxd instructions.
1590 * arc-opc.c (insert_nps_bitop_size): Delete.
1591 (extract_nps_bitop_size): Delete.
1592 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1593 (extract_nps_qcmp_m3): Define.
1594 (extract_nps_qcmp_m2): Define.
1595 (extract_nps_qcmp_m1): Define.
1596 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1597 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1598 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1599 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1600 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1601 NPS_QCMP_M3.
1602
c8f785f2
AB		 16032016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1604
1605 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1606
6fd8e7c2
L		 16072016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1608
1609 * Makefile.in: Regenerated with automake 1.11.6.
1610 * aclocal.m4: Likewise.
1611
4b0c052e
AB		 16122016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1613
1614 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1615 instructions.
1616 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1617 (extract_nps_cmem_uimm16): New function.
1618 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1619
cb040366
AB		 16202016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1621
1622 * arc-dis.c (arc_insn_length): New function.
1623 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1624 (find_format): Change insnLen parameter to unsigned.
1625
accc0180
NC		 16262016-04-13 Nick Clifton <nickc@redhat.com>
1627
1628 PR target/19937
1629 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1630 the LD.B and LD.BU instructions.
1631
f36e33da
CZ		 16322016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1633
1634 * arc-dis.c (find_format): Check for extension flags.
1635 (print_flags): New function.
1636 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1637 .extAuxRegister.
1638 * arc-ext.c (arcExtMap_coreRegName): Use
1639 LAST_EXTENSION_CORE_REGISTER.
1640 (arcExtMap_coreReadWrite): Likewise.
1641 (dump_ARC_extmap): Update printing.
1642 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1643 (arc_aux_regs): Add cpu field.
1644 * arc-regs.h: Add cpu field, lower case name aux registers.
1645
1c2e355e
CZ		 16462016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1647
1648 * arc-tbl.h: Add rtsc, sleep with no arguments.
1649
b99747ae
CZ		 16502016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1651
1652 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1653 Initialize.
1654 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1655 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1656 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1657 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1658 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1659 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1660 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1661 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1662 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1663 (arc_opcode arc_opcodes): Null terminate the array.
1664 (arc_num_opcodes): Remove.
1665 * arc-ext.h (INSERT_XOP): Define.
1666 (extInstruction_t): Likewise.
1667 (arcExtMap_instName): Delete.
1668 (arcExtMap_insn): New function.
1669 (arcExtMap_genOpcode): Likewise.
1670 * arc-ext.c (ExtInstruction): Remove.
1671 (create_map): Zero initialize instruction fields.
1672 (arcExtMap_instName): Remove.
1673 (arcExtMap_insn): New function.
1674 (dump_ARC_extmap): More info while debuging.
1675 (arcExtMap_genOpcode): New function.
1676 * arc-dis.c (find_format): New function.
1677 (print_insn_arc): Use find_format.
1678 (arc_get_disassembler): Enable dump_ARC_extmap only when
1679 debugging.
1680
92708cec
MR		 16812016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1682
1683 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1684 instruction bits out.
1685
a42a4f84
AB		 16862016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1687
1688 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1689 * arc-opc.c (arc_flag_operands): Add new flags.
1690 (arc_flag_classes): Add new classes.
1691
1328504b
AB		 16922016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1693
1694 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1695
820f03ff
AB		 16962016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1697
1698 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1699 encode1, rflt, crc16, and crc32 instructions.
1700 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1701 (arc_flag_classes): Add C_NPS_R.
1702 (insert_nps_bitop_size_2b): New function.
1703 (extract_nps_bitop_size_2b): Likewise.
1704 (insert_nps_bitop_uimm8): Likewise.
1705 (extract_nps_bitop_uimm8): Likewise.
1706 (arc_operands): Add new operand entries.
1707
8ddf6b2a
CZ		 17082016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1709
b99747ae
CZ		 1710 * arc-regs.h: Add a new subclass field. Add double assist
1711 accumulator register values.
1712 * arc-tbl.h: Use DPA subclass to mark the double assist
1713 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1714 * arc-opc.c (RSP): Define instead of SP.
1715 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1716
589a7d88
JW		 17172016-04-05 Jiong Wang <jiong.wang@arm.com>
1718
1719 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1720
0a191de9 17212016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1722
1723 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1724 NPS_R_SRC1.
1725
0a106562
AB		 17262016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1727
1728 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1729 issues. No functional changes.
1730
bd05ac5f
CZ		 17312016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1732
b99747ae
CZ		 1733 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1734 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1735 (RTT): Remove duplicate.
1736 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1737 (PCT_CONFIG*): Remove.
1738 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1739
9885948f
CZ		 17402016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1741
b99747ae 1742 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1743
f2dd8838
CZ		 17442016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1745
b99747ae
CZ		 1746 * arc-tbl.h (invld07): Remove.
1747 * arc-ext-tbl.h: New file.
1748 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1749 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1750
0d2f91fe
JK		 17512016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1752
1753 Fix -Wstack-usage warnings.
1754 * aarch64-dis.c (print_operands): Substitute size.
1755 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1756
a6b71f42
JM		 17572016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1758
1759 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1760 to get a proper diagnostic when an invalid ASR register is used.
1761
9780e045
NC		 17622016-03-22 Nick Clifton <nickc@redhat.com>
1763
1764 * configure: Regenerate.
1765
e23e8ebe
AB		 17662016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1767
1768 * arc-nps400-tbl.h: New file.
1769 * arc-opc.c: Add top level comment.
1770 (insert_nps_3bit_dst): New function.
1771 (extract_nps_3bit_dst): New function.
1772 (insert_nps_3bit_src2): New function.
1773 (extract_nps_3bit_src2): New function.
1774 (insert_nps_bitop_size): New function.
1775 (extract_nps_bitop_size): New function.
1776 (arc_flag_operands): Add nps400 entries.
1777 (arc_flag_classes): Add nps400 entries.
1778 (arc_operands): Add nps400 entries.
1779 (arc_opcodes): Add nps400 include.
1780
1ae8ab47
AB		 17812016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1782
1783 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1784 the new class enum values.
1785
8699fc3e
AB		 17862016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1787
1788 * arc-dis.c (print_insn_arc): Handle nps400.
1789
24740d83
AB		 17902016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1791
1792 * arc-opc.c (BASE): Delete.
1793
8678914f
NC		 17942016-03-18 Nick Clifton <nickc@redhat.com>
1795
1796 PR target/19721
1797 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1798 of MOV insn that aliases an ORR insn.
1799
cc933301
JW		 18002016-03-16 Jiong Wang <jiong.wang@arm.com>
1801
1802 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1803
f86f5863
TS		 18042016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1805
1806 * mcore-opc.h: Add const qualifiers.
1807 * microblaze-opc.h (struct op_code_struct): Likewise.
1808 * sh-opc.h: Likewise.
1809 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1810 (tic4x_print_op): Likewise.
1811
62de1c63
AM		 18122016-03-02 Alan Modra <amodra@gmail.com>
1813
d11698cd 1814 * or1k-desc.h: Regenerate.
62de1c63 1815 * fr30-ibld.c: Regenerate.
c697cf0b 1816 * rl78-decode.c: Regenerate.
62de1c63 1817
020efce5
NC		 18182016-03-01 Nick Clifton <nickc@redhat.com>
1819
1820 PR target/19747
1821 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1822
b0c11777
RL		 18232016-02-24 Renlin Li <renlin.li@arm.com>
1824
1825 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1826 (print_insn_coprocessor): Support fp16 instructions.
1827
3e309328
RL		 18282016-02-24 Renlin Li <renlin.li@arm.com>
1829
1830 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1831 vminnm, vrint(mpna).
1832
8afc7bea
RL		 18332016-02-24 Renlin Li <renlin.li@arm.com>
1834
1835 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1836 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1837
4fd7268a
L		 18382016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1839
1840 * i386-dis.c (print_insn): Parenthesize expression to prevent
1841 truncated addresses.
1842 (OP_J): Likewise.
1843
4670103e
CZ		 18442016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1845 Janek van Oirschot <jvanoirs@synopsys.com>
1846
b99747ae
CZ		 1847 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1848 variable.
4670103e 1849
c1d9289f
NC		 18502016-02-04 Nick Clifton <nickc@redhat.com>
1851
1852 PR target/19561
1853 * msp430-dis.c (print_insn_msp430): Add a special case for
1854 decoding an RRC instruction with the ZC bit set in the extension
1855 word.
1856
a143b004
AB		 18572016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1858
1859 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1860 * epiphany-ibld.c: Regenerate.
1861 * fr30-ibld.c: Regenerate.
1862 * frv-ibld.c: Regenerate.
1863 * ip2k-ibld.c: Regenerate.
1864 * iq2000-ibld.c: Regenerate.
1865 * lm32-ibld.c: Regenerate.
1866 * m32c-ibld.c: Regenerate.
1867 * m32r-ibld.c: Regenerate.
1868 * mep-ibld.c: Regenerate.
1869 * mt-ibld.c: Regenerate.
1870 * or1k-ibld.c: Regenerate.
1871 * xc16x-ibld.c: Regenerate.
1872 * xstormy16-ibld.c: Regenerate.
1873
b89807c6
AB		 18742016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1875
1876 * epiphany-dis.c: Regenerated from latest cpu files.
1877
d8c823c8
MM		 18782016-02-01 Michael McConville <mmcco@mykolab.com>
1879
1880 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1881 test bit.
1882
5bc5ae88
RL		 18832016-01-25 Renlin Li <renlin.li@arm.com>
1884
1885 * arm-dis.c (mapping_symbol_for_insn): New function.
1886 (find_ifthen_state): Call mapping_symbol_for_insn().
1887
0bff6e2d
MW		 18882016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1889
1890 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1891 of MSR UAO immediate operand.
1892
100b4f2e
MR		 18932016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1894
1895 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1896 instruction support.
1897
5c14705f
AM		 18982016-01-17 Alan Modra <amodra@gmail.com>
1899
1900 * configure: Regenerate.
1901
4d82fe66
NC		 19022016-01-14 Nick Clifton <nickc@redhat.com>
1903
1904 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1905 instructions that can support stack pointer operations.
1906 * rl78-decode.c: Regenerate.
1907 * rl78-dis.c: Fix display of stack pointer in MOVW based
1908 instructions.
1909
651657fa
MW		 19102016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1911
1912 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1913 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1914 erxtatus_el1 and erxaddr_el1.
1915
105bde57
MW		 19162016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1917
1918 * arm-dis.c (arm_opcodes): Add "esb".
1919 (thumb_opcodes): Likewise.
1920
afa8d405
PB		 19212016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1922
1923 * ppc-opc.c <xscmpnedp>: Delete.
1924 <xvcmpnedp>: Likewise.
1925 <xvcmpnedp.>: Likewise.
1926 <xvcmpnesp>: Likewise.
1927 <xvcmpnesp.>: Likewise.
1928
83c3256e
AS		 19292016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1930
1931 PR gas/13050
1932 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1933 addition to ISA_A.
1934
6f2750fe
AM		 19352016-01-01 Alan Modra <amodra@gmail.com>
1936
1937 Update year range in copyright notice of all files.
1938
3499769a
AM		 1939For older changes see ChangeLog-2015
1940\f
1941Copyright (C) 2016 Free Software Foundation, Inc.
1942
1943Copying and distribution of this file, with or without modification,
1944are permitted in any medium without royalty provided the copyright
1945notice and this notice are preserved.
1946
1947Local Variables:
1948mode: change-log
1949left-margin: 8
1950fill-column: 74
1951version-control: never
1952End:
GDB Binutils - Deliverables
This page took 0.14512 seconds and 4 git commands to generate.