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[AArch64] Add ARMv8.3 javascript floating-point conversion instruction
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
ccfc90a3
SN		 12016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
2
3 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
4 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
5 * aarch64-asm-2.c: Regenerate.
6 * aarch64-dis-2.c: Regenerate.
7 * aarch64-opc-2.c: Regenerate.
8
3f06e550
SN		 92016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
10
11 * aarch64-tbl.h (QL_X1NIL): New.
12 (arch64_opcode_table): Add ldraa, ldrab.
13 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
14 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
15 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
16 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
17 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
18 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
19 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
20 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
21 (aarch64_print_operand): Likewise.
22 * aarch64-asm-2.c: Regenerate.
23 * aarch64-dis-2.c: Regenerate.
24 * aarch64-opc-2.c: Regenerate.
25
74f5402d
SN		 262016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
27
28 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
29 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
30 * aarch64-asm-2.c: Regenerate.
31 * aarch64-dis-2.c: Regenerate.
32 * aarch64-opc-2.c: Regenerate.
33
c84364ec
SN		 342016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
35
36 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
37 (AARCH64_OPERANDS): Add Rm_SP.
38 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
39 * aarch64-asm-2.c: Regenerate.
40 * aarch64-dis-2.c: Regenerate.
41 * aarch64-opc-2.c: Regenerate.
42
a2cfc830
SN		 432016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
44
45 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
46 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
47 autdzb, xpaci, xpacd.
48 * aarch64-asm-2.c: Regenerate.
49 * aarch64-dis-2.c: Regenerate.
50 * aarch64-opc-2.c: Regenerate.
51
b0bfa7b5
SN		 522016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
53
54 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
55 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
56 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
57 (aarch64_sys_reg_supported_p): Add feature test for new registers.
58
8787d804
SN		 592016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
60
61 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
62 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
63 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
64 autibsp.
65 * aarch64-asm-2.c: Regenerate.
66 * aarch64-dis-2.c: Regenerate.
67
3d731f69
SN		 682016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
69
70 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
71
60227d64
L		 722016-11-09 H.J. Lu <hongjiu.lu@intel.com>
73
74 PR binutils/20799
75 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
76 * i386-dis.c (EdqwS): Removed.
77 (dqw_swap_mode): Likewise.
78 (intel_operand_size): Don't check dqw_swap_mode.
79 (OP_E_register): Likewise.
80 (OP_E_memory): Likewise.
81 (OP_G): Likewise.
82 (OP_EX): Likewise.
83 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
84 * i386-tbl.h: Regerated.
85
7efeed17
L		 862016-11-09 H.J. Lu <hongjiu.lu@intel.com>
87
88 * i386-opc.tbl: Merge AVX512F vmovq.
1032d6eb 89 * i386-tbl.h: Regerated.
7efeed17 90
1f334aeb
L		 912016-11-08 H.J. Lu <hongjiu.lu@intel.com>
92
93 PR binutils/20701
94 * i386-dis.c (THREE_BYTE_0F7A): Removed.
95 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
96 (three_byte_table): Remove THREE_BYTE_0F7A.
97
48c97fa1
L		 982016-11-07 H.J. Lu <hongjiu.lu@intel.com>
99
100 PR binutils/20775
101 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
102 (FGRPd9_4): Replace 1 with 2.
103 (FGRPd9_5): Replace 2 with 3.
104 (FGRPd9_6): Replace 3 with 4.
105 (FGRPd9_7): Replace 4 with 5.
106 (FGRPda_5): Replace 5 with 6.
107 (FGRPdb_4): Replace 6 with 7.
108 (FGRPde_3): Replace 7 with 8.
109 (FGRPdf_4): Replace 8 with 9.
110 (fgrps): Add an entry for Bad_Opcode.
111
b437d035
AB		 1122016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
113
114 * arc-opc.c (arc_flag_operands): Add F_DI14.
115 (arc_flag_classes): Add C_DI14.
116 * arc-nps400-tbl.h: Add new exc instructions.
117
5a736821
GM		 1182016-11-03 Graham Markall <graham.markall@embecosm.com>
119
120 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
121 major opcode 0xa.
122 * arc-nps-400-tbl.h: Add dcmac instruction.
123 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
124 (insert_nps_rbdouble_64): Added.
125 (extract_nps_rbdouble_64): Added.
126 (insert_nps_proto_size): Added.
127 (extract_nps_proto_size): Added.
128
bdfe53e3
AB		 1292016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
130
131 * arc-dis.c (struct arc_operand_iterator): Remove all fields
132 relating to long instruction processing, add new limm field.
133 (OPCODE): Rename to...
134 (OPCODE_32BIT_INSN): ...this.
135 (OPCODE_AC): Delete.
136 (skip_this_opcode): Handle different instruction lengths, update
137 macro name.
138 (special_flag_p): Update parameter type.
139 (find_format_from_table): Update for more instruction lengths.
140 (find_format_long_instructions): Delete.
141 (find_format): Update for more instruction lengths.
142 (arc_insn_length): Likewise.
143 (extract_operand_value): Update for more instruction lengths.
144 (operand_iterator_next): Remove code relating to long
145 instructions.
146 (arc_opcode_to_insn_type): New function.
147 (print_insn_arc):Update for more instructions lengths.
148 * arc-ext.c (extInstruction_t): Change argument type.
149 * arc-ext.h (extInstruction_t): Change argument type.
150 * arc-fxi.h: Change type unsigned to unsigned long long
151 extensively throughout.
152 * arc-nps400-tbl.h: Add long instructions taken from
153 arc_long_opcodes table in arc-opc.c.
154 * arc-opc.c: Update parameter types on insert/extract handlers.
155 (arc_long_opcodes): Delete.
156 (arc_num_long_opcodes): Delete.
157 (arc_opcode_len): Update for more instruction lengths.
158
90f61cce
GM		 1592016-11-03 Graham Markall <graham.markall@embecosm.com>
160
161 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
162
06fe285f
GM		 1632016-11-03 Graham Markall <graham.markall@embecosm.com>
164
165 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
166 with arc_opcode_len.
167 (find_format_long_instructions): Likewise.
168 * arc-opc.c (arc_opcode_len): New function.
169
ecf64ec6
AB		 1702016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
171
172 * arc-nps400-tbl.h: Fix some instruction masks.
173
d039fef3
L		 1742016-11-03 H.J. Lu <hongjiu.lu@intel.com>
175
176 * i386-dis.c (REG_82): Removed.
177 (X86_64_82_REG_0): Likewise.
178 (X86_64_82_REG_1): Likewise.
179 (X86_64_82_REG_2): Likewise.
180 (X86_64_82_REG_3): Likewise.
181 (X86_64_82_REG_4): Likewise.
182 (X86_64_82_REG_5): Likewise.
183 (X86_64_82_REG_6): Likewise.
184 (X86_64_82_REG_7): Likewise.
185 (X86_64_82): New.
186 (dis386): Use X86_64_82 instead of REG_82.
187 (reg_table): Remove REG_82.
188 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
189 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
190 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
191 X86_64_82_REG_7.
192
8b89fe14
L		 1932016-11-03 H.J. Lu <hongjiu.lu@intel.com>
194
195 PR binutils/20754
196 * i386-dis.c (REG_82): New.
197 (X86_64_82_REG_0): Likewise.
198 (X86_64_82_REG_1): Likewise.
199 (X86_64_82_REG_2): Likewise.
200 (X86_64_82_REG_3): Likewise.
201 (X86_64_82_REG_4): Likewise.
202 (X86_64_82_REG_5): Likewise.
203 (X86_64_82_REG_6): Likewise.
204 (X86_64_82_REG_7): Likewise.
205 (dis386): Use REG_82.
206 (reg_table): Add REG_82.
207 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
208 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
209 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
210
7148c369
L		 2112016-11-03 H.J. Lu <hongjiu.lu@intel.com>
212
213 * i386-dis.c (REG_82): Renamed to ...
214 (REG_83): This.
215 (dis386): Updated.
216 (reg_table): Likewise.
217
47acf0bd
IT		 2182016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
219
220 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
221 * i386-dis-evex.h (evex_table): Updated.
222 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
223 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
224 (cpu_flags): Add CpuAVX512_4VNNIW.
225 * i386-opc.h (enum): (AVX512_4VNNIW): New.
226 (i386_cpu_flags): Add cpuavx512_4vnniw.
227 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
228 * i386-init.h: Regenerate.
229 * i386-tbl.h: Ditto.
230
920d2ddc
IT		 2312016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
232
233 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
234 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
235 * i386-dis-evex.h (evex_table): Updated.
236 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
237 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
238 (cpu_flags): Add CpuAVX512_4FMAPS.
239 (opcode_modifiers): Add ImplicitQuadGroup modifier.
240 * i386-opc.h (AVX512_4FMAP): New.
241 (i386_cpu_flags): Add cpuavx512_4fmaps.
242 (ImplicitQuadGroup): New.
243 (i386_opcode_modifier): Add implicitquadgroup.
244 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
245 * i386-init.h: Regenerate.
246 * i386-tbl.h: Ditto.
247
e23eba97
NC		 2482016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
249 Andrew Waterman <andrew@sifive.com>
250
251 Add support for RISC-V architecture.
252 * configure.ac: Add entry for bfd_riscv_arch.
253 * configure: Regenerate.
254 * disassemble.c (disassembler): Add support for riscv.
255 (disassembler_usage): Likewise.
256 * riscv-dis.c: New file.
257 * riscv-opc.c: New file.
258
b5cefcca
L		 2592016-10-21 H.J. Lu <hongjiu.lu@intel.com>
260
261 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
262 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
263 (rm_table): Update the RM_0FAE_REG_7 entry.
264 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
265 (cpu_flags): Remove CpuPCOMMIT.
266 * i386-opc.h (CpuPCOMMIT): Removed.
267 (i386_cpu_flags): Remove cpupcommit.
268 * i386-opc.tbl: Remove pcommit.
269 * i386-init.h: Regenerated.
270 * i386-tbl.h: Likewise.
271
9889cbb1
L		 2722016-10-20 H.J. Lu <hongjiu.lu@intel.com>
273
274 PR binutis/20705
275 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
276 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
277 32-bit mode. Don't check vex.register_specifier in 32-bit
278 mode.
279 (OP_VEX): Check for invalid mask registers.
280
28596323
L		 2812016-10-18 H.J. Lu <hongjiu.lu@intel.com>
282
283 PR binutis/20699
284 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
285 sizeflag.
286
da8d7d66
L		 2872016-10-18 H.J. Lu <hongjiu.lu@intel.com>
288
289 PR binutis/20704
290 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
291
eaf02703
MR		 2922016-10-18 Maciej W. Rozycki <macro@imgtec.com>
293
294 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
295 local variable to `index_regno'.
296
decf5bd1
CM		 2972016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
298
299 * arc-tbl.h: Removed any "inv.+" instructions from the table.
300
e5b06ef0
CZ		 3012016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
302
303 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
304 usage on ISA basis.
305
93562a34
JW		 3062016-10-11 Jiong Wang <jiong.wang@arm.com>
307
308 PR target/20666
309 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
310
362c0c4d
JW		 3112016-10-07 Jiong Wang <jiong.wang@arm.com>
312
313 PR target/20667
314 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
315 available.
316
1047201f
AM		 3172016-10-07 Alan Modra <amodra@gmail.com>
318
319 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
320
1a0670f3
AM		 3212016-10-06 Alan Modra <amodra@gmail.com>
322
323 * aarch64-opc.c: Spell fall through comments consistently.
324 * i386-dis.c: Likewise.
325 * aarch64-dis.c: Add missing fall through comments.
326 * aarch64-opc.c: Likewise.
327 * arc-dis.c: Likewise.
328 * arm-dis.c: Likewise.
329 * i386-dis.c: Likewise.
330 * m68k-dis.c: Likewise.
331 * mep-asm.c: Likewise.
332 * ns32k-dis.c: Likewise.
333 * sh-dis.c: Likewise.
334 * tic4x-dis.c: Likewise.
335 * tic6x-dis.c: Likewise.
336 * vax-dis.c: Likewise.
337
2b804145
AM		 3382016-10-06 Alan Modra <amodra@gmail.com>
339
340 * arc-ext.c (create_map): Add missing break.
341 * msp430-decode.opc (encode_as): Likewise.
342 * msp430-decode.c: Regenerate.
343
616ec358
AM		 3442016-10-06 Alan Modra <amodra@gmail.com>
345
346 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
347 * crx-dis.c (print_insn_crx): Likewise.
348
72da393d
L		 3492016-09-30 H.J. Lu <hongjiu.lu@intel.com>
350
351 PR binutils/20657
352 * i386-dis.c (putop): Don't assign alt twice.
353
744ce302
JW		 3542016-09-29 Jiong Wang <jiong.wang@arm.com>
355
356 PR target/20553
357 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
358
a5721ba2
AM		 3592016-09-29 Alan Modra <amodra@gmail.com>
360
361 * ppc-opc.c (L): Make compulsory.
362 (LOPT): New, optional form of L.
363 (HTM_R): Define as LOPT.
364 (L0, L1): Delete.
365 (L32OPT): New, optional for 32-bit L.
366 (L2OPT): New, 2-bit L for dcbf.
367 (SVC_LEC): Update.
368 (L2): Define.
369 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
370 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
371 <dcbf>: Use L2OPT.
372 <tlbiel, tlbie>: Use LOPT.
373 <wclr, wclrall>: Use L2.
374
c5da1932
VZ		 3752016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
376
377 * Makefile.in: Regenerate.
378 * configure: Likewise.
379
2b848ebd
CZ		 3802016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
381
382 * arc-ext-tbl.h (EXTINSN2OPF): Define.
383 (EXTINSN2OP): Use EXTINSN2OPF.
384 (bspeekm, bspop, modapp): New extension instructions.
385 * arc-opc.c (F_DNZ_ND): Define.
386 (F_DNZ_D): Likewise.
387 (F_SIZEB1): Changed.
388 (C_DNZ_D): Define.
389 (C_HARD): Changed.
390 * arc-tbl.h (dbnz): New instruction.
391 (prealloc): Allow it for ARC EM.
392 (xbfu): Likewise.
393
ad43e107
RS		 3942016-09-21 Richard Sandiford <richard.sandiford@arm.com>
395
396 * aarch64-opc.c (print_immediate_offset_address): Print spaces
397 after commas in addresses.
398 (aarch64_print_operand): Likewise.
399
ab3b8fcf
RS		 4002016-09-21 Richard Sandiford <richard.sandiford@arm.com>
401
402 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
403 rather than "should be" or "expected to be" in error messages.
404
bb7eff52
RS		 4052016-09-21 Richard Sandiford <richard.sandiford@arm.com>
406
407 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
408 (print_mnemonic_name): ...here.
409 (print_comment): New function.
410 (print_aarch64_insn): Call it.
411 * aarch64-opc.c (aarch64_conds): Add SVE names.
412 (aarch64_print_operand): Print alternative condition names in
413 a comment.
414
c0890d26
RS		 4152016-09-21 Richard Sandiford <richard.sandiford@arm.com>
416
417 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
418 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
419 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
420 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
421 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
422 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
423 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
424 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
425 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
426 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
427 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
428 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
429 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
430 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
431 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
432 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
433 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
434 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
435 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
436 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
437 (OP_SVE_XWU, OP_SVE_XXU): New macros.
438 (aarch64_feature_sve): New variable.
439 (SVE): New macro.
440 (_SVE_INSN): Likewise.
441 (aarch64_opcode_table): Add SVE instructions.
442 * aarch64-opc.h (extract_fields): Declare.
443 * aarch64-opc-2.c: Regenerate.
444 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
445 * aarch64-asm-2.c: Regenerate.
446 * aarch64-dis.c (extract_fields): Make global.
447 (do_misc_decoding): Handle the new SVE aarch64_ops.
448 * aarch64-dis-2.c: Regenerate.
449
116b6019
RS		 4502016-09-21 Richard Sandiford <richard.sandiford@arm.com>
451
452 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
453 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
454 aarch64_field_kinds.
455 * aarch64-opc.c (fields): Add corresponding entries.
456 * aarch64-asm.c (aarch64_get_variant): New function.
457 (aarch64_encode_variant_using_iclass): Likewise.
458 (aarch64_opcode_encode): Call it.
459 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
460 (aarch64_opcode_decode): Call it.
461
047cd301
RS		 4622016-09-21 Richard Sandiford <richard.sandiford@arm.com>
463
464 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
465 and FP register operands.
466 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
467 (FLD_SVE_Vn): New aarch64_field_kinds.
468 * aarch64-opc.c (fields): Add corresponding entries.
469 (aarch64_print_operand): Handle the new SVE core and FP register
470 operands.
471 * aarch64-opc-2.c: Regenerate.
472 * aarch64-asm-2.c: Likewise.
473 * aarch64-dis-2.c: Likewise.
474
165d4950
RS		 4752016-09-21 Richard Sandiford <richard.sandiford@arm.com>
476
477 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
478 immediate operands.
479 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
480 * aarch64-opc.c (fields): Add corresponding entry.
481 (operand_general_constraint_met_p): Handle the new SVE FP immediate
482 operands.
483 (aarch64_print_operand): Likewise.
484 * aarch64-opc-2.c: Regenerate.
485 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
486 (ins_sve_float_zero_one): New inserters.
487 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
488 (aarch64_ins_sve_float_half_two): Likewise.
489 (aarch64_ins_sve_float_zero_one): Likewise.
490 * aarch64-asm-2.c: Regenerate.
491 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
492 (ext_sve_float_zero_one): New extractors.
493 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
494 (aarch64_ext_sve_float_half_two): Likewise.
495 (aarch64_ext_sve_float_zero_one): Likewise.
496 * aarch64-dis-2.c: Regenerate.
497
e950b345
RS		 4982016-09-21 Richard Sandiford <richard.sandiford@arm.com>
499
500 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
501 integer immediate operands.
502 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
503 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
504 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
505 * aarch64-opc.c (fields): Add corresponding entries.
506 (operand_general_constraint_met_p): Handle the new SVE integer
507 immediate operands.
508 (aarch64_print_operand): Likewise.
509 (aarch64_sve_dupm_mov_immediate_p): New function.
510 * aarch64-opc-2.c: Regenerate.
511 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
512 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
513 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
514 (aarch64_ins_limm): ...here.
515 (aarch64_ins_inv_limm): New function.
516 (aarch64_ins_sve_aimm): Likewise.
517 (aarch64_ins_sve_asimm): Likewise.
518 (aarch64_ins_sve_limm_mov): Likewise.
519 (aarch64_ins_sve_shlimm): Likewise.
520 (aarch64_ins_sve_shrimm): Likewise.
521 * aarch64-asm-2.c: Regenerate.
522 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
523 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
524 * aarch64-dis.c (decode_limm): New function, split out from...
525 (aarch64_ext_limm): ...here.
526 (aarch64_ext_inv_limm): New function.
527 (decode_sve_aimm): Likewise.
528 (aarch64_ext_sve_aimm): Likewise.
529 (aarch64_ext_sve_asimm): Likewise.
530 (aarch64_ext_sve_limm_mov): Likewise.
531 (aarch64_top_bit): Likewise.
532 (aarch64_ext_sve_shlimm): Likewise.
533 (aarch64_ext_sve_shrimm): Likewise.
534 * aarch64-dis-2.c: Regenerate.
535
98907a70
RS		 5362016-09-21 Richard Sandiford <richard.sandiford@arm.com>
537
538 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
539 operands.
540 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
541 the AARCH64_MOD_MUL_VL entry.
542 (value_aligned_p): Cope with non-power-of-two alignments.
543 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
544 (print_immediate_offset_address): Likewise.
545 (aarch64_print_operand): Likewise.
546 * aarch64-opc-2.c: Regenerate.
547 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
548 (ins_sve_addr_ri_s9xvl): New inserters.
549 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
550 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
551 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
552 * aarch64-asm-2.c: Regenerate.
553 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
554 (ext_sve_addr_ri_s9xvl): New extractors.
555 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
556 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
557 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
558 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
559 * aarch64-dis-2.c: Regenerate.
560
4df068de
RS		 5612016-09-21 Richard Sandiford <richard.sandiford@arm.com>
562
563 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
564 address operands.
565 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
566 (FLD_SVE_xs_22): New aarch64_field_kinds.
567 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
568 (get_operand_specific_data): New function.
569 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
570 FLD_SVE_xs_14 and FLD_SVE_xs_22.
571 (operand_general_constraint_met_p): Handle the new SVE address
572 operands.
573 (sve_reg): New array.
574 (get_addr_sve_reg_name): New function.
575 (aarch64_print_operand): Handle the new SVE address operands.
576 * aarch64-opc-2.c: Regenerate.
577 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
578 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
579 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
580 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
581 (aarch64_ins_sve_addr_rr_lsl): Likewise.
582 (aarch64_ins_sve_addr_rz_xtw): Likewise.
583 (aarch64_ins_sve_addr_zi_u5): Likewise.
584 (aarch64_ins_sve_addr_zz): Likewise.
585 (aarch64_ins_sve_addr_zz_lsl): Likewise.
586 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
587 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
588 * aarch64-asm-2.c: Regenerate.
589 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
590 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
591 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
592 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
593 (aarch64_ext_sve_addr_ri_u6): Likewise.
594 (aarch64_ext_sve_addr_rr_lsl): Likewise.
595 (aarch64_ext_sve_addr_rz_xtw): Likewise.
596 (aarch64_ext_sve_addr_zi_u5): Likewise.
597 (aarch64_ext_sve_addr_zz): Likewise.
598 (aarch64_ext_sve_addr_zz_lsl): Likewise.
599 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
600 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
601 * aarch64-dis-2.c: Regenerate.
602
2442d846
RS		 6032016-09-21 Richard Sandiford <richard.sandiford@arm.com>
604
605 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
606 AARCH64_OPND_SVE_PATTERN_SCALED.
607 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
608 * aarch64-opc.c (fields): Add a corresponding entry.
609 (set_multiplier_out_of_range_error): New function.
610 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
611 (operand_general_constraint_met_p): Handle
612 AARCH64_OPND_SVE_PATTERN_SCALED.
613 (print_register_offset_address): Use PRIi64 to print the
614 shift amount.
615 (aarch64_print_operand): Likewise. Handle
616 AARCH64_OPND_SVE_PATTERN_SCALED.
617 * aarch64-opc-2.c: Regenerate.
618 * aarch64-asm.h (ins_sve_scale): New inserter.
619 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
620 * aarch64-asm-2.c: Regenerate.
621 * aarch64-dis.h (ext_sve_scale): New inserter.
622 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
623 * aarch64-dis-2.c: Regenerate.
624
245d2e3f
RS		 6252016-09-21 Richard Sandiford <richard.sandiford@arm.com>
626
627 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
628 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
629 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
630 (FLD_SVE_prfop): Likewise.
631 * aarch64-opc.c: Include libiberty.h.
632 (aarch64_sve_pattern_array): New variable.
633 (aarch64_sve_prfop_array): Likewise.
634 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
635 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
636 AARCH64_OPND_SVE_PRFOP.
637 * aarch64-asm-2.c: Regenerate.
638 * aarch64-dis-2.c: Likewise.
639 * aarch64-opc-2.c: Likewise.
640
d50c751e
RS		 6412016-09-21 Richard Sandiford <richard.sandiford@arm.com>
642
643 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
644 AARCH64_OPND_QLF_P_[ZM].
645 (aarch64_print_operand): Print /z and /m where appropriate.
646
f11ad6bc
RS		 6472016-09-21 Richard Sandiford <richard.sandiford@arm.com>
648
649 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
650 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
651 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
652 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
653 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
654 * aarch64-opc.c (fields): Add corresponding entries here.
655 (operand_general_constraint_met_p): Check that SVE register lists
656 have the correct length. Check the ranges of SVE index registers.
657 Check for cases where p8-p15 are used in 3-bit predicate fields.
658 (aarch64_print_operand): Handle the new SVE operands.
659 * aarch64-opc-2.c: Regenerate.
660 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
661 * aarch64-asm.c (aarch64_ins_sve_index): New function.
662 (aarch64_ins_sve_reglist): Likewise.
663 * aarch64-asm-2.c: Regenerate.
664 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
665 * aarch64-dis.c (aarch64_ext_sve_index): New function.
666 (aarch64_ext_sve_reglist): Likewise.
667 * aarch64-dis-2.c: Regenerate.
668
0c608d6b
RS		 6692016-09-21 Richard Sandiford <richard.sandiford@arm.com>
670
671 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
672 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
673 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
674 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
675 tied operands.
676
01dbfe4c
RS		 6772016-09-21 Richard Sandiford <richard.sandiford@arm.com>
678
679 * aarch64-opc.c (get_offset_int_reg_name): New function.
680 (print_immediate_offset_address): Likewise.
681 (print_register_offset_address): Take the base and offset
682 registers as parameters.
683 (aarch64_print_operand): Update caller accordingly. Use
684 print_immediate_offset_address.
685
72e9f319
RS		 6862016-09-21 Richard Sandiford <richard.sandiford@arm.com>
687
688 * aarch64-opc.c (BANK): New macro.
689 (R32, R64): Take a register number as argument
690 (int_reg): Use BANK.
691
8a7f0c1b
RS		 6922016-09-21 Richard Sandiford <richard.sandiford@arm.com>
693
694 * aarch64-opc.c (print_register_list): Add a prefix parameter.
695 (aarch64_print_operand): Update accordingly.
696
aa2aa4c6
RS		 6972016-09-21 Richard Sandiford <richard.sandiford@arm.com>
698
699 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
700 for FPIMM.
701 * aarch64-asm.h (ins_fpimm): New inserter.
702 * aarch64-asm.c (aarch64_ins_fpimm): New function.
703 * aarch64-asm-2.c: Regenerate.
704 * aarch64-dis.h (ext_fpimm): New extractor.
705 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
706 (aarch64_ext_fpimm): New function.
707 * aarch64-dis-2.c: Regenerate.
708
b5464a68
RS		 7092016-09-21 Richard Sandiford <richard.sandiford@arm.com>
710
711 * aarch64-asm.c: Include libiberty.h.
712 (insert_fields): New function.
713 (aarch64_ins_imm): Use it.
714 * aarch64-dis.c (extract_fields): New function.
715 (aarch64_ext_imm): Use it.
716
42408347
RS		 7172016-09-21 Richard Sandiford <richard.sandiford@arm.com>
718
719 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
720 with an esize parameter.
721 (operand_general_constraint_met_p): Update accordingly.
722 Fix misindented code.
723 * aarch64-asm.c (aarch64_ins_limm): Update call to
724 aarch64_logical_immediate_p.
725
4989adac
RS		 7262016-09-21 Richard Sandiford <richard.sandiford@arm.com>
727
728 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
729
bd11d5d8
RS		 7302016-09-21 Richard Sandiford <richard.sandiford@arm.com>
731
732 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
733
f807f43d
CZ		 7342016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
735
736 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
737
fd486b63
PB		 7382016-09-14 Peter Bergner <bergner@vnet.ibm.com>
739
740 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
741 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
742 xor3>: Delete mnemonics.
743 <cp_abort>: Rename mnemonic from ...
744 <cpabort>: ...to this.
745 <setb>: Change to a X form instruction.
746 <sync>: Change to 1 operand form.
747 <copy>: Delete mnemonic.
748 <copy_first>: Rename mnemonic from ...
749 <copy>: ...to this.
750 <paste, paste.>: Delete mnemonics.
751 <paste_last>: Rename mnemonic from ...
752 <paste.>: ...to this.
753
dce08442
AK		 7542016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
755
756 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
757
952c3f51
AK		 7582016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
759
760 * s390-mkopc.c (main): Support alternate arch strings.
761
8b71537b
PS		 7622016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
763
764 * s390-opc.txt: Fix kmctr instruction type.
765
5b64d091
L		 7662016-09-07 H.J. Lu <hongjiu.lu@intel.com>
767
768 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
769 * i386-init.h: Regenerated.
770
7763838e
CM		 7712016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
772
773 * opcodes/arc-dis.c (print_insn_arc): Changed.
774
1b8b6532
JM		 7752016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
776
777 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
778 camellia_fl.
779
1a336194
TP		 7802016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
781
782 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
783 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
784 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
785
6b40c462
L		 7862016-08-24 H.J. Lu <hongjiu.lu@intel.com>
787
788 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
789 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
790 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
791 PREFIX_MOD_3_0FAE_REG_4.
792 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
793 PREFIX_MOD_3_0FAE_REG_4.
794 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
795 (cpu_flags): Add CpuPTWRITE.
796 * i386-opc.h (CpuPTWRITE): New.
797 (i386_cpu_flags): Add cpuptwrite.
798 * i386-opc.tbl: Add ptwrite instruction.
799 * i386-init.h: Regenerated.
800 * i386-tbl.h: Likewise.
801
ab548d2d
AK		 8022016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
803
804 * arc-dis.h: Wrap around in extern "C".
805
344bde0a
RS		 8062016-08-23 Richard Sandiford <richard.sandiford@arm.com>
807
808 * aarch64-tbl.h (V8_2_INSN): New macro.
809 (aarch64_opcode_table): Use it.
810
5ce912d8
RS		 8112016-08-23 Richard Sandiford <richard.sandiford@arm.com>
812
813 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
814 CORE_INSN, __FP_INSN and SIMD_INSN.
815
9d30b0bd
RS		 8162016-08-23 Richard Sandiford <richard.sandiford@arm.com>
817
818 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
819 (aarch64_opcode_table): Update uses accordingly.
820
dfdaec14
AJ		 8212016-07-25 Andrew Jenner <andrew@codesourcery.com>
822 Kwok Cheung Yeung <kcy@codesourcery.com>
823
824 opcodes/
825 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
826 'e_cmplwi' to 'e_cmpli' instead.
827 (OPVUPRT, OPVUPRT_MASK): Define.
828 (powerpc_opcodes): Add E200Z4 insns.
829 (vle_opcodes): Add context save/restore insns.
830
7bd374a4
MR		 8312016-07-27 Maciej W. Rozycki <macro@imgtec.com>
832
833 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
834 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
835 "j".
836
db18dbab
GM		 8372016-07-27 Graham Markall <graham.markall@embecosm.com>
838
839 * arc-nps400-tbl.h: Change block comments to GNU format.
840 * arc-dis.c: Add new globals addrtypenames,
841 addrtypenames_max, and addtypeunknown.
842 (get_addrtype): New function.
843 (print_insn_arc): Print colons and address types when
844 required.
845 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
846 define insert and extract functions for all address types.
847 (arc_operands): Add operands for colon and all address
848 types.
849 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
850 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
851 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
852 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
853 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
854 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
855
fecd57f9
L		 8562016-07-21 H.J. Lu <hongjiu.lu@intel.com>
857
858 * configure: Regenerated.
859
37fd5ef3
CZ		 8602016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
861
862 * arc-dis.c (skipclass): New structure.
863 (decodelist): New variable.
864 (is_compatible_p): New function.
865 (new_element): Likewise.
866 (skip_class_p): Likewise.
867 (find_format_from_table): Use skip_class_p function.
868 (find_format): Decode first the extension instructions.
869 (print_insn_arc): Select either ARCEM or ARCHS based on elf
870 e_flags.
871 (parse_option): New function.
872 (parse_disassembler_options): Likewise.
873 (print_arc_disassembler_options): Likewise.
874 (print_insn_arc): Use parse_disassembler_options function. Proper
875 select ARCv2 cpu variant.
876 * disassemble.c (disassembler_usage): Add ARC disassembler
877 options.
878
92281a5b
MR		 8792016-07-13 Maciej W. Rozycki <macro@imgtec.com>
880
881 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
882 annotation from the "nal" entry and reorder it beyond "bltzal".
883
6e7ced37
JM		 8842016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
885
886 * sparc-opc.c (ldtxa): New macro.
887 (sparc_opcodes): Use the macro defined above to add entries for
888 the LDTXA instructions.
889 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
890 instruction.
891
2f831b9a 8922016-07-07 James Bowman <james.bowman@ftdichip.com>
893
894 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
895 and "jmpc".
896
c07315e0
JB		 8972016-07-01 Jan Beulich <jbeulich@suse.com>
898
899 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
900 (movzb): Adjust to cover all permitted suffixes.
901 (movzw): New.
902 * i386-tbl.h: Re-generate.
903
9243100a
JB		 9042016-07-01 Jan Beulich <jbeulich@suse.com>
905
906 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
907 (lgdt): Remove Tbyte from non-64-bit variant.
908 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
909 xsaves64, xsavec64): Remove Disp16.
910 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
911 Remove Disp32S from non-64-bit variants. Remove Disp16 from
912 64-bit variants.
913 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
914 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
915 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
916 64-bit variants.
917 * i386-tbl.h: Re-generate.
918
8325cc63
JB		 9192016-07-01 Jan Beulich <jbeulich@suse.com>
920
921 * i386-opc.tbl (xlat): Remove RepPrefixOk.
922 * i386-tbl.h: Re-generate.
923
838441e4
YQ		 9242016-06-30 Yao Qi <yao.qi@linaro.org>
925
926 * arm-dis.c (print_insn): Fix typo in comment.
927
dab26bf4
RS		 9282016-06-28 Richard Sandiford <richard.sandiford@arm.com>
929
930 * aarch64-opc.c (operand_general_constraint_met_p): Check the
931 range of ldst_elemlist operands.
932 (print_register_list): Use PRIi64 to print the index.
933 (aarch64_print_operand): Likewise.
934
5703197e
TS		 9352016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
936
937 * mcore-opc.h: Remove sentinal.
938 * mcore-dis.c (print_insn_mcore): Adjust.
939
ce440d63
GM		 9402016-06-23 Graham Markall <graham.markall@embecosm.com>
941
942 * arc-opc.c: Correct description of availability of NPS400
943 features.
944
6fd3a02d
PB		 9452016-06-22 Peter Bergner <bergner@vnet.ibm.com>
946
947 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
948 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
949 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
950 xor3>: New mnemonics.
951 <setb>: Change to a VX form instruction.
952 (insert_sh6): Add support for rldixor.
953 (extract_sh6): Likewise.
954
6b477896
TS		 9552016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
956
957 * arc-ext.h: Wrap in extern C.
958
bdd582db
GM		 9592016-06-21 Graham Markall <graham.markall@embecosm.com>
960
961 * arc-dis.c (arc_insn_length): Add comment on instruction length.
962 Use same method for determining instruction length on ARC700 and
963 NPS-400.
964 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
965 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
966 with the NPS400 subclass.
967 * arc-opc.c: Likewise.
968
96074adc
JM		 9692016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
970
971 * sparc-opc.c (rdasr): New macro.
972 (wrasr): Likewise.
973 (rdpr): Likewise.
974 (wrpr): Likewise.
975 (rdhpr): Likewise.
976 (wrhpr): Likewise.
977 (sparc_opcodes): Use the macros above to fix and expand the
978 definition of read/write instructions from/to
979 asr/privileged/hyperprivileged instructions.
980 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
981 %hva_mask_nz. Prefer softint_set and softint_clear over
982 set_softint and clear_softint.
983 (print_insn_sparc): Support %ver in Rd.
984
7a10c22f
JM		 9852016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
986
987 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
988 architecture according to the hardware capabilities they require.
989
4f26fb3a
JM		 9902016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
991
992 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
993 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
994 bfd_mach_sparc_v9{c,d,e,v,m}.
995 * sparc-opc.c (MASK_V9C): Define.
996 (MASK_V9D): Likewise.
997 (MASK_V9E): Likewise.
998 (MASK_V9V): Likewise.
999 (MASK_V9M): Likewise.
1000 (v6): Add MASK_V9{C,D,E,V,M}.
1001 (v6notlet): Likewise.
1002 (v7): Likewise.
1003 (v8): Likewise.
1004 (v9): Likewise.
1005 (v9andleon): Likewise.
1006 (v9a): Likewise.
1007 (v9b): Likewise.
1008 (v9c): Define.
1009 (v9d): Likewise.
1010 (v9e): Likewise.
1011 (v9v): Likewise.
1012 (v9m): Likewise.
1013 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1014
3ee6e4fb
NC		 10152016-06-15 Nick Clifton <nickc@redhat.com>
1016
1017 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1018 constants to match expected behaviour.
1019 (nds32_parse_opcode): Likewise. Also for whitespace.
1020
02f3be19
AB		 10212016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1022
1023 * arc-opc.c (extract_rhv1): Extract value from insn.
1024
6f9f37ed 10252016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 1026
1027 * arc-nps400-tbl.h: Add ldbit instruction.
1028 * arc-opc.c: Add flag classes required for ldbit.
1029
6f9f37ed 10302016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 1031
1032 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1033 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1034 support the above instructions.
1035
6f9f37ed 10362016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 1037
1038 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1039 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1040 csma, cbba, zncv, and hofs.
1041 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1042 support the above instructions.
1043
10442016-06-06 Graham Markall <graham.markall@embecosm.com>
1045
1046 * arc-nps400-tbl.h: Add andab and orab instructions.
1047
10482016-06-06 Graham Markall <graham.markall@embecosm.com>
1049
1050 * arc-nps400-tbl.h: Add addl-like instructions.
1051
10522016-06-06 Graham Markall <graham.markall@embecosm.com>
1053
1054 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1055
10562016-06-06 Graham Markall <graham.markall@embecosm.com>
1057
1058 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1059 instructions.
1060
b2cc3f6f
AK		 10612016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1062
1063 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1064 variable.
1065 (init_disasm): Handle new command line option "insnlength".
1066 (print_s390_disassembler_options): Mention new option in help
1067 output.
1068 (print_insn_s390): Use the encoded insn length when dumping
1069 unknown instructions.
1070
1857fe72
DC		 10712016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1072
1073 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1074 to the address and set as symbol address for LDS/ STS immediate operands.
1075
14b57c7c
AM		 10762016-06-07 Alan Modra <amodra@gmail.com>
1077
1078 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1079 cpu for "vle" to e500.
1080 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1081 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1082 (PPCNONE): Delete, substitute throughout.
1083 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1084 except for major opcode 4 and 31.
1085 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1086
4d1464f2
MW		 10872016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1088
1089 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1090 ARM_EXT_RAS in relevant entries.
1091
026122a6
PB		 10922016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1093
1094 PR binutils/20196
1095 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1096 opcodes for E6500.
1097
07f5af7d
L		 10982016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1099
1100 PR binutis/18386
1101 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1102 (indir_v_mode): New.
1103 Add comments for '&'.
1104 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1105 (putop): Handle '&'.
1106 (intel_operand_size): Handle indir_v_mode.
1107 (OP_E_register): Likewise.
1108 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1109 64-bit indirect call/jmp for AMD64.
1110 * i386-tbl.h: Regenerated
1111
4eb6f892
AB		 11122016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1113
1114 * arc-dis.c (struct arc_operand_iterator): New structure.
1115 (find_format_from_table): All the old content from find_format,
1116 with some minor adjustments, and parameter renaming.
1117 (find_format_long_instructions): New function.
1118 (find_format): Rewritten.
1119 (arc_insn_length): Add LSB parameter.
1120 (extract_operand_value): New function.
1121 (operand_iterator_next): New function.
1122 (print_insn_arc): Use new functions to find opcode, and iterator
1123 over operands.
1124 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1125 (extract_nps_3bit_dst_short): New function.
1126 (insert_nps_3bit_src2_short): New function.
1127 (extract_nps_3bit_src2_short): New function.
1128 (insert_nps_bitop1_size): New function.
1129 (extract_nps_bitop1_size): New function.
1130 (insert_nps_bitop2_size): New function.
1131 (extract_nps_bitop2_size): New function.
1132 (insert_nps_bitop_mod4_msb): New function.
1133 (extract_nps_bitop_mod4_msb): New function.
1134 (insert_nps_bitop_mod4_lsb): New function.
1135 (extract_nps_bitop_mod4_lsb): New function.
1136 (insert_nps_bitop_dst_pos3_pos4): New function.
1137 (extract_nps_bitop_dst_pos3_pos4): New function.
1138 (insert_nps_bitop_ins_ext): New function.
1139 (extract_nps_bitop_ins_ext): New function.
1140 (arc_operands): Add new operands.
1141 (arc_long_opcodes): New global array.
1142 (arc_num_long_opcodes): New global.
1143 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1144
1fe0971e
TS		 11452016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1146
1147 * nds32-asm.h: Add extern "C".
1148 * sh-opc.h: Likewise.
1149
315f180f
GM		 11502016-06-01 Graham Markall <graham.markall@embecosm.com>
1151
1152 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1153 0,b,limm to the rflt instruction.
1154
a2b5fccc
TS		 11552016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1156
1157 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1158 constant.
1159
0cbd0046
L		 11602016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1161
1162 PR gas/20145
1163 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1164 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1165 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1166 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1167 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1168 * i386-init.h: Regenerated.
1169
1848e567
L		 11702016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1171
1172 PR gas/20145
1173 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1174 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1175 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1176 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1177 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1178 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1179 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1180 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1181 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1182 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1183 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1184 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1185 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1186 CpuRegMask for AVX512.
1187 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1188 and CpuRegMask.
1189 (set_bitfield_from_cpu_flag_init): New function.
1190 (set_bitfield): Remove const on f. Call
1191 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1192 * i386-opc.h (CpuRegMMX): New.
1193 (CpuRegXMM): Likewise.
1194 (CpuRegYMM): Likewise.
1195 (CpuRegZMM): Likewise.
1196 (CpuRegMask): Likewise.
1197 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1198 and cpuregmask.
1199 * i386-init.h: Regenerated.
1200 * i386-tbl.h: Likewise.
1201
e92bae62
L		 12022016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1203
1204 PR gas/20154
1205 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1206 (opcode_modifiers): Add AMD64 and Intel64.
1207 (main): Properly verify CpuMax.
1208 * i386-opc.h (CpuAMD64): Removed.
1209 (CpuIntel64): Likewise.
1210 (CpuMax): Set to CpuNo64.
1211 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1212 (AMD64): New.
1213 (Intel64): Likewise.
1214 (i386_opcode_modifier): Add amd64 and intel64.
1215 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1216 on call and jmp.
1217 * i386-init.h: Regenerated.
1218 * i386-tbl.h: Likewise.
1219
e89c5eaa
L		 12202016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1221
1222 PR gas/20154
1223 * i386-gen.c (main): Fail if CpuMax is incorrect.
1224 * i386-opc.h (CpuMax): Set to CpuIntel64.
1225 * i386-tbl.h: Regenerated.
1226
77d66e7b
NC		 12272016-05-27 Nick Clifton <nickc@redhat.com>
1228
1229 PR target/20150
1230 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1231 (msp430dis_opcode_unsigned): New function.
1232 (msp430dis_opcode_signed): New function.
1233 (msp430_singleoperand): Use the new opcode reading functions.
1234 Only disassenmble bytes if they were successfully read.
1235 (msp430_doubleoperand): Likewise.
1236 (msp430_branchinstr): Likewise.
1237 (msp430x_callx_instr): Likewise.
1238 (print_insn_msp430): Check that it is safe to read bytes before
1239 attempting disassembly. Use the new opcode reading functions.
1240
19dfcc89
PB		 12412016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1242
1243 * ppc-opc.c (CY): New define. Document it.
1244 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1245
f3ad7637
L		 12462016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1247
1248 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1249 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1250 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1251 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1252 CPU_ANY_AVX_FLAGS.
1253 * i386-init.h: Regenerated.
1254
f1360d58
L		 12552016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1256
1257 PR gas/20141
1258 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1259 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1260 * i386-init.h: Regenerated.
1261
293f5f65
L		 12622016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1263
1264 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1265 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1266 * i386-init.h: Regenerated.
1267
d9eca1df
CZ		 12682016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1269
1270 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1271 information.
1272 (print_insn_arc): Set insn_type information.
1273 * arc-opc.c (C_CC): Add F_CLASS_COND.
1274 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1275 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1276 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1277 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1278 (brne, brne_s, jeq_s, jne_s): Likewise.
1279
87789e08
CZ		 12802016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1281
1282 * arc-tbl.h (neg): New instruction variant.
1283
c810e0b8
CZ		 12842016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1285
1286 * arc-dis.c (find_format, find_format, get_auxreg)
1287 (print_insn_arc): Changed.
1288 * arc-ext.h (INSERT_XOP): Likewise.
1289
3d207518
TS		 12902016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1291
1292 * tic54x-dis.c (sprint_mmr): Adjust.
1293 * tic54x-opc.c: Likewise.
1294
514e58b7
AM		 12952016-05-19 Alan Modra <amodra@gmail.com>
1296
1297 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1298
e43de63c
AM		 12992016-05-19 Alan Modra <amodra@gmail.com>
1300
1301 * ppc-opc.c: Formatting.
1302 (NSISIGNOPT): Define.
1303 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1304
1401d2fe
MR		 13052016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1306
1307 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1308 replacing references to `micromips_ase' throughout.
1309 (_print_insn_mips): Don't use file-level microMIPS annotation to
1310 determine the disassembly mode with the symbol table.
1311
1178da44
PB		 13122016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1313
1314 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1315
8f4f9071
MF		 13162016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1317
1318 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1319 mips64r6.
1320 * mips-opc.c (D34): New macro.
1321 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1322
8bc52696
AF		 13232016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1324
1325 * i386-dis.c (prefix_table): Add RDPID instruction.
1326 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1327 (cpu_flags): Add RDPID bitfield.
1328 * i386-opc.h (enum): Add RDPID element.
1329 (i386_cpu_flags): Add RDPID field.
1330 * i386-opc.tbl: Add RDPID instruction.
1331 * i386-init.h: Regenerate.
1332 * i386-tbl.h: Regenerate.
1333
39d911fc
TP		 13342016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1335
1336 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1337 branch type of a symbol.
1338 (print_insn): Likewise.
1339
16a1fa25
TP		 13402016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1341
1342 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1343 Mainline Security Extensions instructions.
1344 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1345 Extensions instructions.
1346 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1347 instructions.
1348 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1349 special registers.
1350
d751b79e
JM		 13512016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1352
1353 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1354
945e0f82
CZ		 13552016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1356
1357 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1358 (arcExtMap_genOpcode): Likewise.
1359 * arc-opc.c (arg_32bit_rc): Define new variable.
1360 (arg_32bit_u6): Likewise.
1361 (arg_32bit_limm): Likewise.
1362
20f55f38
SN		 13632016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1364
1365 * aarch64-gen.c (VERIFIER): Define.
1366 * aarch64-opc.c (VERIFIER): Define.
1367 (verify_ldpsw): Use static linkage.
1368 * aarch64-opc.h (verify_ldpsw): Remove.
1369 * aarch64-tbl.h: Use VERIFIER for verifiers.
1370
4bd13cde
NC		 13712016-04-28 Nick Clifton <nickc@redhat.com>
1372
1373 PR target/19722
1374 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1375 * aarch64-opc.c (verify_ldpsw): New function.
1376 * aarch64-opc.h (verify_ldpsw): New prototype.
1377 * aarch64-tbl.h: Add initialiser for verifier field.
1378 (LDPSW): Set verifier to verify_ldpsw.
1379
c0f92bf9
L		 13802016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1381
1382 PR binutils/19983
1383 PR binutils/19984
1384 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1385 smaller than address size.
1386
e6c7cdec
TS		 13872016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1388
1389 * alpha-dis.c: Regenerate.
1390 * crx-dis.c: Likewise.
1391 * disassemble.c: Likewise.
1392 * epiphany-opc.c: Likewise.
1393 * fr30-opc.c: Likewise.
1394 * frv-opc.c: Likewise.
1395 * ip2k-opc.c: Likewise.
1396 * iq2000-opc.c: Likewise.
1397 * lm32-opc.c: Likewise.
1398 * lm32-opinst.c: Likewise.
1399 * m32c-opc.c: Likewise.
1400 * m32r-opc.c: Likewise.
1401 * m32r-opinst.c: Likewise.
1402 * mep-opc.c: Likewise.
1403 * mt-opc.c: Likewise.
1404 * or1k-opc.c: Likewise.
1405 * or1k-opinst.c: Likewise.
1406 * tic80-opc.c: Likewise.
1407 * xc16x-opc.c: Likewise.
1408 * xstormy16-opc.c: Likewise.
1409
537aefaf
AB		 14102016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1411
1412 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1413 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1414 calcsd, and calcxd instructions.
1415 * arc-opc.c (insert_nps_bitop_size): Delete.
1416 (extract_nps_bitop_size): Delete.
1417 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1418 (extract_nps_qcmp_m3): Define.
1419 (extract_nps_qcmp_m2): Define.
1420 (extract_nps_qcmp_m1): Define.
1421 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1422 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1423 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1424 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1425 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1426 NPS_QCMP_M3.
1427
c8f785f2
AB		 14282016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1429
1430 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1431
6fd8e7c2
L		 14322016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1433
1434 * Makefile.in: Regenerated with automake 1.11.6.
1435 * aclocal.m4: Likewise.
1436
4b0c052e
AB		 14372016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1438
1439 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1440 instructions.
1441 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1442 (extract_nps_cmem_uimm16): New function.
1443 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1444
cb040366
AB		 14452016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1446
1447 * arc-dis.c (arc_insn_length): New function.
1448 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1449 (find_format): Change insnLen parameter to unsigned.
1450
accc0180
NC		 14512016-04-13 Nick Clifton <nickc@redhat.com>
1452
1453 PR target/19937
1454 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1455 the LD.B and LD.BU instructions.
1456
f36e33da
CZ		 14572016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1458
1459 * arc-dis.c (find_format): Check for extension flags.
1460 (print_flags): New function.
1461 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1462 .extAuxRegister.
1463 * arc-ext.c (arcExtMap_coreRegName): Use
1464 LAST_EXTENSION_CORE_REGISTER.
1465 (arcExtMap_coreReadWrite): Likewise.
1466 (dump_ARC_extmap): Update printing.
1467 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1468 (arc_aux_regs): Add cpu field.
1469 * arc-regs.h: Add cpu field, lower case name aux registers.
1470
1c2e355e
CZ		 14712016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1472
1473 * arc-tbl.h: Add rtsc, sleep with no arguments.
1474
b99747ae
CZ		 14752016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1476
1477 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1478 Initialize.
1479 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1480 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1481 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1482 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1483 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1484 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1485 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1486 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1487 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1488 (arc_opcode arc_opcodes): Null terminate the array.
1489 (arc_num_opcodes): Remove.
1490 * arc-ext.h (INSERT_XOP): Define.
1491 (extInstruction_t): Likewise.
1492 (arcExtMap_instName): Delete.
1493 (arcExtMap_insn): New function.
1494 (arcExtMap_genOpcode): Likewise.
1495 * arc-ext.c (ExtInstruction): Remove.
1496 (create_map): Zero initialize instruction fields.
1497 (arcExtMap_instName): Remove.
1498 (arcExtMap_insn): New function.
1499 (dump_ARC_extmap): More info while debuging.
1500 (arcExtMap_genOpcode): New function.
1501 * arc-dis.c (find_format): New function.
1502 (print_insn_arc): Use find_format.
1503 (arc_get_disassembler): Enable dump_ARC_extmap only when
1504 debugging.
1505
92708cec
MR		 15062016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1507
1508 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1509 instruction bits out.
1510
a42a4f84
AB		 15112016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1512
1513 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1514 * arc-opc.c (arc_flag_operands): Add new flags.
1515 (arc_flag_classes): Add new classes.
1516
1328504b
AB		 15172016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1518
1519 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1520
820f03ff
AB		 15212016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1522
1523 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1524 encode1, rflt, crc16, and crc32 instructions.
1525 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1526 (arc_flag_classes): Add C_NPS_R.
1527 (insert_nps_bitop_size_2b): New function.
1528 (extract_nps_bitop_size_2b): Likewise.
1529 (insert_nps_bitop_uimm8): Likewise.
1530 (extract_nps_bitop_uimm8): Likewise.
1531 (arc_operands): Add new operand entries.
1532
8ddf6b2a
CZ		 15332016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1534
b99747ae
CZ		 1535 * arc-regs.h: Add a new subclass field. Add double assist
1536 accumulator register values.
1537 * arc-tbl.h: Use DPA subclass to mark the double assist
1538 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1539 * arc-opc.c (RSP): Define instead of SP.
1540 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1541
589a7d88
JW		 15422016-04-05 Jiong Wang <jiong.wang@arm.com>
1543
1544 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1545
0a191de9 15462016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1547
1548 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1549 NPS_R_SRC1.
1550
0a106562
AB		 15512016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1552
1553 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1554 issues. No functional changes.
1555
bd05ac5f
CZ		 15562016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1557
b99747ae
CZ		 1558 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1559 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1560 (RTT): Remove duplicate.
1561 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1562 (PCT_CONFIG*): Remove.
1563 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1564
9885948f
CZ		 15652016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1566
b99747ae 1567 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1568
f2dd8838
CZ		 15692016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1570
b99747ae
CZ		 1571 * arc-tbl.h (invld07): Remove.
1572 * arc-ext-tbl.h: New file.
1573 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1574 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1575
0d2f91fe
JK		 15762016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1577
1578 Fix -Wstack-usage warnings.
1579 * aarch64-dis.c (print_operands): Substitute size.
1580 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1581
a6b71f42
JM		 15822016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1583
1584 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1585 to get a proper diagnostic when an invalid ASR register is used.
1586
9780e045
NC		 15872016-03-22 Nick Clifton <nickc@redhat.com>
1588
1589 * configure: Regenerate.
1590
e23e8ebe
AB		 15912016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1592
1593 * arc-nps400-tbl.h: New file.
1594 * arc-opc.c: Add top level comment.
1595 (insert_nps_3bit_dst): New function.
1596 (extract_nps_3bit_dst): New function.
1597 (insert_nps_3bit_src2): New function.
1598 (extract_nps_3bit_src2): New function.
1599 (insert_nps_bitop_size): New function.
1600 (extract_nps_bitop_size): New function.
1601 (arc_flag_operands): Add nps400 entries.
1602 (arc_flag_classes): Add nps400 entries.
1603 (arc_operands): Add nps400 entries.
1604 (arc_opcodes): Add nps400 include.
1605
1ae8ab47
AB		 16062016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1607
1608 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1609 the new class enum values.
1610
8699fc3e
AB		 16112016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1612
1613 * arc-dis.c (print_insn_arc): Handle nps400.
1614
24740d83
AB		 16152016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1616
1617 * arc-opc.c (BASE): Delete.
1618
8678914f
NC		 16192016-03-18 Nick Clifton <nickc@redhat.com>
1620
1621 PR target/19721
1622 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1623 of MOV insn that aliases an ORR insn.
1624
cc933301
JW		 16252016-03-16 Jiong Wang <jiong.wang@arm.com>
1626
1627 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1628
f86f5863
TS		 16292016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1630
1631 * mcore-opc.h: Add const qualifiers.
1632 * microblaze-opc.h (struct op_code_struct): Likewise.
1633 * sh-opc.h: Likewise.
1634 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1635 (tic4x_print_op): Likewise.
1636
62de1c63
AM		 16372016-03-02 Alan Modra <amodra@gmail.com>
1638
d11698cd 1639 * or1k-desc.h: Regenerate.
62de1c63 1640 * fr30-ibld.c: Regenerate.
c697cf0b 1641 * rl78-decode.c: Regenerate.
62de1c63 1642
020efce5
NC		 16432016-03-01 Nick Clifton <nickc@redhat.com>
1644
1645 PR target/19747
1646 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1647
b0c11777
RL		 16482016-02-24 Renlin Li <renlin.li@arm.com>
1649
1650 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1651 (print_insn_coprocessor): Support fp16 instructions.
1652
3e309328
RL		 16532016-02-24 Renlin Li <renlin.li@arm.com>
1654
1655 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1656 vminnm, vrint(mpna).
1657
8afc7bea
RL		 16582016-02-24 Renlin Li <renlin.li@arm.com>
1659
1660 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1661 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1662
4fd7268a
L		 16632016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1664
1665 * i386-dis.c (print_insn): Parenthesize expression to prevent
1666 truncated addresses.
1667 (OP_J): Likewise.
1668
4670103e
CZ		 16692016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1670 Janek van Oirschot <jvanoirs@synopsys.com>
1671
b99747ae
CZ		 1672 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1673 variable.
4670103e 1674
c1d9289f
NC		 16752016-02-04 Nick Clifton <nickc@redhat.com>
1676
1677 PR target/19561
1678 * msp430-dis.c (print_insn_msp430): Add a special case for
1679 decoding an RRC instruction with the ZC bit set in the extension
1680 word.
1681
a143b004
AB		 16822016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1683
1684 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1685 * epiphany-ibld.c: Regenerate.
1686 * fr30-ibld.c: Regenerate.
1687 * frv-ibld.c: Regenerate.
1688 * ip2k-ibld.c: Regenerate.
1689 * iq2000-ibld.c: Regenerate.
1690 * lm32-ibld.c: Regenerate.
1691 * m32c-ibld.c: Regenerate.
1692 * m32r-ibld.c: Regenerate.
1693 * mep-ibld.c: Regenerate.
1694 * mt-ibld.c: Regenerate.
1695 * or1k-ibld.c: Regenerate.
1696 * xc16x-ibld.c: Regenerate.
1697 * xstormy16-ibld.c: Regenerate.
1698
b89807c6
AB		 16992016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1700
1701 * epiphany-dis.c: Regenerated from latest cpu files.
1702
d8c823c8
MM		 17032016-02-01 Michael McConville <mmcco@mykolab.com>
1704
1705 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1706 test bit.
1707
5bc5ae88
RL		 17082016-01-25 Renlin Li <renlin.li@arm.com>
1709
1710 * arm-dis.c (mapping_symbol_for_insn): New function.
1711 (find_ifthen_state): Call mapping_symbol_for_insn().
1712
0bff6e2d
MW		 17132016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1714
1715 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1716 of MSR UAO immediate operand.
1717
100b4f2e
MR		 17182016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1719
1720 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1721 instruction support.
1722
5c14705f
AM		 17232016-01-17 Alan Modra <amodra@gmail.com>
1724
1725 * configure: Regenerate.
1726
4d82fe66
NC		 17272016-01-14 Nick Clifton <nickc@redhat.com>
1728
1729 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1730 instructions that can support stack pointer operations.
1731 * rl78-decode.c: Regenerate.
1732 * rl78-dis.c: Fix display of stack pointer in MOVW based
1733 instructions.
1734
651657fa
MW		 17352016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1736
1737 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1738 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1739 erxtatus_el1 and erxaddr_el1.
1740
105bde57
MW		 17412016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1742
1743 * arm-dis.c (arm_opcodes): Add "esb".
1744 (thumb_opcodes): Likewise.
1745
afa8d405
PB		 17462016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1747
1748 * ppc-opc.c <xscmpnedp>: Delete.
1749 <xvcmpnedp>: Likewise.
1750 <xvcmpnedp.>: Likewise.
1751 <xvcmpnesp>: Likewise.
1752 <xvcmpnesp.>: Likewise.
1753
83c3256e
AS		 17542016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1755
1756 PR gas/13050
1757 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1758 addition to ISA_A.
1759
6f2750fe
AM		 17602016-01-01 Alan Modra <amodra@gmail.com>
1761
1762 Update year range in copyright notice of all files.
1763
3499769a
AM		 1764For older changes see ChangeLog-2015
1765\f
1766Copyright (C) 2016 Free Software Foundation, Inc.
1767
1768Copying and distribution of this file, with or without modification,
1769are permitted in any medium without royalty provided the copyright
1770notice and this notice are preserved.
1771
1772Local Variables:
1773mode: change-log
1774left-margin: 8
1775fill-column: 74
1776version-control: never
1777End:
GDB Binutils - Deliverables
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