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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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7903e530
RM		 12013-10-10 Roland McGrath <mcgrathr@google.com>
2
2b4e983c
RM		 3 * cr16-opc.c (REG): Cast NAME to 'reg' enum type to suppress
4 possible compiler warnings when the union's initializer is
5 actually meant for the 'preg' enum typed member.
6 * crx-opc.c (REG): Likewise.
7
7903e530
RM		 8 * v850-dis.c (v850_cacheop_codes, v850_prefop_codes):
9 Remove duplicate const qualifier.
10
79e0e31d
JB		 112013-10-08 Jan Beulich <jbeulich@suse.com>
12
13 * i386-opc.tbl (invlpg): Use Anysize instead of Unspecified.
14 (clflush): Use Anysize instead of Byte|Unspecified.
15 (prefetch*): Likewise.
16 * i386-tbl.h: Re-generate.
17
45099dfa
CF		 182013-10-07 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
19
20 * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
21
916fae91
L		 222013-09-30 H.J. Lu <hongjiu.lu@intel.com>
23
24 * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
25 * i386-init.h: Regenerated.
26
c7b0bd56
SE		 272013-09-30 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
28
29 * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
30 * i386-init.h: Regenerated.
31
cc9afea3
AM		 322013-09-20 Alan Modra <amodra@gmail.com>
33
34 * configure: Regenerate.
35
e3f9e852
RS		 362013-09-17 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
37
38 * s390-opc.txt (clih): Make the immediate unsigned.
39
74db7efb
NC		 402013-09-04 Roland McGrath <mcgrathr@google.com>
41
42 PR gas/15914
43 * arm-dis.c (arm_opcodes): Add udf.
44 (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
45 (thumb32_opcodes): Add udf.w.
46 (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
47
c8094e01
AK		 482013-09-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
49
50 * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
51 For the load fp integer instructions only the suppression flag was
52 new with z196 version.
53
7e105031
NC		 542013-08-28 Nick Clifton <nickc@redhat.com>
55
56 * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
57 immediate is not suitable for the 32-bit ABI.
58
fb6f3895
MR		 592013-08-23 Maciej W. Rozycki <macro@codesourcery.com>
60
61 * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
62 replacing NODS.
63
9aff4b7a
NC		 642013-08-23 Yuri Chornoivan <yurchor@ukr.net>
65
66 PR binutils/15834
67 * aarch64-asm.c: Fix typos.
68 * aarch64-dis.c: Likewise.
69 * msp430-dis.c: Likewise.
70
5e0dc5ba
RS		 712013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
72
73 * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
74 macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
75 Use +H rather than +C for the real "dext".
76 * mips-opc.c (mips_builtin_opcodes): Likewise.
77
0f35dbc4
RS		 782013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
79
80 * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
81 * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
82 and OPTIONAL_MAPPED_REG.
83 * mips-opc.c (decode_mips_operand): Likewise.
84 * mips16-opc.c (decode_mips16_operand): Likewise.
85 * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
86
79ceb7cb
L		 872013-08-19 H.J. Lu <hongjiu.lu@intel.com>
88
89 * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
90 (PREFIX_EVEX_0F3A3F): Likewise.
91 * i386-dis-evex.h (evex_table): Updated.
92
ee5734f0
RS		 932013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
94
95 * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
96 VCLIPW.
97
d6787ef9
EB		 982013-08-05 Eric Botcazou <ebotcazou@adacore.com>
99 Konrad Eisele <konrad@gaisler.com>
100
101 * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
102 bfd_mach_sparc.
103 * sparc-opc.c (MASK_LEON): Define.
104 (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
105 (letandleon): New macro.
106 (v9andleon): Likewise.
107 (sparc_opc): Add leon.
108 (umac): Enable for letandleon.
109 (smac): Likewise.
110 (casa): Enable for v9andleon.
111 (cas): Likewise.
112 (casl): Likewise.
113
14daeee3
RS		 1142013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
115 Richard Sandiford <rdsandiford@googlemail.com>
116
117 * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
118 OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
119 (print_vu0_channel): New function.
120 (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
121 (print_insn_args): Handle '#'.
122 (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
123 * mips-opc.c (mips_vu0_channel_mask): New constant.
124 (decode_mips_operand): Handle new VU0 operand types.
125 (VU0, VU0CH): New macros.
126 (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
127 for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
128 Use "+6" rather than "G" for QMFC2 and QMTC2.
129
3ccad066
RS		 1302013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
131
132 * mips-formats.h (PCREL): Reorder parameters and update the definition
133 to match new mips_pcrel_operand layout.
134 (JUMP, JALX, BRANCH): Update accordingly.
135 * mips16-opc.c (decode_mips16_operand): Likewise.
136
df34fbcc
RS		 1372013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
138
139 * micromips-opc.c (WR_s): Delete.
140
fc76e730
RS		 1412013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
142
143 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
144 New macros.
145 (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
146 (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
147 (mips_builtin_opcodes): Use the new position-based read-write flags
148 instead of field-based ones. Use UDI for "udi..." instructions.
149 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
150 New macros.
151 (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
152 (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
153 (WR_SP, RD_16): New macros.
154 (RD_SP): Redefine as an INSN2_* flag.
155 (MOD_SP): Redefine in terms of RD_SP and WR_SP.
156 (mips16_opcodes): Use the new position-based read-write flags
157 instead of field-based ones. Use RD_16 for "nop". Move RD_SP to
158 pinfo2 field.
159 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
160 New macros.
161 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
162 (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
163 (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
164 (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
165 (micromips_opcodes): Use the new position-based read-write flags
166 instead of field-based ones.
167 * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
168 (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
169 of field-based flags.
170
26545944
RS		 1712013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
172
173 * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
174 (WR_SP): Replace with...
175 (MOD_SP): ...this.
176 (mips16_opcodes): Update accordingly.
177 * mips-dis.c (print_insn_mips16): Likewise.
178
a8d92fc6
RS		 1792013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
180
181 * mips16-opc.c (mips16_opcodes): Reformat.
182
6a819047
RS		 1832013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
184
185 * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
186 for operands that are hard-coded to $0.
187 * micromips-opc.c (micromips_opcodes): Likewise.
188
344c74a6
RS		 1892013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
190
191 * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
192 for the single-operand forms of JALR and JALR.HB.
193 * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
194 and JALRS.HB.
195
41989114
RS		 1962013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
197
198 * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
199 instructions. Fix them to use WR_MACC instead of WR_CC and
200 add missing RD_MACCs.
201
6d075bce
RS		 2022013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
203
204 * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
205
4f6ffcd3
PB		 2062013-07-29 Peter Bergner <bergner@vnet.ibm.com>
207
208 * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
209
43234a1e
L		 2102013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
211 Alexander Ivchenko <alexander.ivchenko@intel.com>
212 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
213 Sergey Lega <sergey.s.lega@intel.com>
214 Anna Tikhonova <anna.tikhonova@intel.com>
215 Ilya Tocar <ilya.tocar@intel.com>
216 Andrey Turetskiy <andrey.turetskiy@intel.com>
217 Ilya Verbin <ilya.verbin@intel.com>
218 Kirill Yukhin <kirill.yukhin@intel.com>
219 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
220
221 * i386-dis-evex.h: New.
222 * i386-dis.c (OP_Rounding): New.
223 (VPCMP_Fixup): New.
224 (OP_Mask): New.
225 (Rdq): New.
226 (XMxmmq): New.
227 (EXdScalarS): New.
228 (EXymm): New.
229 (EXEvexHalfBcstXmmq): New.
230 (EXxmm_mdq): New.
231 (EXEvexXGscat): New.
232 (EXEvexXNoBcst): New.
233 (VPCMP): New.
234 (EXxEVexR): New.
235 (EXxEVexS): New.
236 (XMask): New.
237 (MaskG): New.
238 (MaskE): New.
239 (MaskR): New.
240 (MaskVex): New.
241 (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
242 evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
243 evex_rounding_mode, evex_sae_mode, mask_mode.
244 (USE_EVEX_TABLE): New.
245 (EVEX_TABLE): New.
246 (EVEX enum): New.
247 (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
248 REG_EVEX_0F38C7.
249 (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
250 MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
251 MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
252 MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
253 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
254 MOD_EVEX_0F38C7_REG_6.
255 (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
256 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
257 PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
258 PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
259 PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
260 PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
261 PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
262 PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
263 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
264 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
265 PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
266 PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
267 PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
268 PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
269 PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
270 PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
271 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
272 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
273 PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
274 PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
275 PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
276 PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
277 PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
278 PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
279 PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
280 PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
281 PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
282 PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
283 PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
284 PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
285 PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
286 PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
287 PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
288 PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
289 PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
290 PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
291 PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
292 PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
293 PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
294 PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
295 PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
296 PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
297 PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
298 PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
299 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
300 PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
301 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
302 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
303 PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
304 PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
305 PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
306 PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
307 PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
308 PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
309 PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
310 PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
311 PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
312 PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
313 PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
314 PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
315 PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
316 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
317 PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
318 PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
319 PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
320 PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
321 PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
322 PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
323 PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
324 PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
325 PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
326 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
327 PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
328 PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
329 PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
330 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
331 PREFIX_EVEX_0F3A55.
332 (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
333 VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
334 VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
335 VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
336 VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
337 VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
338 VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
339 VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
340 VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
341 VEX_W_0F3A32_P_2_LEN_0.
342 (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
343 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
344 EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
345 EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
346 EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
347 EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
348 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
349 EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
350 EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
351 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
352 EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
353 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
354 EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
355 EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
356 EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
357 EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
358 EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
359 EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
360 EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
361 EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
362 EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
363 EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
364 EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
365 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
366 EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
367 EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
368 EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
369 EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
370 EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
371 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
372 EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
373 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
374 EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
375 EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
376 EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
377 EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
378 EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
379 EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
380 EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
381 EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
382 EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
383 EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
384 EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
385 EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
386 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
387 EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
388 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
389 EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
390 EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
391 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
392 EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
393 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
394 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
395 EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
396 (struct vex): Add fields evex, r, v, mask_register_specifier,
397 zeroing, ll, b.
398 (intel_names_xmm): Add upper 16 registers.
399 (att_names_xmm): Ditto.
400 (intel_names_ymm): Ditto.
401 (att_names_ymm): Ditto.
402 (names_zmm): New.
403 (intel_names_zmm): Ditto.
404 (att_names_zmm): Ditto.
405 (names_mask): Ditto.
406 (intel_names_mask): Ditto.
407 (att_names_mask): Ditto.
408 (names_rounding): Ditto.
409 (names_broadcast): Ditto.
410 (x86_64_table): Add escape to evex-table.
411 (reg_table): Include reg_table evex-entries from
412 i386-dis-evex.h. Fix prefetchwt1 instruction.
413 (prefix_table): Add entries for new instructions.
414 (vex_table): Ditto.
415 (vex_len_table): Ditto.
416 (vex_w_table): Ditto.
417 (mod_table): Ditto.
418 (get_valid_dis386): Properly handle new instructions.
419 (print_insn): Handle zmm and mask registers, print mask operand.
420 (intel_operand_size): Support EVEX, new modes and sizes.
421 (OP_E_register): Handle new modes.
422 (OP_E_memory): Ditto.
423 (OP_G): Ditto.
424 (OP_XMM): Ditto.
425 (OP_EX): Ditto.
426 (OP_VEX): Ditto.
427 * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
428 CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
429 CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
430 (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
431 CpuAVX512PF and CpuVREX.
432 (operand_type_init): Add OPERAND_TYPE_REGZMM,
433 OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
434 (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
435 StaticRounding, SAE, Disp8MemShift, NoDefMask.
436 (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
437 * i386-init.h: Regenerate.
438 * i386-opc.h (CpuAVX512F): New.
439 (CpuAVX512CD): New.
440 (CpuAVX512ER): New.
441 (CpuAVX512PF): New.
442 (CpuVREX): New.
443 (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
444 cpuavx512pf and cpuvrex fields.
445 (VecSIB): Add VecSIB512.
446 (EVex): New.
447 (Masking): New.
448 (VecESize): New.
449 (Broadcast): New.
450 (StaticRounding): New.
451 (SAE): New.
452 (Disp8MemShift): New.
453 (NoDefMask): New.
454 (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
455 staticrounding, sae, disp8memshift and nodefmask.
456 (RegZMM): New.
457 (Zmmword): Ditto.
458 (Vec_Disp8): Ditto.
459 (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
460 fields.
461 (RegVRex): New.
462 * i386-opc.tbl: Add AVX512 instructions.
463 * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
464 registers, mask registers.
465 * i386-tbl.h: Regenerate.
466
1d2db237
RS		 4672013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
468
469 PR gas/15220
470 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
471 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
472
a0046408
L		 4732013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
474
475 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
476 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
477 PREFIX_0F3ACC.
478 (prefix_table): Updated.
479 (three_byte_table): Likewise.
480 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
481 (cpu_flags): Add CpuSHA.
482 (i386_cpu_flags): Add cpusha.
483 * i386-init.h: Regenerate.
484 * i386-opc.h (CpuSHA): New.
485 (CpuUnused): Restored.
486 (i386_cpu_flags): Add cpusha.
487 * i386-opc.tbl: Add SHA instructions.
488 * i386-tbl.h: Regenerate.
489
7e8b059b
L		 4902013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
491 Kirill Yukhin <kirill.yukhin@intel.com>
492 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
493
494 * i386-dis.c (BND_Fixup): New.
495 (Ebnd): New.
496 (Ev_bnd): New.
497 (Gbnd): New.
498 (BND): New.
499 (v_bnd_mode): New.
500 (bnd_mode): New.
c623f86c
L		 501 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
502 MOD_0F1B_PREFIX_1.
503 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
7e8b059b
L		 504 (dis tables): Replace XX with BND for near branch and call
505 instructions.
506 (prefix_table): Add new entries.
507 (mod_table): Likewise.
508 (names_bnd): New.
509 (intel_names_bnd): New.
510 (att_names_bnd): New.
511 (BND_PREFIX): New.
512 (prefix_name): Handle BND_PREFIX.
513 (print_insn): Initialize names_bnd.
514 (intel_operand_size): Handle new modes.
515 (OP_E_register): Likewise.
516 (OP_E_memory): Likewise.
517 (OP_G): Likewise.
518 * i386-gen.c (cpu_flag_init): Add CpuMPX.
519 (cpu_flags): Add CpuMPX.
520 (operand_type_init): Add RegBND.
521 (opcode_modifiers): Add BNDPrefixOk.
522 (operand_types): Add RegBND.
523 * i386-init.h: Regenerate.
524 * i386-opc.h (CpuMPX): New.
525 (CpuUnused): Comment out.
526 (i386_cpu_flags): Add cpumpx.
527 (BNDPrefixOk): New.
528 (i386_opcode_modifier): Add bndprefixok.
529 (RegBND): New.
530 (i386_operand_type): Add regbnd.
531 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
532 Add MPX instructions and bnd prefix.
533 * i386-reg.tbl: Add bnd0-bnd3 registers.
534 * i386-tbl.h: Regenerate.
535
b56e23fb
RS		 5362013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
537
538 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
539 ATTRIBUTE_UNUSED.
540
e7ae278d
RS		 5412013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
542
543 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
544 special rules.
545 * Makefile.in: Regenerate.
546 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
547 all fields. Reformat.
548
c3c07478
RS		 5492013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
550
551 * mips16-opc.c: Include mips-formats.h.
552 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
553 static arrays.
554 (decode_mips16_operand): New function.
555 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
556 (print_insn_arg): Handle OP_ENTRY_EXIT list.
557 Abort for OP_SAVE_RESTORE_LIST.
558 (print_mips16_insn_arg): Change interface. Use mips_operand
559 structures. Delete GET_OP_S. Move GET_OP definition to...
560 (print_insn_mips16): ...here. Call init_print_arg_state.
561 Update the call to print_mips16_insn_arg.
562
ab902481
RS		 5632013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
564
565 * mips-formats.h: New file.
566 * mips-opc.c: Include mips-formats.h.
567 (reg_0_map): New static array.
568 (decode_mips_operand): New function.
569 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
570 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
571 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
572 (int_c_map): New static arrays.
573 (decode_micromips_operand): New function.
574 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
575 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
576 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
577 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
578 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
579 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
580 (micromips_imm_b_map, micromips_imm_c_map): Delete.
581 (print_reg): New function.
582 (mips_print_arg_state): New structure.
583 (init_print_arg_state, print_insn_arg): New functions.
584 (print_insn_args): Change interface and use mips_operand structures.
585 Delete GET_OP_S. Move GET_OP definition to...
586 (print_insn_mips): ...here. Update the call to print_insn_args.
587 (print_insn_micromips): Use print_insn_args.
588
cc537e56
RS		 5892013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
590
591 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
592 in macros.
593
7a5f87ce
RS		 5942013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
595
596 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
597 ADDA.S, MULA.S and SUBA.S.
598
41741fa4
L		 5992013-07-08 H.J. Lu <hongjiu.lu@intel.com>
600
601 PR gas/13572
602 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
603 * i386-tbl.h: Regenerated.
604
f2ae14a1
RS		 6052013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
606
607 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
608 and SD A(B) macros up.
609 * micromips-opc.c (micromips_opcodes): Likewise.
610
04c9d415
RS		 6112013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
612
613 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
614 instructions.
615
5c324c16
RS		 6162013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
617
618 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
619 MDMX-like instructions.
620 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
621 printing "Q" operands for INSN_5400 instructions.
622
23e69e47
RS		 6232013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
624
625 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
626 "+S" for "cins".
627 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
628 Combine cases.
629
27c5c572
RS		 6302013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
631
632 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
633 "jalx".
634 * mips16-opc.c (mips16_opcodes): Likewise.
635 * micromips-opc.c (micromips_opcodes): Likewise.
636 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
637 (print_insn_mips16): Handle "+i".
638 (print_insn_micromips): Likewise. Conditionally preserve the
639 ISA bit for "a" but not for "+i".
640
e76ff5ab
RS		 6412013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
642
643 * micromips-opc.c (WR_mhi): Rename to..
644 (WR_mh): ...this.
645 (micromips_opcodes): Update "movep" entry accordingly. Replace
646 "mh,mi" with "mh".
647 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
648 (micromips_to_32_reg_h_map1): ...this.
649 (micromips_to_32_reg_i_map): Rename to...
650 (micromips_to_32_reg_h_map2): ...this.
651 (print_micromips_insn): Remove "mi" case. Print both registers
652 in the pair for "mh".
653
fa7616a4
RS		 6542013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
655
656 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
657 * micromips-opc.c (micromips_opcodes): Likewise.
658 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
659 and "+T" handling. Check for a "0" suffix when deciding whether to
660 use coprocessor 0 names. In that case, also check for ",H" selectors.
661
fb798c50
AK		 6622013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
663
664 * s390-opc.c (J12_12, J24_24): New macros.
665 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
666 (MASK_MII_UPI): Rename to MASK_MII_UPP.
667 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
668
58ae08f2
AM		 6692013-07-04 Alan Modra <amodra@gmail.com>
670
671 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
672
b5e04c2b
NC		 6732013-06-26 Nick Clifton <nickc@redhat.com>
674
675 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
676 field when checking for type 2 nop.
677 * rx-decode.c: Regenerate.
678
833794fc
MR		 6792013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
680
681 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
682 and "movep" macros.
683
1bbce132
MR		 6842013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
685
686 * mips-dis.c (is_mips16_plt_tail): New function.
687 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
688 word.
689 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
690
34c911a4
NC		 6912013-06-21 DJ Delorie <dj@redhat.com>
692
693 * msp430-decode.opc: New.
694 * msp430-decode.c: New/generated.
695 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
696 (MAINTAINER_CLEANFILES): Likewise.
697 Add rule to build msp430-decode.c frommsp430decode.opc
698 using the opc2c program.
699 * Makefile.in: Regenerate.
700 * configure.in: Add msp430-decode.lo to msp430 architecture files.
701 * configure: Regenerate.
702
b9eead84
YZ		 7032013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
704
705 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
706 (SYMTAB_AVAILABLE): Removed.
707 (#include "elf/aarch64.h): Ditto.
708
7f3c4072
CM		 7092013-06-17 Catherine Moore <clm@codesourcery.com>
710 Maciej W. Rozycki <macro@codesourcery.com>
711 Chao-Ying Fu <fu@mips.com>
712
713 * micromips-opc.c (EVA): Define.
714 (TLBINV): Define.
715 (micromips_opcodes): Add EVA opcodes.
716 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
717 (print_insn_args): Handle EVA offsets.
718 (print_insn_micromips): Likewise.
719 * mips-opc.c (EVA): Define.
720 (TLBINV): Define.
721 (mips_builtin_opcodes): Add EVA opcodes.
722
de40ceb6
AM		 7232013-06-17 Alan Modra <amodra@gmail.com>
724
725 * Makefile.am (mips-opc.lo): Add rules to create automatic
726 dependency files. Pass archdefs.
727 (micromips-opc.lo, mips16-opc.lo): Likewise.
728 * Makefile.in: Regenerate.
729
3531d549
DD		 7302013-06-14 DJ Delorie <dj@redhat.com>
731
732 * rx-decode.opc (rx_decode_opcode): Bit operations on
733 registers are 32-bit operations, not 8-bit operations.
734 * rx-decode.c: Regenerate.
735
ba92f7fb
CF		 7362013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
737
738 * micromips-opc.c (IVIRT): New define.
739 (IVIRT64): New define.
740 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
741 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
742
743 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
744 dmtgc0 to print cp0 names.
745
9daf7bab
SL		 7462013-06-09 Sandra Loosemore <sandra@codesourcery.com>
747
748 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
749 argument.
750
d301a56b
RS		 7512013-06-08 Catherine Moore <clm@codesourcery.com>
752 Richard Sandiford <rdsandiford@googlemail.com>
753
754 * micromips-opc.c (D32, D33, MC): Update definitions.
755 (micromips_opcodes): Initialize ase field.
756 * mips-dis.c (mips_arch_choice): Add ase field.
757 (mips_arch_choices): Initialize ase field.
758 (set_default_mips_dis_options): Declare and setup mips_ase.
759 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
760 MT32, MC): Update definitions.
761 (mips_builtin_opcodes): Initialize ase field.
762
a3dcb6c5
RS		 7632013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
764
765 * s390-opc.txt (flogr): Require a register pair destination.
766
6cf1d90c
AK		 7672013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
768
769 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
770 instruction format.
771
c77c0862
RS		 7722013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
773
774 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
775
c0637f3a
PB		 7762013-05-20 Peter Bergner <bergner@vnet.ibm.com>
777
778 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
779 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
780 XLS_MASK, PPCVSX2): New defines.
781 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
782 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
783 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
784 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
785 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
786 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
787 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
788 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
789 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
790 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
791 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
792 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
793 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
794 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
795 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
796 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
797 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
798 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
799 <lxvx, stxvx>: New extended mnemonics.
800
4934fdaf
AM		 8012013-05-17 Alan Modra <amodra@gmail.com>
802
803 * ia64-raw.tbl: Replace non-ASCII char.
804 * ia64-waw.tbl: Likewise.
805 * ia64-asmtab.c: Regenerate.
806
6091d651
SE		 8072013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
808
809 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
810 * i386-init.h: Regenerated.
811
d2865ed3
YZ		 8122013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
813
814 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
815 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
816 check from [0, 255] to [-128, 255].
817
b015e599
AP		 8182013-05-09 Andrew Pinski <apinski@cavium.com>
819
820 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
821 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
822 (parse_mips_dis_option): Handle the virt option.
823 (print_insn_args): Handle "+J".
824 (print_mips_disassembler_options): Print out message about virt64.
825 * mips-opc.c (IVIRT): New define.
826 (IVIRT64): New define.
827 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
828 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
829 Move rfe to the bottom as it conflicts with tlbgp.
830
9f0682fe
AM		 8312013-05-09 Alan Modra <amodra@gmail.com>
832
833 * ppc-opc.c (extract_vlesi): Properly sign extend.
834 (extract_vlensi): Likewise. Comment reason for setting invalid.
835
13761a11
NC		 8362013-05-02 Nick Clifton <nickc@redhat.com>
837
838 * msp430-dis.c: Add support for MSP430X instructions.
839
e3031850
SL		 8402013-04-24 Sandra Loosemore <sandra@codesourcery.com>
841
842 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
843 to "eccinj".
844
17310e56
NC		 8452013-04-17 Wei-chen Wang <cole945@gmail.com>
846
847 PR binutils/15369
848 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
849 of CGEN_CPU_ENDIAN.
850 (hash_insns_list): Likewise.
851
731df338
JK		 8522013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
853
854 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
855 warning workaround.
856
5f77db52
JB		 8572013-04-08 Jan Beulich <jbeulich@suse.com>
858
859 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
860 * i386-tbl.h: Re-generate.
861
0afd1215
DM		 8622013-04-06 David S. Miller <davem@davemloft.net>
863
864 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
865 of an opcode, prefer the one with F_PREFERRED set.
866 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
867 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
868 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
869 mark existing mnenomics as aliases. Add "cc" suffix to edge
870 instructions generating condition codes, mark existing mnenomics
871 as aliases. Add "fp" prefix to VIS compare instructions, mark
872 existing mnenomics as aliases.
873
41702d50
NC		 8742013-04-03 Nick Clifton <nickc@redhat.com>
875
876 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
877 destination address by subtracting the operand from the current
878 address.
879 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
880 a positive value in the insn.
881 (extract_u16_loop): Do not negate the returned value.
882 (D16_LOOP): Add V850_INVERSE_PCREL flag.
883
884 (ceilf.sw): Remove duplicate entry.
885 (cvtf.hs): New entry.
886 (cvtf.sh): Likewise.
887 (fmaf.s): Likewise.
888 (fmsf.s): Likewise.
889 (fnmaf.s): Likewise.
890 (fnmsf.s): Likewise.
891 (maddf.s): Restrict to E3V5 architectures.
892 (msubf.s): Likewise.
893 (nmaddf.s): Likewise.
894 (nmsubf.s): Likewise.
895
55cf16e1
L		 8962013-03-27 H.J. Lu <hongjiu.lu@intel.com>
897
898 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
899 check address mode.
900 (print_insn): Pass sizeflag to get_sib.
901
51dcdd4d
NC		 9022013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
903
904 PR binutils/15068
905 * tic6x-dis.c: Add support for displaying 16-bit insns.
906
795b8e6b
NC		 9072013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
908
909 PR gas/15095
910 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
911 individual msb and lsb halves in src1 & src2 fields. Discard the
912 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
913 follow what Ti SDK does in that case as any value in the src1
914 field yields the same output with SDK disassembler.
915
314d60dd
ME		 9162013-03-12 Michael Eager <eager@eagercon.com>
917
795b8e6b 918 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd 919
dad60f8e
SL		 9202013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
921
922 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
923
f5cb796a
SL		 9242013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
925
926 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
927
21fde85c
SL		 9282013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
929
930 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
931
dd5181d5
KT		 9322013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
933
934 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
935 (thumb32_opcodes): Likewise.
936 (print_insn_thumb32): Handle 'S' control char.
937
87a8d6cb
NC		 9382013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
939
940 * lm32-desc.c: Regenerate.
941
99dce992
L		 9422013-03-01 H.J. Lu <hongjiu.lu@intel.com>
943
944 * i386-reg.tbl (riz): Add RegRex64.
945 * i386-tbl.h: Regenerated.
946
e60bb1dd
YZ		 9472013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
948
949 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
950 (aarch64_feature_crc): New static.
951 (CRC): New macro.
952 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
953 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
954 * aarch64-asm-2.c: Re-generate.
955 * aarch64-dis-2.c: Ditto.
956 * aarch64-opc-2.c: Ditto.
957
c7570fcd
AM		 9582013-02-27 Alan Modra <amodra@gmail.com>
959
960 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
961 * rl78-decode.c: Regenerate.
962
151fa98f
NC		 9632013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
964
965 * rl78-decode.opc: Fix encoding of DIVWU insn.
966 * rl78-decode.c: Regenerate.
967
5c111e37
L		 9682013-02-19 H.J. Lu <hongjiu.lu@intel.com>
969
970 PR gas/15159
971 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
972
973 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
974 (cpu_flags): Add CpuSMAP.
975
976 * i386-opc.h (CpuSMAP): New.
977 (i386_cpu_flags): Add cpusmap.
978
979 * i386-opc.tbl: Add clac and stac.
980
981 * i386-init.h: Regenerated.
982 * i386-tbl.h: Likewise.
983
9d1df426
NC		 9842013-02-15 Markos Chandras <markos.chandras@imgtec.com>
985
986 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
987 which also makes the disassembler output be in little
988 endian like it should be.
989
a1ccaec9
YZ		 9902013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
991
992 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
993 fields to NULL.
994 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
995
ef068ef4 9962013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e
MR		 997
998 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
999 section disassembled.
1000
6fe6ded9
RE		 10012013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1002
1003 * arm-dis.c: Update strht pattern.
1004
0aa27725
RS		 10052013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
1006
1007 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
1008 single-float. Disable ll, lld, sc and scd for EE. Disable the
1009 trunc.w.s macro for EE.
1010
36591ba1
SL		 10112013-02-06 Sandra Loosemore <sandra@codesourcery.com>
1012 Andrew Jenner <andrew@codesourcery.com>
1013
1014 Based on patches from Altera Corporation.
1015
1016 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
1017 nios2-opc.c.
1018 * Makefile.in: Regenerated.
1019 * configure.in: Add case for bfd_nios2_arch.
1020 * configure: Regenerated.
1021 * disassemble.c (ARCH_nios2): Define.
1022 (disassembler): Add case for bfd_arch_nios2.
1023 * nios2-dis.c: New file.
1024 * nios2-opc.c: New file.
1025
545093a4
AM		 10262013-02-04 Alan Modra <amodra@gmail.com>
1027
1028 * po/POTFILES.in: Regenerate.
1029 * rl78-decode.c: Regenerate.
1030 * rx-decode.c: Regenerate.
1031
e30181a5
YZ		 10322013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
1033
1034 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
1035 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
1036 * aarch64-asm.c (convert_xtl_to_shll): New function.
1037 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1038 calling convert_xtl_to_shll.
1039 * aarch64-dis.c (convert_shll_to_xtl): New function.
1040 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1041 calling convert_shll_to_xtl.
1042 * aarch64-gen.c: Update copyright year.
1043 * aarch64-asm-2.c: Re-generate.
1044 * aarch64-dis-2.c: Re-generate.
1045 * aarch64-opc-2.c: Re-generate.
1046
78c8d46c
NC		 10472013-01-24 Nick Clifton <nickc@redhat.com>
1048
1049 * v850-dis.c: Add support for e3v5 architecture.
1050 * v850-opc.c: Likewise.
1051
f5555712
YZ		 10522013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
1053
1054 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1055 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1056 * aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c 1057 AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712
YZ		 1058 alignment check; change to call set_sft_amount_out_of_range_error
1059 instead of set_imm_out_of_range_error.
1060 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1061 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1062 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1063 SIMD_IMM_SFT.
1064
2f81ff92
L		 10652013-01-16 H.J. Lu <hongjiu.lu@intel.com>
1066
1067 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1068
1069 * i386-init.h: Regenerated.
1070 * i386-tbl.h: Likewise.
1071
dd42f060
NC		 10722013-01-15 Nick Clifton <nickc@redhat.com>
1073
1074 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1075 values.
1076 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1077
a4533ed8
NC		 10782013-01-14 Will Newton <will.newton@imgtec.com>
1079
1080 * metag-dis.c (REG_WIDTH): Increase to 64.
1081
5817ffd1
PB		 10822013-01-10 Peter Bergner <bergner@vnet.ibm.com>
1083
1084 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1085 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1086 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1087 (SH6): Update.
1088 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1089 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1090 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1091 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1092
a3c62988
NC		 10932013-01-10 Will Newton <will.newton@imgtec.com>
1094
1095 * Makefile.am: Add Meta.
1096 * configure.in: Add Meta.
1097 * disassemble.c: Add Meta support.
1098 * metag-dis.c: New file.
1099 * Makefile.in: Regenerate.
1100 * configure: Regenerate.
1101
73335eae
NC		 11022013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
1103
1104 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1105 (match_opcode): Rename to cr16_match_opcode.
1106
e407c74b
NC		 11072013-01-04 Juergen Urban <JuergenUrban@gmx.de>
1108
1109 * mips-dis.c: Add names for CP0 registers of r5900.
1110 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1111 instructions sq and lq.
1112 Add support for MIPS r5900 CPU.
1113 Add support for 128 bit MMI (Multimedia Instructions).
1114 Add support for EE instructions (Emotion Engine).
1115 Disable unsupported floating point instructions (64 bit and
1116 undefined compare operations).
1117 Enable instructions of MIPS ISA IV which are supported by r5900.
1118 Disable 64 bit co processor instructions.
1119 Disable 64 bit multiplication and division instructions.
1120 Disable instructions for co-processor 2 and 3, because these are
1121 not supported (preparation for later VU0 support (Vector Unit)).
1122 Disable cvt.w.s because this behaves like trunc.w.s and the
1123 correct execution can't be ensured on r5900.
1124 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1125 will confuse less developers and compilers.
1126
a32c3ff8
NC		 11272013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1128
fb098a1e
YZ		 1129 * aarch64-opc.c (aarch64_print_operand): Change to print
1130 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1131 in comment.
1132 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1133 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1134 OP_MOV_IMM_WIDE.
1135
11362013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1137
1138 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1139 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8 1140
62658407
L		 11412013-01-02 H.J. Lu <hongjiu.lu@intel.com>
1142
1143 * i386-gen.c (process_copyright): Update copyright year to 2013.
1144
bab4becb 11452013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7 1146
bab4becb
NC		 1147 * cr16-dis.c (match_opcode,make_instruction): Remove static
1148 declaration.
1149 (dwordU,wordU): Moved typedefs to opcode/cr16.h
1150 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7 1151
bab4becb 1152For older changes see ChangeLog-2012
252b5132 1153\f
bab4becb 1154Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC		 1155
1156Copying and distribution of this file, with or without modification,
1157are permitted in any medium without royalty provided the copyright
1158notice and this notice are preserved.
1159
252b5132 1160Local Variables:
2f6d2f85
NC		 1161mode: change-log
1162left-margin: 8
1163fill-column: 74
252b5132
RH		 1164version-control: never
1165End:
GDB Binutils - Deliverables
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