2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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12004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
2
3 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
4 Also correct mistake in the comment.
5
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62004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
7
8 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
9 ensure that double registers have even numbers.
10 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
11 that reserved instruction 0xfffd does not decode the same
12 as 0xfdfd (ftrv).
13 * sh-opc.h: Add REG_N_D nibble type and use it whereever
14 REG_N refers to a double register.
15 Add REG_N_B01 nibble type and use it instead of REG_NM
16 in ftrv.
17 Adjust the bit patterns in a few comments.
18
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192004-02-25 Aldy Hernandez <aldyh@redhat.com>
20
21 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
22
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232004-02-20 Aldy Hernandez <aldyh@redhat.com>
24
25 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
26
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272004-02-20 Aldy Hernandez <aldyh@redhat.com>
28
29 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
30
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312004-02-20 Aldy Hernandez <aldyh@redhat.com>
32
33 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
34 mtivor32, mtivor33, mtivor34.
35
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362004-02-19 Aldy Hernandez <aldyh@redhat.com>
37
f0b26da6 38 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
23d59c56 39
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402004-02-10 Petko Manolov <petkan@nucleusys.com>
41
42 * arm-opc.h Maverick accumulator register opcode fixes.
43
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442004-02-13 Ben Elliston <bje@wasabisystems.com>
45
46 * m32r-dis.c: Regenerate.
47
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482004-01-27 Michael Snyder <msnyder@redhat.com>
49
50 * sh-opc.h (sh_table): "fsrra", not "fssra".
51
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522004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
53
54 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
55 contraints.
56
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572004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
58
59 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
60
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612004-01-19 Alan Modra <amodra@bigpond.net.au>
62
63 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
64 1. Don't print scale factor on AT&T mode when index missing.
65
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662004-01-16 Alexandre Oliva <aoliva@redhat.com>
67
68 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
69 when loaded into XR registers.
70
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712004-01-14 Richard Sandiford <rsandifo@redhat.com>
72
73 * frv-desc.h: Regenerate.
74 * frv-desc.c: Regenerate.
75 * frv-opc.c: Regenerate.
76
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772004-01-13 Michael Snyder <msnyder@redhat.com>
78
79 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
80
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812004-01-09 Paul Brook <paul@codesourcery.com>
82
83 * arm-opc.h (arm_opcodes): Move generic mcrr after known
84 specific opcodes.
85
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862004-01-07 Daniel Jacobowitz <drow@mvista.com>
87
88 * Makefile.am (libopcodes_la_DEPENDENCIES)
89 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
90 comment about the problem.
91 * Makefile.in: Regenerate.
92
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932004-01-06 Alexandre Oliva <aoliva@redhat.com>
94
95 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
96 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
97 cut&paste errors in shifting/truncating numerical operands.
98 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
99 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
100 (parse_uslo16): Likewise.
101 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
102 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
103 (parse_s12): Likewise.
104 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
105 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
106 (parse_uslo16): Likewise.
107 (parse_uhi16): Parse gothi and gotfuncdeschi.
108 (parse_d12): Parse got12 and gotfuncdesc12.
109 (parse_s12): Likewise.
110
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1112004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
112
113 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
114 instruction which looks similar to an 'rla' instruction.
a0bd404e 115
c9e214e5 116For older changes see ChangeLog-0203
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