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Add myself as ft32 maintainer for sim.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
8e464506
AK		 12017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
2
3 * s390-opc.txt (prno, tpei, irbm): New instructions added.
4
ee6767da
AK		 52017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
6
7 * s390-opc.c (INSTR_SI_RD): New macro.
8 (INSTR_S_RD): Adjust example instruction.
9 * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
10 SI_RD.
11
d2e6c9a3
AF		 122017-10-01 Alexander Fedotov <alfedotov@gmail.com>
13
14 * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
15 e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
16 VLE multimple load/store instructions. Old e_ldm* variants are
17 kept as aliases.
18 Add missing e_lmvmcsrrw and e_stmvmcsrrw.
19
8e43602e
NC		 202017-09-27 Nick Clifton <nickc@redhat.com>
21
22 PR 22179
23 * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
24 names for the fmv.x.s and fmv.s.x instructions respectively.
25
58a0b827
NC		 262017-09-26 do <do@nerilex.org>
27
28 PR 22123
29 * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
30 be used on CPUs that have emacs support.
31
57a024f4
SDJ		 322017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
33
34 * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
35
4ec521f2
KLC		 362017-09-09 Kamil Rytarowski <n54@gmx.com>
37
38 * nds32-asm.c: Rename __BIT() to N32_BIT().
39 * nds32-asm.h: Likewise.
40 * nds32-dis.c: Likewise.
41
4e9ac44a
L		 422017-09-09 H.J. Lu <hongjiu.lu@intel.com>
43
44 * i386-dis.c (last_active_prefix): Removed.
45 (ckprefix): Don't set last_active_prefix.
46 (NOTRACK_Fixup): Don't check last_active_prefix.
47
b55f3386
NC		 482017-08-31 Nick Clifton <nickc@redhat.com>
49
50 * po/fr.po: Updated French translation.
51
59e8523b
JB		 522017-08-31 James Bowman <james.bowman@ftdichip.com>
53
54 * ft32-dis.c (print_insn_ft32): Correct display of non-address
55 fields.
56
74081948
AF		 572017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
58 Edmar Wienskoski <edmar.wienskoski@nxp.com>
59
60 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
61 PPC_OPCODE_EFS2 flag to "e200z4" entry.
62 New entries efs2 and spe2.
63 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
64 (SPE2_OPCD_SEGS): New macro.
65 (spe2_opcd_indices): New.
66 (disassemble_init_powerpc): Handle SPE2 opcodes.
67 (lookup_spe2): New function.
68 (print_insn_powerpc): call lookup_spe2.
69 * ppc-opc.c (insert_evuimm1_ex0): New function.
70 (extract_evuimm1_ex0): Likewise.
71 (insert_evuimm_lt8): Likewise.
72 (extract_evuimm_lt8): Likewise.
73 (insert_off_spe2): Likewise.
74 (extract_off_spe2): Likewise.
75 (insert_Ddd): Likewise.
76 (extract_Ddd): Likewise.
77 (DD): New operand.
78 (EVUIMM_LT8): Likewise.
79 (EVUIMM_LT16): Adjust.
80 (MMMM): New operand.
81 (EVUIMM_1): Likewise.
82 (EVUIMM_1_EX0): Likewise.
83 (EVUIMM_2): Adjust.
84 (NNN): New operand.
85 (VX_OFF_SPE2): Likewise.
86 (BBB): Likewise.
87 (DDD): Likewise.
88 (VX_MASK_DDD): New mask.
89 (HH): New operand.
90 (VX_RA_CONST): New macro.
91 (VX_RA_CONST_MASK): Likewise.
92 (VX_RB_CONST): Likewise.
93 (VX_RB_CONST_MASK): Likewise.
94 (VX_OFF_SPE2_MASK): Likewise.
95 (VX_SPE_CRFD): Likewise.
96 (VX_SPE_CRFD_MASK VX): Likewise.
97 (VX_SPE2_CLR): Likewise.
98 (VX_SPE2_CLR_MASK): Likewise.
99 (VX_SPE2_SPLATB): Likewise.
100 (VX_SPE2_SPLATB_MASK): Likewise.
101 (VX_SPE2_OCTET): Likewise.
102 (VX_SPE2_OCTET_MASK): Likewise.
103 (VX_SPE2_DDHH): Likewise.
104 (VX_SPE2_DDHH_MASK): Likewise.
105 (VX_SPE2_HH): Likewise.
106 (VX_SPE2_HH_MASK): Likewise.
107 (VX_SPE2_EVMAR): Likewise.
108 (VX_SPE2_EVMAR_MASK): Likewise.
109 (PPCSPE2): Likewise.
110 (PPCEFS2): Likewise.
111 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
112 (powerpc_macros): Map old SPE instructions have new names
113 with the same opcodes. Add SPE2 instructions which just are
114 mapped to SPE2.
115 (spe2_opcodes): Add SPE2 opcodes.
116
b80c7270
AM		 1172017-08-23 Alan Modra <amodra@gmail.com>
118
119 * ppc-opc.c: Formatting and comment fixes. Move insert and
120 extract functions earlier, deleting forward declarations.
121 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
122 RA_MASK.
123
67d888f5
PD		 1242017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
125
126 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
127
e3c2f928
AF		 1282017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
129 Edmar Wienskoski <edmar.wienskoski@nxp.com>
130
131 * ppc-opc.c (insert_evuimm2_ex0): New function.
132 (extract_evuimm2_ex0): Likewise.
133 (insert_evuimm4_ex0): Likewise.
134 (extract_evuimm4_ex0): Likewise.
135 (insert_evuimm8_ex0): Likewise.
136 (extract_evuimm8_ex0): Likewise.
137 (insert_evuimm_lt16): Likewise.
138 (extract_evuimm_lt16): Likewise.
139 (insert_rD_rS_even): Likewise.
140 (extract_rD_rS_even): Likewise.
141 (insert_off_lsp): Likewise.
142 (extract_off_lsp): Likewise.
143 (RD_EVEN): New operand.
144 (RS_EVEN): Likewise.
145 (RSQ): Adjust.
146 (EVUIMM_LT16): New operand.
147 (HTM_SI): Adjust.
148 (EVUIMM_2_EX0): New operand.
149 (EVUIMM_4): Adjust.
150 (EVUIMM_4_EX0): New operand.
151 (EVUIMM_8): Adjust.
152 (EVUIMM_8_EX0): New operand.
153 (WS): Adjust.
154 (VX_OFF): New operand.
155 (VX_LSP): New macro.
156 (VX_LSP_MASK): Likewise.
157 (VX_LSP_OFF_MASK): Likewise.
158 (PPC_OPCODE_LSP): Likewise.
159 (vle_opcodes): Add LSP opcodes.
160 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
161
cc4a945a
JW		 1622017-08-09 Jiong Wang <jiong.wang@arm.com>
163
164 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
165 register operands in CRC instructions.
166 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
167 comments.
168
b28b8b5e
L		 1692017-08-07 H.J. Lu <hongjiu.lu@intel.com>
170
171 * disassemble.c (disassembler): Mark big and mach with
172 ATTRIBUTE_UNUSED.
173
e347efc3
MR		 1742017-08-07 Maciej W. Rozycki <macro@imgtec.com>
175
176 * disassemble.c (disassembler): Remove arch/mach/endian
177 assertions.
178
7cbc739c
NC		 1792017-07-25 Nick Clifton <nickc@redhat.com>
180
181 PR 21739
182 * arc-opc.c (insert_rhv2): Use lower case first letter in error
183 message.
184 (insert_r0): Likewise.
185 (insert_r1): Likewise.
186 (insert_r2): Likewise.
187 (insert_r3): Likewise.
188 (insert_sp): Likewise.
189 (insert_gp): Likewise.
190 (insert_pcl): Likewise.
191 (insert_blink): Likewise.
192 (insert_ilink1): Likewise.
193 (insert_ilink2): Likewise.
194 (insert_ras): Likewise.
195 (insert_rbs): Likewise.
196 (insert_rcs): Likewise.
197 (insert_simm3s): Likewise.
198 (insert_rrange): Likewise.
199 (insert_r13el): Likewise.
200 (insert_fpel): Likewise.
201 (insert_blinkel): Likewise.
202 (insert_pclel): Likewise.
203 (insert_nps_bitop_size_2b): Likewise.
204 (insert_nps_imm_offset): Likewise.
205 (insert_nps_imm_entry): Likewise.
206 (insert_nps_size_16bit): Likewise.
207 (insert_nps_##NAME##_pos): Likewise.
208 (insert_nps_##NAME): Likewise.
209 (insert_nps_bitop_ins_ext): Likewise.
210 (insert_nps_##NAME): Likewise.
211 (insert_nps_min_hofs): Likewise.
212 (insert_nps_##NAME): Likewise.
213 (insert_nps_rbdouble_64): Likewise.
214 (insert_nps_misc_imm_offset): Likewise.
215 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
216 option description.
217
7684e580
JW		 2182017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
219 Jiong Wang <jiong.wang@arm.com>
220
221 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
222 correct the print.
223 * aarch64-dis-2.c: Regenerated.
224
47826cdb
AK		 2252017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
226
227 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
228 table.
229
2d2dbad0
NC		 2302017-07-20 Nick Clifton <nickc@redhat.com>
231
232 * po/de.po: Updated German translation.
233
70b448ba 2342017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
235
236 * arc-regs.h (sec_stat): New aux register.
237 (aux_kernel_sp): Likewise.
238 (aux_sec_u_sp): Likewise.
239 (aux_sec_k_sp): Likewise.
240 (sec_vecbase_build): Likewise.
241 (nsc_table_top): Likewise.
242 (nsc_table_base): Likewise.
243 (ersec_stat): Likewise.
244 (aux_sec_except): Likewise.
245
7179e0e6
CZ		 2462017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
247
248 * arc-opc.c (extract_uimm12_20): New function.
249 (UIMM12_20): New operand.
250 (SIMM3_5_S): Adjust.
251 * arc-tbl.h (sjli): Add new instruction.
252
684d5a10
JEM		 2532017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
254 John Eric Martin <John.Martin@emmicro-us.com>
255
256 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
257 (UIMM3_23): Adjust accordingly.
258 * arc-regs.h: Add/correct jli_base register.
259 * arc-tbl.h (jli_s): Likewise.
260
de194d85
YC		 2612017-07-18 Nick Clifton <nickc@redhat.com>
262
263 PR 21775
264 * aarch64-opc.c: Fix spelling typos.
265 * i386-dis.c: Likewise.
266
0f6329bd
RB		 2672017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
268
269 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
270 max_addr_offset and octets variables to size_t.
271
429d795d
AM		 2722017-07-12 Alan Modra <amodra@gmail.com>
273
274 * po/da.po: Update from translationproject.org/latest/opcodes/.
275 * po/de.po: Likewise.
276 * po/es.po: Likewise.
277 * po/fi.po: Likewise.
278 * po/fr.po: Likewise.
279 * po/id.po: Likewise.
280 * po/it.po: Likewise.
281 * po/nl.po: Likewise.
282 * po/pt_BR.po: Likewise.
283 * po/ro.po: Likewise.
284 * po/sv.po: Likewise.
285 * po/tr.po: Likewise.
286 * po/uk.po: Likewise.
287 * po/vi.po: Likewise.
288 * po/zh_CN.po: Likewise.
289
4162bb66
AM		 2902017-07-11 Yao Qi <yao.qi@linaro.org>
291 Alan Modra <amodra@gmail.com>
292
293 * cgen.sh: Mark generated files read-only.
294 * epiphany-asm.c: Regenerate.
295 * epiphany-desc.c: Regenerate.
296 * epiphany-desc.h: Regenerate.
297 * epiphany-dis.c: Regenerate.
298 * epiphany-ibld.c: Regenerate.
299 * epiphany-opc.c: Regenerate.
300 * epiphany-opc.h: Regenerate.
301 * fr30-asm.c: Regenerate.
302 * fr30-desc.c: Regenerate.
303 * fr30-desc.h: Regenerate.
304 * fr30-dis.c: Regenerate.
305 * fr30-ibld.c: Regenerate.
306 * fr30-opc.c: Regenerate.
307 * fr30-opc.h: Regenerate.
308 * frv-asm.c: Regenerate.
309 * frv-desc.c: Regenerate.
310 * frv-desc.h: Regenerate.
311 * frv-dis.c: Regenerate.
312 * frv-ibld.c: Regenerate.
313 * frv-opc.c: Regenerate.
314 * frv-opc.h: Regenerate.
315 * ip2k-asm.c: Regenerate.
316 * ip2k-desc.c: Regenerate.
317 * ip2k-desc.h: Regenerate.
318 * ip2k-dis.c: Regenerate.
319 * ip2k-ibld.c: Regenerate.
320 * ip2k-opc.c: Regenerate.
321 * ip2k-opc.h: Regenerate.
322 * iq2000-asm.c: Regenerate.
323 * iq2000-desc.c: Regenerate.
324 * iq2000-desc.h: Regenerate.
325 * iq2000-dis.c: Regenerate.
326 * iq2000-ibld.c: Regenerate.
327 * iq2000-opc.c: Regenerate.
328 * iq2000-opc.h: Regenerate.
329 * lm32-asm.c: Regenerate.
330 * lm32-desc.c: Regenerate.
331 * lm32-desc.h: Regenerate.
332 * lm32-dis.c: Regenerate.
333 * lm32-ibld.c: Regenerate.
334 * lm32-opc.c: Regenerate.
335 * lm32-opc.h: Regenerate.
336 * lm32-opinst.c: Regenerate.
337 * m32c-asm.c: Regenerate.
338 * m32c-desc.c: Regenerate.
339 * m32c-desc.h: Regenerate.
340 * m32c-dis.c: Regenerate.
341 * m32c-ibld.c: Regenerate.
342 * m32c-opc.c: Regenerate.
343 * m32c-opc.h: Regenerate.
344 * m32r-asm.c: Regenerate.
345 * m32r-desc.c: Regenerate.
346 * m32r-desc.h: Regenerate.
347 * m32r-dis.c: Regenerate.
348 * m32r-ibld.c: Regenerate.
349 * m32r-opc.c: Regenerate.
350 * m32r-opc.h: Regenerate.
351 * m32r-opinst.c: Regenerate.
352 * mep-asm.c: Regenerate.
353 * mep-desc.c: Regenerate.
354 * mep-desc.h: Regenerate.
355 * mep-dis.c: Regenerate.
356 * mep-ibld.c: Regenerate.
357 * mep-opc.c: Regenerate.
358 * mep-opc.h: Regenerate.
359 * mt-asm.c: Regenerate.
360 * mt-desc.c: Regenerate.
361 * mt-desc.h: Regenerate.
362 * mt-dis.c: Regenerate.
363 * mt-ibld.c: Regenerate.
364 * mt-opc.c: Regenerate.
365 * mt-opc.h: Regenerate.
366 * or1k-asm.c: Regenerate.
367 * or1k-desc.c: Regenerate.
368 * or1k-desc.h: Regenerate.
369 * or1k-dis.c: Regenerate.
370 * or1k-ibld.c: Regenerate.
371 * or1k-opc.c: Regenerate.
372 * or1k-opc.h: Regenerate.
373 * or1k-opinst.c: Regenerate.
374 * xc16x-asm.c: Regenerate.
375 * xc16x-desc.c: Regenerate.
376 * xc16x-desc.h: Regenerate.
377 * xc16x-dis.c: Regenerate.
378 * xc16x-ibld.c: Regenerate.
379 * xc16x-opc.c: Regenerate.
380 * xc16x-opc.h: Regenerate.
381 * xstormy16-asm.c: Regenerate.
382 * xstormy16-desc.c: Regenerate.
383 * xstormy16-desc.h: Regenerate.
384 * xstormy16-dis.c: Regenerate.
385 * xstormy16-ibld.c: Regenerate.
386 * xstormy16-opc.c: Regenerate.
387 * xstormy16-opc.h: Regenerate.
388
7639175c
AM		 3892017-07-07 Alan Modra <amodra@gmail.com>
390
391 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
392 * m32c-dis.c: Regenerate.
393 * mep-dis.c: Regenerate.
394
e4bdd679
BP		 3952017-07-05 Borislav Petkov <bp@suse.de>
396
397 * i386-dis.c: Enable ModRM.reg /6 aliases.
398
60c96dbf
RR		 3992017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
400
401 * opcodes/arm-dis.c: Support MVFR2 in disassembly
402 with vmrs and vmsr.
403
0d702cfe
TG		 4042017-07-04 Tristan Gingold <gingold@adacore.com>
405
406 * configure: Regenerate.
407
15e6ed8c
TG		 4082017-07-03 Tristan Gingold <gingold@adacore.com>
409
410 * po/opcodes.pot: Regenerate.
411
b1d3c886
MR		 4122017-06-30 Maciej W. Rozycki <macro@imgtec.com>
413
414 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
415 entries to the MSA ASE instruction block.
416
909b4e3d
MR		 4172017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
418 Maciej W. Rozycki <macro@imgtec.com>
419
420 * micromips-opc.c (XPA, XPAVZ): New macros.
421 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
422 "mthgc0".
423
f5b2fd52
MR		 4242017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
425 Maciej W. Rozycki <macro@imgtec.com>
426
427 * micromips-opc.c (I36): New macro.
428 (micromips_opcodes): Add "eretnc".
429
9785fc2a
MR		 4302017-06-30 Maciej W. Rozycki <macro@imgtec.com>
431 Andrew Bennett <andrew.bennett@imgtec.com>
432
433 * mips-dis.c (mips_calculate_combination_ases): Handle the
434 ASE_XPA_VIRT flag.
435 (parse_mips_ase_option): New function.
436 (parse_mips_dis_option): Factor out ASE option handling to the
437 new function. Call `mips_calculate_combination_ases'.
438 * mips-opc.c (XPAVZ): New macro.
439 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
440 "mfhgc0", "mthc0" and "mthgc0".
441
60804c53
MR		 4422017-06-29 Maciej W. Rozycki <macro@imgtec.com>
443
444 * mips-dis.c (mips_calculate_combination_ases): New function.
445 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
446 calculation to the new function.
447 (set_default_mips_dis_options): Call the new function.
448
2e74f9dd
AK		 4492017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
450
451 * arc-dis.c (parse_disassembler_options): Use
452 FOR_EACH_DISASSEMBLER_OPTION.
453
e1e94c49
AK		 4542017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
455
456 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
457 disassembler option strings.
458 (parse_cpu_option): Likewise.
459
65a55fbb
TC		 4602017-06-28 Tamar Christina <tamar.christina@arm.com>
461
462 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
463 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
464 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
465 (aarch64_feature_dotprod, DOT_INSN): New.
466 (udot, sdot): New.
467 * aarch64-dis-2.c: Regenerated.
468
c604a79a
JW		 4692017-06-28 Jiong Wang <jiong.wang@arm.com>
470
471 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
472
38bf472a
MR		 4732017-06-28 Maciej W. Rozycki <macro@imgtec.com>
474 Matthew Fortune <matthew.fortune@imgtec.com>
4151f684 475 Andrew Bennett <andrew.bennett@imgtec.com>
38bf472a
MR		 476
477 * mips-formats.h (INT_BIAS): New macro.
478 (INT_ADJ): Redefine in INT_BIAS terms.
479 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
480 (mips_print_save_restore): New function.
481 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
482 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
483 call.
484 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
485 (print_mips16_insn_arg): Call `mips_print_save_restore' for
486 OP_SAVE_RESTORE_LIST handling, factored out from here.
487 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
488 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
489 (mips_builtin_opcodes): Add "restore" and "save" entries.
490 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
491 (IAMR2): New macro.
492 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
493
9bdfdbf9
AW		 4942017-06-23 Andrew Waterman <andrew@sifive.com>
495
496 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
497 alias; do not mark SLTI instruction as an alias.
498
2234eee6
L		 4992017-06-21 H.J. Lu <hongjiu.lu@intel.com>
500
501 * i386-dis.c (RM_0FAE_REG_5): Removed.
502 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
503 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
504 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
505 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
506 PREFIX_MOD_3_0F01_REG_5_RM_0.
507 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
508 PREFIX_MOD_3_0FAE_REG_5.
509 (mod_table): Update MOD_0FAE_REG_5.
510 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
511 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
512 * i386-tbl.h: Regenerated.
513
c2f76402
L		 5142017-06-21 H.J. Lu <hongjiu.lu@intel.com>
515
516 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
517 * i386-opc.tbl: Likewise.
518 * i386-tbl.h: Regenerated.
519
9fef80d6
L		 5202017-06-21 H.J. Lu <hongjiu.lu@intel.com>
521
522 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
523 and "jmp{&|}".
524 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
525 prefix.
526
0f6d864d
NC		 5272017-06-19 Nick Clifton <nickc@redhat.com>
528
529 PR binutils/21614
530 * score-dis.c (score_opcodes): Add sentinel.
531
e197589b
AM		 5322017-06-16 Alan Modra <amodra@gmail.com>
533
534 * rx-decode.c: Regenerate.
535
0d96e4df
L		 5362017-06-15 H.J. Lu <hongjiu.lu@intel.com>
537
538 PR binutils/21594
539 * i386-dis.c (OP_E_register): Check valid bnd register.
540 (OP_G): Likewise.
541
cd3ea7c6
NC		 5422017-06-15 Nick Clifton <nickc@redhat.com>
543
544 PR binutils/21595
545 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
546 range value.
547
63323b5b
NC		 5482017-06-15 Nick Clifton <nickc@redhat.com>
549
550 PR binutils/21588
551 * rl78-decode.opc (OP_BUF_LEN): Define.
552 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
553 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
554 array.
555 * rl78-decode.c: Regenerate.
556
08c7881b
NC		 5572017-06-15 Nick Clifton <nickc@redhat.com>
558
559 PR binutils/21586
560 * bfin-dis.c (gregs): Clip index to prevent overflow.
561 (regs): Likewise.
562 (regs_lo): Likewise.
563 (regs_hi): Likewise.
564
e64519d1
NC		 5652017-06-14 Nick Clifton <nickc@redhat.com>
566
567 PR binutils/21576
568 * score7-dis.c (score_opcodes): Add sentinel.
569
6394c606
YQ		 5702017-06-14 Yao Qi <yao.qi@linaro.org>
571
572 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
573 * arm-dis.c: Likewise.
574 * ia64-dis.c: Likewise.
575 * mips-dis.c: Likewise.
576 * spu-dis.c: Likewise.
577 * disassemble.h (print_insn_aarch64): New declaration, moved from
578 include/dis-asm.h.
579 (print_insn_big_arm, print_insn_big_mips): Likewise.
580 (print_insn_i386, print_insn_ia64): Likewise.
581 (print_insn_little_arm, print_insn_little_mips): Likewise.
582
db5fa770
NC		 5832017-06-14 Nick Clifton <nickc@redhat.com>
584
585 PR binutils/21587
586 * rx-decode.opc: Include libiberty.h
587 (GET_SCALE): New macro - validates access to SCALE array.
588 (GET_PSCALE): New macro - validates access to PSCALE array.
589 (DIs, SIs, S2Is, rx_disp): Use new macros.
590 * rx-decode.c: Regenerate.
591
05c966f3
AV		 5922017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
593
594 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
595
10045478
AK		 5962017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
597
598 * arc-dis.c (enforced_isa_mask): Declare.
599 (cpu_types): Likewise.
600 (parse_cpu_option): New function.
601 (parse_disassembler_options): Use it.
602 (print_insn_arc): Use enforced_isa_mask.
603 (print_arc_disassembler_options): Document new options.
604
88c1242d
YQ		 6052017-05-24 Yao Qi <yao.qi@linaro.org>
606
607 * alpha-dis.c: Include disassemble.h, don't include
608 dis-asm.h.
609 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
610 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
611 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
612 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
613 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
614 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
615 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
616 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
617 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
618 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
619 * moxie-dis.c, msp430-dis.c, mt-dis.c:
620 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
621 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
622 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
623 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
624 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
625 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
626 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
627 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
628 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
629 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
630 * z80-dis.c, z8k-dis.c: Likewise.
631 * disassemble.h: New file.
632
ab20fa4a
YQ		 6332017-05-24 Yao Qi <yao.qi@linaro.org>
634
635 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
636 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
637
003ca0fd
YQ		 6382017-05-24 Yao Qi <yao.qi@linaro.org>
639
640 * disassemble.c (disassembler): Add arguments a, big and mach.
641 Use them.
642
04ef582a
L		 6432017-05-22 H.J. Lu <hongjiu.lu@intel.com>
644
645 * i386-dis.c (NOTRACK_Fixup): New.
646 (NOTRACK): Likewise.
647 (NOTRACK_PREFIX): Likewise.
648 (last_active_prefix): Likewise.
649 (reg_table): Use NOTRACK on indirect call and jmp.
650 (ckprefix): Set last_active_prefix.
651 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
652 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
653 * i386-opc.h (NoTrackPrefixOk): New.
654 (i386_opcode_modifier): Add notrackprefixok.
655 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
656 Add notrack.
657 * i386-tbl.h: Regenerated.
658
64517994
JM		 6592017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
660
661 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
662 (X_IMM2): Define.
663 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
664 bfd_mach_sparc_v9m8.
665 (print_insn_sparc): Handle new operand types.
666 * sparc-opc.c (MASK_M8): Define.
667 (v6): Add MASK_M8.
668 (v6notlet): Likewise.
669 (v7): Likewise.
670 (v8): Likewise.
671 (v9): Likewise.
672 (v9a): Likewise.
673 (v9b): Likewise.
674 (v9c): Likewise.
675 (v9d): Likewise.
676 (v9e): Likewise.
677 (v9v): Likewise.
678 (v9m): Likewise.
679 (v9andleon): Likewise.
680 (m8): Define.
681 (HWS_VM8): Define.
682 (HWS2_VM8): Likewise.
683 (sparc_opcode_archs): Add entry for "m8".
684 (sparc_opcodes): Add OSA2017 and M8 instructions
685 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
686 fpx{ll,ra,rl}64x,
687 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
688 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
689 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
690 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
691 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
692 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
693 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
694 ASI_CORE_SELECT_COMMIT_NHT.
695
535b785f
AM		 6962017-05-18 Alan Modra <amodra@gmail.com>
697
698 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
699 * aarch64-dis.c: Likewise.
700 * aarch64-gen.c: Likewise.
701 * aarch64-opc.c: Likewise.
702
25499ac7
MR		 7032017-05-15 Maciej W. Rozycki <macro@imgtec.com>
704 Matthew Fortune <matthew.fortune@imgtec.com>
705
706 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
707 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
708 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
709 (print_insn_arg) <OP_REG28>: Add handler.
710 (validate_insn_args) <OP_REG28>: Handle.
711 (print_mips16_insn_arg): Handle MIPS16 instructions that require
712 32-bit encoding and 9-bit immediates.
713 (print_insn_mips16): Handle MIPS16 instructions that require
714 32-bit encoding and MFC0/MTC0 operand decoding.
715 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
716 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
717 (RD_C0, WR_C0, E2, E2MT): New macros.
718 (mips16_opcodes): Add entries for MIPS16e2 instructions:
719 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
720 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
721 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
722 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
723 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
724 instructions, "swl", "swr", "sync" and its "sync_acquire",
725 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
726 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
727 regular/extended entries for original MIPS16 ISA revision
728 instructions whose extended forms are subdecoded in the MIPS16e2
729 ISA revision: "li", "sll" and "srl".
730
fdfb4752
MR		 7312017-05-15 Maciej W. Rozycki <macro@imgtec.com>
732
733 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
734 reference in CP0 move operand decoding.
735
a4f89915
MR		 7362017-05-12 Maciej W. Rozycki <macro@imgtec.com>
737
738 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
739 type to hexadecimal.
740 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
741
99e2d67a
MR		 7422017-05-11 Maciej W. Rozycki <macro@imgtec.com>
743
744 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
745 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
746 "sync_rmb" and "sync_wmb" as aliases.
747 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
748 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
749
53a346d8
CZ		 7502017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
751
752 * arc-dis.c (parse_option): Update quarkse_em option..
753 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
754 QUARKSE1.
755 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
756
f91d48de
KC		 7572017-05-03 Kito Cheng <kito.cheng@gmail.com>
758
759 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
760
43e379d7
MC		 7612017-05-01 Michael Clark <michaeljclark@mac.com>
762
763 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
764 register.
765
a4ddc54e
MR		 7662017-05-02 Maciej W. Rozycki <macro@imgtec.com>
767
768 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
769 and branches and not synthetic data instructions.
770
fe50e98c
BE		 7712017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
772
773 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
774
126124cc
CZ		 7752017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
776
777 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
778 * arc-opc.c (insert_r13el): New function.
779 (R13_EL): Define.
780 * arc-tbl.h: Add new enter/leave variants.
781
be6a24d8
CZ		 7822017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
783
784 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
785
0348fd79
MR		 7862017-04-25 Maciej W. Rozycki <macro@imgtec.com>
787
788 * mips-dis.c (print_mips_disassembler_options): Add
789 `no-aliases'.
790
6e3d1f07
MR		 7912017-04-25 Maciej W. Rozycki <macro@imgtec.com>
792
793 * mips16-opc.c (AL): New macro.
794 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
795 of "ld" and "lw" as aliases.
796
957f6b39
TC		 7972017-04-24 Tamar Christina <tamar.christina@arm.com>
798
799 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
800 arguments.
801
a8cc8a54
AM		 8022017-04-22 Alexander Fedotov <alfedotov@gmail.com>
803 Alan Modra <amodra@gmail.com>
804
805 * ppc-opc.c (ELEV): Define.
806 (vle_opcodes): Add se_rfgi and e_sc.
807 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
808 for E200Z4.
809
3ab87b68
JM		 8102017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
811
812 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
813
792f174f
NC		 8142017-04-21 Nick Clifton <nickc@redhat.com>
815
816 PR binutils/21380
817 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
818 LD3R and LD4R.
819
42742084
AM		 8202017-04-13 Alan Modra <amodra@gmail.com>
821
822 * epiphany-desc.c: Regenerate.
823 * fr30-desc.c: Regenerate.
824 * frv-desc.c: Regenerate.
825 * ip2k-desc.c: Regenerate.
826 * iq2000-desc.c: Regenerate.
827 * lm32-desc.c: Regenerate.
828 * m32c-desc.c: Regenerate.
829 * m32r-desc.c: Regenerate.
830 * mep-desc.c: Regenerate.
831 * mt-desc.c: Regenerate.
832 * or1k-desc.c: Regenerate.
833 * xc16x-desc.c: Regenerate.
834 * xstormy16-desc.c: Regenerate.
835
9a85b496
AM		 8362017-04-11 Alan Modra <amodra@gmail.com>
837
ef85eab0 838 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 839 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
840 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 841 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
842 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 843 (PPCVSX2): Define as PPC_OPCODE_POWER8.
844 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 845 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 846 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 847
62adc510
AM		 8482017-04-10 Alan Modra <amodra@gmail.com>
849
850 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
851 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
852 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
853 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
854
aa808707
PC		 8552017-04-09 Pip Cet <pipcet@gmail.com>
856
857 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
858 appropriate floating-point precision directly.
859
ac8f0f72
AM		 8602017-04-07 Alan Modra <amodra@gmail.com>
861
862 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
863 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
864 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
865 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
866 vector instructions with E6500 not PPCVEC2.
867
62ecb94c
PC		 8682017-04-06 Pip Cet <pipcet@gmail.com>
869
870 * Makefile.am: Add wasm32-dis.c.
871 * configure.ac: Add wasm32-dis.c to wasm32 target.
872 * disassemble.c: Add wasm32 disassembler code.
873 * wasm32-dis.c: New file.
874 * Makefile.in: Regenerate.
875 * configure: Regenerate.
876 * po/POTFILES.in: Regenerate.
877 * po/opcodes.pot: Regenerate.
878
f995bbe8
PA		 8792017-04-05 Pedro Alves <palves@redhat.com>
880
881 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
882 * arm-dis.c (parse_arm_disassembler_options): Constify.
883 * ppc-dis.c (powerpc_init_dialect): Constify local.
884 * vax-dis.c (parse_disassembler_options): Constify.
885
b5292032
PD		 8862017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
887
888 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
889 RISCV_GP_SYMBOL.
890
f96bd6c2
PC		 8912017-03-30 Pip Cet <pipcet@gmail.com>
892
893 * configure.ac: Add (empty) bfd_wasm32_arch target.
894 * configure: Regenerate
895 * po/opcodes.pot: Regenerate.
896
f7c514a3
JM		 8972017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
898
899 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
900 OSA2015.
901 * opcodes/sparc-opc.c (asi_table): New ASIs.
902
52be03fd
AM		 9032017-03-29 Alan Modra <amodra@gmail.com>
904
905 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
906 "raw" option.
907 (lookup_powerpc): Don't special case -1 dialect. Handle
908 PPC_OPCODE_RAW.
909 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
910 lookup_powerpc call, pass it on second.
911
9b753937
AM		 9122017-03-27 Alan Modra <amodra@gmail.com>
913
914 PR 21303
915 * ppc-dis.c (struct ppc_mopt): Comment.
916 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
917
c0c31e91
RZ		 9182017-03-27 Rinat Zelig <rinat@mellanox.com>
919
920 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
921 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
922 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
923 (insert_nps_misc_imm_offset): New function.
924 (extract_nps_misc imm_offset): New function.
925 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
926 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
927
2253c8f0
AK		 9282017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
929
930 * s390-mkopc.c (main): Remove vx2 check.
931 * s390-opc.txt: Remove vx2 instruction flags.
932
645d3342
RZ		 9332017-03-21 Rinat Zelig <rinat@mellanox.com>
934
935 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
936 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
937 (insert_nps_imm_offset): New function.
938 (extract_nps_imm_offset): New function.
939 (insert_nps_imm_entry): New function.
940 (extract_nps_imm_entry): New function.
941
4b94dd2d
AM		 9422017-03-17 Alan Modra <amodra@gmail.com>
943
944 PR 21248
945 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
946 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
947 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
948
b416fe87
KC		 9492017-03-14 Kito Cheng <kito.cheng@gmail.com>
950
951 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
952 <c.andi>: Likewise.
953 <c.addiw> Likewise.
954
03b039a5
KC		 9552017-03-14 Kito Cheng <kito.cheng@gmail.com>
956
957 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
958
2c232b83
AW		 9592017-03-13 Andrew Waterman <andrew@sifive.com>
960
961 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
962 <srl> Likewise.
963 <srai> Likewise.
964 <sra> Likewise.
965
86fa6981
L		 9662017-03-09 H.J. Lu <hongjiu.lu@intel.com>
967
968 * i386-gen.c (opcode_modifiers): Replace S with Load.
969 * i386-opc.h (S): Removed.
970 (Load): New.
971 (i386_opcode_modifier): Replace s with load.
972 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
973 and {evex}. Replace S with Load.
974 * i386-tbl.h: Regenerated.
975
c1fe188b
L		 9762017-03-09 H.J. Lu <hongjiu.lu@intel.com>
977
978 * i386-opc.tbl: Use CpuCET on rdsspq.
979 * i386-tbl.h: Regenerated.
980
4b8b687e
PB		 9812017-03-08 Peter Bergner <bergner@vnet.ibm.com>
982
983 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
984 <vsx>: Do not use PPC_OPCODE_VSX3;
985
1437d063
PB		 9862017-03-08 Peter Bergner <bergner@vnet.ibm.com>
987
988 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
989
603555e5
L		 9902017-03-06 H.J. Lu <hongjiu.lu@intel.com>
991
992 * i386-dis.c (REG_0F1E_MOD_3): New enum.
993 (MOD_0F1E_PREFIX_1): Likewise.
994 (MOD_0F38F5_PREFIX_2): Likewise.
995 (MOD_0F38F6_PREFIX_0): Likewise.
996 (RM_0F1E_MOD_3_REG_7): Likewise.
997 (PREFIX_MOD_0_0F01_REG_5): Likewise.
998 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
999 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1000 (PREFIX_0F1E): Likewise.
1001 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1002 (PREFIX_0F38F5): Likewise.
1003 (dis386_twobyte): Use PREFIX_0F1E.
1004 (reg_table): Add REG_0F1E_MOD_3.
1005 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1006 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1007 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
1008 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1009 (three_byte_table): Use PREFIX_0F38F5.
1010 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1011 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1012 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1013 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1014 PREFIX_MOD_3_0F01_REG_5_RM_2.
1015 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1016 (cpu_flags): Add CpuCET.
1017 * i386-opc.h (CpuCET): New enum.
1018 (CpuUnused): Commented out.
1019 (i386_cpu_flags): Add cpucet.
1020 * i386-opc.tbl: Add Intel CET instructions.
1021 * i386-init.h: Regenerated.
1022 * i386-tbl.h: Likewise.
1023
73f07bff
AM		 10242017-03-06 Alan Modra <amodra@gmail.com>
1025
1026 PR 21124
1027 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1028 (extract_raq, extract_ras, extract_rbx): New functions.
1029 (powerpc_operands): Use opposite corresponding insert function.
1030 (Q_MASK): Define.
1031 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1032 register restriction.
1033
65b48a81
PB		 10342017-02-28 Peter Bergner <bergner@vnet.ibm.com>
1035
1036 * disassemble.c Include "safe-ctype.h".
1037 (disassemble_init_for_target): Handle s390 init.
1038 (remove_whitespace_and_extra_commas): New function.
1039 (disassembler_options_cmp): Likewise.
1040 * arm-dis.c: Include "libiberty.h".
1041 (NUM_ELEM): Delete.
1042 (regnames): Use long disassembler style names.
1043 Add force-thumb and no-force-thumb options.
1044 (NUM_ARM_REGNAMES): Rename from this...
1045 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
1046 (get_arm_regname_num_options): Delete.
1047 (set_arm_regname_option): Likewise.
1048 (get_arm_regnames): Likewise.
1049 (parse_disassembler_options): Likewise.
1050 (parse_arm_disassembler_option): Rename from this...
1051 (parse_arm_disassembler_options): ...to this. Make static.
1052 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1053 (print_insn): Use parse_arm_disassembler_options.
1054 (disassembler_options_arm): New function.
1055 (print_arm_disassembler_options): Handle updated regnames.
1056 * ppc-dis.c: Include "libiberty.h".
1057 (ppc_opts): Add "32" and "64" entries.
1058 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1059 (powerpc_init_dialect): Add break to switch statement.
1060 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1061 (disassembler_options_powerpc): New function.
1062 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1063 Remove printing of "32" and "64".
1064 * s390-dis.c: Include "libiberty.h".
1065 (init_flag): Remove unneeded variable.
1066 (struct s390_options_t): New structure type.
1067 (options): New structure.
1068 (init_disasm): Rename from this...
1069 (disassemble_init_s390): ...to this. Add initializations for
1070 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1071 (print_insn_s390): Delete call to init_disasm.
1072 (disassembler_options_s390): New function.
1073 (print_s390_disassembler_options): Print using information from
1074 struct 'options'.
1075 * po/opcodes.pot: Regenerate.
1076
15c7c1d8
JB		 10772017-02-28 Jan Beulich <jbeulich@suse.com>
1078
1079 * i386-dis.c (PCMPESTR_Fixup): New.
1080 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1081 (prefix_table): Use PCMPESTR_Fixup.
1082 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1083 PCMPESTR_Fixup.
1084 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1085 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1086 Split 64-bit and non-64-bit variants.
1087 * opcodes/i386-tbl.h: Re-generate.
1088
582e12bf
RS		 10892017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1090
1091 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1092 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1093 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1094 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1095 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1096 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1097 (OP_SVE_V_HSD): New macros.
1098 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1099 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1100 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1101 (aarch64_opcode_table): Add new SVE instructions.
1102 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1103 for rotation operands. Add new SVE operands.
1104 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1105 (ins_sve_quad_index): Likewise.
1106 (ins_imm_rotate): Split into...
1107 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1108 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1109 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1110 functions.
1111 (aarch64_ins_sve_addr_ri_s4): New function.
1112 (aarch64_ins_sve_quad_index): Likewise.
1113 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1114 * aarch64-asm-2.c: Regenerate.
1115 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1116 (ext_sve_quad_index): Likewise.
1117 (ext_imm_rotate): Split into...
1118 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1119 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1120 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1121 functions.
1122 (aarch64_ext_sve_addr_ri_s4): New function.
1123 (aarch64_ext_sve_quad_index): Likewise.
1124 (aarch64_ext_sve_index): Allow quad indices.
1125 (do_misc_decoding): Likewise.
1126 * aarch64-dis-2.c: Regenerate.
1127 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1128 aarch64_field_kinds.
1129 (OPD_F_OD_MASK): Widen by one bit.
1130 (OPD_F_NO_ZR): Bump accordingly.
1131 (get_operand_field_width): New function.
1132 * aarch64-opc.c (fields): Add new SVE fields.
1133 (operand_general_constraint_met_p): Handle new SVE operands.
1134 (aarch64_print_operand): Likewise.
1135 * aarch64-opc-2.c: Regenerate.
1136
f482d304
RS		 11372017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1138
1139 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1140 (aarch64_feature_compnum): ...this.
1141 (SIMD_V8_3): Replace with...
1142 (COMPNUM): ...this.
1143 (CNUM_INSN): New macro.
1144 (aarch64_opcode_table): Use it for the complex number instructions.
1145
7db2c588
JB		 11462017-02-24 Jan Beulich <jbeulich@suse.com>
1147
1148 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1149
1e9d41d4
SL		 11502017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1151
1152 Add support for associating SPARC ASIs with an architecture level.
1153 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1154 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1155 decoding of SPARC ASIs.
1156
53c4d625
JB		 11572017-02-23 Jan Beulich <jbeulich@suse.com>
1158
1159 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1160 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1161
11648de5
JB		 11622017-02-21 Jan Beulich <jbeulich@suse.com>
1163
1164 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1165 1 (instead of to itself). Correct typo.
1166
f98d33be
AW		 11672017-02-14 Andrew Waterman <andrew@sifive.com>
1168
1169 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1170 pseudoinstructions.
1171
773fb663
RS		 11722017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1173
1174 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1175 (aarch64_sys_reg_supported_p): Handle them.
1176
cc07cda6
CZ		 11772017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1178
1179 * arc-opc.c (UIMM6_20R): Define.
1180 (SIMM12_20): Use above.
1181 (SIMM12_20R): Define.
1182 (SIMM3_5_S): Use above.
1183 (UIMM7_A32_11R_S): Define.
1184 (UIMM7_9_S): Use above.
1185 (UIMM3_13R_S): Define.
1186 (SIMM11_A32_7_S): Use above.
1187 (SIMM9_8R): Define.
1188 (UIMM10_A32_8_S): Use above.
1189 (UIMM8_8R_S): Define.
1190 (W6): Use above.
1191 (arc_relax_opcodes): Use all above defines.
1192
66a5a740
VG		 11932017-02-15 Vineet Gupta <vgupta@synopsys.com>
1194
1195 * arc-regs.h: Distinguish some of the registers different on
1196 ARC700 and HS38 cpus.
1197
7e0de605
AM		 11982017-02-14 Alan Modra <amodra@gmail.com>
1199
1200 PR 21118
1201 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1202 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1203
54064fdb
AM		 12042017-02-11 Stafford Horne <shorne@gmail.com>
1205 Alan Modra <amodra@gmail.com>
1206
1207 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1208 Use insn_bytes_value and insn_int_value directly instead. Don't
1209 free allocated memory until function exit.
1210
dce75bf9
NP		 12112017-02-10 Nicholas Piggin <npiggin@gmail.com>
1212
1213 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1214
1b7e3d2f
NC		 12152017-02-03 Nick Clifton <nickc@redhat.com>
1216
1217 PR 21096
1218 * aarch64-opc.c (print_register_list): Ensure that the register
1219 list index will fir into the tb buffer.
1220 (print_register_offset_address): Likewise.
1221 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1222
8ec5cf65
AD		 12232017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1224
1225 PR 21056
1226 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1227 instructions when the previous fetch packet ends with a 32-bit
1228 instruction.
1229
a1aa5e81
DD		 12302017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1231
1232 * pru-opc.c: Remove vague reference to a future GDB port.
1233
add3afb2
NC		 12342017-01-20 Nick Clifton <nickc@redhat.com>
1235
1236 * po/ga.po: Updated Irish translation.
1237
c13a63b0
SN		 12382017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1239
1240 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1241
9608051a
YQ		 12422017-01-13 Yao Qi <yao.qi@linaro.org>
1243
1244 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1245 if FETCH_DATA returns 0.
1246 (m68k_scan_mask): Likewise.
1247 (print_insn_m68k): Update code to handle -1 return value.
1248
f622ea96
YQ		 12492017-01-13 Yao Qi <yao.qi@linaro.org>
1250
1251 * m68k-dis.c (enum print_insn_arg_error): New.
1252 (NEXTBYTE): Replace -3 with
1253 PRINT_INSN_ARG_MEMORY_ERROR.
1254 (NEXTULONG): Likewise.
1255 (NEXTSINGLE): Likewise.
1256 (NEXTDOUBLE): Likewise.
1257 (NEXTDOUBLE): Likewise.
1258 (NEXTPACKED): Likewise.
1259 (FETCH_ARG): Likewise.
1260 (FETCH_DATA): Update comments.
1261 (print_insn_arg): Update comments. Replace magic numbers with
1262 enum.
1263 (match_insn_m68k): Likewise.
1264
620214f7
IT		 12652017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1266
1267 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1268 * i386-dis-evex.h (evex_table): Updated.
1269 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1270 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1271 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1272 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1273 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1274 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1275 * i386-init.h: Regenerate.
1276 * i386-tbl.h: Ditto.
1277
d95014a2
YQ		 12782017-01-12 Yao Qi <yao.qi@linaro.org>
1279
1280 * msp430-dis.c (msp430_singleoperand): Return -1 if
1281 msp430dis_opcode_signed returns false.
1282 (msp430_doubleoperand): Likewise.
1283 (msp430_branchinstr): Return -1 if
1284 msp430dis_opcode_unsigned returns false.
1285 (msp430x_calla_instr): Likewise.
1286 (print_insn_msp430): Likewise.
1287
0ae60c3e
NC		 12882017-01-05 Nick Clifton <nickc@redhat.com>
1289
1290 PR 20946
1291 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1292 could not be matched.
1293 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1294 NULL.
1295
d74d4880
SN		 12962017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1297
1298 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1299 (aarch64_opcode_table): Use RCPC_INSN.
1300
cc917fd9
KC		 13012017-01-03 Kito Cheng <kito.cheng@gmail.com>
1302
1303 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1304 extension.
1305 * riscv-opcodes/all-opcodes: Likewise.
1306
b52d3cfc
DP		 13072017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1308
1309 * riscv-dis.c (print_insn_args): Add fall through comment.
1310
f90c58d5
NC		 13112017-01-03 Nick Clifton <nickc@redhat.com>
1312
1313 * po/sr.po: New Serbian translation.
1314 * configure.ac (ALL_LINGUAS): Add sr.
1315 * configure: Regenerate.
1316
f47b0d4a
AM		 13172017-01-02 Alan Modra <amodra@gmail.com>
1318
1319 * epiphany-desc.h: Regenerate.
1320 * epiphany-opc.h: Regenerate.
1321 * fr30-desc.h: Regenerate.
1322 * fr30-opc.h: Regenerate.
1323 * frv-desc.h: Regenerate.
1324 * frv-opc.h: Regenerate.
1325 * ip2k-desc.h: Regenerate.
1326 * ip2k-opc.h: Regenerate.
1327 * iq2000-desc.h: Regenerate.
1328 * iq2000-opc.h: Regenerate.
1329 * lm32-desc.h: Regenerate.
1330 * lm32-opc.h: Regenerate.
1331 * m32c-desc.h: Regenerate.
1332 * m32c-opc.h: Regenerate.
1333 * m32r-desc.h: Regenerate.
1334 * m32r-opc.h: Regenerate.
1335 * mep-desc.h: Regenerate.
1336 * mep-opc.h: Regenerate.
1337 * mt-desc.h: Regenerate.
1338 * mt-opc.h: Regenerate.
1339 * or1k-desc.h: Regenerate.
1340 * or1k-opc.h: Regenerate.
1341 * xc16x-desc.h: Regenerate.
1342 * xc16x-opc.h: Regenerate.
1343 * xstormy16-desc.h: Regenerate.
1344 * xstormy16-opc.h: Regenerate.
1345
2571583a
AM		 13462017-01-02 Alan Modra <amodra@gmail.com>
1347
1348 Update year range in copyright notice of all files.
1349
5c1ad6b5 1350For older changes see ChangeLog-2016
3499769a 1351\f
5c1ad6b5 1352Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 1353
1354Copying and distribution of this file, with or without modification,
1355are permitted in any medium without royalty provided the copyright
1356notice and this notice are preserved.
1357
1358Local Variables:
1359mode: change-log
1360left-margin: 8
1361fill-column: 74
1362version-control: never
1363End:
GDB Binutils - Deliverables
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