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Arm64: correct "sha3" arch-extension directive handling
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
378fd436
AM		 12019-12-05 Alan Modra <amodra@gmail.com>
2
3 PR 25249
4 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
5 (struct string_buf): New.
6 (strbuf): New function.
7 (get_field): Use strbuf rather than strdup of local temp.
8 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
9 (get_field_rfsl, get_field_imm15): Likewise.
10 (get_field_rd, get_field_r1, get_field_r2): Update macros.
11 (get_field_special): Likewise. Don't strcpy spr. Formatting.
12 (print_insn_microblaze): Formatting. Init and pass string_buf to
13 get_field functions.
14
0ba59a29
JB		 152019-12-04 Jan Beulich <jbeulich@suse.com>
16
17 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
18 * i386-tbl.h: Re-generate.
19
77ad8092
JB		 202019-12-04 Jan Beulich <jbeulich@suse.com>
21
22 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
23
3036c899
JB		 242019-12-04 Jan Beulich <jbeulich@suse.com>
25
26 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
27 forms.
28 (xbegin): Drop DefaultSize.
29 * i386-tbl.h: Re-generate.
30
8b301fbb
MI		 312019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
32
33 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
34 Change the coproc CRC conditions to use the extension
35 feature set, second word, base on ARM_EXT2_CRC.
36
6aa385b9
JB		 372019-11-14 Jan Beulich <jbeulich@suse.com>
38
39 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
40 * i386-tbl.h: Re-generate.
41
0cfa3eb3
JB		 422019-11-14 Jan Beulich <jbeulich@suse.com>
43
44 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
45 JumpInterSegment, and JumpAbsolute entries.
46 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
47 JUMP_ABSOLUTE): Define.
48 (struct i386_opcode_modifier): Extend jump field to 3 bits.
49 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
50 fields.
51 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
52 JumpInterSegment): Define.
53 * i386-tbl.h: Re-generate.
54
6f2f06be
JB		 552019-11-14 Jan Beulich <jbeulich@suse.com>
56
57 * i386-gen.c (operand_type_init): Remove
58 OPERAND_TYPE_JUMPABSOLUTE entry.
59 (opcode_modifiers): Add JumpAbsolute entry.
60 (operand_types): Remove JumpAbsolute entry.
61 * i386-opc.h (JumpAbsolute): Move between enums.
62 (struct i386_opcode_modifier): Add jumpabsolute field.
63 (union i386_operand_type): Remove jumpabsolute field.
64 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
65 * i386-init.h, i386-tbl.h: Re-generate.
66
601e8564
JB		 672019-11-14 Jan Beulich <jbeulich@suse.com>
68
69 * i386-gen.c (opcode_modifiers): Add AnySize entry.
70 (operand_types): Remove AnySize entry.
71 * i386-opc.h (AnySize): Move between enums.
72 (struct i386_opcode_modifier): Add anysize field.
73 (OTUnused): Un-comment.
74 (union i386_operand_type): Remove anysize field.
75 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
76 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
77 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
78 AnySize.
79 * i386-tbl.h: Re-generate.
80
7722d40a
JW		 812019-11-12 Nelson Chu <nelson.chu@sifive.com>
82
83 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
84 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
85 use the floating point register (FPR).
86
ce760a76
MI		 872019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
88
89 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
90 cmode 1101.
91 (is_mve_encoding_conflict): Update cmode conflict checks for
92 MVE_VMVN_IMM.
93
51c8edf6
JB		 942019-11-12 Jan Beulich <jbeulich@suse.com>
95
96 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
97 entry.
98 (operand_types): Remove EsSeg entry.
99 (main): Replace stale use of OTMax.
100 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
101 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
102 (EsSeg): Delete.
103 (OTUnused): Comment out.
104 (union i386_operand_type): Remove esseg field.
105 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
106 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
107 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
108 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
109 * i386-init.h, i386-tbl.h: Re-generate.
110
474da251
JB		 1112019-11-12 Jan Beulich <jbeulich@suse.com>
112
113 * i386-gen.c (operand_instances): Add RegB entry.
114 * i386-opc.h (enum operand_instance): Add RegB.
115 * i386-opc.tbl (RegC, RegD, RegB): Define.
116 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
117 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
118 monitorx, mwaitx): Drop ImmExt and convert encodings
119 accordingly.
120 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
121 (edx, rdx): Add Instance=RegD.
122 (ebx, rbx): Add Instance=RegB.
123 * i386-tbl.h: Re-generate.
124
75e5731b
JB		 1252019-11-12 Jan Beulich <jbeulich@suse.com>
126
127 * i386-gen.c (operand_type_init): Adjust
128 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
129 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
130 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
131 (operand_instances): New.
132 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
133 (output_operand_type): New parameter "instance". Process it.
134 (process_i386_operand_type): New local variable "instance".
135 (main): Adjust static assertions.
136 * i386-opc.h (INSTANCE_WIDTH): Define.
137 (enum operand_instance): New.
138 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
139 (union i386_operand_type): Replace acc, inoutportreg, and
140 shiftcount by instance.
141 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
142 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
143 Add Instance=.
144 * i386-init.h, i386-tbl.h: Re-generate.
145
91802f3c
JB		 1462019-11-11 Jan Beulich <jbeulich@suse.com>
147
148 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
149 smaxp/sminp entries' "tied_operand" field to 2.
150
4f5fc85d
JB		 1512019-11-11 Jan Beulich <jbeulich@suse.com>
152
153 * aarch64-opc.c (operand_general_constraint_met_p): Replace
154 "index" local variable by that of the already existing "num".
155
dc2be329
L		 1562019-11-08 H.J. Lu <hongjiu.lu@intel.com>
157
158 PR gas/25167
159 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
160 * i386-tbl.h: Regenerated.
161
f74a6307
JB		 1622019-11-08 Jan Beulich <jbeulich@suse.com>
163
164 * i386-gen.c (operand_type_init): Add Class= to
165 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
166 OPERAND_TYPE_REGBND entry.
167 (operand_classes): Add RegMask and RegBND entries.
168 (operand_types): Drop RegMask and RegBND entry.
169 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
170 (RegMask, RegBND): Delete.
171 (union i386_operand_type): Remove regmask and regbnd fields.
172 * i386-opc.tbl (RegMask, RegBND): Define.
173 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
174 Class=RegBND.
175 * i386-init.h, i386-tbl.h: Re-generate.
176
3528c362
JB		 1772019-11-08 Jan Beulich <jbeulich@suse.com>
178
179 * i386-gen.c (operand_type_init): Add Class= to
180 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
181 OPERAND_TYPE_REGZMM entries.
182 (operand_classes): Add RegMMX and RegSIMD entries.
183 (operand_types): Drop RegMMX and RegSIMD entries.
184 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
185 (RegMMX, RegSIMD): Delete.
186 (union i386_operand_type): Remove regmmx and regsimd fields.
187 * i386-opc.tbl (RegMMX): Define.
188 (RegXMM, RegYMM, RegZMM): Add Class=.
189 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
190 Class=RegSIMD.
191 * i386-init.h, i386-tbl.h: Re-generate.
192
4a5c67ed
JB		 1932019-11-08 Jan Beulich <jbeulich@suse.com>
194
195 * i386-gen.c (operand_type_init): Add Class= to
196 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
197 entries.
198 (operand_classes): Add RegCR, RegDR, and RegTR entries.
199 (operand_types): Drop Control, Debug, and Test entries.
200 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
201 (Control, Debug, Test): Delete.
202 (union i386_operand_type): Remove control, debug, and test
203 fields.
204 * i386-opc.tbl (Control, Debug, Test): Define.
205 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
206 Class=RegDR, and Test by Class=RegTR.
207 * i386-init.h, i386-tbl.h: Re-generate.
208
00cee14f
JB		 2092019-11-08 Jan Beulich <jbeulich@suse.com>
210
211 * i386-gen.c (operand_type_init): Add Class= to
212 OPERAND_TYPE_SREG entry.
213 (operand_classes): Add SReg entry.
214 (operand_types): Drop SReg entry.
215 * i386-opc.h (enum operand_class): Add SReg.
216 (SReg): Delete.
217 (union i386_operand_type): Remove sreg field.
218 * i386-opc.tbl (SReg): Define.
219 * i386-reg.tbl: Replace SReg by Class=SReg.
220 * i386-init.h, i386-tbl.h: Re-generate.
221
bab6aec1
JB		 2222019-11-08 Jan Beulich <jbeulich@suse.com>
223
224 * i386-gen.c (operand_type_init): Add Class=. New
225 OPERAND_TYPE_ANYIMM entry.
226 (operand_classes): New.
227 (operand_types): Drop Reg entry.
228 (output_operand_type): New parameter "class". Process it.
229 (process_i386_operand_type): New local variable "class".
230 (main): Adjust static assertions.
231 * i386-opc.h (CLASS_WIDTH): Define.
232 (enum operand_class): New.
233 (Reg): Replace by Class. Adjust comment.
234 (union i386_operand_type): Replace reg by class.
235 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
236 Class=.
237 * i386-reg.tbl: Replace Reg by Class=Reg.
238 * i386-init.h: Re-generate.
239
1f4cd317
MM		 2402019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
241
242 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
243 (aarch64_opcode_table): Add data gathering hint mnemonic.
244 * opcodes/aarch64-dis-2.c: Account for new instruction.
245
616ce08e
MM		 2462019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
247
248 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
249
250
8382113f
MM		 2512019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
252
253 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
254 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
255 aarch64_feature_f64mm): New feature sets.
256 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
257 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
258 instructions.
259 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
260 macros.
261 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
262 (OP_SVE_QQQ): New qualifier.
263 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
264 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
265 the movprfx constraint.
266 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
267 (aarch64_opcode_table): Define new instructions smmla,
268 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
269 uzip{1/2}, trn{1/2}.
270 * aarch64-opc.c (operand_general_constraint_met_p): Handle
271 AARCH64_OPND_SVE_ADDR_RI_S4x32.
272 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
273 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
274 Account for new instructions.
275 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
276 S4x32 operand.
277 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
278
aab2c27d
MM		 2792019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2802019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
281
282 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
283 Armv8.6-A.
284 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
285 (neon_opcodes): Add bfloat SIMD instructions.
286 (print_insn_coprocessor): Add new control character %b to print
287 condition code without checking cp_num.
288 (print_insn_neon): Account for BFloat16 instructions that have no
289 special top-byte handling.
290
33593eaf
MM		 2912019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2922019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
293
294 * arm-dis.c (print_insn_coprocessor,
295 print_insn_generic_coprocessor): Create wrapper functions around
296 the implementation of the print_insn_coprocessor control codes.
297 (print_insn_coprocessor_1): Original print_insn_coprocessor
298 function that now takes which array to look at as an argument.
299 (print_insn_arm): Use both print_insn_coprocessor and
300 print_insn_generic_coprocessor.
301 (print_insn_thumb32): As above.
302
df678013
MM		 3032019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3042019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
305
306 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
307 in reglane special case.
308 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
309 aarch64_find_next_opcode): Account for new instructions.
310 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
311 in reglane special case.
312 * aarch64-opc.c (struct operand_qualifier_data): Add data for
313 new AARCH64_OPND_QLF_S_2H qualifier.
314 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
315 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
316 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
317 sets.
318 (BFLOAT_SVE, BFLOAT): New feature set macros.
319 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
320 instructions.
321 (aarch64_opcode_table): Define new instructions bfdot,
322 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
323 bfcvtn2, bfcvt.
324
8ae2d3d9
MM		 3252019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3262019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
327
328 * aarch64-tbl.h (ARMV8_6): New macro.
329
142861df
JB		 3302019-11-07 Jan Beulich <jbeulich@suse.com>
331
332 * i386-dis.c (prefix_table): Add mcommit.
333 (rm_table): Add rdpru.
334 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
335 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
336 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
337 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
338 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
339 * i386-opc.tbl (mcommit, rdpru): New.
340 * i386-init.h, i386-tbl.h: Re-generate.
341
081e283f
JB		 3422019-11-07 Jan Beulich <jbeulich@suse.com>
343
344 * i386-dis.c (OP_Mwait): Drop local variable "names", use
345 "names32" instead.
346 (OP_Monitor): Drop local variable "op1_names", re-purpose
347 "names" for it instead, and replace former "names" uses by
348 "names32" ones.
349
c050c89a
JB		 3502019-11-07 Jan Beulich <jbeulich@suse.com>
351
352 PR/gas 25167
353 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
354 operand-less forms.
355 * opcodes/i386-tbl.h: Re-generate.
356
7abb8d81
JB		 3572019-11-05 Jan Beulich <jbeulich@suse.com>
358
359 * i386-dis.c (OP_Mwaitx): Delete.
360 (prefix_table): Use OP_Mwait for mwaitx entry.
361 (OP_Mwait): Also handle mwaitx.
362
267b8516
JB		 3632019-11-05 Jan Beulich <jbeulich@suse.com>
364
365 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
366 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
367 (prefix_table): Add respective entries.
368 (rm_table): Link to those entries.
369
f8687e93
JB		 3702019-11-05 Jan Beulich <jbeulich@suse.com>
371
372 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
373 (REG_0F1C_P_0_MOD_0): ... this.
374 (REG_0F1E_MOD_3): Rename to ...
375 (REG_0F1E_P_1_MOD_3): ... this.
376 (RM_0F01_REG_5): Rename to ...
377 (RM_0F01_REG_5_MOD_3): ... this.
378 (RM_0F01_REG_7): Rename to ...
379 (RM_0F01_REG_7_MOD_3): ... this.
380 (RM_0F1E_MOD_3_REG_7): Rename to ...
381 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
382 (RM_0FAE_REG_6): Rename to ...
383 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
384 (RM_0FAE_REG_7): Rename to ...
385 (RM_0FAE_REG_7_MOD_3): ... this.
386 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
387 (PREFIX_0F01_REG_5_MOD_0): ... this.
388 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
389 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
390 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
391 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
392 (PREFIX_0FAE_REG_0): Rename to ...
393 (PREFIX_0FAE_REG_0_MOD_3): ... this.
394 (PREFIX_0FAE_REG_1): Rename to ...
395 (PREFIX_0FAE_REG_1_MOD_3): ... this.
396 (PREFIX_0FAE_REG_2): Rename to ...
397 (PREFIX_0FAE_REG_2_MOD_3): ... this.
398 (PREFIX_0FAE_REG_3): Rename to ...
399 (PREFIX_0FAE_REG_3_MOD_3): ... this.
400 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
401 (PREFIX_0FAE_REG_4_MOD_0): ... this.
402 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
403 (PREFIX_0FAE_REG_4_MOD_3): ... this.
404 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
405 (PREFIX_0FAE_REG_5_MOD_0): ... this.
406 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
407 (PREFIX_0FAE_REG_5_MOD_3): ... this.
408 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
409 (PREFIX_0FAE_REG_6_MOD_0): ... this.
410 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
411 (PREFIX_0FAE_REG_6_MOD_3): ... this.
412 (PREFIX_0FAE_REG_7): Rename to ...
413 (PREFIX_0FAE_REG_7_MOD_0): ... this.
414 (PREFIX_MOD_0_0FC3): Rename to ...
415 (PREFIX_0FC3_MOD_0): ... this.
416 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
417 (PREFIX_0FC7_REG_6_MOD_0): ... this.
418 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
419 (PREFIX_0FC7_REG_6_MOD_3): ... this.
420 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
421 (PREFIX_0FC7_REG_7_MOD_3): ... this.
422 (reg_table, prefix_table, mod_table, rm_table): Adjust
423 accordingly.
424
5103274f
NC		 4252019-11-04 Nick Clifton <nickc@redhat.com>
426
427 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
428 of a v850 system register. Move the v850_sreg_names array into
429 this function.
430 (get_v850_reg_name): Likewise for ordinary register names.
431 (get_v850_vreg_name): Likewise for vector register names.
432 (get_v850_cc_name): Likewise for condition codes.
433 * get_v850_float_cc_name): Likewise for floating point condition
434 codes.
435 (get_v850_cacheop_name): Likewise for cache-ops.
436 (get_v850_prefop_name): Likewise for pref-ops.
437 (disassemble): Use the new accessor functions.
438
1820262b
DB		 4392019-10-30 Delia Burduv <delia.burduv@arm.com>
440
441 * aarch64-opc.c (print_immediate_offset_address): Don't print the
442 immediate for the writeback form of ldraa/ldrab if it is 0.
443 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
444 * aarch64-opc-2.c: Regenerated.
445
3cc17af5
JB		 4462019-10-30 Jan Beulich <jbeulich@suse.com>
447
448 * i386-gen.c (operand_type_shorthands): Delete.
449 (operand_type_init): Expand previous shorthands.
450 (set_bitfield_from_shorthand): Rename back to ...
451 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
452 of operand_type_init[].
453 (set_bitfield): Adjust call to the above function.
454 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
455 RegXMM, RegYMM, RegZMM): Define.
456 * i386-reg.tbl: Expand prior shorthands.
457
a2cebd03
JB		 4582019-10-30 Jan Beulich <jbeulich@suse.com>
459
460 * i386-gen.c (output_i386_opcode): Change order of fields
461 emitted to output.
462 * i386-opc.h (struct insn_template): Move operands field.
463 Convert extension_opcode field to unsigned short.
464 * i386-tbl.h: Re-generate.
465
507916b8
JB		 4662019-10-30 Jan Beulich <jbeulich@suse.com>
467
468 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
469 of W.
470 * i386-opc.h (W): Extend comment.
471 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
472 general purpose variants not allowing for byte operands.
473 * i386-tbl.h: Re-generate.
474
efea62b4
NC		 4752019-10-29 Nick Clifton <nickc@redhat.com>
476
477 * tic30-dis.c (print_branch): Correct size of operand array.
478
9adb2591
NC		 4792019-10-29 Nick Clifton <nickc@redhat.com>
480
481 * d30v-dis.c (print_insn): Check that operand index is valid
482 before attempting to access the operands array.
483
993a00a9
NC		 4842019-10-29 Nick Clifton <nickc@redhat.com>
485
486 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
487 locating the bit to be tested.
488
66a66a17
NC		 4892019-10-29 Nick Clifton <nickc@redhat.com>
490
491 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
492 values.
493 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
494 (print_insn_s12z): Check for illegal size values.
495
1ee3542c
NC		 4962019-10-28 Nick Clifton <nickc@redhat.com>
497
498 * csky-dis.c (csky_chars_to_number): Check for a negative
499 count. Use an unsigned integer to construct the return value.
500
bbf9a0b5
NC		 5012019-10-28 Nick Clifton <nickc@redhat.com>
502
503 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
504 operand buffer. Set value to 15 not 13.
505 (get_register_operand): Use OPERAND_BUFFER_LEN.
506 (get_indirect_operand): Likewise.
507 (print_two_operand): Likewise.
508 (print_three_operand): Likewise.
509 (print_oar_insn): Likewise.
510
d1e304bc
NC		 5112019-10-28 Nick Clifton <nickc@redhat.com>
512
513 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
514 (bit_extract_simple): Likewise.
515 (bit_copy): Likewise.
516 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
517 index_offset array are not accessed.
518
dee33451
NC		 5192019-10-28 Nick Clifton <nickc@redhat.com>
520
521 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
522 operand.
523
27cee81d
NC		 5242019-10-25 Nick Clifton <nickc@redhat.com>
525
526 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
527 access to opcodes.op array element.
528
de6d8dc2
NC		 5292019-10-23 Nick Clifton <nickc@redhat.com>
530
531 * rx-dis.c (get_register_name): Fix spelling typo in error
532 message.
533 (get_condition_name, get_flag_name, get_double_register_name)
534 (get_double_register_high_name, get_double_register_low_name)
535 (get_double_control_register_name, get_double_condition_name)
536 (get_opsize_name, get_size_name): Likewise.
537
6207ed28
NC		 5382019-10-22 Nick Clifton <nickc@redhat.com>
539
540 * rx-dis.c (get_size_name): New function. Provides safe
541 access to name array.
542 (get_opsize_name): Likewise.
543 (print_insn_rx): Use the accessor functions.
544
12234dfd
NC		 5452019-10-16 Nick Clifton <nickc@redhat.com>
546
547 * rx-dis.c (get_register_name): New function. Provides safe
548 access to name array.
549 (get_condition_name, get_flag_name, get_double_register_name)
550 (get_double_register_high_name, get_double_register_low_name)
551 (get_double_control_register_name, get_double_condition_name):
552 Likewise.
553 (print_insn_rx): Use the accessor functions.
554
1d378749
NC		 5552019-10-09 Nick Clifton <nickc@redhat.com>
556
557 PR 25041
558 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
559 instructions.
560
d241b910
JB		 5612019-10-07 Jan Beulich <jbeulich@suse.com>
562
563 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
564 (cmpsd): Likewise. Move EsSeg to other operand.
565 * opcodes/i386-tbl.h: Re-generate.
566
f5c5b7c1
AM		 5672019-09-23 Alan Modra <amodra@gmail.com>
568
569 * m68k-dis.c: Include cpu-m68k.h
570
7beeaeb8
AM		 5712019-09-23 Alan Modra <amodra@gmail.com>
572
573 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
574 "elf/mips.h" earlier.
575
3f9aad11
JB		 5762018-09-20 Jan Beulich <jbeulich@suse.com>
577
578 PR gas/25012
579 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
580 with SReg operand.
581 * i386-tbl.h: Re-generate.
582
fd361982
AM		 5832019-09-18 Alan Modra <amodra@gmail.com>
584
585 * arc-ext.c: Update throughout for bfd section macro changes.
586
e0b2a78c
SM		 5872019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
588
589 * Makefile.in: Re-generate.
590 * configure: Re-generate.
591
7e9ad3a3
JW		 5922019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
593
594 * riscv-opc.c (riscv_opcodes): Change subset field
595 to insn_class field for all instructions.
596 (riscv_insn_types): Likewise.
597
bb695960
PB		 5982019-09-16 Phil Blundell <pb@pbcl.net>
599
600 * configure: Regenerated.
601
8063ab7e
MV		 6022019-09-10 Miod Vallat <miod@online.fr>
603
604 PR 24982
605 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
606
60391a25
PB		 6072019-09-09 Phil Blundell <pb@pbcl.net>
608
609 binutils 2.33 branch created.
610
f44b758d
NC		 6112019-09-03 Nick Clifton <nickc@redhat.com>
612
613 PR 24961
614 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
615 greater than zero before indexing via (bufcnt -1).
616
1e4b5e7d
NC		 6172019-09-03 Nick Clifton <nickc@redhat.com>
618
619 PR 24958
620 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
621 (MAX_SPEC_REG_NAME_LEN): Define.
622 (struct mmix_dis_info): Use defined constants for array lengths.
623 (get_reg_name): New function.
624 (get_sprec_reg_name): New function.
625 (print_insn_mmix): Use new functions.
626
c4a23bf8
SP		 6272019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
628
629 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
630 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
631 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
632
a051e2f3
KT		 6332019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
634
635 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
636 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
637 (aarch64_sys_reg_supported_p): Update checks for the above.
638
08132bdd
SP		 6392019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
640
641 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
642 cases MVE_SQRSHRL and MVE_UQRSHLL.
643 (print_insn_mve): Add case for specifier 'k' to check
644 specific bit of the instruction.
645
d88bdcb4
PA		 6462019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
647
648 PR 24854
649 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
650 encountering an unknown machine type.
651 (print_insn_arc): Handle arc_insn_length returning 0. In error
652 cases return -1 rather than calling abort.
653
bc750500
JB		 6542019-08-07 Jan Beulich <jbeulich@suse.com>
655
656 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
657 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
658 IgnoreSize.
659 * i386-tbl.h: Re-generate.
660
23d188c7
BW		 6612019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
662
663 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
664 instructions.
665
c0d6f62f
JW		 6662019-07-30 Mel Chen <mel.chen@sifive.com>
667
668 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
669 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
670
671 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
672 fscsr.
673
0f3f7167
CZ		 6742019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
675
676 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
677 and MPY class instructions.
678 (parse_option): Add nps400 option.
679 (print_arc_disassembler_options): Add nps400 info.
680
7e126ba3
CZ		 6812019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
682
683 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
684 (bspop): Likewise.
685 (modapp): Likewise.
686 * arc-opc.c (RAD_CHK): Add.
687 * arc-tbl.h: Regenerate.
688
a028026d
KT		 6892019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
690
691 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
692 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
693
ac79ff9e
NC		 6942019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
695
696 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
697 instructions as UNPREDICTABLE.
698
231097b0
JM		 6992019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
700
701 * bpf-desc.c: Regenerated.
702
1d942ae9
JB		 7032019-07-17 Jan Beulich <jbeulich@suse.com>
704
705 * i386-gen.c (static_assert): Define.
706 (main): Use it.
707 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
708 (Opcode_Modifier_Num): ... this.
709 (Mem): Delete.
710
dfd69174
JB		 7112019-07-16 Jan Beulich <jbeulich@suse.com>
712
713 * i386-gen.c (operand_types): Move RegMem ...
714 (opcode_modifiers): ... here.
715 * i386-opc.h (RegMem): Move to opcode modifer enum.
716 (union i386_operand_type): Move regmem field ...
717 (struct i386_opcode_modifier): ... here.
718 * i386-opc.tbl (RegMem): Define.
719 (mov, movq): Move RegMem on segment, control, debug, and test
720 register flavors.
721 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
722 to non-SSE2AVX flavor.
723 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
724 Move RegMem on register only flavors. Drop IgnoreSize from
725 legacy encoding flavors.
726 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
727 flavors.
728 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
729 register only flavors.
730 (vmovd): Move RegMem and drop IgnoreSize on register only
731 flavor. Change opcode and operand order to store form.
732 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
733
21df382b
JB		 7342019-07-16 Jan Beulich <jbeulich@suse.com>
735
736 * i386-gen.c (operand_type_init, operand_types): Replace SReg
737 entries.
738 * i386-opc.h (SReg2, SReg3): Replace by ...
739 (SReg): ... this.
740 (union i386_operand_type): Replace sreg fields.
741 * i386-opc.tbl (mov, ): Use SReg.
742 (push, pop): Likewies. Drop i386 and x86-64 specific segment
743 register flavors.
744 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
745 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
746
3719fd55
JM		 7472019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
748
749 * bpf-desc.c: Regenerate.
750 * bpf-opc.c: Likewise.
751 * bpf-opc.h: Likewise.
752
92434a14
JM		 7532019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
754
755 * bpf-desc.c: Regenerate.
756 * bpf-opc.c: Likewise.
757
43dd7626
HPN		 7582019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
759
760 * arm-dis.c (print_insn_coprocessor): Rename index to
761 index_operand.
762
98602811
JW		 7632019-07-05 Kito Cheng <kito.cheng@sifive.com>
764
765 * riscv-opc.c (riscv_insn_types): Add r4 type.
766
767 * riscv-opc.c (riscv_insn_types): Add b and j type.
768
769 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
770 format for sb type and correct s type.
771
01c1ee4a
RS		 7722019-07-02 Richard Sandiford <richard.sandiford@arm.com>
773
774 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
775 SVE FMOV alias of FCPY.
776
83adff69
RS		 7772019-07-02 Richard Sandiford <richard.sandiford@arm.com>
778
779 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
780 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
781
89418844
RS		 7822019-07-02 Richard Sandiford <richard.sandiford@arm.com>
783
784 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
785 registers in an instruction prefixed by MOVPRFX.
786
41be57ca
MM		 7872019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
788
789 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
790 sve_size_13 icode to account for variant behaviour of
791 pmull{t,b}.
792 * aarch64-dis-2.c: Regenerate.
793 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
794 sve_size_13 icode to account for variant behaviour of
795 pmull{t,b}.
796 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
797 (OP_SVE_VVV_Q_D): Add new qualifier.
798 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
799 (struct aarch64_opcode): Split pmull{t,b} into those requiring
800 AES and those not.
801
9d3bf266
JB		 8022019-07-01 Jan Beulich <jbeulich@suse.com>
803
804 * opcodes/i386-gen.c (operand_type_init): Remove
805 OPERAND_TYPE_VEC_IMM4 entry.
806 (operand_types): Remove Vec_Imm4.
807 * opcodes/i386-opc.h (Vec_Imm4): Delete.
808 (union i386_operand_type): Remove vec_imm4.
809 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
810 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
811
c3949f43
JB		 8122019-07-01 Jan Beulich <jbeulich@suse.com>
813
814 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
815 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
816 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
817 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
818 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
819 monitorx, mwaitx): Drop ImmExt from operand-less forms.
820 * i386-tbl.h: Re-generate.
821
5641ec01
JB		 8222019-07-01 Jan Beulich <jbeulich@suse.com>
823
824 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
825 register operands.
826 * i386-tbl.h: Re-generate.
827
79dec6b7
JB		 8282019-07-01 Jan Beulich <jbeulich@suse.com>
829
830 * i386-opc.tbl (C): New.
831 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
832 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
833 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
834 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
835 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
836 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
837 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
838 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
839 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
840 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
841 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
842 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
843 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
844 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
845 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
846 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
847 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
848 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
849 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
850 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
851 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
852 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
853 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
854 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
855 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
856 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
857 flavors.
858 * i386-tbl.h: Re-generate.
859
a0a1771e
JB		 8602019-07-01 Jan Beulich <jbeulich@suse.com>
861
862 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
863 register operands.
864 * i386-tbl.h: Re-generate.
865
cd546e7b
JB		 8662019-07-01 Jan Beulich <jbeulich@suse.com>
867
868 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
869 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
870 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
871 * i386-tbl.h: Re-generate.
872
e3bba3fc
JB		 8732019-07-01 Jan Beulich <jbeulich@suse.com>
874
875 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
876 Disp8MemShift from register only templates.
877 * i386-tbl.h: Re-generate.
878
36cc073e
JB		 8792019-07-01 Jan Beulich <jbeulich@suse.com>
880
881 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
882 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
883 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
884 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
885 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
886 EVEX_W_0F11_P_3_M_1): Delete.
887 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
888 EVEX_W_0F11_P_3): New.
889 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
890 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
891 MOD_EVEX_0F11_PREFIX_3 table entries.
892 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
893 PREFIX_EVEX_0F11 table entries.
894 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
895 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
896 EVEX_W_0F11_P_3_M_{0,1} table entries.
897
219920a7
JB		 8982019-07-01 Jan Beulich <jbeulich@suse.com>
899
900 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
901 Delete.
902
e395f487
L		 9032019-06-27 H.J. Lu <hongjiu.lu@intel.com>
904
905 PR binutils/24719
906 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
907 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
908 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
909 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
910 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
911 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
912 EVEX_LEN_0F38C7_R_6_P_2_W_1.
913 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
914 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
915 PREFIX_EVEX_0F38C6_REG_6 entries.
916 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
917 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
918 EVEX_W_0F38C7_R_6_P_2 entries.
919 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
920 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
921 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
922 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
923 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
924 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
925 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
926
2b7bcc87
JB		 9272019-06-27 Jan Beulich <jbeulich@suse.com>
928
929 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
930 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
931 VEX_LEN_0F2D_P_3): Delete.
932 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
933 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
934 (prefix_table): ... here.
935
c1dc7af5
JB		 9362019-06-27 Jan Beulich <jbeulich@suse.com>
937
938 * i386-dis.c (Iq): Delete.
939 (Id): New.
940 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
941 TBM insns.
942 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
943 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
944 (OP_E_memory): Also honor needindex when deciding whether an
945 address size prefix needs printing.
946 (OP_I): Remove handling of q_mode. Add handling of d_mode.
947
d7560e2d
JW		 9482019-06-26 Jim Wilson <jimw@sifive.com>
949
950 PR binutils/24739
951 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
952 Set info->display_endian to info->endian_code.
953
2c703856
JB		 9542019-06-25 Jan Beulich <jbeulich@suse.com>
955
956 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
957 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
958 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
959 OPERAND_TYPE_ACC64 entries.
960 * i386-init.h: Re-generate.
961
54fbadc0
JB		 9622019-06-25 Jan Beulich <jbeulich@suse.com>
963
964 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
965 Delete.
966 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
967 of dqa_mode.
968 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
969 entries here.
970 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
971 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
972
a280ab8e
JB		 9732019-06-25 Jan Beulich <jbeulich@suse.com>
974
975 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
976 variables.
977
e1a1babd
JB		 9782019-06-25 Jan Beulich <jbeulich@suse.com>
979
980 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
981 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
982 movnti.
d7560e2d 983 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 984 * i386-tbl.h: Re-generate.
985
b8364fa7
JB		 9862019-06-25 Jan Beulich <jbeulich@suse.com>
987
988 * i386-opc.tbl (and): Mark Imm8S form for optimization.
989 * i386-tbl.h: Re-generate.
990
ad692897
L		 9912019-06-21 H.J. Lu <hongjiu.lu@intel.com>
992
993 * i386-dis-evex.h: Break into ...
994 * i386-dis-evex-len.h: New file.
995 * i386-dis-evex-mod.h: Likewise.
996 * i386-dis-evex-prefix.h: Likewise.
997 * i386-dis-evex-reg.h: Likewise.
998 * i386-dis-evex-w.h: Likewise.
999 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1000 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1001 i386-dis-evex-mod.h.
1002
f0a6222e
L		 10032019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1004
1005 PR binutils/24700
1006 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1007 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1008 EVEX_W_0F385B_P_2.
1009 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1010 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1011 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1012 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1013 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1014 EVEX_LEN_0F385B_P_2_W_1.
1015 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1016 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1017 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1018 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1019 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1020 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1021 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1022 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1023 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1024 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1025
6e1c90b7
L		 10262019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1027
1028 PR binutils/24691
1029 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1030 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1031 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1032 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1033 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1034 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1035 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1036 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1037 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1038 EVEX_LEN_0F3A43_P_2_W_1.
1039 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1040 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1041 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1042 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1043 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1044 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1045 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1046 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1047 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1048 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1049 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1050 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1051
bcc5a6eb
NC		 10522019-06-14 Nick Clifton <nickc@redhat.com>
1053
1054 * po/fr.po; Updated French translation.
1055
e4c4ac46
SH		 10562019-06-13 Stafford Horne <shorne@gmail.com>
1057
1058 * or1k-asm.c: Regenerated.
1059 * or1k-desc.c: Regenerated.
1060 * or1k-desc.h: Regenerated.
1061 * or1k-dis.c: Regenerated.
1062 * or1k-ibld.c: Regenerated.
1063 * or1k-opc.c: Regenerated.
1064 * or1k-opc.h: Regenerated.
1065 * or1k-opinst.c: Regenerated.
1066
a0e44ef5
PB		 10672019-06-12 Peter Bergner <bergner@linux.ibm.com>
1068
1069 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1070
12efd68d
L		 10712019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1072
1073 PR binutils/24633
1074 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1075 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1076 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1077 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1078 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1079 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1080 EVEX_LEN_0F3A1B_P_2_W_1.
1081 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1082 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1083 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1084 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1085 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1086 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1087 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1088 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1089
63c6fc6c
L		 10902019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1091
1092 PR binutils/24626
1093 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1094 EVEX.vvvv when disassembling VEX and EVEX instructions.
1095 (OP_VEX): Set vex.register_specifier to 0 after readding
1096 vex.register_specifier.
1097 (OP_Vex_2src_1): Likewise.
1098 (OP_Vex_2src_2): Likewise.
1099 (OP_LWP_E): Likewise.
1100 (OP_EX_Vex): Don't check vex.register_specifier.
1101 (OP_XMM_Vex): Likewise.
1102
9186c494
L		 11032019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1104 Lili Cui <lili.cui@intel.com>
1105
1106 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1107 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1108 instructions.
1109 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1110 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1111 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1112 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1113 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1114 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1115 * i386-init.h: Regenerated.
1116 * i386-tbl.h: Likewise.
1117
5d79adc4
L		 11182019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1119 Lili Cui <lili.cui@intel.com>
1120
1121 * doc/c-i386.texi: Document enqcmd.
1122 * testsuite/gas/i386/enqcmd-intel.d: New file.
1123 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1124 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1125 * testsuite/gas/i386/enqcmd.d: Likewise.
1126 * testsuite/gas/i386/enqcmd.s: Likewise.
1127 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1128 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1129 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1130 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1131 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1132 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1133 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1134 and x86-64-enqcmd.
1135
a9d96ab9
AH		 11362019-06-04 Alan Hayward <alan.hayward@arm.com>
1137
1138 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1139
4f6d070a
AM		 11402019-06-03 Alan Modra <amodra@gmail.com>
1141
1142 * ppc-dis.c (prefix_opcd_indices): Correct size.
1143
a2f4b66c
L		 11442019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1145
1146 PR gas/24625
1147 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1148 Disp8ShiftVL.
1149 * i386-tbl.h: Regenerated.
1150
405b5bd8
AM		 11512019-05-24 Alan Modra <amodra@gmail.com>
1152
1153 * po/POTFILES.in: Regenerate.
1154
8acf1435
PB		 11552019-05-24 Peter Bergner <bergner@linux.ibm.com>
1156 Alan Modra <amodra@gmail.com>
1157
1158 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1159 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1160 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1161 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1162 XTOP>): Define and add entries.
1163 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1164 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1165 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1166 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1167
dd7efa79
PB		 11682019-05-24 Peter Bergner <bergner@linux.ibm.com>
1169 Alan Modra <amodra@gmail.com>
1170
1171 * ppc-dis.c (ppc_opts): Add "future" entry.
1172 (PREFIX_OPCD_SEGS): Define.
1173 (prefix_opcd_indices): New array.
1174 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1175 (lookup_prefix): New function.
1176 (print_insn_powerpc): Handle 64-bit prefix instructions.
1177 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1178 (PMRR, POWERXX): Define.
1179 (prefix_opcodes): New instruction table.
1180 (prefix_num_opcodes): New constant.
1181
79472b45
JM		 11822019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1183
1184 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1185 * configure: Regenerated.
1186 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1187 and cpu/bpf.opc.
1188 (HFILES): Add bpf-desc.h and bpf-opc.h.
1189 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1190 bpf-ibld.c and bpf-opc.c.
1191 (BPF_DEPS): Define.
1192 * Makefile.in: Regenerated.
1193 * disassemble.c (ARCH_bpf): Define.
1194 (disassembler): Add case for bfd_arch_bpf.
1195 (disassemble_init_for_target): Likewise.
1196 (enum epbf_isa_attr): Define.
1197 * disassemble.h: extern print_insn_bpf.
1198 * bpf-asm.c: Generated.
1199 * bpf-opc.h: Likewise.
1200 * bpf-opc.c: Likewise.
1201 * bpf-ibld.c: Likewise.
1202 * bpf-dis.c: Likewise.
1203 * bpf-desc.h: Likewise.
1204 * bpf-desc.c: Likewise.
1205
ba6cd17f
SD		 12062019-05-21 Sudakshina Das <sudi.das@arm.com>
1207
1208 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1209 and VMSR with the new operands.
1210
e39c1607
SD		 12112019-05-21 Sudakshina Das <sudi.das@arm.com>
1212
1213 * arm-dis.c (enum mve_instructions): New enum
1214 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1215 and cneg.
1216 (mve_opcodes): New instructions as above.
1217 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1218 csneg and csel.
1219 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1220
23d00a41
SD		 12212019-05-21 Sudakshina Das <sudi.das@arm.com>
1222
1223 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1224 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1225 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1226 uqshl, urshrl and urshr.
1227 (is_mve_okay_in_it): Add new instructions to TRUE list.
1228 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1229 (print_insn_mve): Updated to accept new %j,
1230 %<bitfield>m and %<bitfield>n patterns.
1231
cd4797ee
FS		 12322019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1233
1234 * mips-opc.c (mips_builtin_opcodes): Change source register
1235 constraint for DAUI.
1236
999b073b
NC		 12372019-05-20 Nick Clifton <nickc@redhat.com>
1238
1239 * po/fr.po: Updated French translation.
1240
14b456f2
AV		 12412019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1242 Michael Collison <michael.collison@arm.com>
1243
1244 * arm-dis.c (thumb32_opcodes): Add new instructions.
1245 (enum mve_instructions): Likewise.
1246 (enum mve_undefined): Add new reasons.
1247 (is_mve_encoding_conflict): Handle new instructions.
1248 (is_mve_undefined): Likewise.
1249 (is_mve_unpredictable): Likewise.
1250 (print_mve_undefined): Likewise.
1251 (print_mve_size): Likewise.
1252
f49bb598
AV		 12532019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1254 Michael Collison <michael.collison@arm.com>
1255
1256 * arm-dis.c (thumb32_opcodes): Add new instructions.
1257 (enum mve_instructions): Likewise.
1258 (is_mve_encoding_conflict): Handle new instructions.
1259 (is_mve_undefined): Likewise.
1260 (is_mve_unpredictable): Likewise.
1261 (print_mve_size): Likewise.
1262
56858bea
AV		 12632019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1264 Michael Collison <michael.collison@arm.com>
1265
1266 * arm-dis.c (thumb32_opcodes): Add new instructions.
1267 (enum mve_instructions): Likewise.
1268 (is_mve_encoding_conflict): Likewise.
1269 (is_mve_unpredictable): Likewise.
1270 (print_mve_size): Likewise.
1271
e523f101
AV		 12722019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1273 Michael Collison <michael.collison@arm.com>
1274
1275 * arm-dis.c (thumb32_opcodes): Add new instructions.
1276 (enum mve_instructions): Likewise.
1277 (is_mve_encoding_conflict): Handle new instructions.
1278 (is_mve_undefined): Likewise.
1279 (is_mve_unpredictable): Likewise.
1280 (print_mve_size): Likewise.
1281
66dcaa5d
AV		 12822019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1283 Michael Collison <michael.collison@arm.com>
1284
1285 * arm-dis.c (thumb32_opcodes): Add new instructions.
1286 (enum mve_instructions): Likewise.
1287 (is_mve_encoding_conflict): Handle new instructions.
1288 (is_mve_undefined): Likewise.
1289 (is_mve_unpredictable): Likewise.
1290 (print_mve_size): Likewise.
1291 (print_insn_mve): Likewise.
1292
d052b9b7
AV		 12932019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1294 Michael Collison <michael.collison@arm.com>
1295
1296 * arm-dis.c (thumb32_opcodes): Add new instructions.
1297 (print_insn_thumb32): Handle new instructions.
1298
ed63aa17
AV		 12992019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1300 Michael Collison <michael.collison@arm.com>
1301
1302 * arm-dis.c (enum mve_instructions): Add new instructions.
1303 (enum mve_undefined): Add new reasons.
1304 (is_mve_encoding_conflict): Handle new instructions.
1305 (is_mve_undefined): Likewise.
1306 (is_mve_unpredictable): Likewise.
1307 (print_mve_undefined): Likewise.
1308 (print_mve_size): Likewise.
1309 (print_mve_shift_n): Likewise.
1310 (print_insn_mve): Likewise.
1311
897b9bbc
AV		 13122019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1313 Michael Collison <michael.collison@arm.com>
1314
1315 * arm-dis.c (enum mve_instructions): Add new instructions.
1316 (is_mve_encoding_conflict): Handle new instructions.
1317 (is_mve_unpredictable): Likewise.
1318 (print_mve_rotate): Likewise.
1319 (print_mve_size): Likewise.
1320 (print_insn_mve): Likewise.
1321
1c8f2df8
AV		 13222019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1323 Michael Collison <michael.collison@arm.com>
1324
1325 * arm-dis.c (enum mve_instructions): Add new instructions.
1326 (is_mve_encoding_conflict): Handle new instructions.
1327 (is_mve_unpredictable): Likewise.
1328 (print_mve_size): Likewise.
1329 (print_insn_mve): Likewise.
1330
d3b63143
AV		 13312019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1332 Michael Collison <michael.collison@arm.com>
1333
1334 * arm-dis.c (enum mve_instructions): Add new instructions.
1335 (enum mve_undefined): Add new reasons.
1336 (is_mve_encoding_conflict): Handle new instructions.
1337 (is_mve_undefined): Likewise.
1338 (is_mve_unpredictable): Likewise.
1339 (print_mve_undefined): Likewise.
1340 (print_mve_size): Likewise.
1341 (print_insn_mve): Likewise.
1342
14925797
AV		 13432019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1344 Michael Collison <michael.collison@arm.com>
1345
1346 * arm-dis.c (enum mve_instructions): Add new instructions.
1347 (is_mve_encoding_conflict): Handle new instructions.
1348 (is_mve_undefined): Likewise.
1349 (is_mve_unpredictable): Likewise.
1350 (print_mve_size): Likewise.
1351 (print_insn_mve): Likewise.
1352
c507f10b
AV		 13532019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1354 Michael Collison <michael.collison@arm.com>
1355
1356 * arm-dis.c (enum mve_instructions): Add new instructions.
1357 (enum mve_unpredictable): Add new reasons.
1358 (enum mve_undefined): Likewise.
1359 (is_mve_okay_in_it): Handle new isntructions.
1360 (is_mve_encoding_conflict): Likewise.
1361 (is_mve_undefined): Likewise.
1362 (is_mve_unpredictable): Likewise.
1363 (print_mve_vmov_index): Likewise.
1364 (print_simd_imm8): Likewise.
1365 (print_mve_undefined): Likewise.
1366 (print_mve_unpredictable): Likewise.
1367 (print_mve_size): Likewise.
1368 (print_insn_mve): Likewise.
1369
bf0b396d
AV		 13702019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1371 Michael Collison <michael.collison@arm.com>
1372
1373 * arm-dis.c (enum mve_instructions): Add new instructions.
1374 (enum mve_unpredictable): Add new reasons.
1375 (enum mve_undefined): Likewise.
1376 (is_mve_encoding_conflict): Handle new instructions.
1377 (is_mve_undefined): Likewise.
1378 (is_mve_unpredictable): Likewise.
1379 (print_mve_undefined): Likewise.
1380 (print_mve_unpredictable): Likewise.
1381 (print_mve_rounding_mode): Likewise.
1382 (print_mve_vcvt_size): Likewise.
1383 (print_mve_size): Likewise.
1384 (print_insn_mve): Likewise.
1385
ef1576a1
AV		 13862019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1387 Michael Collison <michael.collison@arm.com>
1388
1389 * arm-dis.c (enum mve_instructions): Add new instructions.
1390 (enum mve_unpredictable): Add new reasons.
1391 (enum mve_undefined): Likewise.
1392 (is_mve_undefined): Handle new instructions.
1393 (is_mve_unpredictable): Likewise.
1394 (print_mve_undefined): Likewise.
1395 (print_mve_unpredictable): Likewise.
1396 (print_mve_size): Likewise.
1397 (print_insn_mve): Likewise.
1398
aef6d006
AV		 13992019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1400 Michael Collison <michael.collison@arm.com>
1401
1402 * arm-dis.c (enum mve_instructions): Add new instructions.
1403 (enum mve_undefined): Add new reasons.
1404 (insns): Add new instructions.
1405 (is_mve_encoding_conflict):
1406 (print_mve_vld_str_addr): New print function.
1407 (is_mve_undefined): Handle new instructions.
1408 (is_mve_unpredictable): Likewise.
1409 (print_mve_undefined): Likewise.
1410 (print_mve_size): Likewise.
1411 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1412 (print_insn_mve): Handle new operands.
1413
04d54ace
AV		 14142019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1415 Michael Collison <michael.collison@arm.com>
1416
1417 * arm-dis.c (enum mve_instructions): Add new instructions.
1418 (enum mve_unpredictable): Add new reasons.
1419 (is_mve_encoding_conflict): Handle new instructions.
1420 (is_mve_unpredictable): Likewise.
1421 (mve_opcodes): Add new instructions.
1422 (print_mve_unpredictable): Handle new reasons.
1423 (print_mve_register_blocks): New print function.
1424 (print_mve_size): Handle new instructions.
1425 (print_insn_mve): Likewise.
1426
9743db03
AV		 14272019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1428 Michael Collison <michael.collison@arm.com>
1429
1430 * arm-dis.c (enum mve_instructions): Add new instructions.
1431 (enum mve_unpredictable): Add new reasons.
1432 (enum mve_undefined): Likewise.
1433 (is_mve_encoding_conflict): Handle new instructions.
1434 (is_mve_undefined): Likewise.
1435 (is_mve_unpredictable): Likewise.
1436 (coprocessor_opcodes): Move NEON VDUP from here...
1437 (neon_opcodes): ... to here.
1438 (mve_opcodes): Add new instructions.
1439 (print_mve_undefined): Handle new reasons.
1440 (print_mve_unpredictable): Likewise.
1441 (print_mve_size): Handle new instructions.
1442 (print_insn_neon): Handle vdup.
1443 (print_insn_mve): Handle new operands.
1444
143275ea
AV		 14452019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1446 Michael Collison <michael.collison@arm.com>
1447
1448 * arm-dis.c (enum mve_instructions): Add new instructions.
1449 (enum mve_unpredictable): Add new values.
1450 (mve_opcodes): Add new instructions.
1451 (vec_condnames): New array with vector conditions.
1452 (mve_predicatenames): New array with predicate suffixes.
1453 (mve_vec_sizename): New array with vector sizes.
1454 (enum vpt_pred_state): New enum with vector predication states.
1455 (struct vpt_block): New struct type for vpt blocks.
1456 (vpt_block_state): Global struct to keep track of state.
1457 (mve_extract_pred_mask): New helper function.
1458 (num_instructions_vpt_block): Likewise.
1459 (mark_outside_vpt_block): Likewise.
1460 (mark_inside_vpt_block): Likewise.
1461 (invert_next_predicate_state): Likewise.
1462 (update_next_predicate_state): Likewise.
1463 (update_vpt_block_state): Likewise.
1464 (is_vpt_instruction): Likewise.
1465 (is_mve_encoding_conflict): Add entries for new instructions.
1466 (is_mve_unpredictable): Likewise.
1467 (print_mve_unpredictable): Handle new cases.
1468 (print_instruction_predicate): Likewise.
1469 (print_mve_size): New function.
1470 (print_vec_condition): New function.
1471 (print_insn_mve): Handle vpt blocks and new print operands.
1472
f08d8ce3
AV		 14732019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1474
1475 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1476 8, 14 and 15 for Armv8.1-M Mainline.
1477
73cd51e5
AV		 14782019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1479 Michael Collison <michael.collison@arm.com>
1480
1481 * arm-dis.c (enum mve_instructions): New enum.
1482 (enum mve_unpredictable): Likewise.
1483 (enum mve_undefined): Likewise.
1484 (struct mopcode32): New struct.
1485 (is_mve_okay_in_it): New function.
1486 (is_mve_architecture): Likewise.
1487 (arm_decode_field): Likewise.
1488 (arm_decode_field_multiple): Likewise.
1489 (is_mve_encoding_conflict): Likewise.
1490 (is_mve_undefined): Likewise.
1491 (is_mve_unpredictable): Likewise.
1492 (print_mve_undefined): Likewise.
1493 (print_mve_unpredictable): Likewise.
1494 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1495 (print_insn_mve): New function.
1496 (print_insn_thumb32): Handle MVE architecture.
1497 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1498
3076e594
NC		 14992019-05-10 Nick Clifton <nickc@redhat.com>
1500
1501 PR 24538
1502 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1503 end of the table prematurely.
1504
387e7624
FS		 15052019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1506
1507 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1508 macros for R6.
1509
0067be51
AM		 15102019-05-11 Alan Modra <amodra@gmail.com>
1511
1512 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1513 when -Mraw is in effect.
1514
42e6288f
MM		 15152019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1516
1517 * aarch64-dis-2.c: Regenerate.
1518 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1519 (OP_SVE_BBB): New variant set.
1520 (OP_SVE_DDDD): New variant set.
1521 (OP_SVE_HHH): New variant set.
1522 (OP_SVE_HHHU): New variant set.
1523 (OP_SVE_SSS): New variant set.
1524 (OP_SVE_SSSU): New variant set.
1525 (OP_SVE_SHH): New variant set.
1526 (OP_SVE_SBBU): New variant set.
1527 (OP_SVE_DSS): New variant set.
1528 (OP_SVE_DHHU): New variant set.
1529 (OP_SVE_VMV_HSD_BHS): New variant set.
1530 (OP_SVE_VVU_HSD_BHS): New variant set.
1531 (OP_SVE_VVVU_SD_BH): New variant set.
1532 (OP_SVE_VVVU_BHSD): New variant set.
1533 (OP_SVE_VVV_QHD_DBS): New variant set.
1534 (OP_SVE_VVV_HSD_BHS): New variant set.
1535 (OP_SVE_VVV_HSD_BHS2): New variant set.
1536 (OP_SVE_VVV_BHS_HSD): New variant set.
1537 (OP_SVE_VV_BHS_HSD): New variant set.
1538 (OP_SVE_VVV_SD): New variant set.
1539 (OP_SVE_VVU_BHS_HSD): New variant set.
1540 (OP_SVE_VZVV_SD): New variant set.
1541 (OP_SVE_VZVV_BH): New variant set.
1542 (OP_SVE_VZV_SD): New variant set.
1543 (aarch64_opcode_table): Add sve2 instructions.
1544
28ed815a
MM		 15452019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1546
1547 * aarch64-asm-2.c: Regenerated.
1548 * aarch64-dis-2.c: Regenerated.
1549 * aarch64-opc-2.c: Regenerated.
1550 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1551 for SVE_SHLIMM_UNPRED_22.
1552 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1553 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1554 operand.
1555
fd1dc4a0
MM		 15562019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1557
1558 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1559 sve_size_tsz_bhs iclass encode.
1560 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1561 sve_size_tsz_bhs iclass decode.
1562
31e36ab3
MM		 15632019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1564
1565 * aarch64-asm-2.c: Regenerated.
1566 * aarch64-dis-2.c: Regenerated.
1567 * aarch64-opc-2.c: Regenerated.
1568 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1569 for SVE_Zm4_11_INDEX.
1570 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1571 (fields): Handle SVE_i2h field.
1572 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1573 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1574
1be5f94f
MM		 15752019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1576
1577 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1578 sve_shift_tsz_bhsd iclass encode.
1579 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1580 sve_shift_tsz_bhsd iclass decode.
1581
3c17238b
MM		 15822019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1583
1584 * aarch64-asm-2.c: Regenerated.
1585 * aarch64-dis-2.c: Regenerated.
1586 * aarch64-opc-2.c: Regenerated.
1587 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1588 (aarch64_encode_variant_using_iclass): Handle
1589 sve_shift_tsz_hsd iclass encode.
1590 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1591 sve_shift_tsz_hsd iclass decode.
1592 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1593 for SVE_SHRIMM_UNPRED_22.
1594 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1595 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1596 operand.
1597
cd50a87a
MM		 15982019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1599
1600 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1601 sve_size_013 iclass encode.
1602 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1603 sve_size_013 iclass decode.
1604
3c705960
MM		 16052019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1606
1607 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1608 sve_size_bh iclass encode.
1609 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1610 sve_size_bh iclass decode.
1611
0a57e14f
MM		 16122019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1613
1614 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1615 sve_size_sd2 iclass encode.
1616 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1617 sve_size_sd2 iclass decode.
1618 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1619 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1620
c469c864
MM		 16212019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1622
1623 * aarch64-asm-2.c: Regenerated.
1624 * aarch64-dis-2.c: Regenerated.
1625 * aarch64-opc-2.c: Regenerated.
1626 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1627 for SVE_ADDR_ZX.
1628 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1629 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1630
116adc27
MM		 16312019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1632
1633 * aarch64-asm-2.c: Regenerated.
1634 * aarch64-dis-2.c: Regenerated.
1635 * aarch64-opc-2.c: Regenerated.
1636 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1637 for SVE_Zm3_11_INDEX.
1638 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1639 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1640 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1641 fields.
1642 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1643
3bd82c86
MM		 16442019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1645
1646 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1647 sve_size_hsd2 iclass encode.
1648 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1649 sve_size_hsd2 iclass decode.
1650 * aarch64-opc.c (fields): Handle SVE_size field.
1651 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1652
adccc507
MM		 16532019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1654
1655 * aarch64-asm-2.c: Regenerated.
1656 * aarch64-dis-2.c: Regenerated.
1657 * aarch64-opc-2.c: Regenerated.
1658 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1659 for SVE_IMM_ROT3.
1660 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1661 (fields): Handle SVE_rot3 field.
1662 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1663 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1664
5cd99750
MM		 16652019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1666
1667 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1668 instructions.
1669
7ce2460a
MM		 16702019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1671
1672 * aarch64-tbl.h
1673 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1674 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1675 aarch64_feature_sve2bitperm): New feature sets.
1676 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1677 for feature set addresses.
1678 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1679 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1680
41cee089
FS		 16812019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1682 Faraz Shahbazker <fshahbazker@wavecomp.com>
1683
1684 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1685 argument and set ASE_EVA_R6 appropriately.
1686 (set_default_mips_dis_options): Pass ISA to above.
1687 (parse_mips_dis_option): Likewise.
1688 * mips-opc.c (EVAR6): New macro.
1689 (mips_builtin_opcodes): Add llwpe, scwpe.
1690
b83b4b13
SD		 16912019-05-01 Sudakshina Das <sudi.das@arm.com>
1692
1693 * aarch64-asm-2.c: Regenerated.
1694 * aarch64-dis-2.c: Regenerated.
1695 * aarch64-opc-2.c: Regenerated.
1696 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1697 AARCH64_OPND_TME_UIMM16.
1698 (aarch64_print_operand): Likewise.
1699 * aarch64-tbl.h (QL_IMM_NIL): New.
1700 (TME): New.
1701 (_TME_INSN): New.
1702 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1703
4a90ce95
JD		 17042019-04-29 John Darrington <john@darrington.wattle.id.au>
1705
1706 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1707
a45328b9
AB		 17082019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1709 Faraz Shahbazker <fshahbazker@wavecomp.com>
1710
1711 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1712
d10be0cb
JD		 17132019-04-24 John Darrington <john@darrington.wattle.id.au>
1714
1715 * s12z-opc.h: Add extern "C" bracketing to help
1716 users who wish to use this interface in c++ code.
1717
a679f24e
JD		 17182019-04-24 John Darrington <john@darrington.wattle.id.au>
1719
1720 * s12z-opc.c (bm_decode): Handle bit map operations with the
1721 "reserved0" mode.
1722
32c36c3c
AV		 17232019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1724
1725 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1726 specifier. Add entries for VLDR and VSTR of system registers.
1727 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1728 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1729 of %J and %K format specifier.
1730
efd6b359
AV		 17312019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1732
1733 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1734 Add new entries for VSCCLRM instruction.
1735 (print_insn_coprocessor): Handle new %C format control code.
1736
6b0dd094
AV		 17372019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1738
1739 * arm-dis.c (enum isa): New enum.
1740 (struct sopcode32): New structure.
1741 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1742 set isa field of all current entries to ANY.
1743 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1744 Only match an entry if its isa field allows the current mode.
1745
4b5a202f
AV		 17462019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1747
1748 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1749 CLRM.
1750 (print_insn_thumb32): Add logic to print %n CLRM register list.
1751
60f993ce
AV		 17522019-04-15 Sudakshina Das <sudi.das@arm.com>
1753
1754 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1755 and %Q patterns.
1756
f6b2b12d
AV		 17572019-04-15 Sudakshina Das <sudi.das@arm.com>
1758
1759 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1760 (print_insn_thumb32): Edit the switch case for %Z.
1761
1889da70
AV		 17622019-04-15 Sudakshina Das <sudi.das@arm.com>
1763
1764 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1765
65d1bc05
AV		 17662019-04-15 Sudakshina Das <sudi.das@arm.com>
1767
1768 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1769
1caf72a5
AV		 17702019-04-15 Sudakshina Das <sudi.das@arm.com>
1771
1772 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1773
f1c7f421
AV		 17742019-04-15 Sudakshina Das <sudi.das@arm.com>
1775
1776 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1777 Arm register with r13 and r15 unpredictable.
1778 (thumb32_opcodes): New instructions for bfx and bflx.
1779
4389b29a
AV		 17802019-04-15 Sudakshina Das <sudi.das@arm.com>
1781
1782 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1783
e5d6e09e
AV		 17842019-04-15 Sudakshina Das <sudi.das@arm.com>
1785
1786 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1787
e12437dc
AV		 17882019-04-15 Sudakshina Das <sudi.das@arm.com>
1789
1790 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1791
031254f2
AV		 17922019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1793
1794 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1795
e5a557ac
JD		 17962019-04-12 John Darrington <john@darrington.wattle.id.au>
1797
1798 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1799 "optr". ("operator" is a reserved word in c++).
1800
bd7ceb8d
SD		 18012019-04-11 Sudakshina Das <sudi.das@arm.com>
1802
1803 * aarch64-opc.c (aarch64_print_operand): Add case for
1804 AARCH64_OPND_Rt_SP.
1805 (verify_constraints): Likewise.
1806 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1807 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1808 to accept Rt|SP as first operand.
1809 (AARCH64_OPERANDS): Add new Rt_SP.
1810 * aarch64-asm-2.c: Regenerated.
1811 * aarch64-dis-2.c: Regenerated.
1812 * aarch64-opc-2.c: Regenerated.
1813
e54010f1
SD		 18142019-04-11 Sudakshina Das <sudi.das@arm.com>
1815
1816 * aarch64-asm-2.c: Regenerated.
1817 * aarch64-dis-2.c: Likewise.
1818 * aarch64-opc-2.c: Likewise.
1819 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1820
7e96e219
RS		 18212019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1822
1823 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1824
6f2791d5
L		 18252019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1826
1827 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1828 * i386-init.h: Regenerated.
1829
e392bad3
AM		 18302019-04-07 Alan Modra <amodra@gmail.com>
1831
1832 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1833 op_separator to control printing of spaces, comma and parens
1834 rather than need_comma, need_paren and spaces vars.
1835
dffaa15c
AM		 18362019-04-07 Alan Modra <amodra@gmail.com>
1837
1838 PR 24421
1839 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1840 (print_insn_neon, print_insn_arm): Likewise.
1841
d6aab7a1
XG		 18422019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1843
1844 * i386-dis-evex.h (evex_table): Updated to support BF16
1845 instructions.
1846 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1847 and EVEX_W_0F3872_P_3.
1848 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1849 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1850 * i386-opc.h (enum): Add CpuAVX512_BF16.
1851 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1852 * i386-opc.tbl: Add AVX512 BF16 instructions.
1853 * i386-init.h: Regenerated.
1854 * i386-tbl.h: Likewise.
1855
66e85460
AM		 18562019-04-05 Alan Modra <amodra@gmail.com>
1857
1858 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1859 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1860 to favour printing of "-" branch hint when using the "y" bit.
1861 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1862
c2b1c275
AM		 18632019-04-05 Alan Modra <amodra@gmail.com>
1864
1865 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1866 opcode until first operand is output.
1867
aae9718e
PB		 18682019-04-04 Peter Bergner <bergner@linux.ibm.com>
1869
1870 PR gas/24349
1871 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1872 (valid_bo_post_v2): Add support for 'at' branch hints.
1873 (insert_bo): Only error on branch on ctr.
1874 (get_bo_hint_mask): New function.
1875 (insert_boe): Add new 'branch_taken' formal argument. Add support
1876 for inserting 'at' branch hints.
1877 (extract_boe): Add new 'branch_taken' formal argument. Add support
1878 for extracting 'at' branch hints.
1879 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1880 (BOE): Delete operand.
1881 (BOM, BOP): New operands.
1882 (RM): Update value.
1883 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1884 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1885 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1886 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1887 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1888 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1889 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1890 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1891 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1892 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1893 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1894 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1895 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1896 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1897 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1898 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1899 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1900 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1901 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1902 bttarl+>: New extended mnemonics.
1903
96a86c01
AM		 19042019-03-28 Alan Modra <amodra@gmail.com>
1905
1906 PR 24390
1907 * ppc-opc.c (BTF): Define.
1908 (powerpc_opcodes): Use for mtfsb*.
1909 * ppc-dis.c (print_insn_powerpc): Print fields with both
1910 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1911
796d6298
TC		 19122019-03-25 Tamar Christina <tamar.christina@arm.com>
1913
1914 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1915 (mapping_symbol_for_insn): Implement new algorithm.
1916 (print_insn): Remove duplicate code.
1917
60df3720
TC		 19182019-03-25 Tamar Christina <tamar.christina@arm.com>
1919
1920 * aarch64-dis.c (print_insn_aarch64):
1921 Implement override.
1922
51457761
TC		 19232019-03-25 Tamar Christina <tamar.christina@arm.com>
1924
1925 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1926 order.
1927
53b2f36b
TC		 19282019-03-25 Tamar Christina <tamar.christina@arm.com>
1929
1930 * aarch64-dis.c (last_stop_offset): New.
1931 (print_insn_aarch64): Use stop_offset.
1932
89199bb5
L		 19332019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1934
1935 PR gas/24359
1936 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1937 CPU_ANY_AVX2_FLAGS.
1938 * i386-init.h: Regenerated.
1939
97ed31ae
L		 19402019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1941
1942 PR gas/24348
1943 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1944 vmovdqu16, vmovdqu32 and vmovdqu64.
1945 * i386-tbl.h: Regenerated.
1946
0919bfe9
AK		 19472019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1948
1949 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1950 from vstrszb, vstrszh, and vstrszf.
1951
19522019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1953
1954 * s390-opc.txt: Add instruction descriptions.
1955
21820ebe
JW		 19562019-02-08 Jim Wilson <jimw@sifive.com>
1957
1958 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1959 <bne>: Likewise.
1960
f7dd2fb2
TC		 19612019-02-07 Tamar Christina <tamar.christina@arm.com>
1962
1963 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1964
6456d318
TC		 19652019-02-07 Tamar Christina <tamar.christina@arm.com>
1966
1967 PR binutils/23212
1968 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1969 * aarch64-opc.c (verify_elem_sd): New.
1970 (fields): Add FLD_sz entr.
1971 * aarch64-tbl.h (_SIMD_INSN): New.
1972 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1973 fmulx scalar and vector by element isns.
1974
4a83b610
NC		 19752019-02-07 Nick Clifton <nickc@redhat.com>
1976
1977 * po/sv.po: Updated Swedish translation.
1978
fc60b8c8
AK		 19792019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1980
1981 * s390-mkopc.c (main): Accept arch13 as cpu string.
1982 * s390-opc.c: Add new instruction formats and instruction opcode
1983 masks.
1984 * s390-opc.txt: Add new arch13 instructions.
1985
e10620d3
TC		 19862019-01-25 Sudakshina Das <sudi.das@arm.com>
1987
1988 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1989 (aarch64_opcode): Change encoding for stg, stzg
1990 st2g and st2zg.
1991 * aarch64-asm-2.c: Regenerated.
1992 * aarch64-dis-2.c: Regenerated.
1993 * aarch64-opc-2.c: Regenerated.
1994
20a4ca55
SD		 19952019-01-25 Sudakshina Das <sudi.das@arm.com>
1996
1997 * aarch64-asm-2.c: Regenerated.
1998 * aarch64-dis-2.c: Likewise.
1999 * aarch64-opc-2.c: Likewise.
2000 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2001
550fd7bf
SD		 20022019-01-25 Sudakshina Das <sudi.das@arm.com>
2003 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2004
2005 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2006 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2007 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2008 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2009 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2010 case for ldstgv_indexed.
2011 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2012 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2013 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2014 * aarch64-asm-2.c: Regenerated.
2015 * aarch64-dis-2.c: Regenerated.
2016 * aarch64-opc-2.c: Regenerated.
2017
d9938630
NC		 20182019-01-23 Nick Clifton <nickc@redhat.com>
2019
2020 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2021
375cd423
NC		 20222019-01-21 Nick Clifton <nickc@redhat.com>
2023
2024 * po/de.po: Updated German translation.
2025 * po/uk.po: Updated Ukranian translation.
2026
57299f48
CX		 20272019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2028 * mips-dis.c (mips_arch_choices): Fix typo in
2029 gs464, gs464e and gs264e descriptors.
2030
f48dfe41
NC		 20312019-01-19 Nick Clifton <nickc@redhat.com>
2032
2033 * configure: Regenerate.
2034 * po/opcodes.pot: Regenerate.
2035
f974f26c
NC		 20362018-06-24 Nick Clifton <nickc@redhat.com>
2037
2038 2.32 branch created.
2039
39f286cd
JD		 20402019-01-09 John Darrington <john@darrington.wattle.id.au>
2041
448b8ca8
JD		 2042 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2043 if it is null.
2044 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 2045 zero.
2046
3107326d
AP		 20472019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2048
2049 * configure: Regenerate.
2050
7e9ca91e
AM		 20512019-01-07 Alan Modra <amodra@gmail.com>
2052
2053 * configure: Regenerate.
2054 * po/POTFILES.in: Regenerate.
2055
ef1ad42b
JD		 20562019-01-03 John Darrington <john@darrington.wattle.id.au>
2057
2058 * s12z-opc.c: New file.
2059 * s12z-opc.h: New file.
2060 * s12z-dis.c: Removed all code not directly related to display
2061 of instructions. Used the interface provided by the new files
2062 instead.
2063 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 2064 * Makefile.in: Regenerate.
ef1ad42b 2065 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 2066 * configure: Regenerate.
ef1ad42b 2067
82704155
AM		 20682019-01-01 Alan Modra <amodra@gmail.com>
2069
2070 Update year range in copyright notice of all files.
2071
d5c04e1b 2072For older changes see ChangeLog-2018
3499769a 2073\f
d5c04e1b 2074Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 2075
2076Copying and distribution of this file, with or without modification,
2077are permitted in any medium without royalty provided the copyright
2078notice and this notice are preserved.
2079
2080Local Variables:
2081mode: change-log
2082left-margin: 8
2083fill-column: 74
2084version-control: never
2085End:
GDB Binutils - Deliverables
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