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x86: use encoding_length() also elsewhere
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
36cc073e
JB		 12019-07-01 Jan Beulich <jbeulich@suse.com>
2
3 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
4 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
5 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
6 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
7 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
8 EVEX_W_0F11_P_3_M_1): Delete.
9 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
10 EVEX_W_0F11_P_3): New.
11 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
12 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
13 MOD_EVEX_0F11_PREFIX_3 table entries.
14 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
15 PREFIX_EVEX_0F11 table entries.
16 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
17 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
18 EVEX_W_0F11_P_3_M_{0,1} table entries.
19
219920a7
JB		 202019-07-01 Jan Beulich <jbeulich@suse.com>
21
22 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
23 Delete.
24
e395f487
L		 252019-06-27 H.J. Lu <hongjiu.lu@intel.com>
26
27 PR binutils/24719
28 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
29 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
30 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
31 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
32 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
33 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
34 EVEX_LEN_0F38C7_R_6_P_2_W_1.
35 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
36 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
37 PREFIX_EVEX_0F38C6_REG_6 entries.
38 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
39 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
40 EVEX_W_0F38C7_R_6_P_2 entries.
41 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
42 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
43 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
44 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
45 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
46 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
47 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
48
2b7bcc87
JB		 492019-06-27 Jan Beulich <jbeulich@suse.com>
50
51 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
52 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
53 VEX_LEN_0F2D_P_3): Delete.
54 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
55 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
56 (prefix_table): ... here.
57
c1dc7af5
JB		 582019-06-27 Jan Beulich <jbeulich@suse.com>
59
60 * i386-dis.c (Iq): Delete.
61 (Id): New.
62 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
63 TBM insns.
64 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
65 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
66 (OP_E_memory): Also honor needindex when deciding whether an
67 address size prefix needs printing.
68 (OP_I): Remove handling of q_mode. Add handling of d_mode.
69
d7560e2d
JW		 702019-06-26 Jim Wilson <jimw@sifive.com>
71
72 PR binutils/24739
73 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
74 Set info->display_endian to info->endian_code.
75
2c703856
JB		 762019-06-25 Jan Beulich <jbeulich@suse.com>
77
78 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
79 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
80 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
81 OPERAND_TYPE_ACC64 entries.
82 * i386-init.h: Re-generate.
83
54fbadc0
JB		 842019-06-25 Jan Beulich <jbeulich@suse.com>
85
86 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
87 Delete.
88 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
89 of dqa_mode.
90 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
91 entries here.
92 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
93 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
94
a280ab8e
JB		 952019-06-25 Jan Beulich <jbeulich@suse.com>
96
97 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
98 variables.
99
e1a1babd
JB		 1002019-06-25 Jan Beulich <jbeulich@suse.com>
101
102 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
103 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
104 movnti.
d7560e2d 105 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 106 * i386-tbl.h: Re-generate.
107
b8364fa7
JB		 1082019-06-25 Jan Beulich <jbeulich@suse.com>
109
110 * i386-opc.tbl (and): Mark Imm8S form for optimization.
111 * i386-tbl.h: Re-generate.
112
ad692897
L		 1132019-06-21 H.J. Lu <hongjiu.lu@intel.com>
114
115 * i386-dis-evex.h: Break into ...
116 * i386-dis-evex-len.h: New file.
117 * i386-dis-evex-mod.h: Likewise.
118 * i386-dis-evex-prefix.h: Likewise.
119 * i386-dis-evex-reg.h: Likewise.
120 * i386-dis-evex-w.h: Likewise.
121 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
122 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
123 i386-dis-evex-mod.h.
124
f0a6222e
L		 1252019-06-19 H.J. Lu <hongjiu.lu@intel.com>
126
127 PR binutils/24700
128 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
129 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
130 EVEX_W_0F385B_P_2.
131 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
132 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
133 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
134 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
135 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
136 EVEX_LEN_0F385B_P_2_W_1.
137 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
138 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
139 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
140 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
141 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
142 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
143 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
144 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
145 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
146 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
147
6e1c90b7
L		 1482019-06-17 H.J. Lu <hongjiu.lu@intel.com>
149
150 PR binutils/24691
151 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
152 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
153 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
154 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
155 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
156 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
157 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
158 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
159 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
160 EVEX_LEN_0F3A43_P_2_W_1.
161 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
162 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
163 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
164 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
165 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
166 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
167 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
168 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
169 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
170 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
171 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
172 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
173
bcc5a6eb
NC		 1742019-06-14 Nick Clifton <nickc@redhat.com>
175
176 * po/fr.po; Updated French translation.
177
e4c4ac46
SH		 1782019-06-13 Stafford Horne <shorne@gmail.com>
179
180 * or1k-asm.c: Regenerated.
181 * or1k-desc.c: Regenerated.
182 * or1k-desc.h: Regenerated.
183 * or1k-dis.c: Regenerated.
184 * or1k-ibld.c: Regenerated.
185 * or1k-opc.c: Regenerated.
186 * or1k-opc.h: Regenerated.
187 * or1k-opinst.c: Regenerated.
188
a0e44ef5
PB		 1892019-06-12 Peter Bergner <bergner@linux.ibm.com>
190
191 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
192
12efd68d
L		 1932019-06-05 H.J. Lu <hongjiu.lu@intel.com>
194
195 PR binutils/24633
196 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
197 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
198 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
199 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
200 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
201 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
202 EVEX_LEN_0F3A1B_P_2_W_1.
203 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
204 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
205 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
206 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
207 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
208 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
209 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
210 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
211
63c6fc6c
L		 2122019-06-04 H.J. Lu <hongjiu.lu@intel.com>
213
214 PR binutils/24626
215 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
216 EVEX.vvvv when disassembling VEX and EVEX instructions.
217 (OP_VEX): Set vex.register_specifier to 0 after readding
218 vex.register_specifier.
219 (OP_Vex_2src_1): Likewise.
220 (OP_Vex_2src_2): Likewise.
221 (OP_LWP_E): Likewise.
222 (OP_EX_Vex): Don't check vex.register_specifier.
223 (OP_XMM_Vex): Likewise.
224
9186c494
L		 2252019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
226 Lili Cui <lili.cui@intel.com>
227
228 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
229 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
230 instructions.
231 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
232 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
233 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
234 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
235 (i386_cpu_flags): Add cpuavx512_vp2intersect.
236 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
237 * i386-init.h: Regenerated.
238 * i386-tbl.h: Likewise.
239
5d79adc4
L		 2402019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
241 Lili Cui <lili.cui@intel.com>
242
243 * doc/c-i386.texi: Document enqcmd.
244 * testsuite/gas/i386/enqcmd-intel.d: New file.
245 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
246 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
247 * testsuite/gas/i386/enqcmd.d: Likewise.
248 * testsuite/gas/i386/enqcmd.s: Likewise.
249 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
250 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
251 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
252 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
253 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
254 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
255 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
256 and x86-64-enqcmd.
257
a9d96ab9
AH		 2582019-06-04 Alan Hayward <alan.hayward@arm.com>
259
260 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
261
4f6d070a
AM		 2622019-06-03 Alan Modra <amodra@gmail.com>
263
264 * ppc-dis.c (prefix_opcd_indices): Correct size.
265
a2f4b66c
L		 2662019-05-28 H.J. Lu <hongjiu.lu@intel.com>
267
268 PR gas/24625
269 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
270 Disp8ShiftVL.
271 * i386-tbl.h: Regenerated.
272
405b5bd8
AM		 2732019-05-24 Alan Modra <amodra@gmail.com>
274
275 * po/POTFILES.in: Regenerate.
276
8acf1435
PB		 2772019-05-24 Peter Bergner <bergner@linux.ibm.com>
278 Alan Modra <amodra@gmail.com>
279
280 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
281 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
282 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
283 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
284 XTOP>): Define and add entries.
285 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
286 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
287 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
288 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
289
dd7efa79
PB		 2902019-05-24 Peter Bergner <bergner@linux.ibm.com>
291 Alan Modra <amodra@gmail.com>
292
293 * ppc-dis.c (ppc_opts): Add "future" entry.
294 (PREFIX_OPCD_SEGS): Define.
295 (prefix_opcd_indices): New array.
296 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
297 (lookup_prefix): New function.
298 (print_insn_powerpc): Handle 64-bit prefix instructions.
299 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
300 (PMRR, POWERXX): Define.
301 (prefix_opcodes): New instruction table.
302 (prefix_num_opcodes): New constant.
303
79472b45
JM		 3042019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
305
306 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
307 * configure: Regenerated.
308 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
309 and cpu/bpf.opc.
310 (HFILES): Add bpf-desc.h and bpf-opc.h.
311 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
312 bpf-ibld.c and bpf-opc.c.
313 (BPF_DEPS): Define.
314 * Makefile.in: Regenerated.
315 * disassemble.c (ARCH_bpf): Define.
316 (disassembler): Add case for bfd_arch_bpf.
317 (disassemble_init_for_target): Likewise.
318 (enum epbf_isa_attr): Define.
319 * disassemble.h: extern print_insn_bpf.
320 * bpf-asm.c: Generated.
321 * bpf-opc.h: Likewise.
322 * bpf-opc.c: Likewise.
323 * bpf-ibld.c: Likewise.
324 * bpf-dis.c: Likewise.
325 * bpf-desc.h: Likewise.
326 * bpf-desc.c: Likewise.
327
ba6cd17f
SD		 3282019-05-21 Sudakshina Das <sudi.das@arm.com>
329
330 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
331 and VMSR with the new operands.
332
e39c1607
SD		 3332019-05-21 Sudakshina Das <sudi.das@arm.com>
334
335 * arm-dis.c (enum mve_instructions): New enum
336 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
337 and cneg.
338 (mve_opcodes): New instructions as above.
339 (is_mve_encoding_conflict): Add cases for csinc, csinv,
340 csneg and csel.
341 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
342
23d00a41
SD		 3432019-05-21 Sudakshina Das <sudi.das@arm.com>
344
345 * arm-dis.c (emun mve_instructions): Updated for new instructions.
346 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
347 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
348 uqshl, urshrl and urshr.
349 (is_mve_okay_in_it): Add new instructions to TRUE list.
350 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
351 (print_insn_mve): Updated to accept new %j,
352 %<bitfield>m and %<bitfield>n patterns.
353
cd4797ee
FS		 3542019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
355
356 * mips-opc.c (mips_builtin_opcodes): Change source register
357 constraint for DAUI.
358
999b073b
NC		 3592019-05-20 Nick Clifton <nickc@redhat.com>
360
361 * po/fr.po: Updated French translation.
362
14b456f2
AV		 3632019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
364 Michael Collison <michael.collison@arm.com>
365
366 * arm-dis.c (thumb32_opcodes): Add new instructions.
367 (enum mve_instructions): Likewise.
368 (enum mve_undefined): Add new reasons.
369 (is_mve_encoding_conflict): Handle new instructions.
370 (is_mve_undefined): Likewise.
371 (is_mve_unpredictable): Likewise.
372 (print_mve_undefined): Likewise.
373 (print_mve_size): Likewise.
374
f49bb598
AV		 3752019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
376 Michael Collison <michael.collison@arm.com>
377
378 * arm-dis.c (thumb32_opcodes): Add new instructions.
379 (enum mve_instructions): Likewise.
380 (is_mve_encoding_conflict): Handle new instructions.
381 (is_mve_undefined): Likewise.
382 (is_mve_unpredictable): Likewise.
383 (print_mve_size): Likewise.
384
56858bea
AV		 3852019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
386 Michael Collison <michael.collison@arm.com>
387
388 * arm-dis.c (thumb32_opcodes): Add new instructions.
389 (enum mve_instructions): Likewise.
390 (is_mve_encoding_conflict): Likewise.
391 (is_mve_unpredictable): Likewise.
392 (print_mve_size): Likewise.
393
e523f101
AV		 3942019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
395 Michael Collison <michael.collison@arm.com>
396
397 * arm-dis.c (thumb32_opcodes): Add new instructions.
398 (enum mve_instructions): Likewise.
399 (is_mve_encoding_conflict): Handle new instructions.
400 (is_mve_undefined): Likewise.
401 (is_mve_unpredictable): Likewise.
402 (print_mve_size): Likewise.
403
66dcaa5d
AV		 4042019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
405 Michael Collison <michael.collison@arm.com>
406
407 * arm-dis.c (thumb32_opcodes): Add new instructions.
408 (enum mve_instructions): Likewise.
409 (is_mve_encoding_conflict): Handle new instructions.
410 (is_mve_undefined): Likewise.
411 (is_mve_unpredictable): Likewise.
412 (print_mve_size): Likewise.
413 (print_insn_mve): Likewise.
414
d052b9b7
AV		 4152019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
416 Michael Collison <michael.collison@arm.com>
417
418 * arm-dis.c (thumb32_opcodes): Add new instructions.
419 (print_insn_thumb32): Handle new instructions.
420
ed63aa17
AV		 4212019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
422 Michael Collison <michael.collison@arm.com>
423
424 * arm-dis.c (enum mve_instructions): Add new instructions.
425 (enum mve_undefined): Add new reasons.
426 (is_mve_encoding_conflict): Handle new instructions.
427 (is_mve_undefined): Likewise.
428 (is_mve_unpredictable): Likewise.
429 (print_mve_undefined): Likewise.
430 (print_mve_size): Likewise.
431 (print_mve_shift_n): Likewise.
432 (print_insn_mve): Likewise.
433
897b9bbc
AV		 4342019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
435 Michael Collison <michael.collison@arm.com>
436
437 * arm-dis.c (enum mve_instructions): Add new instructions.
438 (is_mve_encoding_conflict): Handle new instructions.
439 (is_mve_unpredictable): Likewise.
440 (print_mve_rotate): Likewise.
441 (print_mve_size): Likewise.
442 (print_insn_mve): Likewise.
443
1c8f2df8
AV		 4442019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
445 Michael Collison <michael.collison@arm.com>
446
447 * arm-dis.c (enum mve_instructions): Add new instructions.
448 (is_mve_encoding_conflict): Handle new instructions.
449 (is_mve_unpredictable): Likewise.
450 (print_mve_size): Likewise.
451 (print_insn_mve): Likewise.
452
d3b63143
AV		 4532019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
454 Michael Collison <michael.collison@arm.com>
455
456 * arm-dis.c (enum mve_instructions): Add new instructions.
457 (enum mve_undefined): Add new reasons.
458 (is_mve_encoding_conflict): Handle new instructions.
459 (is_mve_undefined): Likewise.
460 (is_mve_unpredictable): Likewise.
461 (print_mve_undefined): Likewise.
462 (print_mve_size): Likewise.
463 (print_insn_mve): Likewise.
464
14925797
AV		 4652019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
466 Michael Collison <michael.collison@arm.com>
467
468 * arm-dis.c (enum mve_instructions): Add new instructions.
469 (is_mve_encoding_conflict): Handle new instructions.
470 (is_mve_undefined): Likewise.
471 (is_mve_unpredictable): Likewise.
472 (print_mve_size): Likewise.
473 (print_insn_mve): Likewise.
474
c507f10b
AV		 4752019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
476 Michael Collison <michael.collison@arm.com>
477
478 * arm-dis.c (enum mve_instructions): Add new instructions.
479 (enum mve_unpredictable): Add new reasons.
480 (enum mve_undefined): Likewise.
481 (is_mve_okay_in_it): Handle new isntructions.
482 (is_mve_encoding_conflict): Likewise.
483 (is_mve_undefined): Likewise.
484 (is_mve_unpredictable): Likewise.
485 (print_mve_vmov_index): Likewise.
486 (print_simd_imm8): Likewise.
487 (print_mve_undefined): Likewise.
488 (print_mve_unpredictable): Likewise.
489 (print_mve_size): Likewise.
490 (print_insn_mve): Likewise.
491
bf0b396d
AV		 4922019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
493 Michael Collison <michael.collison@arm.com>
494
495 * arm-dis.c (enum mve_instructions): Add new instructions.
496 (enum mve_unpredictable): Add new reasons.
497 (enum mve_undefined): Likewise.
498 (is_mve_encoding_conflict): Handle new instructions.
499 (is_mve_undefined): Likewise.
500 (is_mve_unpredictable): Likewise.
501 (print_mve_undefined): Likewise.
502 (print_mve_unpredictable): Likewise.
503 (print_mve_rounding_mode): Likewise.
504 (print_mve_vcvt_size): Likewise.
505 (print_mve_size): Likewise.
506 (print_insn_mve): Likewise.
507
ef1576a1
AV		 5082019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
509 Michael Collison <michael.collison@arm.com>
510
511 * arm-dis.c (enum mve_instructions): Add new instructions.
512 (enum mve_unpredictable): Add new reasons.
513 (enum mve_undefined): Likewise.
514 (is_mve_undefined): Handle new instructions.
515 (is_mve_unpredictable): Likewise.
516 (print_mve_undefined): Likewise.
517 (print_mve_unpredictable): Likewise.
518 (print_mve_size): Likewise.
519 (print_insn_mve): Likewise.
520
aef6d006
AV		 5212019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
522 Michael Collison <michael.collison@arm.com>
523
524 * arm-dis.c (enum mve_instructions): Add new instructions.
525 (enum mve_undefined): Add new reasons.
526 (insns): Add new instructions.
527 (is_mve_encoding_conflict):
528 (print_mve_vld_str_addr): New print function.
529 (is_mve_undefined): Handle new instructions.
530 (is_mve_unpredictable): Likewise.
531 (print_mve_undefined): Likewise.
532 (print_mve_size): Likewise.
533 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
534 (print_insn_mve): Handle new operands.
535
04d54ace
AV		 5362019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
537 Michael Collison <michael.collison@arm.com>
538
539 * arm-dis.c (enum mve_instructions): Add new instructions.
540 (enum mve_unpredictable): Add new reasons.
541 (is_mve_encoding_conflict): Handle new instructions.
542 (is_mve_unpredictable): Likewise.
543 (mve_opcodes): Add new instructions.
544 (print_mve_unpredictable): Handle new reasons.
545 (print_mve_register_blocks): New print function.
546 (print_mve_size): Handle new instructions.
547 (print_insn_mve): Likewise.
548
9743db03
AV		 5492019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
550 Michael Collison <michael.collison@arm.com>
551
552 * arm-dis.c (enum mve_instructions): Add new instructions.
553 (enum mve_unpredictable): Add new reasons.
554 (enum mve_undefined): Likewise.
555 (is_mve_encoding_conflict): Handle new instructions.
556 (is_mve_undefined): Likewise.
557 (is_mve_unpredictable): Likewise.
558 (coprocessor_opcodes): Move NEON VDUP from here...
559 (neon_opcodes): ... to here.
560 (mve_opcodes): Add new instructions.
561 (print_mve_undefined): Handle new reasons.
562 (print_mve_unpredictable): Likewise.
563 (print_mve_size): Handle new instructions.
564 (print_insn_neon): Handle vdup.
565 (print_insn_mve): Handle new operands.
566
143275ea
AV		 5672019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
568 Michael Collison <michael.collison@arm.com>
569
570 * arm-dis.c (enum mve_instructions): Add new instructions.
571 (enum mve_unpredictable): Add new values.
572 (mve_opcodes): Add new instructions.
573 (vec_condnames): New array with vector conditions.
574 (mve_predicatenames): New array with predicate suffixes.
575 (mve_vec_sizename): New array with vector sizes.
576 (enum vpt_pred_state): New enum with vector predication states.
577 (struct vpt_block): New struct type for vpt blocks.
578 (vpt_block_state): Global struct to keep track of state.
579 (mve_extract_pred_mask): New helper function.
580 (num_instructions_vpt_block): Likewise.
581 (mark_outside_vpt_block): Likewise.
582 (mark_inside_vpt_block): Likewise.
583 (invert_next_predicate_state): Likewise.
584 (update_next_predicate_state): Likewise.
585 (update_vpt_block_state): Likewise.
586 (is_vpt_instruction): Likewise.
587 (is_mve_encoding_conflict): Add entries for new instructions.
588 (is_mve_unpredictable): Likewise.
589 (print_mve_unpredictable): Handle new cases.
590 (print_instruction_predicate): Likewise.
591 (print_mve_size): New function.
592 (print_vec_condition): New function.
593 (print_insn_mve): Handle vpt blocks and new print operands.
594
f08d8ce3
AV		 5952019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
596
597 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
598 8, 14 and 15 for Armv8.1-M Mainline.
599
73cd51e5
AV		 6002019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
601 Michael Collison <michael.collison@arm.com>
602
603 * arm-dis.c (enum mve_instructions): New enum.
604 (enum mve_unpredictable): Likewise.
605 (enum mve_undefined): Likewise.
606 (struct mopcode32): New struct.
607 (is_mve_okay_in_it): New function.
608 (is_mve_architecture): Likewise.
609 (arm_decode_field): Likewise.
610 (arm_decode_field_multiple): Likewise.
611 (is_mve_encoding_conflict): Likewise.
612 (is_mve_undefined): Likewise.
613 (is_mve_unpredictable): Likewise.
614 (print_mve_undefined): Likewise.
615 (print_mve_unpredictable): Likewise.
616 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
617 (print_insn_mve): New function.
618 (print_insn_thumb32): Handle MVE architecture.
619 (select_arm_features): Force thumb for Armv8.1-m Mainline.
620
3076e594
NC		 6212019-05-10 Nick Clifton <nickc@redhat.com>
622
623 PR 24538
624 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
625 end of the table prematurely.
626
387e7624
FS		 6272019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
628
629 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
630 macros for R6.
631
0067be51
AM		 6322019-05-11 Alan Modra <amodra@gmail.com>
633
634 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
635 when -Mraw is in effect.
636
42e6288f
MM		 6372019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
638
639 * aarch64-dis-2.c: Regenerate.
640 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
641 (OP_SVE_BBB): New variant set.
642 (OP_SVE_DDDD): New variant set.
643 (OP_SVE_HHH): New variant set.
644 (OP_SVE_HHHU): New variant set.
645 (OP_SVE_SSS): New variant set.
646 (OP_SVE_SSSU): New variant set.
647 (OP_SVE_SHH): New variant set.
648 (OP_SVE_SBBU): New variant set.
649 (OP_SVE_DSS): New variant set.
650 (OP_SVE_DHHU): New variant set.
651 (OP_SVE_VMV_HSD_BHS): New variant set.
652 (OP_SVE_VVU_HSD_BHS): New variant set.
653 (OP_SVE_VVVU_SD_BH): New variant set.
654 (OP_SVE_VVVU_BHSD): New variant set.
655 (OP_SVE_VVV_QHD_DBS): New variant set.
656 (OP_SVE_VVV_HSD_BHS): New variant set.
657 (OP_SVE_VVV_HSD_BHS2): New variant set.
658 (OP_SVE_VVV_BHS_HSD): New variant set.
659 (OP_SVE_VV_BHS_HSD): New variant set.
660 (OP_SVE_VVV_SD): New variant set.
661 (OP_SVE_VVU_BHS_HSD): New variant set.
662 (OP_SVE_VZVV_SD): New variant set.
663 (OP_SVE_VZVV_BH): New variant set.
664 (OP_SVE_VZV_SD): New variant set.
665 (aarch64_opcode_table): Add sve2 instructions.
666
28ed815a
MM		 6672019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
668
669 * aarch64-asm-2.c: Regenerated.
670 * aarch64-dis-2.c: Regenerated.
671 * aarch64-opc-2.c: Regenerated.
672 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
673 for SVE_SHLIMM_UNPRED_22.
674 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
675 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
676 operand.
677
fd1dc4a0
MM		 6782019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
679
680 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
681 sve_size_tsz_bhs iclass encode.
682 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
683 sve_size_tsz_bhs iclass decode.
684
31e36ab3
MM		 6852019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
686
687 * aarch64-asm-2.c: Regenerated.
688 * aarch64-dis-2.c: Regenerated.
689 * aarch64-opc-2.c: Regenerated.
690 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
691 for SVE_Zm4_11_INDEX.
692 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
693 (fields): Handle SVE_i2h field.
694 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
695 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
696
1be5f94f
MM		 6972019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
698
699 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
700 sve_shift_tsz_bhsd iclass encode.
701 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
702 sve_shift_tsz_bhsd iclass decode.
703
3c17238b
MM		 7042019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
705
706 * aarch64-asm-2.c: Regenerated.
707 * aarch64-dis-2.c: Regenerated.
708 * aarch64-opc-2.c: Regenerated.
709 * aarch64-asm.c (aarch64_ins_sve_shrimm):
710 (aarch64_encode_variant_using_iclass): Handle
711 sve_shift_tsz_hsd iclass encode.
712 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
713 sve_shift_tsz_hsd iclass decode.
714 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
715 for SVE_SHRIMM_UNPRED_22.
716 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
717 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
718 operand.
719
cd50a87a
MM		 7202019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
721
722 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
723 sve_size_013 iclass encode.
724 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
725 sve_size_013 iclass decode.
726
3c705960
MM		 7272019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
728
729 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
730 sve_size_bh iclass encode.
731 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
732 sve_size_bh iclass decode.
733
0a57e14f
MM		 7342019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
735
736 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
737 sve_size_sd2 iclass encode.
738 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
739 sve_size_sd2 iclass decode.
740 * aarch64-opc.c (fields): Handle SVE_sz2 field.
741 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
742
c469c864
MM		 7432019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
744
745 * aarch64-asm-2.c: Regenerated.
746 * aarch64-dis-2.c: Regenerated.
747 * aarch64-opc-2.c: Regenerated.
748 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
749 for SVE_ADDR_ZX.
750 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
751 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
752
116adc27
MM		 7532019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
754
755 * aarch64-asm-2.c: Regenerated.
756 * aarch64-dis-2.c: Regenerated.
757 * aarch64-opc-2.c: Regenerated.
758 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
759 for SVE_Zm3_11_INDEX.
760 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
761 (fields): Handle SVE_i3l and SVE_i3h2 fields.
762 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
763 fields.
764 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
765
3bd82c86
MM		 7662019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
767
768 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
769 sve_size_hsd2 iclass encode.
770 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
771 sve_size_hsd2 iclass decode.
772 * aarch64-opc.c (fields): Handle SVE_size field.
773 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
774
adccc507
MM		 7752019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
776
777 * aarch64-asm-2.c: Regenerated.
778 * aarch64-dis-2.c: Regenerated.
779 * aarch64-opc-2.c: Regenerated.
780 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
781 for SVE_IMM_ROT3.
782 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
783 (fields): Handle SVE_rot3 field.
784 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
785 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
786
5cd99750
MM		 7872019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
788
789 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
790 instructions.
791
7ce2460a
MM		 7922019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
793
794 * aarch64-tbl.h
795 (aarch64_feature_sve2, aarch64_feature_sve2aes,
796 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
797 aarch64_feature_sve2bitperm): New feature sets.
798 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
799 for feature set addresses.
800 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
801 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
802
41cee089
FS		 8032019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
804 Faraz Shahbazker <fshahbazker@wavecomp.com>
805
806 * mips-dis.c (mips_calculate_combination_ases): Add ISA
807 argument and set ASE_EVA_R6 appropriately.
808 (set_default_mips_dis_options): Pass ISA to above.
809 (parse_mips_dis_option): Likewise.
810 * mips-opc.c (EVAR6): New macro.
811 (mips_builtin_opcodes): Add llwpe, scwpe.
812
b83b4b13
SD		 8132019-05-01 Sudakshina Das <sudi.das@arm.com>
814
815 * aarch64-asm-2.c: Regenerated.
816 * aarch64-dis-2.c: Regenerated.
817 * aarch64-opc-2.c: Regenerated.
818 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
819 AARCH64_OPND_TME_UIMM16.
820 (aarch64_print_operand): Likewise.
821 * aarch64-tbl.h (QL_IMM_NIL): New.
822 (TME): New.
823 (_TME_INSN): New.
824 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
825
4a90ce95
JD		 8262019-04-29 John Darrington <john@darrington.wattle.id.au>
827
828 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
829
a45328b9
AB		 8302019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
831 Faraz Shahbazker <fshahbazker@wavecomp.com>
832
833 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
834
d10be0cb
JD		 8352019-04-24 John Darrington <john@darrington.wattle.id.au>
836
837 * s12z-opc.h: Add extern "C" bracketing to help
838 users who wish to use this interface in c++ code.
839
a679f24e
JD		 8402019-04-24 John Darrington <john@darrington.wattle.id.au>
841
842 * s12z-opc.c (bm_decode): Handle bit map operations with the
843 "reserved0" mode.
844
32c36c3c
AV		 8452019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
846
847 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
848 specifier. Add entries for VLDR and VSTR of system registers.
849 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
850 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
851 of %J and %K format specifier.
852
efd6b359
AV		 8532019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
854
855 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
856 Add new entries for VSCCLRM instruction.
857 (print_insn_coprocessor): Handle new %C format control code.
858
6b0dd094
AV		 8592019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
860
861 * arm-dis.c (enum isa): New enum.
862 (struct sopcode32): New structure.
863 (coprocessor_opcodes): change type of entries to struct sopcode32 and
864 set isa field of all current entries to ANY.
865 (print_insn_coprocessor): Change type of insn to struct sopcode32.
866 Only match an entry if its isa field allows the current mode.
867
4b5a202f
AV		 8682019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
869
870 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
871 CLRM.
872 (print_insn_thumb32): Add logic to print %n CLRM register list.
873
60f993ce
AV		 8742019-04-15 Sudakshina Das <sudi.das@arm.com>
875
876 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
877 and %Q patterns.
878
f6b2b12d
AV		 8792019-04-15 Sudakshina Das <sudi.das@arm.com>
880
881 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
882 (print_insn_thumb32): Edit the switch case for %Z.
883
1889da70
AV		 8842019-04-15 Sudakshina Das <sudi.das@arm.com>
885
886 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
887
65d1bc05
AV		 8882019-04-15 Sudakshina Das <sudi.das@arm.com>
889
890 * arm-dis.c (thumb32_opcodes): New instruction bfl.
891
1caf72a5
AV		 8922019-04-15 Sudakshina Das <sudi.das@arm.com>
893
894 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
895
f1c7f421
AV		 8962019-04-15 Sudakshina Das <sudi.das@arm.com>
897
898 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
899 Arm register with r13 and r15 unpredictable.
900 (thumb32_opcodes): New instructions for bfx and bflx.
901
4389b29a
AV		 9022019-04-15 Sudakshina Das <sudi.das@arm.com>
903
904 * arm-dis.c (thumb32_opcodes): New instructions for bf.
905
e5d6e09e
AV		 9062019-04-15 Sudakshina Das <sudi.das@arm.com>
907
908 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
909
e12437dc
AV		 9102019-04-15 Sudakshina Das <sudi.das@arm.com>
911
912 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
913
031254f2
AV		 9142019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
915
916 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
917
e5a557ac
JD		 9182019-04-12 John Darrington <john@darrington.wattle.id.au>
919
920 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
921 "optr". ("operator" is a reserved word in c++).
922
bd7ceb8d
SD		 9232019-04-11 Sudakshina Das <sudi.das@arm.com>
924
925 * aarch64-opc.c (aarch64_print_operand): Add case for
926 AARCH64_OPND_Rt_SP.
927 (verify_constraints): Likewise.
928 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
929 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
930 to accept Rt|SP as first operand.
931 (AARCH64_OPERANDS): Add new Rt_SP.
932 * aarch64-asm-2.c: Regenerated.
933 * aarch64-dis-2.c: Regenerated.
934 * aarch64-opc-2.c: Regenerated.
935
e54010f1
SD		 9362019-04-11 Sudakshina Das <sudi.das@arm.com>
937
938 * aarch64-asm-2.c: Regenerated.
939 * aarch64-dis-2.c: Likewise.
940 * aarch64-opc-2.c: Likewise.
941 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
942
7e96e219
RS		 9432019-04-09 Robert Suchanek <robert.suchanek@mips.com>
944
945 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
946
6f2791d5
L		 9472019-04-08 H.J. Lu <hongjiu.lu@intel.com>
948
949 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
950 * i386-init.h: Regenerated.
951
e392bad3
AM		 9522019-04-07 Alan Modra <amodra@gmail.com>
953
954 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
955 op_separator to control printing of spaces, comma and parens
956 rather than need_comma, need_paren and spaces vars.
957
dffaa15c
AM		 9582019-04-07 Alan Modra <amodra@gmail.com>
959
960 PR 24421
961 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
962 (print_insn_neon, print_insn_arm): Likewise.
963
d6aab7a1
XG		 9642019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
965
966 * i386-dis-evex.h (evex_table): Updated to support BF16
967 instructions.
968 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
969 and EVEX_W_0F3872_P_3.
970 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
971 (cpu_flags): Add bitfield for CpuAVX512_BF16.
972 * i386-opc.h (enum): Add CpuAVX512_BF16.
973 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
974 * i386-opc.tbl: Add AVX512 BF16 instructions.
975 * i386-init.h: Regenerated.
976 * i386-tbl.h: Likewise.
977
66e85460
AM		 9782019-04-05 Alan Modra <amodra@gmail.com>
979
980 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
981 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
982 to favour printing of "-" branch hint when using the "y" bit.
983 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
984
c2b1c275
AM		 9852019-04-05 Alan Modra <amodra@gmail.com>
986
987 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
988 opcode until first operand is output.
989
aae9718e
PB		 9902019-04-04 Peter Bergner <bergner@linux.ibm.com>
991
992 PR gas/24349
993 * ppc-opc.c (valid_bo_pre_v2): Add comments.
994 (valid_bo_post_v2): Add support for 'at' branch hints.
995 (insert_bo): Only error on branch on ctr.
996 (get_bo_hint_mask): New function.
997 (insert_boe): Add new 'branch_taken' formal argument. Add support
998 for inserting 'at' branch hints.
999 (extract_boe): Add new 'branch_taken' formal argument. Add support
1000 for extracting 'at' branch hints.
1001 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1002 (BOE): Delete operand.
1003 (BOM, BOP): New operands.
1004 (RM): Update value.
1005 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1006 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1007 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1008 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1009 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1010 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1011 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1012 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1013 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1014 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1015 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1016 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1017 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1018 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1019 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1020 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1021 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1022 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1023 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1024 bttarl+>: New extended mnemonics.
1025
96a86c01
AM		 10262019-03-28 Alan Modra <amodra@gmail.com>
1027
1028 PR 24390
1029 * ppc-opc.c (BTF): Define.
1030 (powerpc_opcodes): Use for mtfsb*.
1031 * ppc-dis.c (print_insn_powerpc): Print fields with both
1032 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1033
796d6298
TC		 10342019-03-25 Tamar Christina <tamar.christina@arm.com>
1035
1036 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1037 (mapping_symbol_for_insn): Implement new algorithm.
1038 (print_insn): Remove duplicate code.
1039
60df3720
TC		 10402019-03-25 Tamar Christina <tamar.christina@arm.com>
1041
1042 * aarch64-dis.c (print_insn_aarch64):
1043 Implement override.
1044
51457761
TC		 10452019-03-25 Tamar Christina <tamar.christina@arm.com>
1046
1047 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1048 order.
1049
53b2f36b
TC		 10502019-03-25 Tamar Christina <tamar.christina@arm.com>
1051
1052 * aarch64-dis.c (last_stop_offset): New.
1053 (print_insn_aarch64): Use stop_offset.
1054
89199bb5
L		 10552019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1056
1057 PR gas/24359
1058 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1059 CPU_ANY_AVX2_FLAGS.
1060 * i386-init.h: Regenerated.
1061
97ed31ae
L		 10622019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1063
1064 PR gas/24348
1065 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1066 vmovdqu16, vmovdqu32 and vmovdqu64.
1067 * i386-tbl.h: Regenerated.
1068
0919bfe9
AK		 10692019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1070
1071 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1072 from vstrszb, vstrszh, and vstrszf.
1073
10742019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1075
1076 * s390-opc.txt: Add instruction descriptions.
1077
21820ebe
JW		 10782019-02-08 Jim Wilson <jimw@sifive.com>
1079
1080 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1081 <bne>: Likewise.
1082
f7dd2fb2
TC		 10832019-02-07 Tamar Christina <tamar.christina@arm.com>
1084
1085 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1086
6456d318
TC		 10872019-02-07 Tamar Christina <tamar.christina@arm.com>
1088
1089 PR binutils/23212
1090 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1091 * aarch64-opc.c (verify_elem_sd): New.
1092 (fields): Add FLD_sz entr.
1093 * aarch64-tbl.h (_SIMD_INSN): New.
1094 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1095 fmulx scalar and vector by element isns.
1096
4a83b610
NC		 10972019-02-07 Nick Clifton <nickc@redhat.com>
1098
1099 * po/sv.po: Updated Swedish translation.
1100
fc60b8c8
AK		 11012019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1102
1103 * s390-mkopc.c (main): Accept arch13 as cpu string.
1104 * s390-opc.c: Add new instruction formats and instruction opcode
1105 masks.
1106 * s390-opc.txt: Add new arch13 instructions.
1107
e10620d3
TC		 11082019-01-25 Sudakshina Das <sudi.das@arm.com>
1109
1110 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1111 (aarch64_opcode): Change encoding for stg, stzg
1112 st2g and st2zg.
1113 * aarch64-asm-2.c: Regenerated.
1114 * aarch64-dis-2.c: Regenerated.
1115 * aarch64-opc-2.c: Regenerated.
1116
20a4ca55
SD		 11172019-01-25 Sudakshina Das <sudi.das@arm.com>
1118
1119 * aarch64-asm-2.c: Regenerated.
1120 * aarch64-dis-2.c: Likewise.
1121 * aarch64-opc-2.c: Likewise.
1122 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1123
550fd7bf
SD		 11242019-01-25 Sudakshina Das <sudi.das@arm.com>
1125 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1126
1127 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1128 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1129 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1130 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1131 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1132 case for ldstgv_indexed.
1133 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1134 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1135 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1136 * aarch64-asm-2.c: Regenerated.
1137 * aarch64-dis-2.c: Regenerated.
1138 * aarch64-opc-2.c: Regenerated.
1139
d9938630
NC		 11402019-01-23 Nick Clifton <nickc@redhat.com>
1141
1142 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1143
375cd423
NC		 11442019-01-21 Nick Clifton <nickc@redhat.com>
1145
1146 * po/de.po: Updated German translation.
1147 * po/uk.po: Updated Ukranian translation.
1148
57299f48
CX		 11492019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1150 * mips-dis.c (mips_arch_choices): Fix typo in
1151 gs464, gs464e and gs264e descriptors.
1152
f48dfe41
NC		 11532019-01-19 Nick Clifton <nickc@redhat.com>
1154
1155 * configure: Regenerate.
1156 * po/opcodes.pot: Regenerate.
1157
f974f26c
NC		 11582018-06-24 Nick Clifton <nickc@redhat.com>
1159
1160 2.32 branch created.
1161
39f286cd
JD		 11622019-01-09 John Darrington <john@darrington.wattle.id.au>
1163
448b8ca8
JD		 1164 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1165 if it is null.
1166 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 1167 zero.
1168
3107326d
AP		 11692019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1170
1171 * configure: Regenerate.
1172
7e9ca91e
AM		 11732019-01-07 Alan Modra <amodra@gmail.com>
1174
1175 * configure: Regenerate.
1176 * po/POTFILES.in: Regenerate.
1177
ef1ad42b
JD		 11782019-01-03 John Darrington <john@darrington.wattle.id.au>
1179
1180 * s12z-opc.c: New file.
1181 * s12z-opc.h: New file.
1182 * s12z-dis.c: Removed all code not directly related to display
1183 of instructions. Used the interface provided by the new files
1184 instead.
1185 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 1186 * Makefile.in: Regenerate.
ef1ad42b 1187 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 1188 * configure: Regenerate.
ef1ad42b 1189
82704155
AM		 11902019-01-01 Alan Modra <amodra@gmail.com>
1191
1192 Update year range in copyright notice of all files.
1193
d5c04e1b 1194For older changes see ChangeLog-2018
3499769a 1195\f
d5c04e1b 1196Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 1197
1198Copying and distribution of this file, with or without modification,
1199are permitted in any medium without royalty provided the copyright
1200notice and this notice are preserved.
1201
1202Local Variables:
1203mode: change-log
1204left-margin: 8
1205fill-column: 74
1206version-control: never
1207End:
GDB Binutils - Deliverables
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