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MIPS/GAS: Remove extraneous `install_insn' call from `append_insn' (CL)
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
6e7ced37
JM		 12016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
2
3 * sparc-opc.c (ldtxa): New macro.
4 (sparc_opcodes): Use the macro defined above to add entries for
5 the LDTXA instructions.
6 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
7 instruction.
8
2f831b9a 92016-07-07 James Bowman <james.bowman@ftdichip.com>
10
11 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
12 and "jmpc".
13
c07315e0
JB		 142016-07-01 Jan Beulich <jbeulich@suse.com>
15
16 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
17 (movzb): Adjust to cover all permitted suffixes.
18 (movzw): New.
19 * i386-tbl.h: Re-generate.
20
9243100a
JB		 212016-07-01 Jan Beulich <jbeulich@suse.com>
22
23 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
24 (lgdt): Remove Tbyte from non-64-bit variant.
25 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
26 xsaves64, xsavec64): Remove Disp16.
27 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
28 Remove Disp32S from non-64-bit variants. Remove Disp16 from
29 64-bit variants.
30 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
31 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
32 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
33 64-bit variants.
34 * i386-tbl.h: Re-generate.
35
8325cc63
JB		 362016-07-01 Jan Beulich <jbeulich@suse.com>
37
38 * i386-opc.tbl (xlat): Remove RepPrefixOk.
39 * i386-tbl.h: Re-generate.
40
838441e4
YQ		 412016-06-30 Yao Qi <yao.qi@linaro.org>
42
43 * arm-dis.c (print_insn): Fix typo in comment.
44
dab26bf4
RS		 452016-06-28 Richard Sandiford <richard.sandiford@arm.com>
46
47 * aarch64-opc.c (operand_general_constraint_met_p): Check the
48 range of ldst_elemlist operands.
49 (print_register_list): Use PRIi64 to print the index.
50 (aarch64_print_operand): Likewise.
51
5703197e
TS		 522016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
53
54 * mcore-opc.h: Remove sentinal.
55 * mcore-dis.c (print_insn_mcore): Adjust.
56
ce440d63
GM		 572016-06-23 Graham Markall <graham.markall@embecosm.com>
58
59 * arc-opc.c: Correct description of availability of NPS400
60 features.
61
6fd3a02d
PB		 622016-06-22 Peter Bergner <bergner@vnet.ibm.com>
63
64 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
65 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
66 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
67 xor3>: New mnemonics.
68 <setb>: Change to a VX form instruction.
69 (insert_sh6): Add support for rldixor.
70 (extract_sh6): Likewise.
71
6b477896
TS		 722016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
73
74 * arc-ext.h: Wrap in extern C.
75
bdd582db
GM		 762016-06-21 Graham Markall <graham.markall@embecosm.com>
77
78 * arc-dis.c (arc_insn_length): Add comment on instruction length.
79 Use same method for determining instruction length on ARC700 and
80 NPS-400.
81 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
82 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
83 with the NPS400 subclass.
84 * arc-opc.c: Likewise.
85
96074adc
JM		 862016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
87
88 * sparc-opc.c (rdasr): New macro.
89 (wrasr): Likewise.
90 (rdpr): Likewise.
91 (wrpr): Likewise.
92 (rdhpr): Likewise.
93 (wrhpr): Likewise.
94 (sparc_opcodes): Use the macros above to fix and expand the
95 definition of read/write instructions from/to
96 asr/privileged/hyperprivileged instructions.
97 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
98 %hva_mask_nz. Prefer softint_set and softint_clear over
99 set_softint and clear_softint.
100 (print_insn_sparc): Support %ver in Rd.
101
7a10c22f
JM		 1022016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
103
104 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
105 architecture according to the hardware capabilities they require.
106
4f26fb3a
JM		 1072016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
108
109 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
110 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
111 bfd_mach_sparc_v9{c,d,e,v,m}.
112 * sparc-opc.c (MASK_V9C): Define.
113 (MASK_V9D): Likewise.
114 (MASK_V9E): Likewise.
115 (MASK_V9V): Likewise.
116 (MASK_V9M): Likewise.
117 (v6): Add MASK_V9{C,D,E,V,M}.
118 (v6notlet): Likewise.
119 (v7): Likewise.
120 (v8): Likewise.
121 (v9): Likewise.
122 (v9andleon): Likewise.
123 (v9a): Likewise.
124 (v9b): Likewise.
125 (v9c): Define.
126 (v9d): Likewise.
127 (v9e): Likewise.
128 (v9v): Likewise.
129 (v9m): Likewise.
130 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
131
3ee6e4fb
NC		 1322016-06-15 Nick Clifton <nickc@redhat.com>
133
134 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
135 constants to match expected behaviour.
136 (nds32_parse_opcode): Likewise. Also for whitespace.
137
02f3be19
AB		 1382016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
139
140 * arc-opc.c (extract_rhv1): Extract value from insn.
141
6f9f37ed 1422016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 143
144 * arc-nps400-tbl.h: Add ldbit instruction.
145 * arc-opc.c: Add flag classes required for ldbit.
146
6f9f37ed 1472016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 148
149 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
150 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
151 support the above instructions.
152
6f9f37ed 1532016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 154
155 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
156 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
157 csma, cbba, zncv, and hofs.
158 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
159 support the above instructions.
160
1612016-06-06 Graham Markall <graham.markall@embecosm.com>
162
163 * arc-nps400-tbl.h: Add andab and orab instructions.
164
1652016-06-06 Graham Markall <graham.markall@embecosm.com>
166
167 * arc-nps400-tbl.h: Add addl-like instructions.
168
1692016-06-06 Graham Markall <graham.markall@embecosm.com>
170
171 * arc-nps400-tbl.h: Add mxb and imxb instructions.
172
1732016-06-06 Graham Markall <graham.markall@embecosm.com>
174
175 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
176 instructions.
177
b2cc3f6f
AK		 1782016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
179
180 * s390-dis.c (option_use_insn_len_bits_p): New file scope
181 variable.
182 (init_disasm): Handle new command line option "insnlength".
183 (print_s390_disassembler_options): Mention new option in help
184 output.
185 (print_insn_s390): Use the encoded insn length when dumping
186 unknown instructions.
187
1857fe72
DC		 1882016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
189
190 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
191 to the address and set as symbol address for LDS/ STS immediate operands.
192
14b57c7c
AM		 1932016-06-07 Alan Modra <amodra@gmail.com>
194
195 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
196 cpu for "vle" to e500.
197 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
198 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
199 (PPCNONE): Delete, substitute throughout.
200 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
201 except for major opcode 4 and 31.
202 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
203
4d1464f2
MW		 2042016-06-07 Matthew Wahab <matthew.wahab@arm.com>
205
206 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
207 ARM_EXT_RAS in relevant entries.
208
026122a6
PB		 2092016-06-03 Peter Bergner <bergner@vnet.ibm.com>
210
211 PR binutils/20196
212 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
213 opcodes for E6500.
214
07f5af7d
L		 2152016-06-03 H.J. Lu <hongjiu.lu@intel.com>
216
217 PR binutis/18386
218 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
219 (indir_v_mode): New.
220 Add comments for '&'.
221 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
222 (putop): Handle '&'.
223 (intel_operand_size): Handle indir_v_mode.
224 (OP_E_register): Likewise.
225 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
226 64-bit indirect call/jmp for AMD64.
227 * i386-tbl.h: Regenerated
228
4eb6f892
AB		 2292016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
230
231 * arc-dis.c (struct arc_operand_iterator): New structure.
232 (find_format_from_table): All the old content from find_format,
233 with some minor adjustments, and parameter renaming.
234 (find_format_long_instructions): New function.
235 (find_format): Rewritten.
236 (arc_insn_length): Add LSB parameter.
237 (extract_operand_value): New function.
238 (operand_iterator_next): New function.
239 (print_insn_arc): Use new functions to find opcode, and iterator
240 over operands.
241 * arc-opc.c (insert_nps_3bit_dst_short): New function.
242 (extract_nps_3bit_dst_short): New function.
243 (insert_nps_3bit_src2_short): New function.
244 (extract_nps_3bit_src2_short): New function.
245 (insert_nps_bitop1_size): New function.
246 (extract_nps_bitop1_size): New function.
247 (insert_nps_bitop2_size): New function.
248 (extract_nps_bitop2_size): New function.
249 (insert_nps_bitop_mod4_msb): New function.
250 (extract_nps_bitop_mod4_msb): New function.
251 (insert_nps_bitop_mod4_lsb): New function.
252 (extract_nps_bitop_mod4_lsb): New function.
253 (insert_nps_bitop_dst_pos3_pos4): New function.
254 (extract_nps_bitop_dst_pos3_pos4): New function.
255 (insert_nps_bitop_ins_ext): New function.
256 (extract_nps_bitop_ins_ext): New function.
257 (arc_operands): Add new operands.
258 (arc_long_opcodes): New global array.
259 (arc_num_long_opcodes): New global.
260 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
261
1fe0971e
TS		 2622016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
263
264 * nds32-asm.h: Add extern "C".
265 * sh-opc.h: Likewise.
266
315f180f
GM		 2672016-06-01 Graham Markall <graham.markall@embecosm.com>
268
269 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
270 0,b,limm to the rflt instruction.
271
a2b5fccc
TS		 2722016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
273
274 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
275 constant.
276
0cbd0046
L		 2772016-05-29 H.J. Lu <hongjiu.lu@intel.com>
278
279 PR gas/20145
280 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
281 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
282 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
283 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
284 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
285 * i386-init.h: Regenerated.
286
1848e567
L		 2872016-05-27 H.J. Lu <hongjiu.lu@intel.com>
288
289 PR gas/20145
290 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
291 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
292 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
293 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
294 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
295 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
296 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
297 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
298 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
299 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
300 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
301 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
302 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
303 CpuRegMask for AVX512.
304 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
305 and CpuRegMask.
306 (set_bitfield_from_cpu_flag_init): New function.
307 (set_bitfield): Remove const on f. Call
308 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
309 * i386-opc.h (CpuRegMMX): New.
310 (CpuRegXMM): Likewise.
311 (CpuRegYMM): Likewise.
312 (CpuRegZMM): Likewise.
313 (CpuRegMask): Likewise.
314 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
315 and cpuregmask.
316 * i386-init.h: Regenerated.
317 * i386-tbl.h: Likewise.
318
e92bae62
L		 3192016-05-27 H.J. Lu <hongjiu.lu@intel.com>
320
321 PR gas/20154
322 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
323 (opcode_modifiers): Add AMD64 and Intel64.
324 (main): Properly verify CpuMax.
325 * i386-opc.h (CpuAMD64): Removed.
326 (CpuIntel64): Likewise.
327 (CpuMax): Set to CpuNo64.
328 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
329 (AMD64): New.
330 (Intel64): Likewise.
331 (i386_opcode_modifier): Add amd64 and intel64.
332 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
333 on call and jmp.
334 * i386-init.h: Regenerated.
335 * i386-tbl.h: Likewise.
336
e89c5eaa
L		 3372016-05-27 H.J. Lu <hongjiu.lu@intel.com>
338
339 PR gas/20154
340 * i386-gen.c (main): Fail if CpuMax is incorrect.
341 * i386-opc.h (CpuMax): Set to CpuIntel64.
342 * i386-tbl.h: Regenerated.
343
77d66e7b
NC		 3442016-05-27 Nick Clifton <nickc@redhat.com>
345
346 PR target/20150
347 * msp430-dis.c (msp430dis_read_two_bytes): New function.
348 (msp430dis_opcode_unsigned): New function.
349 (msp430dis_opcode_signed): New function.
350 (msp430_singleoperand): Use the new opcode reading functions.
351 Only disassenmble bytes if they were successfully read.
352 (msp430_doubleoperand): Likewise.
353 (msp430_branchinstr): Likewise.
354 (msp430x_callx_instr): Likewise.
355 (print_insn_msp430): Check that it is safe to read bytes before
356 attempting disassembly. Use the new opcode reading functions.
357
19dfcc89
PB		 3582016-05-26 Peter Bergner <bergner@vnet.ibm.com>
359
360 * ppc-opc.c (CY): New define. Document it.
361 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
362
f3ad7637
L		 3632016-05-25 H.J. Lu <hongjiu.lu@intel.com>
364
365 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
366 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
367 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
368 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
369 CPU_ANY_AVX_FLAGS.
370 * i386-init.h: Regenerated.
371
f1360d58
L		 3722016-05-25 H.J. Lu <hongjiu.lu@intel.com>
373
374 PR gas/20141
375 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
376 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
377 * i386-init.h: Regenerated.
378
293f5f65
L		 3792016-05-25 H.J. Lu <hongjiu.lu@intel.com>
380
381 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
382 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
383 * i386-init.h: Regenerated.
384
d9eca1df
CZ		 3852016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
386
387 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
388 information.
389 (print_insn_arc): Set insn_type information.
390 * arc-opc.c (C_CC): Add F_CLASS_COND.
391 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
392 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
393 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
394 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
395 (brne, brne_s, jeq_s, jne_s): Likewise.
396
87789e08
CZ		 3972016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
398
399 * arc-tbl.h (neg): New instruction variant.
400
c810e0b8
CZ		 4012016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
402
403 * arc-dis.c (find_format, find_format, get_auxreg)
404 (print_insn_arc): Changed.
405 * arc-ext.h (INSERT_XOP): Likewise.
406
3d207518
TS		 4072016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
408
409 * tic54x-dis.c (sprint_mmr): Adjust.
410 * tic54x-opc.c: Likewise.
411
514e58b7
AM		 4122016-05-19 Alan Modra <amodra@gmail.com>
413
414 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
415
e43de63c
AM		 4162016-05-19 Alan Modra <amodra@gmail.com>
417
418 * ppc-opc.c: Formatting.
419 (NSISIGNOPT): Define.
420 (powerpc_opcodes <subis>): Use NSISIGNOPT.
421
1401d2fe
MR		 4222016-05-18 Maciej W. Rozycki <macro@imgtec.com>
423
424 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
425 replacing references to `micromips_ase' throughout.
426 (_print_insn_mips): Don't use file-level microMIPS annotation to
427 determine the disassembly mode with the symbol table.
428
1178da44
PB		 4292016-05-13 Peter Bergner <bergner@vnet.ibm.com>
430
431 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
432
8f4f9071
MF		 4332016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
434
435 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
436 mips64r6.
437 * mips-opc.c (D34): New macro.
438 (mips_builtin_opcodes): Define bposge32c for DSPr3.
439
8bc52696
AF		 4402016-05-10 Alexander Fomin <alexander.fomin@intel.com>
441
442 * i386-dis.c (prefix_table): Add RDPID instruction.
443 * i386-gen.c (cpu_flag_init): Add RDPID flag.
444 (cpu_flags): Add RDPID bitfield.
445 * i386-opc.h (enum): Add RDPID element.
446 (i386_cpu_flags): Add RDPID field.
447 * i386-opc.tbl: Add RDPID instruction.
448 * i386-init.h: Regenerate.
449 * i386-tbl.h: Regenerate.
450
39d911fc
TP		 4512016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
452
453 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
454 branch type of a symbol.
455 (print_insn): Likewise.
456
16a1fa25
TP		 4572016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
458
459 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
460 Mainline Security Extensions instructions.
461 (thumb_opcodes): Add entries for narrow ARMv8-M Security
462 Extensions instructions.
463 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
464 instructions.
465 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
466 special registers.
467
d751b79e
JM		 4682016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
469
470 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
471
945e0f82
CZ		 4722016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
473
474 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
475 (arcExtMap_genOpcode): Likewise.
476 * arc-opc.c (arg_32bit_rc): Define new variable.
477 (arg_32bit_u6): Likewise.
478 (arg_32bit_limm): Likewise.
479
20f55f38
SN		 4802016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
481
482 * aarch64-gen.c (VERIFIER): Define.
483 * aarch64-opc.c (VERIFIER): Define.
484 (verify_ldpsw): Use static linkage.
485 * aarch64-opc.h (verify_ldpsw): Remove.
486 * aarch64-tbl.h: Use VERIFIER for verifiers.
487
4bd13cde
NC		 4882016-04-28 Nick Clifton <nickc@redhat.com>
489
490 PR target/19722
491 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
492 * aarch64-opc.c (verify_ldpsw): New function.
493 * aarch64-opc.h (verify_ldpsw): New prototype.
494 * aarch64-tbl.h: Add initialiser for verifier field.
495 (LDPSW): Set verifier to verify_ldpsw.
496
c0f92bf9
L		 4972016-04-23 H.J. Lu <hongjiu.lu@intel.com>
498
499 PR binutils/19983
500 PR binutils/19984
501 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
502 smaller than address size.
503
e6c7cdec
TS		 5042016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
505
506 * alpha-dis.c: Regenerate.
507 * crx-dis.c: Likewise.
508 * disassemble.c: Likewise.
509 * epiphany-opc.c: Likewise.
510 * fr30-opc.c: Likewise.
511 * frv-opc.c: Likewise.
512 * ip2k-opc.c: Likewise.
513 * iq2000-opc.c: Likewise.
514 * lm32-opc.c: Likewise.
515 * lm32-opinst.c: Likewise.
516 * m32c-opc.c: Likewise.
517 * m32r-opc.c: Likewise.
518 * m32r-opinst.c: Likewise.
519 * mep-opc.c: Likewise.
520 * mt-opc.c: Likewise.
521 * or1k-opc.c: Likewise.
522 * or1k-opinst.c: Likewise.
523 * tic80-opc.c: Likewise.
524 * xc16x-opc.c: Likewise.
525 * xstormy16-opc.c: Likewise.
526
537aefaf
AB		 5272016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
528
529 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
530 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
531 calcsd, and calcxd instructions.
532 * arc-opc.c (insert_nps_bitop_size): Delete.
533 (extract_nps_bitop_size): Delete.
534 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
535 (extract_nps_qcmp_m3): Define.
536 (extract_nps_qcmp_m2): Define.
537 (extract_nps_qcmp_m1): Define.
538 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
539 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
540 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
541 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
542 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
543 NPS_QCMP_M3.
544
c8f785f2
AB		 5452016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
546
547 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
548
6fd8e7c2
L		 5492016-04-15 H.J. Lu <hongjiu.lu@intel.com>
550
551 * Makefile.in: Regenerated with automake 1.11.6.
552 * aclocal.m4: Likewise.
553
4b0c052e
AB		 5542016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
555
556 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
557 instructions.
558 * arc-opc.c (insert_nps_cmem_uimm16): New function.
559 (extract_nps_cmem_uimm16): New function.
560 (arc_operands): Add NPS_XLDST_UIMM16 operand.
561
cb040366
AB		 5622016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
563
564 * arc-dis.c (arc_insn_length): New function.
565 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
566 (find_format): Change insnLen parameter to unsigned.
567
accc0180
NC		 5682016-04-13 Nick Clifton <nickc@redhat.com>
569
570 PR target/19937
571 * v850-opc.c (v850_opcodes): Correct masks for long versions of
572 the LD.B and LD.BU instructions.
573
f36e33da
CZ		 5742016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
575
576 * arc-dis.c (find_format): Check for extension flags.
577 (print_flags): New function.
578 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
579 .extAuxRegister.
580 * arc-ext.c (arcExtMap_coreRegName): Use
581 LAST_EXTENSION_CORE_REGISTER.
582 (arcExtMap_coreReadWrite): Likewise.
583 (dump_ARC_extmap): Update printing.
584 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
585 (arc_aux_regs): Add cpu field.
586 * arc-regs.h: Add cpu field, lower case name aux registers.
587
1c2e355e
CZ		 5882016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
589
590 * arc-tbl.h: Add rtsc, sleep with no arguments.
591
b99747ae
CZ		 5922016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
593
594 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
595 Initialize.
596 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
597 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
598 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
599 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
600 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
601 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
602 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
603 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
604 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
605 (arc_opcode arc_opcodes): Null terminate the array.
606 (arc_num_opcodes): Remove.
607 * arc-ext.h (INSERT_XOP): Define.
608 (extInstruction_t): Likewise.
609 (arcExtMap_instName): Delete.
610 (arcExtMap_insn): New function.
611 (arcExtMap_genOpcode): Likewise.
612 * arc-ext.c (ExtInstruction): Remove.
613 (create_map): Zero initialize instruction fields.
614 (arcExtMap_instName): Remove.
615 (arcExtMap_insn): New function.
616 (dump_ARC_extmap): More info while debuging.
617 (arcExtMap_genOpcode): New function.
618 * arc-dis.c (find_format): New function.
619 (print_insn_arc): Use find_format.
620 (arc_get_disassembler): Enable dump_ARC_extmap only when
621 debugging.
622
92708cec
MR		 6232016-04-11 Maciej W. Rozycki <macro@imgtec.com>
624
625 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
626 instruction bits out.
627
a42a4f84
AB		 6282016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
629
630 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
631 * arc-opc.c (arc_flag_operands): Add new flags.
632 (arc_flag_classes): Add new classes.
633
1328504b
AB		 6342016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
635
636 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
637
820f03ff
AB		 6382016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
639
640 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
641 encode1, rflt, crc16, and crc32 instructions.
642 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
643 (arc_flag_classes): Add C_NPS_R.
644 (insert_nps_bitop_size_2b): New function.
645 (extract_nps_bitop_size_2b): Likewise.
646 (insert_nps_bitop_uimm8): Likewise.
647 (extract_nps_bitop_uimm8): Likewise.
648 (arc_operands): Add new operand entries.
649
8ddf6b2a
CZ		 6502016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
651
b99747ae
CZ		 652 * arc-regs.h: Add a new subclass field. Add double assist
653 accumulator register values.
654 * arc-tbl.h: Use DPA subclass to mark the double assist
655 instructions. Use DPX/SPX subclas to mark the FPX instructions.
656 * arc-opc.c (RSP): Define instead of SP.
657 (arc_aux_regs): Add the subclass field.
8ddf6b2a 658
589a7d88
JW		 6592016-04-05 Jiong Wang <jiong.wang@arm.com>
660
661 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
662
0a191de9 6632016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 664
665 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
666 NPS_R_SRC1.
667
0a106562
AB		 6682016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
669
670 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
671 issues. No functional changes.
672
bd05ac5f
CZ		 6732016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
674
b99747ae
CZ		 675 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
676 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
677 (RTT): Remove duplicate.
678 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
679 (PCT_CONFIG*): Remove.
680 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 681
9885948f
CZ		 6822016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
683
b99747ae 684 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 685
f2dd8838
CZ		 6862016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
687
b99747ae
CZ		 688 * arc-tbl.h (invld07): Remove.
689 * arc-ext-tbl.h: New file.
690 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
691 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 692
0d2f91fe
JK		 6932016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
694
695 Fix -Wstack-usage warnings.
696 * aarch64-dis.c (print_operands): Substitute size.
697 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
698
a6b71f42
JM		 6992016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
700
701 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
702 to get a proper diagnostic when an invalid ASR register is used.
703
9780e045
NC		 7042016-03-22 Nick Clifton <nickc@redhat.com>
705
706 * configure: Regenerate.
707
e23e8ebe
AB		 7082016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
709
710 * arc-nps400-tbl.h: New file.
711 * arc-opc.c: Add top level comment.
712 (insert_nps_3bit_dst): New function.
713 (extract_nps_3bit_dst): New function.
714 (insert_nps_3bit_src2): New function.
715 (extract_nps_3bit_src2): New function.
716 (insert_nps_bitop_size): New function.
717 (extract_nps_bitop_size): New function.
718 (arc_flag_operands): Add nps400 entries.
719 (arc_flag_classes): Add nps400 entries.
720 (arc_operands): Add nps400 entries.
721 (arc_opcodes): Add nps400 include.
722
1ae8ab47
AB		 7232016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
724
725 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
726 the new class enum values.
727
8699fc3e
AB		 7282016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
729
730 * arc-dis.c (print_insn_arc): Handle nps400.
731
24740d83
AB		 7322016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
733
734 * arc-opc.c (BASE): Delete.
735
8678914f
NC		 7362016-03-18 Nick Clifton <nickc@redhat.com>
737
738 PR target/19721
739 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
740 of MOV insn that aliases an ORR insn.
741
cc933301
JW		 7422016-03-16 Jiong Wang <jiong.wang@arm.com>
743
744 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
745
f86f5863
TS		 7462016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
747
748 * mcore-opc.h: Add const qualifiers.
749 * microblaze-opc.h (struct op_code_struct): Likewise.
750 * sh-opc.h: Likewise.
751 * tic4x-dis.c (tic4x_print_indirect): Likewise.
752 (tic4x_print_op): Likewise.
753
62de1c63
AM		 7542016-03-02 Alan Modra <amodra@gmail.com>
755
d11698cd 756 * or1k-desc.h: Regenerate.
62de1c63 757 * fr30-ibld.c: Regenerate.
c697cf0b 758 * rl78-decode.c: Regenerate.
62de1c63 759
020efce5
NC		 7602016-03-01 Nick Clifton <nickc@redhat.com>
761
762 PR target/19747
763 * rl78-dis.c (print_insn_rl78_common): Fix typo.
764
b0c11777
RL		 7652016-02-24 Renlin Li <renlin.li@arm.com>
766
767 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
768 (print_insn_coprocessor): Support fp16 instructions.
769
3e309328
RL		 7702016-02-24 Renlin Li <renlin.li@arm.com>
771
772 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
773 vminnm, vrint(mpna).
774
8afc7bea
RL		 7752016-02-24 Renlin Li <renlin.li@arm.com>
776
777 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
778 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
779
4fd7268a
L		 7802016-02-15 H.J. Lu <hongjiu.lu@intel.com>
781
782 * i386-dis.c (print_insn): Parenthesize expression to prevent
783 truncated addresses.
784 (OP_J): Likewise.
785
4670103e
CZ		 7862016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
787 Janek van Oirschot <jvanoirs@synopsys.com>
788
b99747ae
CZ		 789 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
790 variable.
4670103e 791
c1d9289f
NC		 7922016-02-04 Nick Clifton <nickc@redhat.com>
793
794 PR target/19561
795 * msp430-dis.c (print_insn_msp430): Add a special case for
796 decoding an RRC instruction with the ZC bit set in the extension
797 word.
798
a143b004
AB		 7992016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
800
801 * cgen-ibld.in (insert_normal): Rework calculation of shift.
802 * epiphany-ibld.c: Regenerate.
803 * fr30-ibld.c: Regenerate.
804 * frv-ibld.c: Regenerate.
805 * ip2k-ibld.c: Regenerate.
806 * iq2000-ibld.c: Regenerate.
807 * lm32-ibld.c: Regenerate.
808 * m32c-ibld.c: Regenerate.
809 * m32r-ibld.c: Regenerate.
810 * mep-ibld.c: Regenerate.
811 * mt-ibld.c: Regenerate.
812 * or1k-ibld.c: Regenerate.
813 * xc16x-ibld.c: Regenerate.
814 * xstormy16-ibld.c: Regenerate.
815
b89807c6
AB		 8162016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
817
818 * epiphany-dis.c: Regenerated from latest cpu files.
819
d8c823c8
MM		 8202016-02-01 Michael McConville <mmcco@mykolab.com>
821
822 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
823 test bit.
824
5bc5ae88
RL		 8252016-01-25 Renlin Li <renlin.li@arm.com>
826
827 * arm-dis.c (mapping_symbol_for_insn): New function.
828 (find_ifthen_state): Call mapping_symbol_for_insn().
829
0bff6e2d
MW		 8302016-01-20 Matthew Wahab <matthew.wahab@arm.com>
831
832 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
833 of MSR UAO immediate operand.
834
100b4f2e
MR		 8352016-01-18 Maciej W. Rozycki <macro@imgtec.com>
836
837 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
838 instruction support.
839
5c14705f
AM		 8402016-01-17 Alan Modra <amodra@gmail.com>
841
842 * configure: Regenerate.
843
4d82fe66
NC		 8442016-01-14 Nick Clifton <nickc@redhat.com>
845
846 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
847 instructions that can support stack pointer operations.
848 * rl78-decode.c: Regenerate.
849 * rl78-dis.c: Fix display of stack pointer in MOVW based
850 instructions.
851
651657fa
MW		 8522016-01-14 Matthew Wahab <matthew.wahab@arm.com>
853
854 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
855 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
856 erxtatus_el1 and erxaddr_el1.
857
105bde57
MW		 8582016-01-12 Matthew Wahab <matthew.wahab@arm.com>
859
860 * arm-dis.c (arm_opcodes): Add "esb".
861 (thumb_opcodes): Likewise.
862
afa8d405
PB		 8632016-01-11 Peter Bergner <bergner@vnet.ibm.com>
864
865 * ppc-opc.c <xscmpnedp>: Delete.
866 <xvcmpnedp>: Likewise.
867 <xvcmpnedp.>: Likewise.
868 <xvcmpnesp>: Likewise.
869 <xvcmpnesp.>: Likewise.
870
83c3256e
AS		 8712016-01-08 Andreas Schwab <schwab@linux-m68k.org>
872
873 PR gas/13050
874 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
875 addition to ISA_A.
876
6f2750fe
AM		 8772016-01-01 Alan Modra <amodra@gmail.com>
878
879 Update year range in copyright notice of all files.
880
3499769a
AM		 881For older changes see ChangeLog-2015
882\f
883Copyright (C) 2016 Free Software Foundation, Inc.
884
885Copying and distribution of this file, with or without modification,
886are permitted in any medium without royalty provided the copyright
887notice and this notice are preserved.
888
889Local Variables:
890mode: change-log
891left-margin: 8
892fill-column: 74
893version-control: never
894End:
GDB Binutils - Deliverables
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