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Begin implementing ARC NPS-400 Accelerator instructions
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
db18dbab
GM		 12016-07-27 Graham Markall <graham.markall@embecosm.com>
2
3 * arc-nps400-tbl.h: Change block comments to GNU format.
4 * arc-dis.c: Add new globals addrtypenames,
5 addrtypenames_max, and addtypeunknown.
6 (get_addrtype): New function.
7 (print_insn_arc): Print colons and address types when
8 required.
9 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
10 define insert and extract functions for all address types.
11 (arc_operands): Add operands for colon and all address
12 types.
13 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
14 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
15 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
16 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
17 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
18 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
19
fecd57f9
L		 202016-07-21 H.J. Lu <hongjiu.lu@intel.com>
21
22 * configure: Regenerated.
23
37fd5ef3
CZ		 242016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
25
26 * arc-dis.c (skipclass): New structure.
27 (decodelist): New variable.
28 (is_compatible_p): New function.
29 (new_element): Likewise.
30 (skip_class_p): Likewise.
31 (find_format_from_table): Use skip_class_p function.
32 (find_format): Decode first the extension instructions.
33 (print_insn_arc): Select either ARCEM or ARCHS based on elf
34 e_flags.
35 (parse_option): New function.
36 (parse_disassembler_options): Likewise.
37 (print_arc_disassembler_options): Likewise.
38 (print_insn_arc): Use parse_disassembler_options function. Proper
39 select ARCv2 cpu variant.
40 * disassemble.c (disassembler_usage): Add ARC disassembler
41 options.
42
92281a5b
MR		 432016-07-13 Maciej W. Rozycki <macro@imgtec.com>
44
45 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
46 annotation from the "nal" entry and reorder it beyond "bltzal".
47
6e7ced37
JM		 482016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
49
50 * sparc-opc.c (ldtxa): New macro.
51 (sparc_opcodes): Use the macro defined above to add entries for
52 the LDTXA instructions.
53 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
54 instruction.
55
2f831b9a 562016-07-07 James Bowman <james.bowman@ftdichip.com>
57
58 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
59 and "jmpc".
60
c07315e0
JB		 612016-07-01 Jan Beulich <jbeulich@suse.com>
62
63 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
64 (movzb): Adjust to cover all permitted suffixes.
65 (movzw): New.
66 * i386-tbl.h: Re-generate.
67
9243100a
JB		 682016-07-01 Jan Beulich <jbeulich@suse.com>
69
70 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
71 (lgdt): Remove Tbyte from non-64-bit variant.
72 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
73 xsaves64, xsavec64): Remove Disp16.
74 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
75 Remove Disp32S from non-64-bit variants. Remove Disp16 from
76 64-bit variants.
77 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
78 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
79 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
80 64-bit variants.
81 * i386-tbl.h: Re-generate.
82
8325cc63
JB		 832016-07-01 Jan Beulich <jbeulich@suse.com>
84
85 * i386-opc.tbl (xlat): Remove RepPrefixOk.
86 * i386-tbl.h: Re-generate.
87
838441e4
YQ		 882016-06-30 Yao Qi <yao.qi@linaro.org>
89
90 * arm-dis.c (print_insn): Fix typo in comment.
91
dab26bf4
RS		 922016-06-28 Richard Sandiford <richard.sandiford@arm.com>
93
94 * aarch64-opc.c (operand_general_constraint_met_p): Check the
95 range of ldst_elemlist operands.
96 (print_register_list): Use PRIi64 to print the index.
97 (aarch64_print_operand): Likewise.
98
5703197e
TS		 992016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
100
101 * mcore-opc.h: Remove sentinal.
102 * mcore-dis.c (print_insn_mcore): Adjust.
103
ce440d63
GM		 1042016-06-23 Graham Markall <graham.markall@embecosm.com>
105
106 * arc-opc.c: Correct description of availability of NPS400
107 features.
108
6fd3a02d
PB		 1092016-06-22 Peter Bergner <bergner@vnet.ibm.com>
110
111 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
112 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
113 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
114 xor3>: New mnemonics.
115 <setb>: Change to a VX form instruction.
116 (insert_sh6): Add support for rldixor.
117 (extract_sh6): Likewise.
118
6b477896
TS		 1192016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
120
121 * arc-ext.h: Wrap in extern C.
122
bdd582db
GM		 1232016-06-21 Graham Markall <graham.markall@embecosm.com>
124
125 * arc-dis.c (arc_insn_length): Add comment on instruction length.
126 Use same method for determining instruction length on ARC700 and
127 NPS-400.
128 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
129 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
130 with the NPS400 subclass.
131 * arc-opc.c: Likewise.
132
96074adc
JM		 1332016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
134
135 * sparc-opc.c (rdasr): New macro.
136 (wrasr): Likewise.
137 (rdpr): Likewise.
138 (wrpr): Likewise.
139 (rdhpr): Likewise.
140 (wrhpr): Likewise.
141 (sparc_opcodes): Use the macros above to fix and expand the
142 definition of read/write instructions from/to
143 asr/privileged/hyperprivileged instructions.
144 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
145 %hva_mask_nz. Prefer softint_set and softint_clear over
146 set_softint and clear_softint.
147 (print_insn_sparc): Support %ver in Rd.
148
7a10c22f
JM		 1492016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
150
151 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
152 architecture according to the hardware capabilities they require.
153
4f26fb3a
JM		 1542016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
155
156 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
157 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
158 bfd_mach_sparc_v9{c,d,e,v,m}.
159 * sparc-opc.c (MASK_V9C): Define.
160 (MASK_V9D): Likewise.
161 (MASK_V9E): Likewise.
162 (MASK_V9V): Likewise.
163 (MASK_V9M): Likewise.
164 (v6): Add MASK_V9{C,D,E,V,M}.
165 (v6notlet): Likewise.
166 (v7): Likewise.
167 (v8): Likewise.
168 (v9): Likewise.
169 (v9andleon): Likewise.
170 (v9a): Likewise.
171 (v9b): Likewise.
172 (v9c): Define.
173 (v9d): Likewise.
174 (v9e): Likewise.
175 (v9v): Likewise.
176 (v9m): Likewise.
177 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
178
3ee6e4fb
NC		 1792016-06-15 Nick Clifton <nickc@redhat.com>
180
181 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
182 constants to match expected behaviour.
183 (nds32_parse_opcode): Likewise. Also for whitespace.
184
02f3be19
AB		 1852016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
186
187 * arc-opc.c (extract_rhv1): Extract value from insn.
188
6f9f37ed 1892016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 190
191 * arc-nps400-tbl.h: Add ldbit instruction.
192 * arc-opc.c: Add flag classes required for ldbit.
193
6f9f37ed 1942016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 195
196 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
197 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
198 support the above instructions.
199
6f9f37ed 2002016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 201
202 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
203 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
204 csma, cbba, zncv, and hofs.
205 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
206 support the above instructions.
207
2082016-06-06 Graham Markall <graham.markall@embecosm.com>
209
210 * arc-nps400-tbl.h: Add andab and orab instructions.
211
2122016-06-06 Graham Markall <graham.markall@embecosm.com>
213
214 * arc-nps400-tbl.h: Add addl-like instructions.
215
2162016-06-06 Graham Markall <graham.markall@embecosm.com>
217
218 * arc-nps400-tbl.h: Add mxb and imxb instructions.
219
2202016-06-06 Graham Markall <graham.markall@embecosm.com>
221
222 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
223 instructions.
224
b2cc3f6f
AK		 2252016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
226
227 * s390-dis.c (option_use_insn_len_bits_p): New file scope
228 variable.
229 (init_disasm): Handle new command line option "insnlength".
230 (print_s390_disassembler_options): Mention new option in help
231 output.
232 (print_insn_s390): Use the encoded insn length when dumping
233 unknown instructions.
234
1857fe72
DC		 2352016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
236
237 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
238 to the address and set as symbol address for LDS/ STS immediate operands.
239
14b57c7c
AM		 2402016-06-07 Alan Modra <amodra@gmail.com>
241
242 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
243 cpu for "vle" to e500.
244 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
245 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
246 (PPCNONE): Delete, substitute throughout.
247 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
248 except for major opcode 4 and 31.
249 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
250
4d1464f2
MW		 2512016-06-07 Matthew Wahab <matthew.wahab@arm.com>
252
253 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
254 ARM_EXT_RAS in relevant entries.
255
026122a6
PB		 2562016-06-03 Peter Bergner <bergner@vnet.ibm.com>
257
258 PR binutils/20196
259 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
260 opcodes for E6500.
261
07f5af7d
L		 2622016-06-03 H.J. Lu <hongjiu.lu@intel.com>
263
264 PR binutis/18386
265 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
266 (indir_v_mode): New.
267 Add comments for '&'.
268 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
269 (putop): Handle '&'.
270 (intel_operand_size): Handle indir_v_mode.
271 (OP_E_register): Likewise.
272 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
273 64-bit indirect call/jmp for AMD64.
274 * i386-tbl.h: Regenerated
275
4eb6f892
AB		 2762016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
277
278 * arc-dis.c (struct arc_operand_iterator): New structure.
279 (find_format_from_table): All the old content from find_format,
280 with some minor adjustments, and parameter renaming.
281 (find_format_long_instructions): New function.
282 (find_format): Rewritten.
283 (arc_insn_length): Add LSB parameter.
284 (extract_operand_value): New function.
285 (operand_iterator_next): New function.
286 (print_insn_arc): Use new functions to find opcode, and iterator
287 over operands.
288 * arc-opc.c (insert_nps_3bit_dst_short): New function.
289 (extract_nps_3bit_dst_short): New function.
290 (insert_nps_3bit_src2_short): New function.
291 (extract_nps_3bit_src2_short): New function.
292 (insert_nps_bitop1_size): New function.
293 (extract_nps_bitop1_size): New function.
294 (insert_nps_bitop2_size): New function.
295 (extract_nps_bitop2_size): New function.
296 (insert_nps_bitop_mod4_msb): New function.
297 (extract_nps_bitop_mod4_msb): New function.
298 (insert_nps_bitop_mod4_lsb): New function.
299 (extract_nps_bitop_mod4_lsb): New function.
300 (insert_nps_bitop_dst_pos3_pos4): New function.
301 (extract_nps_bitop_dst_pos3_pos4): New function.
302 (insert_nps_bitop_ins_ext): New function.
303 (extract_nps_bitop_ins_ext): New function.
304 (arc_operands): Add new operands.
305 (arc_long_opcodes): New global array.
306 (arc_num_long_opcodes): New global.
307 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
308
1fe0971e
TS		 3092016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
310
311 * nds32-asm.h: Add extern "C".
312 * sh-opc.h: Likewise.
313
315f180f
GM		 3142016-06-01 Graham Markall <graham.markall@embecosm.com>
315
316 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
317 0,b,limm to the rflt instruction.
318
a2b5fccc
TS		 3192016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
320
321 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
322 constant.
323
0cbd0046
L		 3242016-05-29 H.J. Lu <hongjiu.lu@intel.com>
325
326 PR gas/20145
327 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
328 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
329 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
330 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
331 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
332 * i386-init.h: Regenerated.
333
1848e567
L		 3342016-05-27 H.J. Lu <hongjiu.lu@intel.com>
335
336 PR gas/20145
337 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
338 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
339 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
340 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
341 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
342 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
343 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
344 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
345 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
346 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
347 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
348 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
349 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
350 CpuRegMask for AVX512.
351 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
352 and CpuRegMask.
353 (set_bitfield_from_cpu_flag_init): New function.
354 (set_bitfield): Remove const on f. Call
355 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
356 * i386-opc.h (CpuRegMMX): New.
357 (CpuRegXMM): Likewise.
358 (CpuRegYMM): Likewise.
359 (CpuRegZMM): Likewise.
360 (CpuRegMask): Likewise.
361 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
362 and cpuregmask.
363 * i386-init.h: Regenerated.
364 * i386-tbl.h: Likewise.
365
e92bae62
L		 3662016-05-27 H.J. Lu <hongjiu.lu@intel.com>
367
368 PR gas/20154
369 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
370 (opcode_modifiers): Add AMD64 and Intel64.
371 (main): Properly verify CpuMax.
372 * i386-opc.h (CpuAMD64): Removed.
373 (CpuIntel64): Likewise.
374 (CpuMax): Set to CpuNo64.
375 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
376 (AMD64): New.
377 (Intel64): Likewise.
378 (i386_opcode_modifier): Add amd64 and intel64.
379 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
380 on call and jmp.
381 * i386-init.h: Regenerated.
382 * i386-tbl.h: Likewise.
383
e89c5eaa
L		 3842016-05-27 H.J. Lu <hongjiu.lu@intel.com>
385
386 PR gas/20154
387 * i386-gen.c (main): Fail if CpuMax is incorrect.
388 * i386-opc.h (CpuMax): Set to CpuIntel64.
389 * i386-tbl.h: Regenerated.
390
77d66e7b
NC		 3912016-05-27 Nick Clifton <nickc@redhat.com>
392
393 PR target/20150
394 * msp430-dis.c (msp430dis_read_two_bytes): New function.
395 (msp430dis_opcode_unsigned): New function.
396 (msp430dis_opcode_signed): New function.
397 (msp430_singleoperand): Use the new opcode reading functions.
398 Only disassenmble bytes if they were successfully read.
399 (msp430_doubleoperand): Likewise.
400 (msp430_branchinstr): Likewise.
401 (msp430x_callx_instr): Likewise.
402 (print_insn_msp430): Check that it is safe to read bytes before
403 attempting disassembly. Use the new opcode reading functions.
404
19dfcc89
PB		 4052016-05-26 Peter Bergner <bergner@vnet.ibm.com>
406
407 * ppc-opc.c (CY): New define. Document it.
408 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
409
f3ad7637
L		 4102016-05-25 H.J. Lu <hongjiu.lu@intel.com>
411
412 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
413 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
414 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
415 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
416 CPU_ANY_AVX_FLAGS.
417 * i386-init.h: Regenerated.
418
f1360d58
L		 4192016-05-25 H.J. Lu <hongjiu.lu@intel.com>
420
421 PR gas/20141
422 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
423 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
424 * i386-init.h: Regenerated.
425
293f5f65
L		 4262016-05-25 H.J. Lu <hongjiu.lu@intel.com>
427
428 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
429 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
430 * i386-init.h: Regenerated.
431
d9eca1df
CZ		 4322016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
433
434 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
435 information.
436 (print_insn_arc): Set insn_type information.
437 * arc-opc.c (C_CC): Add F_CLASS_COND.
438 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
439 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
440 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
441 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
442 (brne, brne_s, jeq_s, jne_s): Likewise.
443
87789e08
CZ		 4442016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
445
446 * arc-tbl.h (neg): New instruction variant.
447
c810e0b8
CZ		 4482016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
449
450 * arc-dis.c (find_format, find_format, get_auxreg)
451 (print_insn_arc): Changed.
452 * arc-ext.h (INSERT_XOP): Likewise.
453
3d207518
TS		 4542016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
455
456 * tic54x-dis.c (sprint_mmr): Adjust.
457 * tic54x-opc.c: Likewise.
458
514e58b7
AM		 4592016-05-19 Alan Modra <amodra@gmail.com>
460
461 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
462
e43de63c
AM		 4632016-05-19 Alan Modra <amodra@gmail.com>
464
465 * ppc-opc.c: Formatting.
466 (NSISIGNOPT): Define.
467 (powerpc_opcodes <subis>): Use NSISIGNOPT.
468
1401d2fe
MR		 4692016-05-18 Maciej W. Rozycki <macro@imgtec.com>
470
471 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
472 replacing references to `micromips_ase' throughout.
473 (_print_insn_mips): Don't use file-level microMIPS annotation to
474 determine the disassembly mode with the symbol table.
475
1178da44
PB		 4762016-05-13 Peter Bergner <bergner@vnet.ibm.com>
477
478 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
479
8f4f9071
MF		 4802016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
481
482 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
483 mips64r6.
484 * mips-opc.c (D34): New macro.
485 (mips_builtin_opcodes): Define bposge32c for DSPr3.
486
8bc52696
AF		 4872016-05-10 Alexander Fomin <alexander.fomin@intel.com>
488
489 * i386-dis.c (prefix_table): Add RDPID instruction.
490 * i386-gen.c (cpu_flag_init): Add RDPID flag.
491 (cpu_flags): Add RDPID bitfield.
492 * i386-opc.h (enum): Add RDPID element.
493 (i386_cpu_flags): Add RDPID field.
494 * i386-opc.tbl: Add RDPID instruction.
495 * i386-init.h: Regenerate.
496 * i386-tbl.h: Regenerate.
497
39d911fc
TP		 4982016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
499
500 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
501 branch type of a symbol.
502 (print_insn): Likewise.
503
16a1fa25
TP		 5042016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
505
506 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
507 Mainline Security Extensions instructions.
508 (thumb_opcodes): Add entries for narrow ARMv8-M Security
509 Extensions instructions.
510 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
511 instructions.
512 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
513 special registers.
514
d751b79e
JM		 5152016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
516
517 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
518
945e0f82
CZ		 5192016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
520
521 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
522 (arcExtMap_genOpcode): Likewise.
523 * arc-opc.c (arg_32bit_rc): Define new variable.
524 (arg_32bit_u6): Likewise.
525 (arg_32bit_limm): Likewise.
526
20f55f38
SN		 5272016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
528
529 * aarch64-gen.c (VERIFIER): Define.
530 * aarch64-opc.c (VERIFIER): Define.
531 (verify_ldpsw): Use static linkage.
532 * aarch64-opc.h (verify_ldpsw): Remove.
533 * aarch64-tbl.h: Use VERIFIER for verifiers.
534
4bd13cde
NC		 5352016-04-28 Nick Clifton <nickc@redhat.com>
536
537 PR target/19722
538 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
539 * aarch64-opc.c (verify_ldpsw): New function.
540 * aarch64-opc.h (verify_ldpsw): New prototype.
541 * aarch64-tbl.h: Add initialiser for verifier field.
542 (LDPSW): Set verifier to verify_ldpsw.
543
c0f92bf9
L		 5442016-04-23 H.J. Lu <hongjiu.lu@intel.com>
545
546 PR binutils/19983
547 PR binutils/19984
548 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
549 smaller than address size.
550
e6c7cdec
TS		 5512016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
552
553 * alpha-dis.c: Regenerate.
554 * crx-dis.c: Likewise.
555 * disassemble.c: Likewise.
556 * epiphany-opc.c: Likewise.
557 * fr30-opc.c: Likewise.
558 * frv-opc.c: Likewise.
559 * ip2k-opc.c: Likewise.
560 * iq2000-opc.c: Likewise.
561 * lm32-opc.c: Likewise.
562 * lm32-opinst.c: Likewise.
563 * m32c-opc.c: Likewise.
564 * m32r-opc.c: Likewise.
565 * m32r-opinst.c: Likewise.
566 * mep-opc.c: Likewise.
567 * mt-opc.c: Likewise.
568 * or1k-opc.c: Likewise.
569 * or1k-opinst.c: Likewise.
570 * tic80-opc.c: Likewise.
571 * xc16x-opc.c: Likewise.
572 * xstormy16-opc.c: Likewise.
573
537aefaf
AB		 5742016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
575
576 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
577 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
578 calcsd, and calcxd instructions.
579 * arc-opc.c (insert_nps_bitop_size): Delete.
580 (extract_nps_bitop_size): Delete.
581 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
582 (extract_nps_qcmp_m3): Define.
583 (extract_nps_qcmp_m2): Define.
584 (extract_nps_qcmp_m1): Define.
585 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
586 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
587 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
588 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
589 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
590 NPS_QCMP_M3.
591
c8f785f2
AB		 5922016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
593
594 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
595
6fd8e7c2
L		 5962016-04-15 H.J. Lu <hongjiu.lu@intel.com>
597
598 * Makefile.in: Regenerated with automake 1.11.6.
599 * aclocal.m4: Likewise.
600
4b0c052e
AB		 6012016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
602
603 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
604 instructions.
605 * arc-opc.c (insert_nps_cmem_uimm16): New function.
606 (extract_nps_cmem_uimm16): New function.
607 (arc_operands): Add NPS_XLDST_UIMM16 operand.
608
cb040366
AB		 6092016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
610
611 * arc-dis.c (arc_insn_length): New function.
612 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
613 (find_format): Change insnLen parameter to unsigned.
614
accc0180
NC		 6152016-04-13 Nick Clifton <nickc@redhat.com>
616
617 PR target/19937
618 * v850-opc.c (v850_opcodes): Correct masks for long versions of
619 the LD.B and LD.BU instructions.
620
f36e33da
CZ		 6212016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
622
623 * arc-dis.c (find_format): Check for extension flags.
624 (print_flags): New function.
625 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
626 .extAuxRegister.
627 * arc-ext.c (arcExtMap_coreRegName): Use
628 LAST_EXTENSION_CORE_REGISTER.
629 (arcExtMap_coreReadWrite): Likewise.
630 (dump_ARC_extmap): Update printing.
631 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
632 (arc_aux_regs): Add cpu field.
633 * arc-regs.h: Add cpu field, lower case name aux registers.
634
1c2e355e
CZ		 6352016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
636
637 * arc-tbl.h: Add rtsc, sleep with no arguments.
638
b99747ae
CZ		 6392016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
640
641 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
642 Initialize.
643 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
644 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
645 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
646 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
647 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
648 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
649 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
650 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
651 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
652 (arc_opcode arc_opcodes): Null terminate the array.
653 (arc_num_opcodes): Remove.
654 * arc-ext.h (INSERT_XOP): Define.
655 (extInstruction_t): Likewise.
656 (arcExtMap_instName): Delete.
657 (arcExtMap_insn): New function.
658 (arcExtMap_genOpcode): Likewise.
659 * arc-ext.c (ExtInstruction): Remove.
660 (create_map): Zero initialize instruction fields.
661 (arcExtMap_instName): Remove.
662 (arcExtMap_insn): New function.
663 (dump_ARC_extmap): More info while debuging.
664 (arcExtMap_genOpcode): New function.
665 * arc-dis.c (find_format): New function.
666 (print_insn_arc): Use find_format.
667 (arc_get_disassembler): Enable dump_ARC_extmap only when
668 debugging.
669
92708cec
MR		 6702016-04-11 Maciej W. Rozycki <macro@imgtec.com>
671
672 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
673 instruction bits out.
674
a42a4f84
AB		 6752016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
676
677 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
678 * arc-opc.c (arc_flag_operands): Add new flags.
679 (arc_flag_classes): Add new classes.
680
1328504b
AB		 6812016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
682
683 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
684
820f03ff
AB		 6852016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
686
687 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
688 encode1, rflt, crc16, and crc32 instructions.
689 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
690 (arc_flag_classes): Add C_NPS_R.
691 (insert_nps_bitop_size_2b): New function.
692 (extract_nps_bitop_size_2b): Likewise.
693 (insert_nps_bitop_uimm8): Likewise.
694 (extract_nps_bitop_uimm8): Likewise.
695 (arc_operands): Add new operand entries.
696
8ddf6b2a
CZ		 6972016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
698
b99747ae
CZ		 699 * arc-regs.h: Add a new subclass field. Add double assist
700 accumulator register values.
701 * arc-tbl.h: Use DPA subclass to mark the double assist
702 instructions. Use DPX/SPX subclas to mark the FPX instructions.
703 * arc-opc.c (RSP): Define instead of SP.
704 (arc_aux_regs): Add the subclass field.
8ddf6b2a 705
589a7d88
JW		 7062016-04-05 Jiong Wang <jiong.wang@arm.com>
707
708 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
709
0a191de9 7102016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 711
712 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
713 NPS_R_SRC1.
714
0a106562
AB		 7152016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
716
717 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
718 issues. No functional changes.
719
bd05ac5f
CZ		 7202016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
721
b99747ae
CZ		 722 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
723 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
724 (RTT): Remove duplicate.
725 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
726 (PCT_CONFIG*): Remove.
727 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 728
9885948f
CZ		 7292016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
730
b99747ae 731 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 732
f2dd8838
CZ		 7332016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
734
b99747ae
CZ		 735 * arc-tbl.h (invld07): Remove.
736 * arc-ext-tbl.h: New file.
737 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
738 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 739
0d2f91fe
JK		 7402016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
741
742 Fix -Wstack-usage warnings.
743 * aarch64-dis.c (print_operands): Substitute size.
744 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
745
a6b71f42
JM		 7462016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
747
748 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
749 to get a proper diagnostic when an invalid ASR register is used.
750
9780e045
NC		 7512016-03-22 Nick Clifton <nickc@redhat.com>
752
753 * configure: Regenerate.
754
e23e8ebe
AB		 7552016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
756
757 * arc-nps400-tbl.h: New file.
758 * arc-opc.c: Add top level comment.
759 (insert_nps_3bit_dst): New function.
760 (extract_nps_3bit_dst): New function.
761 (insert_nps_3bit_src2): New function.
762 (extract_nps_3bit_src2): New function.
763 (insert_nps_bitop_size): New function.
764 (extract_nps_bitop_size): New function.
765 (arc_flag_operands): Add nps400 entries.
766 (arc_flag_classes): Add nps400 entries.
767 (arc_operands): Add nps400 entries.
768 (arc_opcodes): Add nps400 include.
769
1ae8ab47
AB		 7702016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
771
772 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
773 the new class enum values.
774
8699fc3e
AB		 7752016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
776
777 * arc-dis.c (print_insn_arc): Handle nps400.
778
24740d83
AB		 7792016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
780
781 * arc-opc.c (BASE): Delete.
782
8678914f
NC		 7832016-03-18 Nick Clifton <nickc@redhat.com>
784
785 PR target/19721
786 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
787 of MOV insn that aliases an ORR insn.
788
cc933301
JW		 7892016-03-16 Jiong Wang <jiong.wang@arm.com>
790
791 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
792
f86f5863
TS		 7932016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
794
795 * mcore-opc.h: Add const qualifiers.
796 * microblaze-opc.h (struct op_code_struct): Likewise.
797 * sh-opc.h: Likewise.
798 * tic4x-dis.c (tic4x_print_indirect): Likewise.
799 (tic4x_print_op): Likewise.
800
62de1c63
AM		 8012016-03-02 Alan Modra <amodra@gmail.com>
802
d11698cd 803 * or1k-desc.h: Regenerate.
62de1c63 804 * fr30-ibld.c: Regenerate.
c697cf0b 805 * rl78-decode.c: Regenerate.
62de1c63 806
020efce5
NC		 8072016-03-01 Nick Clifton <nickc@redhat.com>
808
809 PR target/19747
810 * rl78-dis.c (print_insn_rl78_common): Fix typo.
811
b0c11777
RL		 8122016-02-24 Renlin Li <renlin.li@arm.com>
813
814 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
815 (print_insn_coprocessor): Support fp16 instructions.
816
3e309328
RL		 8172016-02-24 Renlin Li <renlin.li@arm.com>
818
819 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
820 vminnm, vrint(mpna).
821
8afc7bea
RL		 8222016-02-24 Renlin Li <renlin.li@arm.com>
823
824 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
825 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
826
4fd7268a
L		 8272016-02-15 H.J. Lu <hongjiu.lu@intel.com>
828
829 * i386-dis.c (print_insn): Parenthesize expression to prevent
830 truncated addresses.
831 (OP_J): Likewise.
832
4670103e
CZ		 8332016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
834 Janek van Oirschot <jvanoirs@synopsys.com>
835
b99747ae
CZ		 836 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
837 variable.
4670103e 838
c1d9289f
NC		 8392016-02-04 Nick Clifton <nickc@redhat.com>
840
841 PR target/19561
842 * msp430-dis.c (print_insn_msp430): Add a special case for
843 decoding an RRC instruction with the ZC bit set in the extension
844 word.
845
a143b004
AB		 8462016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
847
848 * cgen-ibld.in (insert_normal): Rework calculation of shift.
849 * epiphany-ibld.c: Regenerate.
850 * fr30-ibld.c: Regenerate.
851 * frv-ibld.c: Regenerate.
852 * ip2k-ibld.c: Regenerate.
853 * iq2000-ibld.c: Regenerate.
854 * lm32-ibld.c: Regenerate.
855 * m32c-ibld.c: Regenerate.
856 * m32r-ibld.c: Regenerate.
857 * mep-ibld.c: Regenerate.
858 * mt-ibld.c: Regenerate.
859 * or1k-ibld.c: Regenerate.
860 * xc16x-ibld.c: Regenerate.
861 * xstormy16-ibld.c: Regenerate.
862
b89807c6
AB		 8632016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
864
865 * epiphany-dis.c: Regenerated from latest cpu files.
866
d8c823c8
MM		 8672016-02-01 Michael McConville <mmcco@mykolab.com>
868
869 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
870 test bit.
871
5bc5ae88
RL		 8722016-01-25 Renlin Li <renlin.li@arm.com>
873
874 * arm-dis.c (mapping_symbol_for_insn): New function.
875 (find_ifthen_state): Call mapping_symbol_for_insn().
876
0bff6e2d
MW		 8772016-01-20 Matthew Wahab <matthew.wahab@arm.com>
878
879 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
880 of MSR UAO immediate operand.
881
100b4f2e
MR		 8822016-01-18 Maciej W. Rozycki <macro@imgtec.com>
883
884 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
885 instruction support.
886
5c14705f
AM		 8872016-01-17 Alan Modra <amodra@gmail.com>
888
889 * configure: Regenerate.
890
4d82fe66
NC		 8912016-01-14 Nick Clifton <nickc@redhat.com>
892
893 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
894 instructions that can support stack pointer operations.
895 * rl78-decode.c: Regenerate.
896 * rl78-dis.c: Fix display of stack pointer in MOVW based
897 instructions.
898
651657fa
MW		 8992016-01-14 Matthew Wahab <matthew.wahab@arm.com>
900
901 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
902 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
903 erxtatus_el1 and erxaddr_el1.
904
105bde57
MW		 9052016-01-12 Matthew Wahab <matthew.wahab@arm.com>
906
907 * arm-dis.c (arm_opcodes): Add "esb".
908 (thumb_opcodes): Likewise.
909
afa8d405
PB		 9102016-01-11 Peter Bergner <bergner@vnet.ibm.com>
911
912 * ppc-opc.c <xscmpnedp>: Delete.
913 <xvcmpnedp>: Likewise.
914 <xvcmpnedp.>: Likewise.
915 <xvcmpnesp>: Likewise.
916 <xvcmpnesp.>: Likewise.
917
83c3256e
AS		 9182016-01-08 Andreas Schwab <schwab@linux-m68k.org>
919
920 PR gas/13050
921 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
922 addition to ISA_A.
923
6f2750fe
AM		 9242016-01-01 Alan Modra <amodra@gmail.com>
925
926 Update year range in copyright notice of all files.
927
3499769a
AM		 928For older changes see ChangeLog-2015
929\f
930Copyright (C) 2016 Free Software Foundation, Inc.
931
932Copying and distribution of this file, with or without modification,
933are permitted in any medium without royalty provided the copyright
934notice and this notice are preserved.
935
936Local Variables:
937mode: change-log
938left-margin: 8
939fill-column: 74
940version-control: never
941End:
GDB Binutils - Deliverables
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