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57b17940
SSF		 12020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
2
3 * s390-opc.txt: Relocate vector load/store instructions with
4 additional alignment parameter and change architecture level
5 constraint from z14 to z13.
6
d96bf37b
AM		 72020-05-21 Alan Modra <amodra@gmail.com>
8
9 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
10 * sparc-dis.c: Likewise.
11 * tic4x-dis.c: Likewise.
12 * xtensa-dis.c: Likewise.
13 * bpf-desc.c: Regenerate.
14 * epiphany-desc.c: Regenerate.
15 * fr30-desc.c: Regenerate.
16 * frv-desc.c: Regenerate.
17 * ip2k-desc.c: Regenerate.
18 * iq2000-desc.c: Regenerate.
19 * lm32-desc.c: Regenerate.
20 * m32c-desc.c: Regenerate.
21 * m32r-desc.c: Regenerate.
22 * mep-asm.c: Regenerate.
23 * mep-desc.c: Regenerate.
24 * mt-desc.c: Regenerate.
25 * or1k-desc.c: Regenerate.
26 * xc16x-desc.c: Regenerate.
27 * xstormy16-desc.c: Regenerate.
28
8f595e9b
NC		 292020-05-20 Nelson Chu <nelson.chu@sifive.com>
30
31 * riscv-opc.c (riscv_ext_version_table): The table used to store
32 all information about the supported spec and the corresponding ISA
33 versions. Currently, only Zicsr is supported to verify the
34 correctness of Z sub extension settings. Others will be supported
35 in the future patches.
36 (struct isa_spec_t, isa_specs): List for all supported ISA spec
37 classes and the corresponding strings.
38 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
39 spec class by giving a ISA spec string.
40 * riscv-opc.c (struct priv_spec_t): New structure.
41 (struct priv_spec_t priv_specs): List for all supported privilege spec
42 classes and the corresponding strings.
43 (riscv_get_priv_spec_class): New function. Get the corresponding
44 privilege spec class by giving a spec string.
45 (riscv_get_priv_spec_name): New function. Get the corresponding
46 privilege spec string by giving a CSR version class.
47 * riscv-dis.c: Updated since DECLARE_CSR is changed.
48 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
49 according to the chosen version. Build a hash table riscv_csr_hash to
50 store the valid CSR for the chosen pirv verison. Dump the direct
51 CSR address rather than it's name if it is invalid.
52 (parse_riscv_dis_option_without_args): New function. Parse the options
53 without arguments.
54 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
55 parse the options without arguments first, and then handle the options
56 with arguments. Add the new option -Mpriv-spec, which has argument.
57 * riscv-dis.c (print_riscv_disassembler_options): Add description
58 about the new OBJDUMP option.
59
3d205eb4
PB		 602020-05-19 Peter Bergner <bergner@linux.ibm.com>
61
62 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
63 WC values on POWER10 sync, dcbf and wait instructions.
64 (insert_pl, extract_pl): New functions.
65 (L2OPT, LS, WC): Use insert_ls and extract_ls.
66 (LS3): New , 3-bit L for sync.
67 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
68 (SC2, PL): New, 2-bit SC and PL for sync and wait.
69 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
70 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
71 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
72 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
73 <wait>: Enable PL operand on POWER10.
74 <dcbf>: Enable L3OPT operand on POWER10.
75 <sync>: Enable SC2 operand on POWER10.
76
a501eb44
SH		 772020-05-19 Stafford Horne <shorne@gmail.com>
78
79 PR 25184
80 * or1k-asm.c: Regenerate.
81 * or1k-desc.c: Regenerate.
82 * or1k-desc.h: Regenerate.
83 * or1k-dis.c: Regenerate.
84 * or1k-ibld.c: Regenerate.
85 * or1k-opc.c: Regenerate.
86 * or1k-opc.h: Regenerate.
87 * or1k-opinst.c: Regenerate.
88
3b646889
AM		 892020-05-11 Alan Modra <amodra@gmail.com>
90
91 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
92 xsmaxcqp, xsmincqp.
93
9cc4ce88
AM		 942020-05-11 Alan Modra <amodra@gmail.com>
95
96 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
97 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
98
5d57bc3f
AM		 992020-05-11 Alan Modra <amodra@gmail.com>
100
101 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
102
66ef5847
AM		 1032020-05-11 Alan Modra <amodra@gmail.com>
104
105 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
106 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
107
4f3e9537
PB		 1082020-05-11 Peter Bergner <bergner@linux.ibm.com>
109
110 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
111 mnemonics.
112
ec40e91c
AM		 1132020-05-11 Alan Modra <amodra@gmail.com>
114
115 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
116 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
117 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
118 (prefix_opcodes): Add xxeval.
119
d7e97a76
AM		 1202020-05-11 Alan Modra <amodra@gmail.com>
121
122 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
123 xxgenpcvwm, xxgenpcvdm.
124
fdefed7c
AM		 1252020-05-11 Alan Modra <amodra@gmail.com>
126
127 * ppc-opc.c (MP, VXVAM_MASK): Define.
128 (VXVAPS_MASK): Use VXVA_MASK.
129 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
130 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
131 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
132 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
133
aa3c112f
AM		 1342020-05-11 Alan Modra <amodra@gmail.com>
135 Peter Bergner <bergner@linux.ibm.com>
136
137 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
138 New functions.
139 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
140 YMSK2, XA6a, XA6ap, XB6a entries.
141 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
142 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
143 (PPCVSX4): Define.
144 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
145 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
146 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
147 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
148 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
149 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
150 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
151 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
152 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
153 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
154 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
155 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
156 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
157 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
158
6edbfd3b
AM		 1592020-05-11 Alan Modra <amodra@gmail.com>
160
161 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
162 (insert_xts, extract_xts): New functions.
163 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
164 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
165 (VXRC_MASK, VXSH_MASK): Define.
166 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
167 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
168 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
169 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
170 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
171 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
172 xxblendvh, xxblendvw, xxblendvd, xxpermx.
173
c7d7aea2
AM		 1742020-05-11 Alan Modra <amodra@gmail.com>
175
176 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
177 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
178 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
179 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
180 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
181
94ba9882
AM		 1822020-05-11 Alan Modra <amodra@gmail.com>
183
184 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
185 (XTP, DQXP, DQXP_MASK): Define.
186 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
187 (prefix_opcodes): Add plxvp and pstxvp.
188
f4791f1a
AM		 1892020-05-11 Alan Modra <amodra@gmail.com>
190
191 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
192 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
193 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
194
3ff0a5ba
PB		 1952020-05-11 Peter Bergner <bergner@linux.ibm.com>
196
197 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
198
afef4fe9
PB		 1992020-05-11 Peter Bergner <bergner@linux.ibm.com>
200
201 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
202 (L1OPT): Define.
203 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
204
1224c05d
PB		 2052020-05-11 Peter Bergner <bergner@linux.ibm.com>
206
207 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
208
6bbb0c05
AM		 2092020-05-11 Alan Modra <amodra@gmail.com>
210
211 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
212
7c1f4227
AM		 2132020-05-11 Alan Modra <amodra@gmail.com>
214
215 * ppc-dis.c (ppc_opts): Add "power10" entry.
216 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
217 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
218
73199c2b
NC		 2192020-05-11 Nick Clifton <nickc@redhat.com>
220
221 * po/fr.po: Updated French translation.
222
09c1e68a
AC		 2232020-04-30 Alex Coplan <alex.coplan@arm.com>
224
225 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
226 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
227 (operand_general_constraint_met_p): validate
228 AARCH64_OPND_UNDEFINED.
229 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
230 for FLD_imm16_2.
231 * aarch64-asm-2.c: Regenerated.
232 * aarch64-dis-2.c: Regenerated.
233 * aarch64-opc-2.c: Regenerated.
234
9654d51a
NC		 2352020-04-29 Nick Clifton <nickc@redhat.com>
236
237 PR 22699
238 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
239 and SETRC insns.
240
c2e71e57
NC		 2412020-04-29 Nick Clifton <nickc@redhat.com>
242
243 * po/sv.po: Updated Swedish translation.
244
5c936ef5
NC		 2452020-04-29 Nick Clifton <nickc@redhat.com>
246
247 PR 22699
248 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
249 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
250 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
251 IMM0_8U case.
252
bb2a1453
AS		 2532020-04-21 Andreas Schwab <schwab@linux-m68k.org>
254
255 PR 25848
256 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
257 cmpi only on m68020up and cpu32.
258
c2e5c986
SD		 2592020-04-20 Sudakshina Das <sudi.das@arm.com>
260
261 * aarch64-asm.c (aarch64_ins_none): New.
262 * aarch64-asm.h (ins_none): New declaration.
263 * aarch64-dis.c (aarch64_ext_none): New.
264 * aarch64-dis.h (ext_none): New declaration.
265 * aarch64-opc.c (aarch64_print_operand): Update case for
266 AARCH64_OPND_BARRIER_PSB.
267 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
268 (AARCH64_OPERANDS): Update inserter/extracter for
269 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
270 * aarch64-asm-2.c: Regenerated.
271 * aarch64-dis-2.c: Regenerated.
272 * aarch64-opc-2.c: Regenerated.
273
8a6e1d1d
SD		 2742020-04-20 Sudakshina Das <sudi.das@arm.com>
275
276 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
277 (aarch64_feature_ras, RAS): Likewise.
278 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
279 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
280 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
281 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
282 * aarch64-asm-2.c: Regenerated.
283 * aarch64-dis-2.c: Regenerated.
284 * aarch64-opc-2.c: Regenerated.
285
e409955d
FS		 2862020-04-17 Fredrik Strupe <fredrik@strupe.net>
287
288 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
289 (print_insn_neon): Support disassembly of conditional
290 instructions.
291
c54a9b56
DF		 2922020-02-16 David Faust <david.faust@oracle.com>
293
294 * bpf-desc.c: Regenerate.
295 * bpf-desc.h: Likewise.
296 * bpf-opc.c: Regenerate.
297 * bpf-opc.h: Likewise.
298
bb651e8b
CL		 2992020-04-07 Lili Cui <lili.cui@intel.com>
300
301 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
302 (prefix_table): New instructions (see prefixes above).
303 (rm_table): Likewise
304 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
305 CPU_ANY_TSXLDTRK_FLAGS.
306 (cpu_flags): Add CpuTSXLDTRK.
307 * i386-opc.h (enum): Add CpuTSXLDTRK.
308 (i386_cpu_flags): Add cputsxldtrk.
309 * i386-opc.tbl: Add XSUSPLDTRK insns.
310 * i386-init.h: Regenerate.
311 * i386-tbl.h: Likewise.
312
4b27d27c
L		 3132020-04-02 Lili Cui <lili.cui@intel.com>
314
315 * i386-dis.c (prefix_table): New instructions serialize.
316 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
317 CPU_ANY_SERIALIZE_FLAGS.
318 (cpu_flags): Add CpuSERIALIZE.
319 * i386-opc.h (enum): Add CpuSERIALIZE.
320 (i386_cpu_flags): Add cpuserialize.
321 * i386-opc.tbl: Add SERIALIZE insns.
322 * i386-init.h: Regenerate.
323 * i386-tbl.h: Likewise.
324
832a5807
AM		 3252020-03-26 Alan Modra <amodra@gmail.com>
326
327 * disassemble.h (opcodes_assert): Declare.
328 (OPCODES_ASSERT): Define.
329 * disassemble.c: Don't include assert.h. Include opintl.h.
330 (opcodes_assert): New function.
331 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
332 (bfd_h8_disassemble): Reduce size of data array. Correctly
333 calculate maxlen. Omit insn decoding when insn length exceeds
334 maxlen. Exit from nibble loop when looking for E, before
335 accessing next data byte. Move processing of E outside loop.
336 Replace tests of maxlen in loop with assertions.
337
4c4addbe
AM		 3382020-03-26 Alan Modra <amodra@gmail.com>
339
340 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
341
a18cd0ca
AM		 3422020-03-25 Alan Modra <amodra@gmail.com>
343
344 * z80-dis.c (suffix): Init mybuf.
345
57cb32b3
AM		 3462020-03-22 Alan Modra <amodra@gmail.com>
347
348 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
349 successflly read from section.
350
beea5cc1
AM		 3512020-03-22 Alan Modra <amodra@gmail.com>
352
353 * arc-dis.c (find_format): Use ISO C string concatenation rather
354 than line continuation within a string. Don't access needs_limm
355 before testing opcode != NULL.
356
03704c77
AM		 3572020-03-22 Alan Modra <amodra@gmail.com>
358
359 * ns32k-dis.c (print_insn_arg): Update comment.
360 (print_insn_ns32k): Reduce size of index_offset array, and
361 initialize, passing -1 to print_insn_arg for args that are not
362 an index. Don't exit arg loop early. Abort on bad arg number.
363
d1023b5d
AM		 3642020-03-22 Alan Modra <amodra@gmail.com>
365
366 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
367 * s12z-opc.c: Formatting.
368 (operands_f): Return an int.
369 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
370 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
371 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
372 (exg_sex_discrim): Likewise.
373 (create_immediate_operand, create_bitfield_operand),
374 (create_register_operand_with_size, create_register_all_operand),
375 (create_register_all16_operand, create_simple_memory_operand),
376 (create_memory_operand, create_memory_auto_operand): Don't
377 segfault on malloc failure.
378 (z_ext24_decode): Return an int status, negative on fail, zero
379 on success.
380 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
381 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
382 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
383 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
384 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
385 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
386 (loop_primitive_decode, shift_decode, psh_pul_decode),
387 (bit_field_decode): Similarly.
388 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
389 to return value, update callers.
390 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
391 Don't segfault on NULL operand.
392 (decode_operation): Return OP_INVALID on first fail.
393 (decode_s12z): Check all reads, returning -1 on fail.
394
340f3ac8
AM		 3952020-03-20 Alan Modra <amodra@gmail.com>
396
397 * metag-dis.c (print_insn_metag): Don't ignore status from
398 read_memory_func.
399
fe90ae8a
AM		 4002020-03-20 Alan Modra <amodra@gmail.com>
401
402 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
403 Initialize parts of buffer not written when handling a possible
404 2-byte insn at end of section. Don't attempt decoding of such
405 an insn by the 4-byte machinery.
406
833d919c
AM		 4072020-03-20 Alan Modra <amodra@gmail.com>
408
409 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
410 partially filled buffer. Prevent lookup of 4-byte insns when
411 only VLE 2-byte insns are possible due to section size. Print
412 ".word" rather than ".long" for 2-byte leftovers.
413
327ef784
NC		 4142020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
415
416 PR 25641
417 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
418
1673df32
JB		 4192020-03-13 Jan Beulich <jbeulich@suse.com>
420
421 * i386-dis.c (X86_64_0D): Rename to ...
422 (X86_64_0E): ... this.
423
384f3689
L		 4242020-03-09 H.J. Lu <hongjiu.lu@intel.com>
425
426 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
427 * Makefile.in: Regenerated.
428
865e2027
JB		 4292020-03-09 Jan Beulich <jbeulich@suse.com>
430
431 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
432 3-operand pseudos.
433 * i386-tbl.h: Re-generate.
434
2f13234b
JB		 4352020-03-09 Jan Beulich <jbeulich@suse.com>
436
437 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
438 vprot*, vpsha*, and vpshl*.
439 * i386-tbl.h: Re-generate.
440
3fabc179
JB		 4412020-03-09 Jan Beulich <jbeulich@suse.com>
442
443 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
444 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
445 * i386-tbl.h: Re-generate.
446
3677e4c1
JB		 4472020-03-09 Jan Beulich <jbeulich@suse.com>
448
449 * i386-gen.c (set_bitfield): Ignore zero-length field names.
450 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
451 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
452 * i386-tbl.h: Re-generate.
453
4c4898e8
JB		 4542020-03-09 Jan Beulich <jbeulich@suse.com>
455
456 * i386-gen.c (struct template_arg, struct template_instance,
457 struct template_param, struct template, templates,
458 parse_template, expand_templates): New.
459 (process_i386_opcodes): Various local variables moved to
460 expand_templates. Call parse_template and expand_templates.
461 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
462 * i386-tbl.h: Re-generate.
463
bc49bfd8
JB		 4642020-03-06 Jan Beulich <jbeulich@suse.com>
465
466 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
467 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
468 register and memory source templates. Replace VexW= by VexW*
469 where applicable.
470 * i386-tbl.h: Re-generate.
471
4873e243
JB		 4722020-03-06 Jan Beulich <jbeulich@suse.com>
473
474 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
475 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
476 * i386-tbl.h: Re-generate.
477
672a349b
JB		 4782020-03-06 Jan Beulich <jbeulich@suse.com>
479
480 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
481 * i386-tbl.h: Re-generate.
482
4ed21b58
JB		 4832020-03-06 Jan Beulich <jbeulich@suse.com>
484
485 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
486 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
487 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
488 VexW0 on SSE2AVX variants.
489 (vmovq): Drop NoRex64 from XMM/XMM variants.
490 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
491 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
492 applicable use VexW0.
493 * i386-tbl.h: Re-generate.
494
643bb870
JB		 4952020-03-06 Jan Beulich <jbeulich@suse.com>
496
497 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
498 * i386-opc.h (Rex64): Delete.
499 (struct i386_opcode_modifier): Remove rex64 field.
500 * i386-opc.tbl (crc32): Drop Rex64.
501 Replace Rex64 with Size64 everywhere else.
502 * i386-tbl.h: Re-generate.
503
a23b33b3
JB		 5042020-03-06 Jan Beulich <jbeulich@suse.com>
505
506 * i386-dis.c (OP_E_memory): Exclude recording of used address
507 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
508 addressed memory operands for MPX insns.
509
a0497384
JB		 5102020-03-06 Jan Beulich <jbeulich@suse.com>
511
512 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
513 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
514 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
515 (ptwrite): Split into non-64-bit and 64-bit forms.
516 * i386-tbl.h: Re-generate.
517
b630c145
JB		 5182020-03-06 Jan Beulich <jbeulich@suse.com>
519
520 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
521 template.
522 * i386-tbl.h: Re-generate.
523
a847e322
JB		 5242020-03-04 Jan Beulich <jbeulich@suse.com>
525
526 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
527 (prefix_table): Move vmmcall here. Add vmgexit.
528 (rm_table): Replace vmmcall entry by prefix_table[] escape.
529 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
530 (cpu_flags): Add CpuSEV_ES entry.
531 * i386-opc.h (CpuSEV_ES): New.
532 (union i386_cpu_flags): Add cpusev_es field.
533 * i386-opc.tbl (vmgexit): New.
534 * i386-init.h, i386-tbl.h: Re-generate.
535
3cd7f3e3
L		 5362020-03-03 H.J. Lu <hongjiu.lu@intel.com>
537
538 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
539 with MnemonicSize.
540 * i386-opc.h (IGNORESIZE): New.
541 (DEFAULTSIZE): Likewise.
542 (IgnoreSize): Removed.
543 (DefaultSize): Likewise.
544 (MnemonicSize): New.
545 (i386_opcode_modifier): Replace ignoresize/defaultsize with
546 mnemonicsize.
547 * i386-opc.tbl (IgnoreSize): New.
548 (DefaultSize): Likewise.
549 * i386-tbl.h: Regenerated.
550
b8ba1385
SB		 5512020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
552
553 PR 25627
554 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
555 instructions.
556
10d97a0f
L		 5572020-03-03 H.J. Lu <hongjiu.lu@intel.com>
558
559 PR gas/25622
560 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
561 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
562 * i386-tbl.h: Regenerated.
563
dc1e8a47
AM		 5642020-02-26 Alan Modra <amodra@gmail.com>
565
566 * aarch64-asm.c: Indent labels correctly.
567 * aarch64-dis.c: Likewise.
568 * aarch64-gen.c: Likewise.
569 * aarch64-opc.c: Likewise.
570 * alpha-dis.c: Likewise.
571 * i386-dis.c: Likewise.
572 * nds32-asm.c: Likewise.
573 * nfp-dis.c: Likewise.
574 * visium-dis.c: Likewise.
575
265b4673
CZ		 5762020-02-25 Claudiu Zissulescu <claziss@gmail.com>
577
578 * arc-regs.h (int_vector_base): Make it available for all ARC
579 CPUs.
580
bd0cf5a6
NC		 5812020-02-20 Nelson Chu <nelson.chu@sifive.com>
582
583 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
584 changed.
585
fa164239
JW		 5862020-02-19 Nelson Chu <nelson.chu@sifive.com>
587
588 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
589 c.mv/c.li if rs1 is zero.
590
272a84b1
L		 5912020-02-17 H.J. Lu <hongjiu.lu@intel.com>
592
593 * i386-gen.c (cpu_flag_init): Replace CpuABM with
594 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
595 CPU_POPCNT_FLAGS.
596 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
597 * i386-opc.h (CpuABM): Removed.
598 (CpuPOPCNT): New.
599 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
600 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
601 popcnt. Remove CpuABM from lzcnt.
602 * i386-init.h: Regenerated.
603 * i386-tbl.h: Likewise.
604
1f730c46
JB		 6052020-02-17 Jan Beulich <jbeulich@suse.com>
606
607 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
608 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
609 VexW1 instead of open-coding them.
610 * i386-tbl.h: Re-generate.
611
c8f8eebc
JB		 6122020-02-17 Jan Beulich <jbeulich@suse.com>
613
614 * i386-opc.tbl (AddrPrefixOpReg): Define.
615 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
616 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
617 templates. Drop NoRex64.
618 * i386-tbl.h: Re-generate.
619
b9915cbc
JB		 6202020-02-17 Jan Beulich <jbeulich@suse.com>
621
622 PR gas/6518
623 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
624 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
625 into Intel syntax instance (with Unpsecified) and AT&T one
626 (without).
627 (vcvtneps2bf16): Likewise, along with folding the two so far
628 separate ones.
629 * i386-tbl.h: Re-generate.
630
ce504911
L		 6312020-02-16 H.J. Lu <hongjiu.lu@intel.com>
632
633 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
634 CPU_ANY_SSE4A_FLAGS.
635
dabec65d
AM		 6362020-02-17 Alan Modra <amodra@gmail.com>
637
638 * i386-gen.c (cpu_flag_init): Correct last change.
639
af5c13b0
L		 6402020-02-16 H.J. Lu <hongjiu.lu@intel.com>
641
642 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
643 CPU_ANY_SSE4_FLAGS.
644
6867aac0
L		 6452020-02-14 H.J. Lu <hongjiu.lu@intel.com>
646
647 * i386-opc.tbl (movsx): Remove Intel syntax comments.
648 (movzx): Likewise.
649
65fca059
JB		 6502020-02-14 Jan Beulich <jbeulich@suse.com>
651
652 PR gas/25438
653 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
654 destination for Cpu64-only variant.
655 (movzx): Fold patterns.
656 * i386-tbl.h: Re-generate.
657
7deea9aa
JB		 6582020-02-13 Jan Beulich <jbeulich@suse.com>
659
660 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
661 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
662 CPU_ANY_SSE4_FLAGS entry.
663 * i386-init.h: Re-generate.
664
6c0946d0
JB		 6652020-02-12 Jan Beulich <jbeulich@suse.com>
666
667 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
668 with Unspecified, making the present one AT&T syntax only.
669 * i386-tbl.h: Re-generate.
670
ddb56fe6
JB		 6712020-02-12 Jan Beulich <jbeulich@suse.com>
672
673 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
674 * i386-tbl.h: Re-generate.
675
5990e377
JB		 6762020-02-12 Jan Beulich <jbeulich@suse.com>
677
678 PR gas/24546
679 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
680 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
681 Amd64 and Intel64 templates.
682 (call, jmp): Likewise for far indirect variants. Dro
683 Unspecified.
684 * i386-tbl.h: Re-generate.
685
50128d0c
JB		 6862020-02-11 Jan Beulich <jbeulich@suse.com>
687
688 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
689 * i386-opc.h (ShortForm): Delete.
690 (struct i386_opcode_modifier): Remove shortform field.
691 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
692 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
693 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
694 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
695 Drop ShortForm.
696 * i386-tbl.h: Re-generate.
697
1e05b5c4
JB		 6982020-02-11 Jan Beulich <jbeulich@suse.com>
699
700 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
701 fucompi): Drop ShortForm from operand-less templates.
702 * i386-tbl.h: Re-generate.
703
2f5dd314
AM		 7042020-02-11 Alan Modra <amodra@gmail.com>
705
706 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
707 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
708 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
709 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
710 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
711
5aae9ae9
MM		 7122020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
713
714 * arm-dis.c (print_insn_cde): Define 'V' parse character.
715 (cde_opcodes): Add VCX* instructions.
716
4934a27c
MM		 7172020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
718 Matthew Malcomson <matthew.malcomson@arm.com>
719
720 * arm-dis.c (struct cdeopcode32): New.
721 (CDE_OPCODE): New macro.
722 (cde_opcodes): New disassembly table.
723 (regnames): New option to table.
724 (cde_coprocs): New global variable.
725 (print_insn_cde): New
726 (print_insn_thumb32): Use print_insn_cde.
727 (parse_arm_disassembler_options): Parse coprocN args.
728
4b5aaf5f
L		 7292020-02-10 H.J. Lu <hongjiu.lu@intel.com>
730
731 PR gas/25516
732 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
733 with ISA64.
734 * i386-opc.h (AMD64): Removed.
735 (Intel64): Likewose.
736 (AMD64): New.
737 (INTEL64): Likewise.
738 (INTEL64ONLY): Likewise.
739 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
740 * i386-opc.tbl (Amd64): New.
741 (Intel64): Likewise.
742 (Intel64Only): Likewise.
743 Replace AMD64 with Amd64. Update sysenter/sysenter with
744 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
745 * i386-tbl.h: Regenerated.
746
9fc0b501
SB		 7472020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
748
749 PR 25469
750 * z80-dis.c: Add support for GBZ80 opcodes.
751
c5d7be0c
AM		 7522020-02-04 Alan Modra <amodra@gmail.com>
753
754 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
755
44e4546f
AM		 7562020-02-03 Alan Modra <amodra@gmail.com>
757
758 * m32c-ibld.c: Regenerate.
759
b2b1453a
AM		 7602020-02-01 Alan Modra <amodra@gmail.com>
761
762 * frv-ibld.c: Regenerate.
763
4102be5c
JB		 7642020-01-31 Jan Beulich <jbeulich@suse.com>
765
766 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
767 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
768 (OP_E_memory): Replace xmm_mdq_mode case label by
769 vex_scalar_w_dq_mode one.
770 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
771
825bd36c
JB		 7722020-01-31 Jan Beulich <jbeulich@suse.com>
773
774 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
775 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
776 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
777 (intel_operand_size): Drop vex_w_dq_mode case label.
778
c3036ed0
RS		 7792020-01-31 Richard Sandiford <richard.sandiford@arm.com>
780
781 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
782 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
783
0c115f84
AM		 7842020-01-30 Alan Modra <amodra@gmail.com>
785
786 * m32c-ibld.c: Regenerate.
787
bd434cc4
JM		 7882020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
789
790 * bpf-opc.c: Regenerate.
791
aeab2b26
JB		 7922020-01-30 Jan Beulich <jbeulich@suse.com>
793
794 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
795 (dis386): Use them to replace C2/C3 table entries.
796 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
797 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
798 ones. Use Size64 instead of DefaultSize on Intel64 ones.
799 * i386-tbl.h: Re-generate.
800
62b3f548
JB		 8012020-01-30 Jan Beulich <jbeulich@suse.com>
802
803 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
804 forms.
805 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
806 DefaultSize.
807 * i386-tbl.h: Re-generate.
808
1bd8ae10
AM		 8092020-01-30 Alan Modra <amodra@gmail.com>
810
811 * tic4x-dis.c (tic4x_dp): Make unsigned.
812
bc31405e
L		 8132020-01-27 H.J. Lu <hongjiu.lu@intel.com>
814 Jan Beulich <jbeulich@suse.com>
815
816 PR binutils/25445
817 * i386-dis.c (MOVSXD_Fixup): New function.
818 (movsxd_mode): New enum.
819 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
820 (intel_operand_size): Handle movsxd_mode.
821 (OP_E_register): Likewise.
822 (OP_G): Likewise.
823 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
824 register on movsxd. Add movsxd with 16-bit destination register
825 for AMD64 and Intel64 ISAs.
826 * i386-tbl.h: Regenerated.
827
7568c93b
TC		 8282020-01-27 Tamar Christina <tamar.christina@arm.com>
829
830 PR 25403
831 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
832 * aarch64-asm-2.c: Regenerate
833 * aarch64-dis-2.c: Likewise.
834 * aarch64-opc-2.c: Likewise.
835
c006a730
JB		 8362020-01-21 Jan Beulich <jbeulich@suse.com>
837
838 * i386-opc.tbl (sysret): Drop DefaultSize.
839 * i386-tbl.h: Re-generate.
840
c906a69a
JB		 8412020-01-21 Jan Beulich <jbeulich@suse.com>
842
843 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
844 Dword.
845 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
846 * i386-tbl.h: Re-generate.
847
26916852
NC		 8482020-01-20 Nick Clifton <nickc@redhat.com>
849
850 * po/de.po: Updated German translation.
851 * po/pt_BR.po: Updated Brazilian Portuguese translation.
852 * po/uk.po: Updated Ukranian translation.
853
4d6cbb64
AM		 8542020-01-20 Alan Modra <amodra@gmail.com>
855
856 * hppa-dis.c (fput_const): Remove useless cast.
857
2bddb71a
AM		 8582020-01-20 Alan Modra <amodra@gmail.com>
859
860 * arm-dis.c (print_insn_arm): Wrap 'T' value.
861
1b1bb2c6
NC		 8622020-01-18 Nick Clifton <nickc@redhat.com>
863
864 * configure: Regenerate.
865 * po/opcodes.pot: Regenerate.
866
ae774686
NC		 8672020-01-18 Nick Clifton <nickc@redhat.com>
868
869 Binutils 2.34 branch created.
870
07f1f3aa
CB		 8712020-01-17 Christian Biesinger <cbiesinger@google.com>
872
873 * opintl.h: Fix spelling error (seperate).
874
42e04b36
L		 8752020-01-17 H.J. Lu <hongjiu.lu@intel.com>
876
877 * i386-opc.tbl: Add {vex} pseudo prefix.
878 * i386-tbl.h: Regenerated.
879
2da2eaf4
AV		 8802020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
881
882 PR 25376
883 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
884 (neon_opcodes): Likewise.
885 (select_arm_features): Make sure we enable MVE bits when selecting
886 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
887 any architecture.
888
d0849eed
JB		 8892020-01-16 Jan Beulich <jbeulich@suse.com>
890
891 * i386-opc.tbl: Drop stale comment from XOP section.
892
9cf70a44
JB		 8932020-01-16 Jan Beulich <jbeulich@suse.com>
894
895 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
896 (extractps): Add VexWIG to SSE2AVX forms.
897 * i386-tbl.h: Re-generate.
898
4814632e
JB		 8992020-01-16 Jan Beulich <jbeulich@suse.com>
900
901 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
902 Size64 from and use VexW1 on SSE2AVX forms.
903 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
904 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
905 * i386-tbl.h: Re-generate.
906
aad09917
AM		 9072020-01-15 Alan Modra <amodra@gmail.com>
908
909 * tic4x-dis.c (tic4x_version): Make unsigned long.
910 (optab, optab_special, registernames): New file scope vars.
911 (tic4x_print_register): Set up registernames rather than
912 malloc'd registertable.
913 (tic4x_disassemble): Delete optable and optable_special. Use
914 optab and optab_special instead. Throw away old optab,
915 optab_special and registernames when info->mach changes.
916
7a6bf3be
SB		 9172020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
918
919 PR 25377
920 * z80-dis.c (suffix): Use .db instruction to generate double
921 prefix.
922
ca1eaac0
AM		 9232020-01-14 Alan Modra <amodra@gmail.com>
924
925 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
926 values to unsigned before shifting.
927
1d67fe3b
TT		 9282020-01-13 Thomas Troeger <tstroege@gmx.de>
929
930 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
931 flow instructions.
932 (print_insn_thumb16, print_insn_thumb32): Likewise.
933 (print_insn): Initialize the insn info.
934 * i386-dis.c (print_insn): Initialize the insn info fields, and
935 detect jumps.
936
5e4f7e05
CZ		 9372012-01-13 Claudiu Zissulescu <claziss@gmail.com>
938
939 * arc-opc.c (C_NE): Make it required.
940
b9fe6b8a
CZ		 9412012-01-13 Claudiu Zissulescu <claziss@gmail.com>
942
943 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
944 reserved register name.
945
90dee485
AM		 9462020-01-13 Alan Modra <amodra@gmail.com>
947
948 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
949 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
950
febda64f
AM		 9512020-01-13 Alan Modra <amodra@gmail.com>
952
953 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
954 result of wasm_read_leb128 in a uint64_t and check that bits
955 are not lost when copying to other locals. Use uint32_t for
956 most locals. Use PRId64 when printing int64_t.
957
df08b588
AM		 9582020-01-13 Alan Modra <amodra@gmail.com>
959
960 * score-dis.c: Formatting.
961 * score7-dis.c: Formatting.
962
b2c759ce
AM		 9632020-01-13 Alan Modra <amodra@gmail.com>
964
965 * score-dis.c (print_insn_score48): Use unsigned variables for
966 unsigned values. Don't left shift negative values.
967 (print_insn_score32): Likewise.
968 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
969
5496abe1
AM		 9702020-01-13 Alan Modra <amodra@gmail.com>
971
972 * tic4x-dis.c (tic4x_print_register): Remove dead code.
973
202e762b
AM		 9742020-01-13 Alan Modra <amodra@gmail.com>
975
976 * fr30-ibld.c: Regenerate.
977
7ef412cf
AM		 9782020-01-13 Alan Modra <amodra@gmail.com>
979
980 * xgate-dis.c (print_insn): Don't left shift signed value.
981 (ripBits): Formatting, use 1u.
982
7f578b95
AM		 9832020-01-10 Alan Modra <amodra@gmail.com>
984
985 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
986 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
987
441af85b
AM		 9882020-01-10 Alan Modra <amodra@gmail.com>
989
990 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
991 and XRREG value earlier to avoid a shift with negative exponent.
992 * m10200-dis.c (disassemble): Similarly.
993
bce58db4
NC		 9942020-01-09 Nick Clifton <nickc@redhat.com>
995
996 PR 25224
997 * z80-dis.c (ld_ii_ii): Use correct cast.
998
40c75bc8
SB		 9992020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1000
1001 PR 25224
1002 * z80-dis.c (ld_ii_ii): Use character constant when checking
1003 opcode byte value.
1004
d835a58b
JB		 10052020-01-09 Jan Beulich <jbeulich@suse.com>
1006
1007 * i386-dis.c (SEP_Fixup): New.
1008 (SEP): Define.
1009 (dis386_twobyte): Use it for sysenter/sysexit.
1010 (enum x86_64_isa): Change amd64 enumerator to value 1.
1011 (OP_J): Compare isa64 against intel64 instead of amd64.
1012 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1013 forms.
1014 * i386-tbl.h: Re-generate.
1015
030a2e78
AM		 10162020-01-08 Alan Modra <amodra@gmail.com>
1017
1018 * z8k-dis.c: Include libiberty.h
1019 (instr_data_s): Make max_fetched unsigned.
1020 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1021 Don't exceed byte_info bounds.
1022 (output_instr): Make num_bytes unsigned.
1023 (unpack_instr): Likewise for nibl_count and loop.
1024 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1025 idx unsigned.
1026 * z8k-opc.h: Regenerate.
1027
bb82aefe
SV		 10282020-01-07 Shahab Vahedi <shahab@synopsys.com>
1029
1030 * arc-tbl.h (llock): Use 'LLOCK' as class.
1031 (llockd): Likewise.
1032 (scond): Use 'SCOND' as class.
1033 (scondd): Likewise.
1034 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1035 (scondd): Likewise.
1036
cc6aa1a6
AM		 10372020-01-06 Alan Modra <amodra@gmail.com>
1038
1039 * m32c-ibld.c: Regenerate.
1040
660e62b1
AM		 10412020-01-06 Alan Modra <amodra@gmail.com>
1042
1043 PR 25344
1044 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1045 Peek at next byte to prevent recursion on repeated prefix bytes.
1046 Ensure uninitialised "mybuf" is not accessed.
1047 (print_insn_z80): Don't zero n_fetch and n_used here,..
1048 (print_insn_z80_buf): ..do it here instead.
1049
c9ae58fe
AM		 10502020-01-04 Alan Modra <amodra@gmail.com>
1051
1052 * m32r-ibld.c: Regenerate.
1053
5f57d4ec
AM		 10542020-01-04 Alan Modra <amodra@gmail.com>
1055
1056 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1057
2c5c1196
AM		 10582020-01-04 Alan Modra <amodra@gmail.com>
1059
1060 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1061
2e98c6c5
AM		 10622020-01-04 Alan Modra <amodra@gmail.com>
1063
1064 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1065
567dfba2
JB		 10662020-01-03 Jan Beulich <jbeulich@suse.com>
1067
5437a02a
JB		 1068 * aarch64-tbl.h (aarch64_opcode_table): Use
1069 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1070
10712020-01-03 Jan Beulich <jbeulich@suse.com>
1072
1073 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 1074 forms of SUDOT and USDOT.
1075
8c45011a
JB		 10762020-01-03 Jan Beulich <jbeulich@suse.com>
1077
5437a02a 1078 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 1079 uzip{1,2}.
1080 * opcodes/aarch64-dis-2.c: Re-generate.
1081
f4950f76
JB		 10822020-01-03 Jan Beulich <jbeulich@suse.com>
1083
5437a02a 1084 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 1085 FMMLA encoding.
1086 * opcodes/aarch64-dis-2.c: Re-generate.
1087
6655dba2
SB		 10882020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1089
1090 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1091
b14ce8bf
AM		 10922020-01-01 Alan Modra <amodra@gmail.com>
1093
1094 Update year range in copyright notice of all files.
1095
0b114740 1096For older changes see ChangeLog-2019
3499769a 1097\f
0b114740 1098Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 1099
1100Copying and distribution of this file, with or without modification,
1101are permitted in any medium without royalty provided the copyright
1102notice and this notice are preserved.
1103
1104Local Variables:
1105mode: change-log
1106left-margin: 8
1107fill-column: 74
1108version-control: never
1109End:
GDB Binutils - Deliverables
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