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2005-01-19 Fred Fish <fnf@specifixinc.com>
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
e38bc3b5
NC		 12005-01-17 Andrew Stubbs <andrew.stubbs@st.com>
2
3 * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
4 (inheritance diagram): Add missing edge.
5 (arch_sh1_up): Rename arch_sh_up to match external name to make life
6 easier for the testsuite.
7 (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
8 (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
9 (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
10 arch_sh2a_or_sh4_up child.
11 (sh_table): Do renaming as above.
12 Correct comment for ldc.l for gas testsuite to read.
13 Remove rogue mul.l from sh1 (duplicate of the one for sh2).
14 Correct comments for movy.w and movy.l for gas testsuite to read.
15 Correct comments for fmov.d and fmov.s for gas testsuite to read.
16
9df48ba9
L		 172005-01-12 H.J. Lu <hongjiu.lu@intel.com>
18
19 * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
20
2033b4b9
L		 212005-01-12 H.J. Lu <hongjiu.lu@intel.com>
22
23 * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
24
0bcb06d2
AS		 252005-01-10 Andreas Schwab <schwab@suse.de>
26
27 * disassemble.c (disassemble_init_for_target) <case
28 bfd_arch_ia64>: Set skip_zeroes to 16.
29 <case bfd_arch_tic4x>: Set skip_zeroes to 32.
30
47add74d
TL		 312004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
32
33 * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
34
246f4c05
SS		 352004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
36
37 * avr-dis.c: Prettyprint. Added printing of symbol names in all
38 memory references. Convert avr_operand() to C90 formatting.
39
0e1200e5
TL		 402004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
41
42 * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
43
89a649f7
TL		 442004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
45
46 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
47 (no_op_insn): Initialize array with instructions that have no
48 operands.
49 * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
50
6255809c
RE		 512004-11-29 Richard Earnshaw <rearnsha@arm.com>
52
53 * arm-dis.c: Correct top-level comment.
54
2fbad815
RE		 552004-11-27 Richard Earnshaw <rearnsha@arm.com>
56
57 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
58 architecuture defining the insn.
59 (arm_opcodes, thumb_opcodes): Delete. Move to ...
6b8725b9
RE		 60 * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
61 field.
2fbad815
RE		 62 Also include opcode/arm.h.
63 * Makefile.am (arm-dis.lo): Update dependency list.
64 * Makefile.in: Regenerate.
65
d81acc42
NC		 662004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
67
68 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
69 reflect the change to the short immediate syntax.
70
ca4f2377
AM		 712004-11-19 Alan Modra <amodra@bigpond.net.au>
72
5da8bf1b
AM		 73 * or32-opc.c (debug): Warning fix.
74 * po/POTFILES.in: Regenerate.
75
ca4f2377
AM		 76 * maxq-dis.c: Formatting.
77 (print_insn): Warning fix.
78
b7693d02
DJ		 792004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
80
81 * arm-dis.c (WORD_ADDRESS): Define.
82 (print_insn): Use it. Correct big-endian end-of-section handling.
83
300dac7e
NC		 842004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
85 Vineet Sharma <vineets@noida.hcltech.com>
86
87 * maxq-dis.c: New file.
88 * disassemble.c (ARCH_maxq): Define.
89 (disassembler): Add 'print_insn_maxq_little' for handling maxq
90 instructions..
91 * configure.in: Add case for bfd_maxq_arch.
92 * configure: Regenerate.
93 * Makefile.am: Add support for maxq-dis.c
94 * Makefile.in: Regenerate.
95 * aclocal.m4: Regenerate.
96
42048ee7
TL		 972004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
98
99 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
100 mode.
101 * crx-dis.c: Likewise.
102
bd21e58e
HPN		 1032004-11-04 Hans-Peter Nilsson <hp@axis.com>
104
105 Generally, handle CRISv32.
106 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
107 (struct cris_disasm_data): New type.
108 (format_reg, format_hex, cris_constraint, print_flags)
109 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
110 callers changed.
111 (format_sup_reg, print_insn_crisv32_with_register_prefix)
112 (print_insn_crisv32_without_register_prefix)
113 (print_insn_crisv10_v32_with_register_prefix)
114 (print_insn_crisv10_v32_without_register_prefix)
115 (cris_parse_disassembler_options): New functions.
116 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
117 parameter. All callers changed.
118 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
119 failure.
120 (cris_constraint) <case 'Y', 'U'>: New cases.
121 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
122 for constraint 'n'.
123 (print_with_operands) <case 'Y'>: New case.
124 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
125 <case 'N', 'Y', 'Q'>: New cases.
126 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
127 (print_insn_cris_with_register_prefix)
128 (print_insn_cris_without_register_prefix): Call
129 cris_parse_disassembler_options.
130 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
131 for CRISv32 and the size of immediate operands. New v32-only
132 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
133 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
134 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
135 Change brp to be v3..v10.
136 (cris_support_regs): New vector.
137 (cris_opcodes): Update head comment. New format characters '[',
138 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
139 Add new opcodes for v32 and adjust existing opcodes to accommodate
140 differences to earlier variants.
141 (cris_cond15s): New vector.
142
9306ca4a
JB		 1432004-11-04 Jan Beulich <jbeulich@novell.com>
144
145 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
146 (indirEb): Remove.
147 (Mp): Use f_mode rather than none at all.
148 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
149 replaces what previously was x_mode; x_mode now means 128-bit SSE
150 operands.
151 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
152 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
153 pinsrw's second operand is Edqw.
154 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
155 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
156 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
157 mode when an operand size override is present or always suffixing.
158 More instructions will need to be added to this group.
159 (putop): Handle new macro chars 'C' (short/long suffix selector),
160 'I' (Intel mode override for following macro char), and 'J' (for
161 adding the 'l' prefix to far branches in AT&T mode). When an
162 alternative was specified in the template, honor macro character when
163 specified for Intel mode.
164 (OP_E): Handle new *_mode values. Correct pointer specifications for
165 memory operands. Consolidate output of index register.
166 (OP_G): Handle new *_mode values.
167 (OP_I): Handle const_1_mode.
168 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
169 respective opcode prefix bits have been consumed.
170 (OP_EM, OP_EX): Provide some default handling for generating pointer
171 specifications.
172
f39c96a9
TL		 1732004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
174
175 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
176 COP_INST macro.
177
812337be
TL		 1782004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
179
180 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
181 (getregliststring): Support HI/LO and user registers.
182 * crx-opc.c (crx_instruction): Update data structure according to the
183 rearrangement done in CRX opcode header file.
184 (crx_regtab): Likewise.
185 (crx_optab): Likewise.
186 (crx_instruction): Reorder load/stor instructions, remove unsupported
187 formats.
188 support new Co-Processor instruction 'cpi'.
189
4030fa5a
NC		 1902004-10-27 Nick Clifton <nickc@redhat.com>
191
192 * opcodes/iq2000-asm.c: Regenerate.
193 * opcodes/iq2000-desc.c: Regenerate.
194 * opcodes/iq2000-desc.h: Regenerate.
195 * opcodes/iq2000-dis.c: Regenerate.
196 * opcodes/iq2000-ibld.c: Regenerate.
197 * opcodes/iq2000-opc.c: Regenerate.
198 * opcodes/iq2000-opc.h: Regenerate.
199
fc3d45e8
TL		 2002004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
201
202 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
203 us4, us5 (respectively).
204 Remove unsupported 'popa' instruction.
205 Reverse operands order in store co-processor instructions.
206
3c55da70
AM		 2072004-10-15 Alan Modra <amodra@bigpond.net.au>
208
209 * Makefile.am: Run "make dep-am"
210 * Makefile.in: Regenerate.
211
7fa3d080
BW		 2122004-10-12 Bob Wilson <bob.wilson@acm.org>
213
214 * xtensa-dis.c: Use ISO C90 formatting.
215
e612bb4d
AM		 2162004-10-09 Alan Modra <amodra@bigpond.net.au>
217
218 * ppc-opc.c: Revert 2004-09-09 change.
219
43cd72b9
BW		 2202004-10-07 Bob Wilson <bob.wilson@acm.org>
221
222 * xtensa-dis.c (state_names): Delete.
223 (fetch_data): Use xtensa_isa_maxlength.
224 (print_xtensa_operand): Replace operand parameter with opcode/operand
225 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
226 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
227 instruction bundles. Use xmalloc instead of malloc.
228
bbac1f2a
NC		 2292004-10-07 David Gibson <david@gibson.dropbear.id.au>
230
231 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
232 initializers.
233
48c9f030
NC		 2342004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
235
236 * crx-opc.c (crx_instruction): Support Co-processor insns.
237 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
238 (getregliststring): Change function to use the above enum.
239 (print_arg): Handle CO-Processor insns.
240 (crx_cinvs): Add 'b' option to invalidate the branch-target
241 cache.
242
12c64a4e
AH		 2432004-10-06 Aldy Hernandez <aldyh@redhat.com>
244
245 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
246 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
247 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
248 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
249 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
250
14127cc4
NC		 2512004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
252
253 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
254 rather than add it.
255
0dd132b6
NC		 2562004-09-30 Paul Brook <paul@codesourcery.com>
257
258 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
259 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
260
3f85e526
L		 2612004-09-17 H.J. Lu <hongjiu.lu@intel.com>
262
263 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
264 (CONFIG_STATUS_DEPENDENCIES): New.
265 (Makefile): Removed.
266 (config.status): Likewise.
267 * Makefile.in: Regenerated.
268
8ae85421
AM		 2692004-09-17 Alan Modra <amodra@bigpond.net.au>
270
271 * Makefile.am: Run "make dep-am".
272 * Makefile.in: Regenerate.
273 * aclocal.m4: Regenerate.
274 * configure: Regenerate.
275 * po/POTFILES.in: Regenerate.
276 * po/opcodes.pot: Regenerate.
277
24443139
AS		 2782004-09-11 Andreas Schwab <schwab@suse.de>
279
280 * configure: Rebuild.
281
2a309db0
AM		 2822004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
283
284 * ppc-opc.c (L): Make this field not optional.
285
42851540
NC		 2862004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
287
288 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
289 Fix parameter to 'm[t|f]csr' insns.
290
979273e3
NN		 2912004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
292
293 * configure.in: Autoupdate to autoconf 2.59.
294 * aclocal.m4: Rebuild with aclocal 1.4p6.
295 * configure: Rebuild with autoconf 2.59.
296 * Makefile.in: Rebuild with automake 1.4p6 (picking up
297 bfd changes for autoconf 2.59 on the way).
298 * config.in: Rebuild with autoheader 2.59.
299
ac28a1cb
RS		 3002004-08-27 Richard Sandiford <rsandifo@redhat.com>
301
302 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
303
30d1c836
ML		 3042004-07-30 Michal Ludvig <mludvig@suse.cz>
305
306 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
307 (GRPPADLCK2): New define.
308 (twobyte_has_modrm): True for 0xA6.
309 (grps): GRPPADLCK2 for opcode 0xA6.
310
0b0ac059
AO		 3112004-07-29 Alexandre Oliva <aoliva@redhat.com>
312
313 Introduce SH2a support.
314 * sh-opc.h (arch_sh2a_base): Renumber.
315 (arch_sh2a_nofpu_base): Remove.
316 (arch_sh_base_mask): Adjust.
317 (arch_opann_mask): New.
318 (arch_sh2a, arch_sh2a_nofpu): Adjust.
319 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
320 (sh_table): Adjust whitespace.
321 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
322 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
323 instruction list throughout.
324 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
325 of arch_sh2a in instruction list throughout.
326 (arch_sh2e_up): Accomodate above changes.
327 (arch_sh2_up): Ditto.
328 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
329 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
330 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
331 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
332 * sh-opc.h (arch_sh2a_nofpu): New.
333 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
334 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
335 instruction.
336 2004-01-20 DJ Delorie <dj@redhat.com>
337 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
338 2003-12-29 DJ Delorie <dj@redhat.com>
339 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
340 sh_opcode_info, sh_table): Add sh2a support.
341 (arch_op32): New, to tag 32-bit opcodes.
342 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
343 2003-12-02 Michael Snyder <msnyder@redhat.com>
344 * sh-opc.h (arch_sh2a): Add.
345 * sh-dis.c (arch_sh2a): Handle.
346 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
347
670ec21d
NC		 3482004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
349
350 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
351
ed049af3
NC		 3522004-07-22 Nick Clifton <nickc@redhat.com>
353
354 PR/280
355 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
356 insns - this is done by objdump itself.
357 * h8500-dis.c (print_insn_h8500): Likewise.
358
20f0a1fc
NC		 3592004-07-21 Jan Beulich <jbeulich@novell.com>
360
361 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
362 regardless of address size prefix in effect.
363 (ptr_reg): Size or address registers does not depend on rex64, but
364 on the presence of an address size override.
365 (OP_MMX): Use rex.x only for xmm registers.
366 (OP_EM): Use rex.z only for xmm registers.
367
6f14957b
MR		 3682004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
369
370 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
371 move/branch operations to the bottom so that VR5400 multimedia
372 instructions take precedence in disassembly.
373
1586d91e
MR		 3742004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
375
376 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
377 ISA-specific "break" encoding.
378
982de27a
NC		 3792004-07-13 Elvis Chiang <elvisfb@gmail.com>
380
381 * arm-opc.h: Fix typo in comment.
382
4300ab10
AS		 3832004-07-11 Andreas Schwab <schwab@suse.de>
384
385 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
386
8577e690
AS		 3872004-07-09 Andreas Schwab <schwab@suse.de>
388
389 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
390
1fe1f39c
NC		 3912004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
392
393 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
394 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
395 (crx-dis.lo): New target.
396 (crx-opc.lo): Likewise.
397 * Makefile.in: Regenerate.
398 * configure.in: Handle bfd_crx_arch.
399 * configure: Regenerate.
400 * crx-dis.c: New file.
401 * crx-opc.c: New file.
402 * disassemble.c (ARCH_crx): Define.
403 (disassembler): Handle ARCH_crx.
404
7a33b495
JW		 4052004-06-29 James E Wilson <wilson@specifixinc.com>
406
407 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
408 * ia64-asmtab.c: Regnerate.
409
98e69875
AM		 4102004-06-28 Alan Modra <amodra@bigpond.net.au>
411
412 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
413 (extract_fxm): Don't test dialect.
414 (XFXFXM_MASK): Include the power4 bit.
415 (XFXM): Add p4 param.
416 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
417
a53b85e2
AO		 4182004-06-27 Alexandre Oliva <aoliva@redhat.com>
419
420 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
421 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
422
d0618d1c
AM		 4232004-06-26 Alan Modra <amodra@bigpond.net.au>
424
425 * ppc-opc.c (BH, XLBH_MASK): Define.
426 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
427
1d9f512f
AM		 4282004-06-24 Alan Modra <amodra@bigpond.net.au>
429
430 * i386-dis.c (x_mode): Comment.
431 (two_source_ops): File scope.
432 (float_mem): Correct fisttpll and fistpll.
433 (float_mem_mode): New table.
434 (dofloat): Use it.
435 (OP_E): Correct intel mode PTR output.
436 (ptr_reg): Use open_char and close_char.
437 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
438 operands. Set two_source_ops.
439
52886d70
AM		 4402004-06-15 Alan Modra <amodra@bigpond.net.au>
441
442 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
443 instead of _raw_size.
444
bad9ceea
JJ		 4452004-06-08 Jakub Jelinek <jakub@redhat.com>
446
447 * ia64-gen.c (in_iclass): Handle more postinc st
448 and ld variants.
449 * ia64-asmtab.c: Rebuilt.
450
0451f5df
MS		 4512004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
452
453 * s390-opc.txt: Correct architecture mask for some opcodes.
454 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
455 in the esa mode as well.
456
f6f9408f
JR		 4572004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
458
459 * sh-dis.c (target_arch): Make unsigned.
460 (print_insn_sh): Replace (most of) switch with a call to
461 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
462 * sh-opc.h: Redefine architecture flags values.
463 Add sh3-nommu architecture.
464 Reorganise <arch>_up macros so they make more visual sense.
465 (SH_MERGE_ARCH_SET): Define new macro.
466 (SH_VALID_BASE_ARCH_SET): Likewise.
467 (SH_VALID_MMU_ARCH_SET): Likewise.
468 (SH_VALID_CO_ARCH_SET): Likewise.
469 (SH_VALID_ARCH_SET): Likewise.
470 (SH_MERGE_ARCH_SET_VALID): Likewise.
471 (SH_ARCH_SET_HAS_FPU): Likewise.
472 (SH_ARCH_SET_HAS_DSP): Likewise.
473 (SH_ARCH_UNKNOWN_ARCH): Likewise.
474 (sh_get_arch_from_bfd_mach): Add prototype.
475 (sh_get_arch_up_from_bfd_mach): Likewise.
476 (sh_get_bfd_mach_from_arch_set): Likewise.
477 (sh_merge_bfd_arc): Likewise.
478
be8c092b
NC		 4792004-05-24 Peter Barada <peter@the-baradas.com>
480
481 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
482 into new match_insn_m68k function. Loop over canidate
483 matches and select first that completely matches.
484 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
485 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
486 to verify addressing for MAC/EMAC.
487 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
488 reigster halves since 'fpu' and 'spl' look misleading.
489 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
490 * m68k-opc.c: Rearragne mac/emac cases to use longest for
491 first, tighten up match masks.
492 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
493 'size' from special case code in print_insn_m68k to
494 determine decode size of insns.
495
a30e9cc4
AM		 4962004-05-19 Alan Modra <amodra@bigpond.net.au>
497
498 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
499 well as when -mpower4.
500
9598fbe5
NC		 5012004-05-13 Nick Clifton <nickc@redhat.com>
502
503 * po/fr.po: Updated French translation.
504
6b6e92f4
NC		 5052004-05-05 Peter Barada <peter@the-baradas.com>
506
507 * m68k-dis.c(print_insn_m68k): Add new chips, use core
508 variants in arch_mask. Only set m68881/68851 for 68k chips.
509 * m68k-op.c: Switch from ColdFire chips to core variants.
510
a404d431
AM		 5112004-05-05 Alan Modra <amodra@bigpond.net.au>
512
a30e9cc4 513 PR 147.
a404d431
AM		 514 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
515
f3806e43
BE		 5162004-04-29 Ben Elliston <bje@au.ibm.com>
517
520ceea4
BE		 518 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
519 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
f3806e43 520
1f1799d5
KK		 5212004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
522
523 * sh-dis.c (print_insn_sh): Print the value in constant pool
524 as a symbol if it looks like a symbol.
525
fd99574b
NC		 5262004-04-22 Peter Barada <peter@the-baradas.com>
527
528 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
529 appropriate ColdFire architectures.
530 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
531 mask addressing.
532 Add EMAC instructions, fix MAC instructions. Remove
533 macmw/macml/msacmw/msacml instructions since mask addressing now
534 supported.
535
b4781d44
JJ		 5362004-04-20 Jakub Jelinek <jakub@redhat.com>
537
538 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
539 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
540 suffix. Use fmov*x macros, create all 3 fpsize variants in one
541 macro. Adjust all users.
542
91809fda
NC		 5432004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
544
545 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
546 separately.
547
f4453dfa
NC		 5482004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
549
550 * m32r-asm.c: Regenerate.
551
9b0de91a
SS		 5522004-03-29 Stan Shebs <shebs@apple.com>
553
554 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
555 used.
556
e20c0b3d
AM		 5572004-03-19 Alan Modra <amodra@bigpond.net.au>
558
559 * aclocal.m4: Regenerate.
560 * config.in: Regenerate.
561 * configure: Regenerate.
562 * po/POTFILES.in: Regenerate.
563 * po/opcodes.pot: Regenerate.
564
fdd12ef3
AM		 5652004-03-16 Alan Modra <amodra@bigpond.net.au>
566
567 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
568 PPC_OPERANDS_GPR_0.
569 * ppc-opc.c (RA0): Define.
570 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
571 (RAOPT): Rename from RAO. Update all uses.
a9c3619e 572 (powerpc_opcodes): Use RA0 as appropriate.
fdd12ef3 573
2dc111b3 5742004-03-15 Aldy Hernandez <aldyh@redhat.com>
fdd12ef3
AM		 575
576 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
2dc111b3 577
7bfeee7b
AM		 5782004-03-15 Alan Modra <amodra@bigpond.net.au>
579
580 * sparc-dis.c (print_insn_sparc): Update getword prototype.
581
7ffdda93
ML		 5822004-03-12 Michal Ludvig <mludvig@suse.cz>
583
584 * i386-dis.c (GRPPLOCK): Delete.
7bfeee7b 585 (grps): Delete GRPPLOCK entry.
7ffdda93 586
cc0ec051
AM		 5872004-03-12 Alan Modra <amodra@bigpond.net.au>
588
589 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
590 (M, Mp): Use OP_M.
591 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
592 (GRPPADLCK): Define.
593 (dis386): Use NOP_Fixup on "nop".
594 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
595 (twobyte_has_modrm): Set for 0xa7.
596 (padlock_table): Delete. Move to..
597 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
598 and clflush.
599 (print_insn): Revert PADLOCK_SPECIAL code.
600 (OP_E): Delete sfence, lfence, mfence checks.
601
4fd61dcb
JJ		 6022004-03-12 Jakub Jelinek <jakub@redhat.com>
603
604 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
605 (INVLPG_Fixup): New function.
606 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
607
0f10071e
ML		 6082004-03-12 Michal Ludvig <mludvig@suse.cz>
609
610 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
611 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
612 (padlock_table): New struct with PadLock instructions.
613 (print_insn): Handle PADLOCK_SPECIAL.
614
c02908d2
AM		 6152004-03-12 Alan Modra <amodra@bigpond.net.au>
616
617 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
618 (OP_E): Twiddle clflush to sfence here.
619
d5bb7600
NC		 6202004-03-08 Nick Clifton <nickc@redhat.com>
621
622 * po/de.po: Updated German translation.
623
ae51a426
JR		 6242003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
625
626 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
627 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
628 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
629 accordingly.
630
676a64f4
RS		 6312004-03-01 Richard Sandiford <rsandifo@redhat.com>
632
633 * frv-asm.c: Regenerate.
634 * frv-desc.c: Regenerate.
635 * frv-desc.h: Regenerate.
636 * frv-dis.c: Regenerate.
637 * frv-ibld.c: Regenerate.
638 * frv-opc.c: Regenerate.
639 * frv-opc.h: Regenerate.
640
c7a48b9a
RS		 6412004-03-01 Richard Sandiford <rsandifo@redhat.com>
642
643 * frv-desc.c, frv-opc.c: Regenerate.
644
8ae0baa2
RS		 6452004-03-01 Richard Sandiford <rsandifo@redhat.com>
646
647 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
648
ce11586c
JR		 6492004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
650
651 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
652 Also correct mistake in the comment.
653
6a5709a5
JR		 6542004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
655
656 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
657 ensure that double registers have even numbers.
658 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
659 that reserved instruction 0xfffd does not decode the same
660 as 0xfdfd (ftrv).
661 * sh-opc.h: Add REG_N_D nibble type and use it whereever
662 REG_N refers to a double register.
663 Add REG_N_B01 nibble type and use it instead of REG_NM
664 in ftrv.
665 Adjust the bit patterns in a few comments.
666
e5d2b64f 6672004-02-25 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 668
669 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
e5d2b64f 670
1f04b05f
AH		 6712004-02-20 Aldy Hernandez <aldyh@redhat.com>
672
673 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
674
2f3b8700
AH		 6752004-02-20 Aldy Hernandez <aldyh@redhat.com>
676
677 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
678
f0b26da6 6792004-02-20 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 680
681 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
682 mtivor32, mtivor33, mtivor34.
f0b26da6 683
23d59c56 6842004-02-19 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 685
686 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
23d59c56 687
34920d91
NC		 6882004-02-10 Petko Manolov <petkan@nucleusys.com>
689
690 * arm-opc.h Maverick accumulator register opcode fixes.
691
44d86481
BE		 6922004-02-13 Ben Elliston <bje@wasabisystems.com>
693
694 * m32r-dis.c: Regenerate.
695
17707c23
MS		 6962004-01-27 Michael Snyder <msnyder@redhat.com>
697
698 * sh-opc.h (sh_table): "fsrra", not "fssra".
699
fe3a9bc4
NC		 7002004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
701
702 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
703 contraints.
704
ff24f124
JJ		 7052004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
706
707 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
708
a02a862a
AM		 7092004-01-19 Alan Modra <amodra@bigpond.net.au>
710
711 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
712 1. Don't print scale factor on AT&T mode when index missing.
713
d164ea7f
AO		 7142004-01-16 Alexandre Oliva <aoliva@redhat.com>
715
716 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
717 when loaded into XR registers.
718
cb10e79a
RS		 7192004-01-14 Richard Sandiford <rsandifo@redhat.com>
720
721 * frv-desc.h: Regenerate.
722 * frv-desc.c: Regenerate.
723 * frv-opc.c: Regenerate.
724
f532f3fa
MS		 7252004-01-13 Michael Snyder <msnyder@redhat.com>
726
727 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
728
e45d0630
PB		 7292004-01-09 Paul Brook <paul@codesourcery.com>
730
731 * arm-opc.h (arm_opcodes): Move generic mcrr after known
732 specific opcodes.
733
3ba7a1aa
DJ		 7342004-01-07 Daniel Jacobowitz <drow@mvista.com>
735
736 * Makefile.am (libopcodes_la_DEPENDENCIES)
737 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
738 comment about the problem.
739 * Makefile.in: Regenerate.
740
ba2d3f07
AO		 7412004-01-06 Alexandre Oliva <aoliva@redhat.com>
742
743 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
744 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
745 cut&paste errors in shifting/truncating numerical operands.
746 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
747 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
748 (parse_uslo16): Likewise.
749 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
750 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
751 (parse_s12): Likewise.
752 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
753 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
754 (parse_uslo16): Likewise.
755 (parse_uhi16): Parse gothi and gotfuncdeschi.
756 (parse_d12): Parse got12 and gotfuncdesc12.
757 (parse_s12): Likewise.
758
3ab48931
NC		 7592004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
760
761 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
762 instruction which looks similar to an 'rla' instruction.
a0bd404e 763
c9e214e5 764For older changes see ChangeLog-0203
252b5132
RH		 765\f
766Local Variables:
2f6d2f85
NC		 767mode: change-log
768left-margin: 8
769fill-column: 74
252b5132
RH		 770version-control: never
771End:
GDB Binutils - Deliverables
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