PR 14072
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
df7b86aa
NC
12012-05-17 Daniel Richard G. <skunk@iskunk.org>
2 Nick Clifton <nickc@redhat.com>
3
4 PR 14072
5 * configure.in: Add check that sysdep.h has been included before
6 any system header files.
7 * configure: Regenerate.
8 * config.in: Regenerate.
9 * sysdep.h: Generate an error if included before config.h.
10 * alpha-opc.c: Include sysdep.h before any other header file.
11 * alpha-dis.c: Likewise.
12 * avr-dis.c: Likewise.
13 * cgen-opc.c: Likewise.
14 * cr16-dis.c: Likewise.
15 * cris-dis.c: Likewise.
16 * crx-dis.c: Likewise.
17 * d10v-dis.c: Likewise.
18 * d10v-opc.c: Likewise.
19 * d30v-dis.c: Likewise.
20 * d30v-opc.c: Likewise.
21 * h8500-dis.c: Likewise.
22 * i370-dis.c: Likewise.
23 * i370-opc.c: Likewise.
24 * m10200-dis.c: Likewise.
25 * m10300-dis.c: Likewise.
26 * micromips-opc.c: Likewise.
27 * mips-opc.c: Likewise.
28 * mips61-opc.c: Likewise.
29 * moxie-dis.c: Likewise.
30 * or32-opc.c: Likewise.
31 * pj-dis.c: Likewise.
32 * ppc-dis.c: Likewise.
33 * ppc-opc.c: Likewise.
34 * s390-dis.c: Likewise.
35 * sh-dis.c: Likewise.
36 * sh64-dis.c: Likewise.
37 * sparc-dis.c: Likewise.
38 * sparc-opc.c: Likewise.
39 * spu-dis.c: Likewise.
40 * tic30-dis.c: Likewise.
41 * tic54x-dis.c: Likewise.
42 * tic80-dis.c: Likewise.
43 * tic80-opc.c: Likewise.
44 * tilegx-dis.c: Likewise.
45 * tilepro-dis.c: Likewise.
46 * v850-dis.c: Likewise.
47 * v850-opc.c: Likewise.
48 * vax-dis.c: Likewise.
49 * w65-dis.c: Likewise.
50 * xgate-dis.c: Likewise.
51 * xtensa-dis.c: Likewise.
52 * rl78-decode.opc: Likewise.
53 * rl78-decode.c: Regenerate.
54 * rx-decode.opc: Likewise.
55 * rx-decode.c: Regenerate.
56
e1dad58d
AM
572012-05-17 Alan Modra <amodra@gmail.com>
58
59 * ppc_dis.c: Don't include elf/ppc.h.
60
101af531
NC
612012-05-16 Meador Inge <meadori@codesourcery.com>
62
63 * arm-dis.c (arm_opcodes): Don't disassemble STMFD/LDMIA sp!, {reg}
64 to PUSH/POP {reg}.
65
6927f982
NC
662012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
67 Stephane Carrez <stcarrez@nerim.fr>
68
69 * configure.in: Add S12X and XGATE co-processor support to m68hc11
70 target.
71 * disassemble.c: Likewise.
72 * configure: Regenerate.
73 * m68hc11-dis.c: Make objdump output more consistent, use hex
74 instead of decimal and use 0x prefix for hex.
75 * m68hc11-opc.c: Add S12X and XGATE opcodes.
76
b9c361e0
JL
772012-05-14 James Lemke <jwlemke@codesourcery.com>
78
79 * ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
80 (PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines.
81 (vle_opcd_indices): New array.
82 (lookup_vle): New function.
83 (disassemble_init_powerpc): Revise for second (VLE) opcode table.
84 (print_insn_powerpc): Likewise.
85 * ppc-opc.c: Likewise.
86
872012-05-14 Catherine Moore <clm@codesourcery.com>
88 Maciej W. Rozycki <macro@codesourcery.com>
89 Rhonda Wittels <rhonda@codesourcery.com>
90 Nathan Froyd <froydnj@codesourcery.com>
91
92 * ppc-opc.c (insert_arx, extract_arx): New functions.
93 (insert_ary, extract_ary): New functions.
94 (insert_li20, extract_li20): New functions.
95 (insert_rx, extract_rx): New functions.
96 (insert_ry, extract_ry): New functions.
97 (insert_sci8, extract_sci8): New functions.
98 (insert_sci8n, extract_sci8n): New functions.
99 (insert_sd4h, extract_sd4h): New functions.
100 (insert_sd4w, extract_sd4w): New functions.
101 (insert_vlesi, extract_vlesi): New functions.
102 (insert_vlensi, extract_vlensi): New functions.
103 (insert_vleui, extract_vleui): New functions.
104 (insert_vleil, extract_vleil): New functions.
105 (BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT.
106 (BI16, BI32, BO32, B8): New.
107 (B15, B24, CRD32, CRS): New.
108 (CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG.
109 (DB, IMM20, RD, Rx, ARX, RY, RZ): New.
110 (ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New.
111 (SH6_MASK): Use PPC_OPSHIFT_INV.
112 (SI8, UI5, OIMM5, UI7, BO16): New.
113 (VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New.
114 (XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV.
115 (ALLOW8_SPRG): New.
116 (insert_sprg, extract_sprg): Check ALLOW8_SPRG.
117 (OPVUP, OPVUP_MASK OPVUP): New
118 (BD8, BD8_MASK, BD8IO, BD8IO_MASK): New.
119 (EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New.
120 (BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New.
121 (BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New.
122 (IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New.
123 (IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New.
124 (SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New.
125 (SE_IM5, SE_IM5_MASK): New.
126 (SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New.
127 (EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New.
128 (BO32DNZ, BO32DZ): New.
129 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE.
130 (PPCVLE): New.
131 (powerpc_opcodes): Add new VLE instructions. Update existing
132 instruction to include PPCVLE if supported.
133 * ppc-dis.c (ppc_opts): Add vle entry.
134 (get_powerpc_dialect): New function.
135 (powerpc_init_dialect): VLE support.
136 (print_insn_big_powerpc): Call get_powerpc_dialect.
137 (print_insn_little_powerpc): Likewise.
138 (operand_value_powerpc): Handle negative shift counts.
139 (print_insn_powerpc): Handle 2-byte instruction lengths.
140
208a4923
NC
1412012-05-11 Daniel Richard G. <skunk@iskunk.org>
142
143 PR binutils/14028
144 * configure.in: Invoke ACX_HEADER_STRING.
145 * configure: Regenerate.
146 * config.in: Regenerate.
147 * sysdep.h: If STRINGS_WITH_STRING is defined then include both
148 string.h and strings.h.
149
6750a3a7
NC
1502012-05-11 Nick Clifton <nickc@redhat.com>
151
152 PR binutils/14006
153 * arm-dis.c (print_insn): Fix detection of instruction mode in
154 files containing multiple executable sections.
155
f6c1a2d5
NC
1562012-05-03 Sean Keys <skeys@ipdatasys.com>
157
158 * Makefile.in, configure: regenerate
159 * disassemble.c (disassembler): Recognize ARCH_XGATE.
160 * xgate-dis.c (read_memory, print_insn, print_insn_xgate):
161 New functions.
162 * configure.in: Recognize xgate.
163 * xgate-dis.c, xgate-opc.c: New files for support of xgate
164 * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
165 and opcode generation for xgate.
166
78e98aab
DD
1672012-04-30 DJ Delorie <dj@redhat.com>
168
169 * rx-decode.opc (MOV): Do not sign-extend immediates which are
170 already the maximum bit size.
171 * rx-decode.c: Regenerate.
172
ec668d69
DM
1732012-04-27 David S. Miller <davem@davemloft.net>
174
2e52845b
DM
175 * sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
176 * sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.
177
58004e23
DM
178 * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
179 * sparc-dis.c (v9a_asr_reg_names): Add 'pause'.
180
698544e1
DM
181 * sparc-opc.c (CBCOND): New define.
182 (CBCOND_XCC): Likewise.
183 (cbcond): New helper macro.
184 (sparc_opcodes): Add compare-and-branch instructions.
185
6cda1326
DM
186 * sparc-dis.c (print_insn_sparc): Handle ')'.
187 * sparc-opc.c (sparc_opcodes): Add crypto instructions.
188
ec668d69
DM
189 * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
190 into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
191
2615994e
DM
1922012-04-12 David S. Miller <davem@davemloft.net>
193
194 * sparc-dis.c (X_DISP10): Define.
195 (print_insn_sparc): Handle '='.
196
5de10af0
MF
1972012-04-01 Mike Frysinger <vapier@gentoo.org>
198
199 * bfin-dis.c (fmtconst): Replace decimal handling with a single
200 sprintf call and the '*' field width.
201
55a36193
MK
2022012-03-23 Maxim Kuvyrkov <maxim@codesourcery.com>
203
204 * mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.
205
d6688282
AM
2062012-03-16 Alan Modra <amodra@gmail.com>
207
208 * ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete.
209 (powerpc_opcd_indices): Bump array size.
210 (disassemble_init_powerpc): Set powerpc_opcd_indices entries
211 corresponding to unused opcodes to following entry.
212 (lookup_powerpc): New function, extracted and optimised from..
213 (print_insn_powerpc): ..here.
214
b240011a
AM
2152012-03-15 Alan Modra <amodra@gmail.com>
216 James Lemke <jwlemke@codesourcery.com>
217
218 * disassemble.c (disassemble_init_for_target): Handle ppc init.
219 * ppc-dis.c (private): New var.
220 (powerpc_init_dialect): Don't return calloc failure, instead use
221 private.
222 (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
223 (powerpc_opcd_indices): New array.
224 (disassemble_init_powerpc): New function.
225 (print_insn_big_powerpc): Don't init dialect here.
226 (print_insn_little_powerpc): Likewise.
227 (print_insn_powerpc): Start search using powerpc_opcd_indices.
228
aea77599
AM
2292012-03-10 Edmar Wienskoski <edmar@freescale.com>
230
231 * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
232 * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
233 (PPCVEC2, PPCTMR, E6500): New short names.
234 (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
235 mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
236 lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
237 lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
238 lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
239 optional operands on sync instruction for E6500 target.
240
5333187a
AK
2412012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
242
243 * s390-opc.txt: Set instruction type of pku to SS_L2RDRD.
244
a597d2d3
AM
2452012-02-27 Alan Modra <amodra@gmail.com>
246
247 * mt-dis.c: Regenerate.
248
3f26eb3a
AM
2492012-02-27 Alan Modra <amodra@gmail.com>
250
251 * v850-opc.c (extract_v8): Rearrange to make it obvious this
252 is the inverse of corresponding insert function.
253 (extract_d22, extract_u9, extract_r4): Likewise.
254 (extract_d9): Correct sign extension.
255 (extract_d16_15): Don't assume "long" is 32 bits, and don't
256 rely on implementation defined behaviour for shift right of
257 signed types.
258 (extract_d16_16, extract_d17_16, extract_i9): Likewise.
259 (extract_d23): Likewise, and correct mask.
260
1f42f8b3
AM
2612012-02-27 Alan Modra <amodra@gmail.com>
262
263 * crx-dis.c (print_arg): Mask constant to 32 bits.
264 * crx-opc.c (cst4_map): Use int array.
265
cdb06235
AM
2662012-02-27 Alan Modra <amodra@gmail.com>
267
268 * arc-dis.c (BITS): Don't use shifts to mask off bits.
269 (FIELDD): Sign extend with xor,sub.
270
6f7be959
WL
2712012-02-25 Walter Lee <walt@tilera.com>
272
273 * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
274 * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
275 TILEPRO_OPC_LW_TLS_SN.
276
82c2def5
L
2772012-02-21 H.J. Lu <hongjiu.lu@intel.com>
278
279 * i386-opc.h (HLEPrefixNone): New.
280 (HLEPrefixLock): Likewise.
281 (HLEPrefixAny): Likewise.
282 (HLEPrefixRelease): Likewise.
283
42164a71
L
2842012-02-08 H.J. Lu <hongjiu.lu@intel.com>
285
286 * i386-dis.c (HLE_Fixup1): New.
287 (HLE_Fixup2): Likewise.
288 (HLE_Fixup3): Likewise.
289 (Ebh1): Likewise.
290 (Evh1): Likewise.
291 (Ebh2): Likewise.
292 (Evh2): Likewise.
293 (Ebh3): Likewise.
294 (Evh3): Likewise.
295 (MOD_C6_REG_7): Likewise.
296 (MOD_C7_REG_7): Likewise.
297 (RM_C6_REG_7): Likewise.
298 (RM_C7_REG_7): Likewise.
299 (XACQUIRE_PREFIX): Likewise.
300 (XRELEASE_PREFIX): Likewise.
301 (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
302 cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
303 Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
304 (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
305 not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
306 MOD_C6_REG_7 and MOD_C7_REG_7.
307 (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
308 (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
309 xtest.
310 (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
311 (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
312
313 * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
314 CPU_RTM_FLAGS.
315 (cpu_flags): Add CpuHLE and CpuRTM.
316 (opcode_modifiers): Add HLEPrefixOk.
317
318 * i386-opc.h (CpuHLE): New.
319 (CpuRTM): Likewise.
320 (HLEPrefixOk): Likewise.
321 (i386_cpu_flags): Add cpuhle and cpurtm.
322 (i386_opcode_modifier): Add hleprefixok.
323
324 * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
325 add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
326 sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
327 operand. Add xacquire, xrelease, xabort, xbegin, xend and
328 xtest.
329 * i386-init.h: Regenerated.
330 * i386-tbl.h: Likewise.
331
21abe33a
DD
3322012-01-24 DJ Delorie <dj@redhat.com>
333
334 * rl78-decode.opc (rl78_decode_opcode): Add NOT1.
335 * rl78-decode.c: Regenerate.
336
e20cc039
AM
3372012-01-17 James Murray <jsm@jsm-net.demon.co.uk>
338
339 PR binutils/10173
340 * cr16-dis.c (print_arg): Test symtab_size not num_symbols.
341
e143d25c
AS
3422012-01-17 Andreas Schwab <schwab@linux-m68k.org>
343
344 * m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx
345 register and move them after pmove with PSR/PCSR register.
346
8729a6f6
L
3472012-01-13 H.J. Lu <hongjiu.lu@intel.com>
348
349 * i386-dis.c (mod_table): Add vmfunc.
350
351 * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
352 (cpu_flags): CpuVMFUNC.
353
354 * i386-opc.h (CpuVMFUNC): New.
355 (i386_cpu_flags): Add cpuvmfunc.
356
357 * i386-opc.tbl: Add vmfunc.
358 * i386-init.h: Regenerated.
359 * i386-tbl.h: Likewise.
5011093d 360
23e1d329 361For older changes see ChangeLog-2011
252b5132
RH
362\f
363Local Variables:
2f6d2f85
NC
364mode: change-log
365left-margin: 8
366fill-column: 74
252b5132
RH
367version-control: never
368End:
This page took 0.559983 seconds and 4 git commands to generate.