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x86: don't emit REX.W for SLDT and STR
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
dfd27d41
JB		 12018-06-01 Jan Beulich <jbeulich@suse.com>
2
3 * i386-opc.tbl (sldt, str): Add NoRex64.
4 * i386-tbl.h: Re-generate.
5
64795710
JB		 62018-06-01 Jan Beulich <jbeulich@suse.com>
7
8 * i386-opc.tbl (invpcid): Add Oword.
9 * i386-tbl.h: Re-generate.
10
030157d8
AM		 112018-06-01 Alan Modra <amodra@gmail.com>
12
13 * sysdep.h (_bfd_error_handler): Don't declare.
14 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
15 * rl78-decode.opc: Likewise.
16 * msp430-decode.c: Regenerate.
17 * rl78-decode.c: Regenerate.
18
a9660a6f
AP		 192018-05-30 Amit Pawar <Amit.Pawar@amd.com>
20
21 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
22 * i386-init.h : Regenerated.
23
277eb7f6
AM		 242018-05-25 Alan Modra <amodra@gmail.com>
25
26 * Makefile.in: Regenerate.
27 * po/POTFILES.in: Regenerate.
28
98553ad3
PB		 292018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
30
31 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
32 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
33 (insert_bab, extract_bab, insert_btab, extract_btab,
34 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
35 (BAT, BBA VBA RBS XB6S): Delete macros.
36 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
37 (BB, BD, RBX, XC6): Update for new macros.
38 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
39 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
40 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
41 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
42
7b4ae824
JD		 432018-05-18 John Darrington <john@darrington.wattle.id.au>
44
45 * Makefile.am: Add support for s12z architecture.
46 * configure.ac: Likewise.
47 * disassemble.c: Likewise.
48 * disassemble.h: Likewise.
49 * Makefile.in: Regenerate.
50 * configure: Regenerate.
51 * s12z-dis.c: New file.
52 * s12z.h: New file.
53
29e0f0a1
AM		 542018-05-18 Alan Modra <amodra@gmail.com>
55
56 * nfp-dis.c: Don't #include libbfd.h.
57 (init_nfp3200_priv): Use bfd_get_section_contents.
58 (nit_nfp6000_mecsr_sec): Likewise.
59
809276d2
NC		 602018-05-17 Nick Clifton <nickc@redhat.com>
61
62 * po/zh_CN.po: Updated simplified Chinese translation.
63
ff329288
TC		 642018-05-16 Tamar Christina <tamar.christina@arm.com>
65
66 PR binutils/23109
67 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
68 * aarch64-dis-2.c: Regenerate.
69
f9830ec1
TC		 702018-05-15 Tamar Christina <tamar.christina@arm.com>
71
72 PR binutils/21446
73 * aarch64-asm.c (opintl.h): Include.
74 (aarch64_ins_sysreg): Enforce read/write constraints.
75 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
76 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
77 (F_REG_READ, F_REG_WRITE): New.
78 * aarch64-opc.c (aarch64_print_operand): Generate notes for
79 AARCH64_OPND_SYSREG.
80 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
81 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
82 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
83 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
84 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
85 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
86 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
87 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
88 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
89 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
90 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
91 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
92 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
93 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
94 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
95 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
96 msr (F_SYS_WRITE), mrs (F_SYS_READ).
97
7d02540a
TC		 982018-05-15 Tamar Christina <tamar.christina@arm.com>
99
100 PR binutils/21446
101 * aarch64-dis.c (no_notes: New.
102 (parse_aarch64_dis_option): Support notes.
103 (aarch64_decode_insn, print_operands): Likewise.
104 (print_aarch64_disassembler_options): Document notes.
105 * aarch64-opc.c (aarch64_print_operand): Support notes.
106
561a72d4
TC		 1072018-05-15 Tamar Christina <tamar.christina@arm.com>
108
109 PR binutils/21446
110 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
111 and take error struct.
112 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
113 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
114 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
115 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
116 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
117 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
118 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
119 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
120 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
121 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
122 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
123 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
124 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
125 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
126 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
127 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
128 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
129 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
130 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
131 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
132 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
133 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
134 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
135 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
136 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
137 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
138 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
139 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
140 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
141 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
142 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
143 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
144 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
145 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
146 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
147 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
148 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
149 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
150 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
151 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
152 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
153 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
154 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
155 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
156 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
157 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
158 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
159 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
160 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
161 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
162 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
163 (determine_disassembling_preference, aarch64_decode_insn,
164 print_insn_aarch64_word, print_insn_data): Take errors struct.
165 (print_insn_aarch64): Use errors.
166 * aarch64-asm-2.c: Regenerate.
167 * aarch64-dis-2.c: Regenerate.
168 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
169 boolean in aarch64_insert_operan.
170 (print_operand_extractor): Likewise.
171 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
172
1678bd35
FT		 1732018-05-15 Francois H. Theron <francois.theron@netronome.com>
174
175 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
176
06cfb1c8
L		 1772018-05-09 H.J. Lu <hongjiu.lu@intel.com>
178
179 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
180
84f9f8c3
AM		 1812018-05-09 Sebastian Rasmussen <sebras@gmail.com>
182
183 * cr16-opc.c (cr16_instruction): Comment typo fix.
184 * hppa-dis.c (print_insn_hppa): Likewise.
185
e6f372ba
JW		 1862018-05-08 Jim Wilson <jimw@sifive.com>
187
188 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
189 (match_c_slli64, match_srxi_as_c_srxi): New.
190 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
191 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
192 <c.slli, c.srli, c.srai>: Use match_s_slli.
193 <c.slli64, c.srli64, c.srai64>: New.
194
f413a913
AM		 1952018-05-08 Alan Modra <amodra@gmail.com>
196
197 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
198 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
199 partition opcode space for index lookup.
200
a87a6478
PB		 2012018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
202
203 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
204 <insn_length>: ...with this. Update usage.
205 Remove duplicate call to *info->memory_error_func.
206
c0a30a9f
L		 2072018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
208 H.J. Lu <hongjiu.lu@intel.com>
209
210 * i386-dis.c (Gva): New.
211 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
212 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
213 (prefix_table): New instructions (see prefix above).
214 (mod_table): New instructions (see prefix above).
215 (OP_G): Handle va_mode.
216 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
217 CPU_MOVDIR64B_FLAGS.
218 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
219 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
220 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
221 * i386-opc.tbl: Add movidir{i,64b}.
222 * i386-init.h: Regenerated.
223 * i386-tbl.h: Likewise.
224
75c0a438
L		 2252018-05-07 H.J. Lu <hongjiu.lu@intel.com>
226
227 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
228 AddrPrefixOpReg.
229 * i386-opc.h (AddrPrefixOp0): Renamed to ...
230 (AddrPrefixOpReg): This.
231 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
232 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
233
2ceb7719
PB		 2342018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
235
236 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
237 (vle_num_opcodes): Likewise.
238 (spe2_num_opcodes): Likewise.
239 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
240 initialization loop.
241 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
242 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
243 only once.
244
b3ac5c6c
TC		 2452018-05-01 Tamar Christina <tamar.christina@arm.com>
246
247 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
248
fe944acf
FT		 2492018-04-30 Francois H. Theron <francois.theron@netronome.com>
250
251 Makefile.am: Added nfp-dis.c.
252 configure.ac: Added bfd_nfp_arch.
253 disassemble.h: Added print_insn_nfp prototype.
254 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
255 nfp-dis.c: New, for NFP support.
256 po/POTFILES.in: Added nfp-dis.c to the list.
257 Makefile.in: Regenerate.
258 configure: Regenerate.
259
e2195274
JB		 2602018-04-26 Jan Beulich <jbeulich@suse.com>
261
262 * i386-opc.tbl: Fold various non-memory operand AVX512VL
263 templates into their base ones.
264 * i386-tlb.h: Re-generate.
265
59ef5df4
JB		 2662018-04-26 Jan Beulich <jbeulich@suse.com>
267
268 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
269 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
270 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
271 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
272 * i386-init.h: Re-generate.
273
6e041cf4
JB		 2742018-04-26 Jan Beulich <jbeulich@suse.com>
275
276 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
277 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
278 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
279 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
280 comment.
281 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
282 and CpuRegMask.
283 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
284 CpuRegMask: Delete.
285 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
286 cpuregzmm, and cpuregmask.
287 * i386-init.h: Re-generate.
288 * i386-tbl.h: Re-generate.
289
0e0eea78
JB		 2902018-04-26 Jan Beulich <jbeulich@suse.com>
291
292 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
293 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
294 * i386-init.h: Re-generate.
295
2f1bada2
JB		 2962018-04-26 Jan Beulich <jbeulich@suse.com>
297
298 * i386-gen.c (VexImmExt): Delete.
299 * i386-opc.h (VexImmExt, veximmext): Delete.
300 * i386-opc.tbl: Drop all VexImmExt uses.
301 * i386-tlb.h: Re-generate.
302
bacd1457
JB		 3032018-04-25 Jan Beulich <jbeulich@suse.com>
304
305 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
306 register-only forms.
307 * i386-tlb.h: Re-generate.
308
10bba94b
TC		 3092018-04-25 Tamar Christina <tamar.christina@arm.com>
310
311 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
312
c48935d7
IT		 3132018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
314
315 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
316 PREFIX_0F1C.
317 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
318 (cpu_flags): Add CpuCLDEMOTE.
319 * i386-init.h: Regenerate.
320 * i386-opc.h (enum): Add CpuCLDEMOTE,
321 (i386_cpu_flags): Add cpucldemote.
322 * i386-opc.tbl: Add cldemote.
323 * i386-tbl.h: Regenerate.
324
211dc24b
AM		 3252018-04-16 Alan Modra <amodra@gmail.com>
326
327 * Makefile.am: Remove sh5 and sh64 support.
328 * configure.ac: Likewise.
329 * disassemble.c: Likewise.
330 * disassemble.h: Likewise.
331 * sh-dis.c: Likewise.
332 * sh64-dis.c: Delete.
333 * sh64-opc.c: Delete.
334 * sh64-opc.h: Delete.
335 * Makefile.in: Regenerate.
336 * configure: Regenerate.
337 * po/POTFILES.in: Regenerate.
338
a9a4b302
AM		 3392018-04-16 Alan Modra <amodra@gmail.com>
340
341 * Makefile.am: Remove w65 support.
342 * configure.ac: Likewise.
343 * disassemble.c: Likewise.
344 * disassemble.h: Likewise.
345 * w65-dis.c: Delete.
346 * w65-opc.h: Delete.
347 * Makefile.in: Regenerate.
348 * configure: Regenerate.
349 * po/POTFILES.in: Regenerate.
350
04cb01fd
AM		 3512018-04-16 Alan Modra <amodra@gmail.com>
352
353 * configure.ac: Remove we32k support.
354 * configure: Regenerate.
355
c2bf1eec
AM		 3562018-04-16 Alan Modra <amodra@gmail.com>
357
358 * Makefile.am: Remove m88k support.
359 * configure.ac: Likewise.
360 * disassemble.c: Likewise.
361 * disassemble.h: Likewise.
362 * m88k-dis.c: Delete.
363 * Makefile.in: Regenerate.
364 * configure: Regenerate.
365 * po/POTFILES.in: Regenerate.
366
6793974d
AM		 3672018-04-16 Alan Modra <amodra@gmail.com>
368
369 * Makefile.am: Remove i370 support.
370 * configure.ac: Likewise.
371 * disassemble.c: Likewise.
372 * disassemble.h: Likewise.
373 * i370-dis.c: Delete.
374 * i370-opc.c: Delete.
375 * Makefile.in: Regenerate.
376 * configure: Regenerate.
377 * po/POTFILES.in: Regenerate.
378
e82aa794
AM		 3792018-04-16 Alan Modra <amodra@gmail.com>
380
381 * Makefile.am: Remove h8500 support.
382 * configure.ac: Likewise.
383 * disassemble.c: Likewise.
384 * disassemble.h: Likewise.
385 * h8500-dis.c: Delete.
386 * h8500-opc.h: Delete.
387 * Makefile.in: Regenerate.
388 * configure: Regenerate.
389 * po/POTFILES.in: Regenerate.
390
fceadf09
AM		 3912018-04-16 Alan Modra <amodra@gmail.com>
392
393 * configure.ac: Remove tahoe support.
394 * configure: Regenerate.
395
ae1d3843
L		 3962018-04-15 H.J. Lu <hongjiu.lu@intel.com>
397
398 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
399 umwait.
400 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
401 64-bit mode.
402 * i386-tbl.h: Regenerated.
403
de89d0a3
IT		 4042018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
405
406 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
407 PREFIX_MOD_1_0FAE_REG_6.
408 (va_mode): New.
409 (OP_E_register): Use va_mode.
410 * i386-dis-evex.h (prefix_table):
411 New instructions (see prefixes above).
412 * i386-gen.c (cpu_flag_init): Add WAITPKG.
413 (cpu_flags): Likewise.
414 * i386-opc.h (enum): Likewise.
415 (i386_cpu_flags): Likewise.
416 * i386-opc.tbl: Add umonitor, umwait, tpause.
417 * i386-init.h: Regenerate.
418 * i386-tbl.h: Likewise.
419
a8eb42a8
AM		 4202018-04-11 Alan Modra <amodra@gmail.com>
421
422 * opcodes/i860-dis.c: Delete.
423 * opcodes/i960-dis.c: Delete.
424 * Makefile.am: Remove i860 and i960 support.
425 * configure.ac: Likewise.
426 * disassemble.c: Likewise.
427 * disassemble.h: Likewise.
428 * Makefile.in: Regenerate.
429 * configure: Regenerate.
430 * po/POTFILES.in: Regenerate.
431
caf0678c
L		 4322018-04-04 H.J. Lu <hongjiu.lu@intel.com>
433
434 PR binutils/23025
435 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
436 to 0.
437 (print_insn): Clear vex instead of vex.evex.
438
4fb0d2b9
NC		 4392018-04-04 Nick Clifton <nickc@redhat.com>
440
441 * po/es.po: Updated Spanish translation.
442
c39e5b26
JB		 4432018-03-28 Jan Beulich <jbeulich@suse.com>
444
445 * i386-gen.c (opcode_modifiers): Delete VecESize.
446 * i386-opc.h (VecESize): Delete.
447 (struct i386_opcode_modifier): Delete vecesize.
448 * i386-opc.tbl: Drop VecESize.
449 * i386-tlb.h: Re-generate.
450
8e6e0792
JB		 4512018-03-28 Jan Beulich <jbeulich@suse.com>
452
453 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
454 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
455 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
456 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
457 * i386-tlb.h: Re-generate.
458
9f123b91
JB		 4592018-03-28 Jan Beulich <jbeulich@suse.com>
460
461 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
462 Fold AVX512 forms
463 * i386-tlb.h: Re-generate.
464
9646c87b
JB		 4652018-03-28 Jan Beulich <jbeulich@suse.com>
466
467 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
468 (vex_len_table): Drop Y for vcvt*2si.
469 (putop): Replace plain 'Y' handling by abort().
470
c8d59609
NC		 4712018-03-28 Nick Clifton <nickc@redhat.com>
472
473 PR 22988
474 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
475 instructions with only a base address register.
476 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
477 handle AARHC64_OPND_SVE_ADDR_R.
478 (aarch64_print_operand): Likewise.
479 * aarch64-asm-2.c: Regenerate.
480 * aarch64_dis-2.c: Regenerate.
481 * aarch64-opc-2.c: Regenerate.
482
b8c169f3
JB		 4832018-03-22 Jan Beulich <jbeulich@suse.com>
484
485 * i386-opc.tbl: Drop VecESize from register only insn forms and
486 memory forms not allowing broadcast.
487 * i386-tlb.h: Re-generate.
488
96bc132a
JB		 4892018-03-22 Jan Beulich <jbeulich@suse.com>
490
491 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
492 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
493 sha256*): Drop Disp<N>.
494
9f79e886
JB		 4952018-03-22 Jan Beulich <jbeulich@suse.com>
496
497 * i386-dis.c (EbndS, bnd_swap_mode): New.
498 (prefix_table): Use EbndS.
499 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
500 * i386-opc.tbl (bndmov): Move misplaced Load.
501 * i386-tlb.h: Re-generate.
502
d6793fa1
JB		 5032018-03-22 Jan Beulich <jbeulich@suse.com>
504
505 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
506 templates allowing memory operands and folded ones for register
507 only flavors.
508 * i386-tlb.h: Re-generate.
509
f7768225
JB		 5102018-03-22 Jan Beulich <jbeulich@suse.com>
511
512 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
513 256-bit templates. Drop redundant leftover Disp<N>.
514 * i386-tlb.h: Re-generate.
515
0e35537d
JW		 5162018-03-14 Kito Cheng <kito.cheng@gmail.com>
517
518 * riscv-opc.c (riscv_insn_types): New.
519
b4a3689a
NC		 5202018-03-13 Nick Clifton <nickc@redhat.com>
521
522 * po/pt_BR.po: Updated Brazilian Portuguese translation.
523
d3d50934
L		 5242018-03-08 H.J. Lu <hongjiu.lu@intel.com>
525
526 * i386-opc.tbl: Add Optimize to clr.
527 * i386-tbl.h: Regenerated.
528
bd5dea88
L		 5292018-03-08 H.J. Lu <hongjiu.lu@intel.com>
530
531 * i386-gen.c (opcode_modifiers): Remove OldGcc.
532 * i386-opc.h (OldGcc): Removed.
533 (i386_opcode_modifier): Remove oldgcc.
534 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
535 instructions for old (<= 2.8.1) versions of gcc.
536 * i386-tbl.h: Regenerated.
537
e771e7c9
JB		 5382018-03-08 Jan Beulich <jbeulich@suse.com>
539
540 * i386-opc.h (EVEXDYN): New.
541 * i386-opc.tbl: Fold various AVX512VL templates.
542 * i386-tlb.h: Re-generate.
543
ed438a93
JB		 5442018-03-08 Jan Beulich <jbeulich@suse.com>
545
546 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
547 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
548 vpexpandd, vpexpandq): Fold AFX512VF templates.
549 * i386-tlb.h: Re-generate.
550
454172a9
JB		 5512018-03-08 Jan Beulich <jbeulich@suse.com>
552
553 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
554 Fold 128- and 256-bit VEX-encoded templates.
555 * i386-tlb.h: Re-generate.
556
36824150
JB		 5572018-03-08 Jan Beulich <jbeulich@suse.com>
558
559 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
560 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
561 vpexpandd, vpexpandq): Fold AVX512F templates.
562 * i386-tlb.h: Re-generate.
563
e7f5c0a9
JB		 5642018-03-08 Jan Beulich <jbeulich@suse.com>
565
566 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
567 64-bit templates. Drop Disp<N>.
568 * i386-tlb.h: Re-generate.
569
25a4277f
JB		 5702018-03-08 Jan Beulich <jbeulich@suse.com>
571
572 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
573 and 256-bit templates.
574 * i386-tlb.h: Re-generate.
575
d2224064
JB		 5762018-03-08 Jan Beulich <jbeulich@suse.com>
577
578 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
579 * i386-tlb.h: Re-generate.
580
1b193f0b
JB		 5812018-03-08 Jan Beulich <jbeulich@suse.com>
582
583 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
584 Drop NoAVX.
585 * i386-tlb.h: Re-generate.
586
f2f6a710
JB		 5872018-03-08 Jan Beulich <jbeulich@suse.com>
588
589 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
590 * i386-tlb.h: Re-generate.
591
38e314eb
JB		 5922018-03-08 Jan Beulich <jbeulich@suse.com>
593
594 * i386-gen.c (opcode_modifiers): Delete FloatD.
595 * i386-opc.h (FloatD): Delete.
596 (struct i386_opcode_modifier): Delete floatd.
597 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
598 FloatD by D.
599 * i386-tlb.h: Re-generate.
600
d53e6b98
JB		 6012018-03-08 Jan Beulich <jbeulich@suse.com>
602
603 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
604
2907c2f5
JB		 6052018-03-08 Jan Beulich <jbeulich@suse.com>
606
607 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
608 * i386-tlb.h: Re-generate.
609
73053c1f
JB		 6102018-03-08 Jan Beulich <jbeulich@suse.com>
611
612 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
613 forms.
614 * i386-tlb.h: Re-generate.
615
52fe4420
AM		 6162018-03-07 Alan Modra <amodra@gmail.com>
617
618 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
619 bfd_arch_rs6000.
620 * disassemble.h (print_insn_rs6000): Delete.
621 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
622 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
623 (print_insn_rs6000): Delete.
624
a6743a54
AM		 6252018-03-03 Alan Modra <amodra@gmail.com>
626
627 * sysdep.h (opcodes_error_handler): Define.
628 (_bfd_error_handler): Declare.
629 * Makefile.am: Remove stray #.
630 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
631 EDIT" comment.
632 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
633 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
634 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
635 opcodes_error_handler to print errors. Standardize error messages.
636 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
637 and include opintl.h.
638 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
639 * i386-gen.c: Standardize error messages.
640 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
641 * Makefile.in: Regenerate.
642 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
643 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
644 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
645 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
646 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
647 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
648 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
649 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
650 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
651 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
652 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
653 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
654 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
655
8305403a
L		 6562018-03-01 H.J. Lu <hongjiu.lu@intel.com>
657
658 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
659 vpsub[bwdq] instructions.
660 * i386-tbl.h: Regenerated.
661
e184813f
AM		 6622018-03-01 Alan Modra <amodra@gmail.com>
663
664 * configure.ac (ALL_LINGUAS): Sort.
665 * configure: Regenerate.
666
5b616bef
TP		 6672018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
668
669 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
670 macro by assignements.
671
b6f8c7c4
L		 6722018-02-27 H.J. Lu <hongjiu.lu@intel.com>
673
674 PR gas/22871
675 * i386-gen.c (opcode_modifiers): Add Optimize.
676 * i386-opc.h (Optimize): New enum.
677 (i386_opcode_modifier): Add optimize.
678 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
679 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
680 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
681 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
682 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
683 vpxord and vpxorq.
684 * i386-tbl.h: Regenerated.
685
e95b887f
AM		 6862018-02-26 Alan Modra <amodra@gmail.com>
687
688 * crx-dis.c (getregliststring): Allocate a large enough buffer
689 to silence false positive gcc8 warning.
690
0bccfb29
JW		 6912018-02-22 Shea Levy <shea@shealevy.com>
692
693 * disassemble.c (ARCH_riscv): Define if ARCH_all.
694
6b6b6807
L		 6952018-02-22 H.J. Lu <hongjiu.lu@intel.com>
696
697 * i386-opc.tbl: Add {rex},
698 * i386-tbl.h: Regenerated.
699
75f31665
MR		 7002018-02-20 Maciej W. Rozycki <macro@mips.com>
701
702 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
703 (mips16_opcodes): Replace `M' with `m' for "restore".
704
e207bc53
TP		 7052018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
706
707 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
708
87993319
MR		 7092018-02-13 Maciej W. Rozycki <macro@mips.com>
710
711 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
712 variable to `function_index'.
713
68d20676
NC		 7142018-02-13 Nick Clifton <nickc@redhat.com>
715
716 PR 22823
717 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
718 about truncation of printing.
719
d2159fdc
HW		 7202018-02-12 Henry Wong <henry@stuffedcow.net>
721
722 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
723
f174ef9f
NC		 7242018-02-05 Nick Clifton <nickc@redhat.com>
725
726 * po/pt_BR.po: Updated Brazilian Portuguese translation.
727
be3a8dca
IT		 7282018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
729
730 * i386-dis.c (enum): Add pconfig.
731 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
732 (cpu_flags): Add CpuPCONFIG.
733 * i386-opc.h (enum): Add CpuPCONFIG.
734 (i386_cpu_flags): Add cpupconfig.
735 * i386-opc.tbl: Add PCONFIG instruction.
736 * i386-init.h: Regenerate.
737 * i386-tbl.h: Likewise.
738
3233d7d0
IT		 7392018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
740
741 * i386-dis.c (enum): Add PREFIX_0F09.
742 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
743 (cpu_flags): Add CpuWBNOINVD.
744 * i386-opc.h (enum): Add CpuWBNOINVD.
745 (i386_cpu_flags): Add cpuwbnoinvd.
746 * i386-opc.tbl: Add WBNOINVD instruction.
747 * i386-init.h: Regenerate.
748 * i386-tbl.h: Likewise.
749
e925c834
JW		 7502018-01-17 Jim Wilson <jimw@sifive.com>
751
752 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
753
d777820b
IT		 7542018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
755
756 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
757 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
758 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
759 (cpu_flags): Add CpuIBT, CpuSHSTK.
760 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
761 (i386_cpu_flags): Add cpuibt, cpushstk.
762 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
763 * i386-init.h: Regenerate.
764 * i386-tbl.h: Likewise.
765
f6efed01
NC		 7662018-01-16 Nick Clifton <nickc@redhat.com>
767
768 * po/pt_BR.po: Updated Brazilian Portugese translation.
769 * po/de.po: Updated German translation.
770
2721d702
JW		 7712018-01-15 Jim Wilson <jimw@sifive.com>
772
773 * riscv-opc.c (match_c_nop): New.
774 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
775
616dcb87
NC		 7762018-01-15 Nick Clifton <nickc@redhat.com>
777
778 * po/uk.po: Updated Ukranian translation.
779
3957a496
NC		 7802018-01-13 Nick Clifton <nickc@redhat.com>
781
782 * po/opcodes.pot: Regenerated.
783
769c7ea5
NC		 7842018-01-13 Nick Clifton <nickc@redhat.com>
785
786 * configure: Regenerate.
787
faf766e3
NC		 7882018-01-13 Nick Clifton <nickc@redhat.com>
789
790 2.30 branch created.
791
888a89da
IT		 7922018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
793
794 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
795 * i386-tbl.h: Regenerate.
796
cbda583a
JB		 7972018-01-10 Jan Beulich <jbeulich@suse.com>
798
799 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
800 * i386-tbl.h: Re-generate.
801
c9e92278
JB		 8022018-01-10 Jan Beulich <jbeulich@suse.com>
803
804 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
805 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
806 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
807 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
808 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
809 Disp8MemShift of AVX512VL forms.
810 * i386-tbl.h: Re-generate.
811
35fd2b2b
JW		 8122018-01-09 Jim Wilson <jimw@sifive.com>
813
814 * riscv-dis.c (maybe_print_address): If base_reg is zero,
815 then the hi_addr value is zero.
816
91d8b670
JG		 8172018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
818
819 * arm-dis.c (arm_opcodes): Add csdb.
820 (thumb32_opcodes): Add csdb.
821
be2e7d95
JG		 8222018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
823
824 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
825 * aarch64-asm-2.c: Regenerate.
826 * aarch64-dis-2.c: Regenerate.
827 * aarch64-opc-2.c: Regenerate.
828
704a705d
L		 8292018-01-08 H.J. Lu <hongjiu.lu@intel.com>
830
831 PR gas/22681
832 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
833 Remove AVX512 vmovd with 64-bit operands.
834 * i386-tbl.h: Regenerated.
835
35eeb78f
JW		 8362018-01-05 Jim Wilson <jimw@sifive.com>
837
838 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
839 jalr.
840
219d1afa
AM		 8412018-01-03 Alan Modra <amodra@gmail.com>
842
843 Update year range in copyright notice of all files.
844
1508bbf5
JB		 8452018-01-02 Jan Beulich <jbeulich@suse.com>
846
847 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
848 and OPERAND_TYPE_REGZMM entries.
849
1e563868 850For older changes see ChangeLog-2017
3499769a 851\f
1e563868 852Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 853
854Copying and distribution of this file, with or without modification,
855are permitted in any medium without royalty provided the copyright
856notice and this notice are preserved.
857
858Local Variables:
859mode: change-log
860left-margin: 8
861fill-column: 74
862version-control: never
863End:
GDB Binutils - Deliverables
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