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Re-generate many configure and Makefile.in files
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
e0b2a78c
SM		 12019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
2
3 * Makefile.in: Re-generate.
4 * configure: Re-generate.
5
7e9ad3a3
JW		 62019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
7
8 * riscv-opc.c (riscv_opcodes): Change subset field
9 to insn_class field for all instructions.
10 (riscv_insn_types): Likewise.
11
bb695960
PB		 122019-09-16 Phil Blundell <pb@pbcl.net>
13
14 * configure: Regenerated.
15
8063ab7e
MV		 162019-09-10 Miod Vallat <miod@online.fr>
17
18 PR 24982
19 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
20
60391a25
PB		 212019-09-09 Phil Blundell <pb@pbcl.net>
22
23 binutils 2.33 branch created.
24
f44b758d
NC		 252019-09-03 Nick Clifton <nickc@redhat.com>
26
27 PR 24961
28 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
29 greater than zero before indexing via (bufcnt -1).
30
1e4b5e7d
NC		 312019-09-03 Nick Clifton <nickc@redhat.com>
32
33 PR 24958
34 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
35 (MAX_SPEC_REG_NAME_LEN): Define.
36 (struct mmix_dis_info): Use defined constants for array lengths.
37 (get_reg_name): New function.
38 (get_sprec_reg_name): New function.
39 (print_insn_mmix): Use new functions.
40
c4a23bf8
SP		 412019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
42
43 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
44 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
45 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
46
a051e2f3
KT		 472019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
48
49 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
50 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
51 (aarch64_sys_reg_supported_p): Update checks for the above.
52
08132bdd
SP		 532019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
54
55 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
56 cases MVE_SQRSHRL and MVE_UQRSHLL.
57 (print_insn_mve): Add case for specifier 'k' to check
58 specific bit of the instruction.
59
d88bdcb4
PA		 602019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
61
62 PR 24854
63 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
64 encountering an unknown machine type.
65 (print_insn_arc): Handle arc_insn_length returning 0. In error
66 cases return -1 rather than calling abort.
67
bc750500
JB		 682019-08-07 Jan Beulich <jbeulich@suse.com>
69
70 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
71 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
72 IgnoreSize.
73 * i386-tbl.h: Re-generate.
74
23d188c7
BW		 752019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
76
77 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
78 instructions.
79
c0d6f62f
JW		 802019-07-30 Mel Chen <mel.chen@sifive.com>
81
82 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
83 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
84
85 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
86 fscsr.
87
0f3f7167
CZ		 882019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
89
90 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
91 and MPY class instructions.
92 (parse_option): Add nps400 option.
93 (print_arc_disassembler_options): Add nps400 info.
94
7e126ba3
CZ		 952019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
96
97 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
98 (bspop): Likewise.
99 (modapp): Likewise.
100 * arc-opc.c (RAD_CHK): Add.
101 * arc-tbl.h: Regenerate.
102
a028026d
KT		 1032019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
104
105 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
106 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
107
ac79ff9e
NC		 1082019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
109
110 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
111 instructions as UNPREDICTABLE.
112
231097b0
JM		 1132019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
114
115 * bpf-desc.c: Regenerated.
116
1d942ae9
JB		 1172019-07-17 Jan Beulich <jbeulich@suse.com>
118
119 * i386-gen.c (static_assert): Define.
120 (main): Use it.
121 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
122 (Opcode_Modifier_Num): ... this.
123 (Mem): Delete.
124
dfd69174
JB		 1252019-07-16 Jan Beulich <jbeulich@suse.com>
126
127 * i386-gen.c (operand_types): Move RegMem ...
128 (opcode_modifiers): ... here.
129 * i386-opc.h (RegMem): Move to opcode modifer enum.
130 (union i386_operand_type): Move regmem field ...
131 (struct i386_opcode_modifier): ... here.
132 * i386-opc.tbl (RegMem): Define.
133 (mov, movq): Move RegMem on segment, control, debug, and test
134 register flavors.
135 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
136 to non-SSE2AVX flavor.
137 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
138 Move RegMem on register only flavors. Drop IgnoreSize from
139 legacy encoding flavors.
140 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
141 flavors.
142 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
143 register only flavors.
144 (vmovd): Move RegMem and drop IgnoreSize on register only
145 flavor. Change opcode and operand order to store form.
146 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
147
21df382b
JB		 1482019-07-16 Jan Beulich <jbeulich@suse.com>
149
150 * i386-gen.c (operand_type_init, operand_types): Replace SReg
151 entries.
152 * i386-opc.h (SReg2, SReg3): Replace by ...
153 (SReg): ... this.
154 (union i386_operand_type): Replace sreg fields.
155 * i386-opc.tbl (mov, ): Use SReg.
156 (push, pop): Likewies. Drop i386 and x86-64 specific segment
157 register flavors.
158 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
159 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
160
3719fd55
JM		 1612019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
162
163 * bpf-desc.c: Regenerate.
164 * bpf-opc.c: Likewise.
165 * bpf-opc.h: Likewise.
166
92434a14
JM		 1672019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
168
169 * bpf-desc.c: Regenerate.
170 * bpf-opc.c: Likewise.
171
43dd7626
HPN		 1722019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
173
174 * arm-dis.c (print_insn_coprocessor): Rename index to
175 index_operand.
176
98602811
JW		 1772019-07-05 Kito Cheng <kito.cheng@sifive.com>
178
179 * riscv-opc.c (riscv_insn_types): Add r4 type.
180
181 * riscv-opc.c (riscv_insn_types): Add b and j type.
182
183 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
184 format for sb type and correct s type.
185
01c1ee4a
RS		 1862019-07-02 Richard Sandiford <richard.sandiford@arm.com>
187
188 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
189 SVE FMOV alias of FCPY.
190
83adff69
RS		 1912019-07-02 Richard Sandiford <richard.sandiford@arm.com>
192
193 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
194 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
195
89418844
RS		 1962019-07-02 Richard Sandiford <richard.sandiford@arm.com>
197
198 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
199 registers in an instruction prefixed by MOVPRFX.
200
41be57ca
MM		 2012019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
202
203 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
204 sve_size_13 icode to account for variant behaviour of
205 pmull{t,b}.
206 * aarch64-dis-2.c: Regenerate.
207 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
208 sve_size_13 icode to account for variant behaviour of
209 pmull{t,b}.
210 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
211 (OP_SVE_VVV_Q_D): Add new qualifier.
212 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
213 (struct aarch64_opcode): Split pmull{t,b} into those requiring
214 AES and those not.
215
9d3bf266
JB		 2162019-07-01 Jan Beulich <jbeulich@suse.com>
217
218 * opcodes/i386-gen.c (operand_type_init): Remove
219 OPERAND_TYPE_VEC_IMM4 entry.
220 (operand_types): Remove Vec_Imm4.
221 * opcodes/i386-opc.h (Vec_Imm4): Delete.
222 (union i386_operand_type): Remove vec_imm4.
223 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
224 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
225
c3949f43
JB		 2262019-07-01 Jan Beulich <jbeulich@suse.com>
227
228 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
229 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
230 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
231 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
232 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
233 monitorx, mwaitx): Drop ImmExt from operand-less forms.
234 * i386-tbl.h: Re-generate.
235
5641ec01
JB		 2362019-07-01 Jan Beulich <jbeulich@suse.com>
237
238 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
239 register operands.
240 * i386-tbl.h: Re-generate.
241
79dec6b7
JB		 2422019-07-01 Jan Beulich <jbeulich@suse.com>
243
244 * i386-opc.tbl (C): New.
245 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
246 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
247 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
248 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
249 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
250 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
251 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
252 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
253 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
254 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
255 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
256 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
257 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
258 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
259 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
260 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
261 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
262 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
263 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
264 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
265 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
266 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
267 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
268 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
269 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
270 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
271 flavors.
272 * i386-tbl.h: Re-generate.
273
a0a1771e
JB		 2742019-07-01 Jan Beulich <jbeulich@suse.com>
275
276 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
277 register operands.
278 * i386-tbl.h: Re-generate.
279
cd546e7b
JB		 2802019-07-01 Jan Beulich <jbeulich@suse.com>
281
282 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
283 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
284 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
285 * i386-tbl.h: Re-generate.
286
e3bba3fc
JB		 2872019-07-01 Jan Beulich <jbeulich@suse.com>
288
289 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
290 Disp8MemShift from register only templates.
291 * i386-tbl.h: Re-generate.
292
36cc073e
JB		 2932019-07-01 Jan Beulich <jbeulich@suse.com>
294
295 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
296 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
297 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
298 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
299 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
300 EVEX_W_0F11_P_3_M_1): Delete.
301 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
302 EVEX_W_0F11_P_3): New.
303 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
304 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
305 MOD_EVEX_0F11_PREFIX_3 table entries.
306 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
307 PREFIX_EVEX_0F11 table entries.
308 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
309 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
310 EVEX_W_0F11_P_3_M_{0,1} table entries.
311
219920a7
JB		 3122019-07-01 Jan Beulich <jbeulich@suse.com>
313
314 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
315 Delete.
316
e395f487
L		 3172019-06-27 H.J. Lu <hongjiu.lu@intel.com>
318
319 PR binutils/24719
320 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
321 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
322 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
323 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
324 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
325 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
326 EVEX_LEN_0F38C7_R_6_P_2_W_1.
327 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
328 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
329 PREFIX_EVEX_0F38C6_REG_6 entries.
330 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
331 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
332 EVEX_W_0F38C7_R_6_P_2 entries.
333 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
334 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
335 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
336 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
337 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
338 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
339 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
340
2b7bcc87
JB		 3412019-06-27 Jan Beulich <jbeulich@suse.com>
342
343 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
344 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
345 VEX_LEN_0F2D_P_3): Delete.
346 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
347 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
348 (prefix_table): ... here.
349
c1dc7af5
JB		 3502019-06-27 Jan Beulich <jbeulich@suse.com>
351
352 * i386-dis.c (Iq): Delete.
353 (Id): New.
354 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
355 TBM insns.
356 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
357 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
358 (OP_E_memory): Also honor needindex when deciding whether an
359 address size prefix needs printing.
360 (OP_I): Remove handling of q_mode. Add handling of d_mode.
361
d7560e2d
JW		 3622019-06-26 Jim Wilson <jimw@sifive.com>
363
364 PR binutils/24739
365 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
366 Set info->display_endian to info->endian_code.
367
2c703856
JB		 3682019-06-25 Jan Beulich <jbeulich@suse.com>
369
370 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
371 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
372 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
373 OPERAND_TYPE_ACC64 entries.
374 * i386-init.h: Re-generate.
375
54fbadc0
JB		 3762019-06-25 Jan Beulich <jbeulich@suse.com>
377
378 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
379 Delete.
380 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
381 of dqa_mode.
382 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
383 entries here.
384 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
385 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
386
a280ab8e
JB		 3872019-06-25 Jan Beulich <jbeulich@suse.com>
388
389 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
390 variables.
391
e1a1babd
JB		 3922019-06-25 Jan Beulich <jbeulich@suse.com>
393
394 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
395 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
396 movnti.
d7560e2d 397 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 398 * i386-tbl.h: Re-generate.
399
b8364fa7
JB		 4002019-06-25 Jan Beulich <jbeulich@suse.com>
401
402 * i386-opc.tbl (and): Mark Imm8S form for optimization.
403 * i386-tbl.h: Re-generate.
404
ad692897
L		 4052019-06-21 H.J. Lu <hongjiu.lu@intel.com>
406
407 * i386-dis-evex.h: Break into ...
408 * i386-dis-evex-len.h: New file.
409 * i386-dis-evex-mod.h: Likewise.
410 * i386-dis-evex-prefix.h: Likewise.
411 * i386-dis-evex-reg.h: Likewise.
412 * i386-dis-evex-w.h: Likewise.
413 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
414 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
415 i386-dis-evex-mod.h.
416
f0a6222e
L		 4172019-06-19 H.J. Lu <hongjiu.lu@intel.com>
418
419 PR binutils/24700
420 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
421 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
422 EVEX_W_0F385B_P_2.
423 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
424 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
425 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
426 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
427 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
428 EVEX_LEN_0F385B_P_2_W_1.
429 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
430 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
431 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
432 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
433 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
434 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
435 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
436 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
437 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
438 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
439
6e1c90b7
L		 4402019-06-17 H.J. Lu <hongjiu.lu@intel.com>
441
442 PR binutils/24691
443 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
444 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
445 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
446 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
447 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
448 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
449 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
450 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
451 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
452 EVEX_LEN_0F3A43_P_2_W_1.
453 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
454 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
455 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
456 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
457 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
458 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
459 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
460 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
461 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
462 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
463 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
464 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
465
bcc5a6eb
NC		 4662019-06-14 Nick Clifton <nickc@redhat.com>
467
468 * po/fr.po; Updated French translation.
469
e4c4ac46
SH		 4702019-06-13 Stafford Horne <shorne@gmail.com>
471
472 * or1k-asm.c: Regenerated.
473 * or1k-desc.c: Regenerated.
474 * or1k-desc.h: Regenerated.
475 * or1k-dis.c: Regenerated.
476 * or1k-ibld.c: Regenerated.
477 * or1k-opc.c: Regenerated.
478 * or1k-opc.h: Regenerated.
479 * or1k-opinst.c: Regenerated.
480
a0e44ef5
PB		 4812019-06-12 Peter Bergner <bergner@linux.ibm.com>
482
483 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
484
12efd68d
L		 4852019-06-05 H.J. Lu <hongjiu.lu@intel.com>
486
487 PR binutils/24633
488 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
489 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
490 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
491 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
492 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
493 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
494 EVEX_LEN_0F3A1B_P_2_W_1.
495 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
496 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
497 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
498 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
499 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
500 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
501 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
502 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
503
63c6fc6c
L		 5042019-06-04 H.J. Lu <hongjiu.lu@intel.com>
505
506 PR binutils/24626
507 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
508 EVEX.vvvv when disassembling VEX and EVEX instructions.
509 (OP_VEX): Set vex.register_specifier to 0 after readding
510 vex.register_specifier.
511 (OP_Vex_2src_1): Likewise.
512 (OP_Vex_2src_2): Likewise.
513 (OP_LWP_E): Likewise.
514 (OP_EX_Vex): Don't check vex.register_specifier.
515 (OP_XMM_Vex): Likewise.
516
9186c494
L		 5172019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
518 Lili Cui <lili.cui@intel.com>
519
520 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
521 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
522 instructions.
523 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
524 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
525 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
526 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
527 (i386_cpu_flags): Add cpuavx512_vp2intersect.
528 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
529 * i386-init.h: Regenerated.
530 * i386-tbl.h: Likewise.
531
5d79adc4
L		 5322019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
533 Lili Cui <lili.cui@intel.com>
534
535 * doc/c-i386.texi: Document enqcmd.
536 * testsuite/gas/i386/enqcmd-intel.d: New file.
537 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
538 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
539 * testsuite/gas/i386/enqcmd.d: Likewise.
540 * testsuite/gas/i386/enqcmd.s: Likewise.
541 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
542 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
543 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
544 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
545 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
546 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
547 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
548 and x86-64-enqcmd.
549
a9d96ab9
AH		 5502019-06-04 Alan Hayward <alan.hayward@arm.com>
551
552 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
553
4f6d070a
AM		 5542019-06-03 Alan Modra <amodra@gmail.com>
555
556 * ppc-dis.c (prefix_opcd_indices): Correct size.
557
a2f4b66c
L		 5582019-05-28 H.J. Lu <hongjiu.lu@intel.com>
559
560 PR gas/24625
561 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
562 Disp8ShiftVL.
563 * i386-tbl.h: Regenerated.
564
405b5bd8
AM		 5652019-05-24 Alan Modra <amodra@gmail.com>
566
567 * po/POTFILES.in: Regenerate.
568
8acf1435
PB		 5692019-05-24 Peter Bergner <bergner@linux.ibm.com>
570 Alan Modra <amodra@gmail.com>
571
572 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
573 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
574 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
575 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
576 XTOP>): Define and add entries.
577 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
578 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
579 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
580 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
581
dd7efa79
PB		 5822019-05-24 Peter Bergner <bergner@linux.ibm.com>
583 Alan Modra <amodra@gmail.com>
584
585 * ppc-dis.c (ppc_opts): Add "future" entry.
586 (PREFIX_OPCD_SEGS): Define.
587 (prefix_opcd_indices): New array.
588 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
589 (lookup_prefix): New function.
590 (print_insn_powerpc): Handle 64-bit prefix instructions.
591 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
592 (PMRR, POWERXX): Define.
593 (prefix_opcodes): New instruction table.
594 (prefix_num_opcodes): New constant.
595
79472b45
JM		 5962019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
597
598 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
599 * configure: Regenerated.
600 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
601 and cpu/bpf.opc.
602 (HFILES): Add bpf-desc.h and bpf-opc.h.
603 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
604 bpf-ibld.c and bpf-opc.c.
605 (BPF_DEPS): Define.
606 * Makefile.in: Regenerated.
607 * disassemble.c (ARCH_bpf): Define.
608 (disassembler): Add case for bfd_arch_bpf.
609 (disassemble_init_for_target): Likewise.
610 (enum epbf_isa_attr): Define.
611 * disassemble.h: extern print_insn_bpf.
612 * bpf-asm.c: Generated.
613 * bpf-opc.h: Likewise.
614 * bpf-opc.c: Likewise.
615 * bpf-ibld.c: Likewise.
616 * bpf-dis.c: Likewise.
617 * bpf-desc.h: Likewise.
618 * bpf-desc.c: Likewise.
619
ba6cd17f
SD		 6202019-05-21 Sudakshina Das <sudi.das@arm.com>
621
622 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
623 and VMSR with the new operands.
624
e39c1607
SD		 6252019-05-21 Sudakshina Das <sudi.das@arm.com>
626
627 * arm-dis.c (enum mve_instructions): New enum
628 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
629 and cneg.
630 (mve_opcodes): New instructions as above.
631 (is_mve_encoding_conflict): Add cases for csinc, csinv,
632 csneg and csel.
633 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
634
23d00a41
SD		 6352019-05-21 Sudakshina Das <sudi.das@arm.com>
636
637 * arm-dis.c (emun mve_instructions): Updated for new instructions.
638 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
639 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
640 uqshl, urshrl and urshr.
641 (is_mve_okay_in_it): Add new instructions to TRUE list.
642 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
643 (print_insn_mve): Updated to accept new %j,
644 %<bitfield>m and %<bitfield>n patterns.
645
cd4797ee
FS		 6462019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
647
648 * mips-opc.c (mips_builtin_opcodes): Change source register
649 constraint for DAUI.
650
999b073b
NC		 6512019-05-20 Nick Clifton <nickc@redhat.com>
652
653 * po/fr.po: Updated French translation.
654
14b456f2
AV		 6552019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
656 Michael Collison <michael.collison@arm.com>
657
658 * arm-dis.c (thumb32_opcodes): Add new instructions.
659 (enum mve_instructions): Likewise.
660 (enum mve_undefined): Add new reasons.
661 (is_mve_encoding_conflict): Handle new instructions.
662 (is_mve_undefined): Likewise.
663 (is_mve_unpredictable): Likewise.
664 (print_mve_undefined): Likewise.
665 (print_mve_size): Likewise.
666
f49bb598
AV		 6672019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
668 Michael Collison <michael.collison@arm.com>
669
670 * arm-dis.c (thumb32_opcodes): Add new instructions.
671 (enum mve_instructions): Likewise.
672 (is_mve_encoding_conflict): Handle new instructions.
673 (is_mve_undefined): Likewise.
674 (is_mve_unpredictable): Likewise.
675 (print_mve_size): Likewise.
676
56858bea
AV		 6772019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
678 Michael Collison <michael.collison@arm.com>
679
680 * arm-dis.c (thumb32_opcodes): Add new instructions.
681 (enum mve_instructions): Likewise.
682 (is_mve_encoding_conflict): Likewise.
683 (is_mve_unpredictable): Likewise.
684 (print_mve_size): Likewise.
685
e523f101
AV		 6862019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
687 Michael Collison <michael.collison@arm.com>
688
689 * arm-dis.c (thumb32_opcodes): Add new instructions.
690 (enum mve_instructions): Likewise.
691 (is_mve_encoding_conflict): Handle new instructions.
692 (is_mve_undefined): Likewise.
693 (is_mve_unpredictable): Likewise.
694 (print_mve_size): Likewise.
695
66dcaa5d
AV		 6962019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
697 Michael Collison <michael.collison@arm.com>
698
699 * arm-dis.c (thumb32_opcodes): Add new instructions.
700 (enum mve_instructions): Likewise.
701 (is_mve_encoding_conflict): Handle new instructions.
702 (is_mve_undefined): Likewise.
703 (is_mve_unpredictable): Likewise.
704 (print_mve_size): Likewise.
705 (print_insn_mve): Likewise.
706
d052b9b7
AV		 7072019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
708 Michael Collison <michael.collison@arm.com>
709
710 * arm-dis.c (thumb32_opcodes): Add new instructions.
711 (print_insn_thumb32): Handle new instructions.
712
ed63aa17
AV		 7132019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
714 Michael Collison <michael.collison@arm.com>
715
716 * arm-dis.c (enum mve_instructions): Add new instructions.
717 (enum mve_undefined): Add new reasons.
718 (is_mve_encoding_conflict): Handle new instructions.
719 (is_mve_undefined): Likewise.
720 (is_mve_unpredictable): Likewise.
721 (print_mve_undefined): Likewise.
722 (print_mve_size): Likewise.
723 (print_mve_shift_n): Likewise.
724 (print_insn_mve): Likewise.
725
897b9bbc
AV		 7262019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
727 Michael Collison <michael.collison@arm.com>
728
729 * arm-dis.c (enum mve_instructions): Add new instructions.
730 (is_mve_encoding_conflict): Handle new instructions.
731 (is_mve_unpredictable): Likewise.
732 (print_mve_rotate): Likewise.
733 (print_mve_size): Likewise.
734 (print_insn_mve): Likewise.
735
1c8f2df8
AV		 7362019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
737 Michael Collison <michael.collison@arm.com>
738
739 * arm-dis.c (enum mve_instructions): Add new instructions.
740 (is_mve_encoding_conflict): Handle new instructions.
741 (is_mve_unpredictable): Likewise.
742 (print_mve_size): Likewise.
743 (print_insn_mve): Likewise.
744
d3b63143
AV		 7452019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
746 Michael Collison <michael.collison@arm.com>
747
748 * arm-dis.c (enum mve_instructions): Add new instructions.
749 (enum mve_undefined): Add new reasons.
750 (is_mve_encoding_conflict): Handle new instructions.
751 (is_mve_undefined): Likewise.
752 (is_mve_unpredictable): Likewise.
753 (print_mve_undefined): Likewise.
754 (print_mve_size): Likewise.
755 (print_insn_mve): Likewise.
756
14925797
AV		 7572019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
758 Michael Collison <michael.collison@arm.com>
759
760 * arm-dis.c (enum mve_instructions): Add new instructions.
761 (is_mve_encoding_conflict): Handle new instructions.
762 (is_mve_undefined): Likewise.
763 (is_mve_unpredictable): Likewise.
764 (print_mve_size): Likewise.
765 (print_insn_mve): Likewise.
766
c507f10b
AV		 7672019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
768 Michael Collison <michael.collison@arm.com>
769
770 * arm-dis.c (enum mve_instructions): Add new instructions.
771 (enum mve_unpredictable): Add new reasons.
772 (enum mve_undefined): Likewise.
773 (is_mve_okay_in_it): Handle new isntructions.
774 (is_mve_encoding_conflict): Likewise.
775 (is_mve_undefined): Likewise.
776 (is_mve_unpredictable): Likewise.
777 (print_mve_vmov_index): Likewise.
778 (print_simd_imm8): Likewise.
779 (print_mve_undefined): Likewise.
780 (print_mve_unpredictable): Likewise.
781 (print_mve_size): Likewise.
782 (print_insn_mve): Likewise.
783
bf0b396d
AV		 7842019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
785 Michael Collison <michael.collison@arm.com>
786
787 * arm-dis.c (enum mve_instructions): Add new instructions.
788 (enum mve_unpredictable): Add new reasons.
789 (enum mve_undefined): Likewise.
790 (is_mve_encoding_conflict): Handle new instructions.
791 (is_mve_undefined): Likewise.
792 (is_mve_unpredictable): Likewise.
793 (print_mve_undefined): Likewise.
794 (print_mve_unpredictable): Likewise.
795 (print_mve_rounding_mode): Likewise.
796 (print_mve_vcvt_size): Likewise.
797 (print_mve_size): Likewise.
798 (print_insn_mve): Likewise.
799
ef1576a1
AV		 8002019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
801 Michael Collison <michael.collison@arm.com>
802
803 * arm-dis.c (enum mve_instructions): Add new instructions.
804 (enum mve_unpredictable): Add new reasons.
805 (enum mve_undefined): Likewise.
806 (is_mve_undefined): Handle new instructions.
807 (is_mve_unpredictable): Likewise.
808 (print_mve_undefined): Likewise.
809 (print_mve_unpredictable): Likewise.
810 (print_mve_size): Likewise.
811 (print_insn_mve): Likewise.
812
aef6d006
AV		 8132019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
814 Michael Collison <michael.collison@arm.com>
815
816 * arm-dis.c (enum mve_instructions): Add new instructions.
817 (enum mve_undefined): Add new reasons.
818 (insns): Add new instructions.
819 (is_mve_encoding_conflict):
820 (print_mve_vld_str_addr): New print function.
821 (is_mve_undefined): Handle new instructions.
822 (is_mve_unpredictable): Likewise.
823 (print_mve_undefined): Likewise.
824 (print_mve_size): Likewise.
825 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
826 (print_insn_mve): Handle new operands.
827
04d54ace
AV		 8282019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
829 Michael Collison <michael.collison@arm.com>
830
831 * arm-dis.c (enum mve_instructions): Add new instructions.
832 (enum mve_unpredictable): Add new reasons.
833 (is_mve_encoding_conflict): Handle new instructions.
834 (is_mve_unpredictable): Likewise.
835 (mve_opcodes): Add new instructions.
836 (print_mve_unpredictable): Handle new reasons.
837 (print_mve_register_blocks): New print function.
838 (print_mve_size): Handle new instructions.
839 (print_insn_mve): Likewise.
840
9743db03
AV		 8412019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
842 Michael Collison <michael.collison@arm.com>
843
844 * arm-dis.c (enum mve_instructions): Add new instructions.
845 (enum mve_unpredictable): Add new reasons.
846 (enum mve_undefined): Likewise.
847 (is_mve_encoding_conflict): Handle new instructions.
848 (is_mve_undefined): Likewise.
849 (is_mve_unpredictable): Likewise.
850 (coprocessor_opcodes): Move NEON VDUP from here...
851 (neon_opcodes): ... to here.
852 (mve_opcodes): Add new instructions.
853 (print_mve_undefined): Handle new reasons.
854 (print_mve_unpredictable): Likewise.
855 (print_mve_size): Handle new instructions.
856 (print_insn_neon): Handle vdup.
857 (print_insn_mve): Handle new operands.
858
143275ea
AV		 8592019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
860 Michael Collison <michael.collison@arm.com>
861
862 * arm-dis.c (enum mve_instructions): Add new instructions.
863 (enum mve_unpredictable): Add new values.
864 (mve_opcodes): Add new instructions.
865 (vec_condnames): New array with vector conditions.
866 (mve_predicatenames): New array with predicate suffixes.
867 (mve_vec_sizename): New array with vector sizes.
868 (enum vpt_pred_state): New enum with vector predication states.
869 (struct vpt_block): New struct type for vpt blocks.
870 (vpt_block_state): Global struct to keep track of state.
871 (mve_extract_pred_mask): New helper function.
872 (num_instructions_vpt_block): Likewise.
873 (mark_outside_vpt_block): Likewise.
874 (mark_inside_vpt_block): Likewise.
875 (invert_next_predicate_state): Likewise.
876 (update_next_predicate_state): Likewise.
877 (update_vpt_block_state): Likewise.
878 (is_vpt_instruction): Likewise.
879 (is_mve_encoding_conflict): Add entries for new instructions.
880 (is_mve_unpredictable): Likewise.
881 (print_mve_unpredictable): Handle new cases.
882 (print_instruction_predicate): Likewise.
883 (print_mve_size): New function.
884 (print_vec_condition): New function.
885 (print_insn_mve): Handle vpt blocks and new print operands.
886
f08d8ce3
AV		 8872019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
888
889 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
890 8, 14 and 15 for Armv8.1-M Mainline.
891
73cd51e5
AV		 8922019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
893 Michael Collison <michael.collison@arm.com>
894
895 * arm-dis.c (enum mve_instructions): New enum.
896 (enum mve_unpredictable): Likewise.
897 (enum mve_undefined): Likewise.
898 (struct mopcode32): New struct.
899 (is_mve_okay_in_it): New function.
900 (is_mve_architecture): Likewise.
901 (arm_decode_field): Likewise.
902 (arm_decode_field_multiple): Likewise.
903 (is_mve_encoding_conflict): Likewise.
904 (is_mve_undefined): Likewise.
905 (is_mve_unpredictable): Likewise.
906 (print_mve_undefined): Likewise.
907 (print_mve_unpredictable): Likewise.
908 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
909 (print_insn_mve): New function.
910 (print_insn_thumb32): Handle MVE architecture.
911 (select_arm_features): Force thumb for Armv8.1-m Mainline.
912
3076e594
NC		 9132019-05-10 Nick Clifton <nickc@redhat.com>
914
915 PR 24538
916 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
917 end of the table prematurely.
918
387e7624
FS		 9192019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
920
921 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
922 macros for R6.
923
0067be51
AM		 9242019-05-11 Alan Modra <amodra@gmail.com>
925
926 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
927 when -Mraw is in effect.
928
42e6288f
MM		 9292019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
930
931 * aarch64-dis-2.c: Regenerate.
932 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
933 (OP_SVE_BBB): New variant set.
934 (OP_SVE_DDDD): New variant set.
935 (OP_SVE_HHH): New variant set.
936 (OP_SVE_HHHU): New variant set.
937 (OP_SVE_SSS): New variant set.
938 (OP_SVE_SSSU): New variant set.
939 (OP_SVE_SHH): New variant set.
940 (OP_SVE_SBBU): New variant set.
941 (OP_SVE_DSS): New variant set.
942 (OP_SVE_DHHU): New variant set.
943 (OP_SVE_VMV_HSD_BHS): New variant set.
944 (OP_SVE_VVU_HSD_BHS): New variant set.
945 (OP_SVE_VVVU_SD_BH): New variant set.
946 (OP_SVE_VVVU_BHSD): New variant set.
947 (OP_SVE_VVV_QHD_DBS): New variant set.
948 (OP_SVE_VVV_HSD_BHS): New variant set.
949 (OP_SVE_VVV_HSD_BHS2): New variant set.
950 (OP_SVE_VVV_BHS_HSD): New variant set.
951 (OP_SVE_VV_BHS_HSD): New variant set.
952 (OP_SVE_VVV_SD): New variant set.
953 (OP_SVE_VVU_BHS_HSD): New variant set.
954 (OP_SVE_VZVV_SD): New variant set.
955 (OP_SVE_VZVV_BH): New variant set.
956 (OP_SVE_VZV_SD): New variant set.
957 (aarch64_opcode_table): Add sve2 instructions.
958
28ed815a
MM		 9592019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
960
961 * aarch64-asm-2.c: Regenerated.
962 * aarch64-dis-2.c: Regenerated.
963 * aarch64-opc-2.c: Regenerated.
964 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
965 for SVE_SHLIMM_UNPRED_22.
966 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
967 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
968 operand.
969
fd1dc4a0
MM		 9702019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
971
972 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
973 sve_size_tsz_bhs iclass encode.
974 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
975 sve_size_tsz_bhs iclass decode.
976
31e36ab3
MM		 9772019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
978
979 * aarch64-asm-2.c: Regenerated.
980 * aarch64-dis-2.c: Regenerated.
981 * aarch64-opc-2.c: Regenerated.
982 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
983 for SVE_Zm4_11_INDEX.
984 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
985 (fields): Handle SVE_i2h field.
986 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
987 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
988
1be5f94f
MM		 9892019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
990
991 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
992 sve_shift_tsz_bhsd iclass encode.
993 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
994 sve_shift_tsz_bhsd iclass decode.
995
3c17238b
MM		 9962019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
997
998 * aarch64-asm-2.c: Regenerated.
999 * aarch64-dis-2.c: Regenerated.
1000 * aarch64-opc-2.c: Regenerated.
1001 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1002 (aarch64_encode_variant_using_iclass): Handle
1003 sve_shift_tsz_hsd iclass encode.
1004 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1005 sve_shift_tsz_hsd iclass decode.
1006 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1007 for SVE_SHRIMM_UNPRED_22.
1008 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1009 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1010 operand.
1011
cd50a87a
MM		 10122019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1013
1014 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1015 sve_size_013 iclass encode.
1016 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1017 sve_size_013 iclass decode.
1018
3c705960
MM		 10192019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1020
1021 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1022 sve_size_bh iclass encode.
1023 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1024 sve_size_bh iclass decode.
1025
0a57e14f
MM		 10262019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1027
1028 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1029 sve_size_sd2 iclass encode.
1030 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1031 sve_size_sd2 iclass decode.
1032 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1033 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1034
c469c864
MM		 10352019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1036
1037 * aarch64-asm-2.c: Regenerated.
1038 * aarch64-dis-2.c: Regenerated.
1039 * aarch64-opc-2.c: Regenerated.
1040 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1041 for SVE_ADDR_ZX.
1042 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1043 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1044
116adc27
MM		 10452019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1046
1047 * aarch64-asm-2.c: Regenerated.
1048 * aarch64-dis-2.c: Regenerated.
1049 * aarch64-opc-2.c: Regenerated.
1050 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1051 for SVE_Zm3_11_INDEX.
1052 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1053 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1054 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1055 fields.
1056 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1057
3bd82c86
MM		 10582019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1059
1060 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1061 sve_size_hsd2 iclass encode.
1062 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1063 sve_size_hsd2 iclass decode.
1064 * aarch64-opc.c (fields): Handle SVE_size field.
1065 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1066
adccc507
MM		 10672019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1068
1069 * aarch64-asm-2.c: Regenerated.
1070 * aarch64-dis-2.c: Regenerated.
1071 * aarch64-opc-2.c: Regenerated.
1072 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1073 for SVE_IMM_ROT3.
1074 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1075 (fields): Handle SVE_rot3 field.
1076 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1077 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1078
5cd99750
MM		 10792019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1080
1081 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1082 instructions.
1083
7ce2460a
MM		 10842019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1085
1086 * aarch64-tbl.h
1087 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1088 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1089 aarch64_feature_sve2bitperm): New feature sets.
1090 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1091 for feature set addresses.
1092 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1093 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1094
41cee089
FS		 10952019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1096 Faraz Shahbazker <fshahbazker@wavecomp.com>
1097
1098 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1099 argument and set ASE_EVA_R6 appropriately.
1100 (set_default_mips_dis_options): Pass ISA to above.
1101 (parse_mips_dis_option): Likewise.
1102 * mips-opc.c (EVAR6): New macro.
1103 (mips_builtin_opcodes): Add llwpe, scwpe.
1104
b83b4b13
SD		 11052019-05-01 Sudakshina Das <sudi.das@arm.com>
1106
1107 * aarch64-asm-2.c: Regenerated.
1108 * aarch64-dis-2.c: Regenerated.
1109 * aarch64-opc-2.c: Regenerated.
1110 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1111 AARCH64_OPND_TME_UIMM16.
1112 (aarch64_print_operand): Likewise.
1113 * aarch64-tbl.h (QL_IMM_NIL): New.
1114 (TME): New.
1115 (_TME_INSN): New.
1116 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1117
4a90ce95
JD		 11182019-04-29 John Darrington <john@darrington.wattle.id.au>
1119
1120 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1121
a45328b9
AB		 11222019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1123 Faraz Shahbazker <fshahbazker@wavecomp.com>
1124
1125 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1126
d10be0cb
JD		 11272019-04-24 John Darrington <john@darrington.wattle.id.au>
1128
1129 * s12z-opc.h: Add extern "C" bracketing to help
1130 users who wish to use this interface in c++ code.
1131
a679f24e
JD		 11322019-04-24 John Darrington <john@darrington.wattle.id.au>
1133
1134 * s12z-opc.c (bm_decode): Handle bit map operations with the
1135 "reserved0" mode.
1136
32c36c3c
AV		 11372019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1138
1139 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1140 specifier. Add entries for VLDR and VSTR of system registers.
1141 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1142 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1143 of %J and %K format specifier.
1144
efd6b359
AV		 11452019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1146
1147 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1148 Add new entries for VSCCLRM instruction.
1149 (print_insn_coprocessor): Handle new %C format control code.
1150
6b0dd094
AV		 11512019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1152
1153 * arm-dis.c (enum isa): New enum.
1154 (struct sopcode32): New structure.
1155 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1156 set isa field of all current entries to ANY.
1157 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1158 Only match an entry if its isa field allows the current mode.
1159
4b5a202f
AV		 11602019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1161
1162 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1163 CLRM.
1164 (print_insn_thumb32): Add logic to print %n CLRM register list.
1165
60f993ce
AV		 11662019-04-15 Sudakshina Das <sudi.das@arm.com>
1167
1168 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1169 and %Q patterns.
1170
f6b2b12d
AV		 11712019-04-15 Sudakshina Das <sudi.das@arm.com>
1172
1173 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1174 (print_insn_thumb32): Edit the switch case for %Z.
1175
1889da70
AV		 11762019-04-15 Sudakshina Das <sudi.das@arm.com>
1177
1178 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1179
65d1bc05
AV		 11802019-04-15 Sudakshina Das <sudi.das@arm.com>
1181
1182 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1183
1caf72a5
AV		 11842019-04-15 Sudakshina Das <sudi.das@arm.com>
1185
1186 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1187
f1c7f421
AV		 11882019-04-15 Sudakshina Das <sudi.das@arm.com>
1189
1190 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1191 Arm register with r13 and r15 unpredictable.
1192 (thumb32_opcodes): New instructions for bfx and bflx.
1193
4389b29a
AV		 11942019-04-15 Sudakshina Das <sudi.das@arm.com>
1195
1196 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1197
e5d6e09e
AV		 11982019-04-15 Sudakshina Das <sudi.das@arm.com>
1199
1200 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1201
e12437dc
AV		 12022019-04-15 Sudakshina Das <sudi.das@arm.com>
1203
1204 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1205
031254f2
AV		 12062019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1207
1208 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1209
e5a557ac
JD		 12102019-04-12 John Darrington <john@darrington.wattle.id.au>
1211
1212 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1213 "optr". ("operator" is a reserved word in c++).
1214
bd7ceb8d
SD		 12152019-04-11 Sudakshina Das <sudi.das@arm.com>
1216
1217 * aarch64-opc.c (aarch64_print_operand): Add case for
1218 AARCH64_OPND_Rt_SP.
1219 (verify_constraints): Likewise.
1220 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1221 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1222 to accept Rt|SP as first operand.
1223 (AARCH64_OPERANDS): Add new Rt_SP.
1224 * aarch64-asm-2.c: Regenerated.
1225 * aarch64-dis-2.c: Regenerated.
1226 * aarch64-opc-2.c: Regenerated.
1227
e54010f1
SD		 12282019-04-11 Sudakshina Das <sudi.das@arm.com>
1229
1230 * aarch64-asm-2.c: Regenerated.
1231 * aarch64-dis-2.c: Likewise.
1232 * aarch64-opc-2.c: Likewise.
1233 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1234
7e96e219
RS		 12352019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1236
1237 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1238
6f2791d5
L		 12392019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1240
1241 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1242 * i386-init.h: Regenerated.
1243
e392bad3
AM		 12442019-04-07 Alan Modra <amodra@gmail.com>
1245
1246 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1247 op_separator to control printing of spaces, comma and parens
1248 rather than need_comma, need_paren and spaces vars.
1249
dffaa15c
AM		 12502019-04-07 Alan Modra <amodra@gmail.com>
1251
1252 PR 24421
1253 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1254 (print_insn_neon, print_insn_arm): Likewise.
1255
d6aab7a1
XG		 12562019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1257
1258 * i386-dis-evex.h (evex_table): Updated to support BF16
1259 instructions.
1260 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1261 and EVEX_W_0F3872_P_3.
1262 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1263 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1264 * i386-opc.h (enum): Add CpuAVX512_BF16.
1265 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1266 * i386-opc.tbl: Add AVX512 BF16 instructions.
1267 * i386-init.h: Regenerated.
1268 * i386-tbl.h: Likewise.
1269
66e85460
AM		 12702019-04-05 Alan Modra <amodra@gmail.com>
1271
1272 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1273 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1274 to favour printing of "-" branch hint when using the "y" bit.
1275 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1276
c2b1c275
AM		 12772019-04-05 Alan Modra <amodra@gmail.com>
1278
1279 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1280 opcode until first operand is output.
1281
aae9718e
PB		 12822019-04-04 Peter Bergner <bergner@linux.ibm.com>
1283
1284 PR gas/24349
1285 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1286 (valid_bo_post_v2): Add support for 'at' branch hints.
1287 (insert_bo): Only error on branch on ctr.
1288 (get_bo_hint_mask): New function.
1289 (insert_boe): Add new 'branch_taken' formal argument. Add support
1290 for inserting 'at' branch hints.
1291 (extract_boe): Add new 'branch_taken' formal argument. Add support
1292 for extracting 'at' branch hints.
1293 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1294 (BOE): Delete operand.
1295 (BOM, BOP): New operands.
1296 (RM): Update value.
1297 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1298 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1299 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1300 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1301 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1302 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1303 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1304 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1305 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1306 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1307 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1308 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1309 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1310 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1311 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1312 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1313 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1314 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1315 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1316 bttarl+>: New extended mnemonics.
1317
96a86c01
AM		 13182019-03-28 Alan Modra <amodra@gmail.com>
1319
1320 PR 24390
1321 * ppc-opc.c (BTF): Define.
1322 (powerpc_opcodes): Use for mtfsb*.
1323 * ppc-dis.c (print_insn_powerpc): Print fields with both
1324 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1325
796d6298
TC		 13262019-03-25 Tamar Christina <tamar.christina@arm.com>
1327
1328 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1329 (mapping_symbol_for_insn): Implement new algorithm.
1330 (print_insn): Remove duplicate code.
1331
60df3720
TC		 13322019-03-25 Tamar Christina <tamar.christina@arm.com>
1333
1334 * aarch64-dis.c (print_insn_aarch64):
1335 Implement override.
1336
51457761
TC		 13372019-03-25 Tamar Christina <tamar.christina@arm.com>
1338
1339 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1340 order.
1341
53b2f36b
TC		 13422019-03-25 Tamar Christina <tamar.christina@arm.com>
1343
1344 * aarch64-dis.c (last_stop_offset): New.
1345 (print_insn_aarch64): Use stop_offset.
1346
89199bb5
L		 13472019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1348
1349 PR gas/24359
1350 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1351 CPU_ANY_AVX2_FLAGS.
1352 * i386-init.h: Regenerated.
1353
97ed31ae
L		 13542019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1355
1356 PR gas/24348
1357 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1358 vmovdqu16, vmovdqu32 and vmovdqu64.
1359 * i386-tbl.h: Regenerated.
1360
0919bfe9
AK		 13612019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1362
1363 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1364 from vstrszb, vstrszh, and vstrszf.
1365
13662019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1367
1368 * s390-opc.txt: Add instruction descriptions.
1369
21820ebe
JW		 13702019-02-08 Jim Wilson <jimw@sifive.com>
1371
1372 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1373 <bne>: Likewise.
1374
f7dd2fb2
TC		 13752019-02-07 Tamar Christina <tamar.christina@arm.com>
1376
1377 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1378
6456d318
TC		 13792019-02-07 Tamar Christina <tamar.christina@arm.com>
1380
1381 PR binutils/23212
1382 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1383 * aarch64-opc.c (verify_elem_sd): New.
1384 (fields): Add FLD_sz entr.
1385 * aarch64-tbl.h (_SIMD_INSN): New.
1386 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1387 fmulx scalar and vector by element isns.
1388
4a83b610
NC		 13892019-02-07 Nick Clifton <nickc@redhat.com>
1390
1391 * po/sv.po: Updated Swedish translation.
1392
fc60b8c8
AK		 13932019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1394
1395 * s390-mkopc.c (main): Accept arch13 as cpu string.
1396 * s390-opc.c: Add new instruction formats and instruction opcode
1397 masks.
1398 * s390-opc.txt: Add new arch13 instructions.
1399
e10620d3
TC		 14002019-01-25 Sudakshina Das <sudi.das@arm.com>
1401
1402 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1403 (aarch64_opcode): Change encoding for stg, stzg
1404 st2g and st2zg.
1405 * aarch64-asm-2.c: Regenerated.
1406 * aarch64-dis-2.c: Regenerated.
1407 * aarch64-opc-2.c: Regenerated.
1408
20a4ca55
SD		 14092019-01-25 Sudakshina Das <sudi.das@arm.com>
1410
1411 * aarch64-asm-2.c: Regenerated.
1412 * aarch64-dis-2.c: Likewise.
1413 * aarch64-opc-2.c: Likewise.
1414 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1415
550fd7bf
SD		 14162019-01-25 Sudakshina Das <sudi.das@arm.com>
1417 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1418
1419 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1420 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1421 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1422 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1423 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1424 case for ldstgv_indexed.
1425 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1426 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1427 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1428 * aarch64-asm-2.c: Regenerated.
1429 * aarch64-dis-2.c: Regenerated.
1430 * aarch64-opc-2.c: Regenerated.
1431
d9938630
NC		 14322019-01-23 Nick Clifton <nickc@redhat.com>
1433
1434 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1435
375cd423
NC		 14362019-01-21 Nick Clifton <nickc@redhat.com>
1437
1438 * po/de.po: Updated German translation.
1439 * po/uk.po: Updated Ukranian translation.
1440
57299f48
CX		 14412019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1442 * mips-dis.c (mips_arch_choices): Fix typo in
1443 gs464, gs464e and gs264e descriptors.
1444
f48dfe41
NC		 14452019-01-19 Nick Clifton <nickc@redhat.com>
1446
1447 * configure: Regenerate.
1448 * po/opcodes.pot: Regenerate.
1449
f974f26c
NC		 14502018-06-24 Nick Clifton <nickc@redhat.com>
1451
1452 2.32 branch created.
1453
39f286cd
JD		 14542019-01-09 John Darrington <john@darrington.wattle.id.au>
1455
448b8ca8
JD		 1456 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1457 if it is null.
1458 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 1459 zero.
1460
3107326d
AP		 14612019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1462
1463 * configure: Regenerate.
1464
7e9ca91e
AM		 14652019-01-07 Alan Modra <amodra@gmail.com>
1466
1467 * configure: Regenerate.
1468 * po/POTFILES.in: Regenerate.
1469
ef1ad42b
JD		 14702019-01-03 John Darrington <john@darrington.wattle.id.au>
1471
1472 * s12z-opc.c: New file.
1473 * s12z-opc.h: New file.
1474 * s12z-dis.c: Removed all code not directly related to display
1475 of instructions. Used the interface provided by the new files
1476 instead.
1477 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 1478 * Makefile.in: Regenerate.
ef1ad42b 1479 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 1480 * configure: Regenerate.
ef1ad42b 1481
82704155
AM		 14822019-01-01 Alan Modra <amodra@gmail.com>
1483
1484 Update year range in copyright notice of all files.
1485
d5c04e1b 1486For older changes see ChangeLog-2018
3499769a 1487\f
d5c04e1b 1488Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 1489
1490Copying and distribution of this file, with or without modification,
1491are permitted in any medium without royalty provided the copyright
1492notice and this notice are preserved.
1493
1494Local Variables:
1495mode: change-log
1496left-margin: 8
1497fill-column: 74
1498version-control: never
1499End:
GDB Binutils - Deliverables
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