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[ARC] Fix handling of cpu=... disassembler option value
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
e1e94c49
AK		 12017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
2
3 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
4 disassembler option strings.
5 (parse_cpu_option): Likewise.
6
65a55fbb
TC		 72017-06-28 Tamar Christina <tamar.christina@arm.com>
8
9 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
10 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
11 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
12 (aarch64_feature_dotprod, DOT_INSN): New.
13 (udot, sdot): New.
14 * aarch64-dis-2.c: Regenerated.
15
c604a79a
JW		 162017-06-28 Jiong Wang <jiong.wang@arm.com>
17
18 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
19
38bf472a
MR		 202017-06-28 Maciej W. Rozycki <macro@imgtec.com>
21 Matthew Fortune <matthew.fortune@imgtec.com>
22 Andrew Bennett <andrew.bennett@imgtec.com>
23
24 * mips-formats.h (INT_BIAS): New macro.
25 (INT_ADJ): Redefine in INT_BIAS terms.
26 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
27 (mips_print_save_restore): New function.
28 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
29 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
30 call.
31 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
32 (print_mips16_insn_arg): Call `mips_print_save_restore' for
33 OP_SAVE_RESTORE_LIST handling, factored out from here.
34 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
35 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
36 (mips_builtin_opcodes): Add "restore" and "save" entries.
37 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
38 (IAMR2): New macro.
39 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
40
9bdfdbf9
AW		 412017-06-23 Andrew Waterman <andrew@sifive.com>
42
43 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
44 alias; do not mark SLTI instruction as an alias.
45
2234eee6
L		 462017-06-21 H.J. Lu <hongjiu.lu@intel.com>
47
48 * i386-dis.c (RM_0FAE_REG_5): Removed.
49 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
50 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
51 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
52 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
53 PREFIX_MOD_3_0F01_REG_5_RM_0.
54 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
55 PREFIX_MOD_3_0FAE_REG_5.
56 (mod_table): Update MOD_0FAE_REG_5.
57 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
58 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
59 * i386-tbl.h: Regenerated.
60
c2f76402
L		 612017-06-21 H.J. Lu <hongjiu.lu@intel.com>
62
63 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
64 * i386-opc.tbl: Likewise.
65 * i386-tbl.h: Regenerated.
66
9fef80d6
L		 672017-06-21 H.J. Lu <hongjiu.lu@intel.com>
68
69 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
70 and "jmp{&|}".
71 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
72 prefix.
73
0f6d864d
NC		 742017-06-19 Nick Clifton <nickc@redhat.com>
75
76 PR binutils/21614
77 * score-dis.c (score_opcodes): Add sentinel.
78
e197589b
AM		 792017-06-16 Alan Modra <amodra@gmail.com>
80
81 * rx-decode.c: Regenerate.
82
0d96e4df
L		 832017-06-15 H.J. Lu <hongjiu.lu@intel.com>
84
85 PR binutils/21594
86 * i386-dis.c (OP_E_register): Check valid bnd register.
87 (OP_G): Likewise.
88
cd3ea7c6
NC		 892017-06-15 Nick Clifton <nickc@redhat.com>
90
91 PR binutils/21595
92 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
93 range value.
94
63323b5b
NC		 952017-06-15 Nick Clifton <nickc@redhat.com>
96
97 PR binutils/21588
98 * rl78-decode.opc (OP_BUF_LEN): Define.
99 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
100 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
101 array.
102 * rl78-decode.c: Regenerate.
103
08c7881b
NC		 1042017-06-15 Nick Clifton <nickc@redhat.com>
105
106 PR binutils/21586
107 * bfin-dis.c (gregs): Clip index to prevent overflow.
108 (regs): Likewise.
109 (regs_lo): Likewise.
110 (regs_hi): Likewise.
111
e64519d1
NC		 1122017-06-14 Nick Clifton <nickc@redhat.com>
113
114 PR binutils/21576
115 * score7-dis.c (score_opcodes): Add sentinel.
116
6394c606
YQ		 1172017-06-14 Yao Qi <yao.qi@linaro.org>
118
119 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
120 * arm-dis.c: Likewise.
121 * ia64-dis.c: Likewise.
122 * mips-dis.c: Likewise.
123 * spu-dis.c: Likewise.
124 * disassemble.h (print_insn_aarch64): New declaration, moved from
125 include/dis-asm.h.
126 (print_insn_big_arm, print_insn_big_mips): Likewise.
127 (print_insn_i386, print_insn_ia64): Likewise.
128 (print_insn_little_arm, print_insn_little_mips): Likewise.
129
db5fa770
NC		 1302017-06-14 Nick Clifton <nickc@redhat.com>
131
132 PR binutils/21587
133 * rx-decode.opc: Include libiberty.h
134 (GET_SCALE): New macro - validates access to SCALE array.
135 (GET_PSCALE): New macro - validates access to PSCALE array.
136 (DIs, SIs, S2Is, rx_disp): Use new macros.
137 * rx-decode.c: Regenerate.
138
05c966f3
AV		 1392017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
140
141 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
142
10045478
AK		 1432017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
144
145 * arc-dis.c (enforced_isa_mask): Declare.
146 (cpu_types): Likewise.
147 (parse_cpu_option): New function.
148 (parse_disassembler_options): Use it.
149 (print_insn_arc): Use enforced_isa_mask.
150 (print_arc_disassembler_options): Document new options.
151
88c1242d
YQ		 1522017-05-24 Yao Qi <yao.qi@linaro.org>
153
154 * alpha-dis.c: Include disassemble.h, don't include
155 dis-asm.h.
156 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
157 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
158 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
159 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
160 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
161 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
162 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
163 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
164 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
165 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
166 * moxie-dis.c, msp430-dis.c, mt-dis.c:
167 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
168 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
169 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
170 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
171 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
172 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
173 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
174 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
175 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
176 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
177 * z80-dis.c, z8k-dis.c: Likewise.
178 * disassemble.h: New file.
179
ab20fa4a
YQ		 1802017-05-24 Yao Qi <yao.qi@linaro.org>
181
182 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
183 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
184
003ca0fd
YQ		 1852017-05-24 Yao Qi <yao.qi@linaro.org>
186
187 * disassemble.c (disassembler): Add arguments a, big and mach.
188 Use them.
189
04ef582a
L		 1902017-05-22 H.J. Lu <hongjiu.lu@intel.com>
191
192 * i386-dis.c (NOTRACK_Fixup): New.
193 (NOTRACK): Likewise.
194 (NOTRACK_PREFIX): Likewise.
195 (last_active_prefix): Likewise.
196 (reg_table): Use NOTRACK on indirect call and jmp.
197 (ckprefix): Set last_active_prefix.
198 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
199 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
200 * i386-opc.h (NoTrackPrefixOk): New.
201 (i386_opcode_modifier): Add notrackprefixok.
202 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
203 Add notrack.
204 * i386-tbl.h: Regenerated.
205
64517994
JM		 2062017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
207
208 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
209 (X_IMM2): Define.
210 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
211 bfd_mach_sparc_v9m8.
212 (print_insn_sparc): Handle new operand types.
213 * sparc-opc.c (MASK_M8): Define.
214 (v6): Add MASK_M8.
215 (v6notlet): Likewise.
216 (v7): Likewise.
217 (v8): Likewise.
218 (v9): Likewise.
219 (v9a): Likewise.
220 (v9b): Likewise.
221 (v9c): Likewise.
222 (v9d): Likewise.
223 (v9e): Likewise.
224 (v9v): Likewise.
225 (v9m): Likewise.
226 (v9andleon): Likewise.
227 (m8): Define.
228 (HWS_VM8): Define.
229 (HWS2_VM8): Likewise.
230 (sparc_opcode_archs): Add entry for "m8".
231 (sparc_opcodes): Add OSA2017 and M8 instructions
232 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
233 fpx{ll,ra,rl}64x,
234 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
235 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
236 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
237 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
238 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
239 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
240 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
241 ASI_CORE_SELECT_COMMIT_NHT.
242
535b785f
AM		 2432017-05-18 Alan Modra <amodra@gmail.com>
244
245 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
246 * aarch64-dis.c: Likewise.
247 * aarch64-gen.c: Likewise.
248 * aarch64-opc.c: Likewise.
249
25499ac7
MR		 2502017-05-15 Maciej W. Rozycki <macro@imgtec.com>
251 Matthew Fortune <matthew.fortune@imgtec.com>
252
253 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
254 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
255 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
256 (print_insn_arg) <OP_REG28>: Add handler.
257 (validate_insn_args) <OP_REG28>: Handle.
258 (print_mips16_insn_arg): Handle MIPS16 instructions that require
259 32-bit encoding and 9-bit immediates.
260 (print_insn_mips16): Handle MIPS16 instructions that require
261 32-bit encoding and MFC0/MTC0 operand decoding.
262 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
263 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
264 (RD_C0, WR_C0, E2, E2MT): New macros.
265 (mips16_opcodes): Add entries for MIPS16e2 instructions:
266 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
267 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
268 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
269 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
270 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
271 instructions, "swl", "swr", "sync" and its "sync_acquire",
272 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
273 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
274 regular/extended entries for original MIPS16 ISA revision
275 instructions whose extended forms are subdecoded in the MIPS16e2
276 ISA revision: "li", "sll" and "srl".
277
fdfb4752
MR		 2782017-05-15 Maciej W. Rozycki <macro@imgtec.com>
279
280 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
281 reference in CP0 move operand decoding.
282
a4f89915
MR		 2832017-05-12 Maciej W. Rozycki <macro@imgtec.com>
284
285 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
286 type to hexadecimal.
287 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
288
99e2d67a
MR		 2892017-05-11 Maciej W. Rozycki <macro@imgtec.com>
290
291 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
292 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
293 "sync_rmb" and "sync_wmb" as aliases.
294 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
295 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
296
53a346d8
CZ		 2972017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
298
299 * arc-dis.c (parse_option): Update quarkse_em option..
300 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
301 QUARKSE1.
302 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
303
f91d48de
KC		 3042017-05-03 Kito Cheng <kito.cheng@gmail.com>
305
306 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
307
43e379d7
MC		 3082017-05-01 Michael Clark <michaeljclark@mac.com>
309
310 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
311 register.
312
a4ddc54e
MR		 3132017-05-02 Maciej W. Rozycki <macro@imgtec.com>
314
315 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
316 and branches and not synthetic data instructions.
317
fe50e98c
BE		 3182017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
319
320 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
321
126124cc
CZ		 3222017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
323
324 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
325 * arc-opc.c (insert_r13el): New function.
326 (R13_EL): Define.
327 * arc-tbl.h: Add new enter/leave variants.
328
be6a24d8
CZ		 3292017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
330
331 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
332
0348fd79
MR		 3332017-04-25 Maciej W. Rozycki <macro@imgtec.com>
334
335 * mips-dis.c (print_mips_disassembler_options): Add
336 `no-aliases'.
337
6e3d1f07
MR		 3382017-04-25 Maciej W. Rozycki <macro@imgtec.com>
339
340 * mips16-opc.c (AL): New macro.
341 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
342 of "ld" and "lw" as aliases.
343
957f6b39
TC		 3442017-04-24 Tamar Christina <tamar.christina@arm.com>
345
346 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
347 arguments.
348
a8cc8a54
AM		 3492017-04-22 Alexander Fedotov <alfedotov@gmail.com>
350 Alan Modra <amodra@gmail.com>
351
352 * ppc-opc.c (ELEV): Define.
353 (vle_opcodes): Add se_rfgi and e_sc.
354 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
355 for E200Z4.
356
3ab87b68
JM		 3572017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
358
359 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
360
792f174f
NC		 3612017-04-21 Nick Clifton <nickc@redhat.com>
362
363 PR binutils/21380
364 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
365 LD3R and LD4R.
366
42742084
AM		 3672017-04-13 Alan Modra <amodra@gmail.com>
368
369 * epiphany-desc.c: Regenerate.
370 * fr30-desc.c: Regenerate.
371 * frv-desc.c: Regenerate.
372 * ip2k-desc.c: Regenerate.
373 * iq2000-desc.c: Regenerate.
374 * lm32-desc.c: Regenerate.
375 * m32c-desc.c: Regenerate.
376 * m32r-desc.c: Regenerate.
377 * mep-desc.c: Regenerate.
378 * mt-desc.c: Regenerate.
379 * or1k-desc.c: Regenerate.
380 * xc16x-desc.c: Regenerate.
381 * xstormy16-desc.c: Regenerate.
382
9a85b496
AM		 3832017-04-11 Alan Modra <amodra@gmail.com>
384
ef85eab0 385 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 386 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
387 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 388 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
389 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 390 (PPCVSX2): Define as PPC_OPCODE_POWER8.
391 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 392 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 393 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 394
62adc510
AM		 3952017-04-10 Alan Modra <amodra@gmail.com>
396
397 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
398 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
399 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
400 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
401
aa808707
PC		 4022017-04-09 Pip Cet <pipcet@gmail.com>
403
404 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
405 appropriate floating-point precision directly.
406
ac8f0f72
AM		 4072017-04-07 Alan Modra <amodra@gmail.com>
408
409 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
410 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
411 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
412 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
413 vector instructions with E6500 not PPCVEC2.
414
62ecb94c
PC		 4152017-04-06 Pip Cet <pipcet@gmail.com>
416
417 * Makefile.am: Add wasm32-dis.c.
418 * configure.ac: Add wasm32-dis.c to wasm32 target.
419 * disassemble.c: Add wasm32 disassembler code.
420 * wasm32-dis.c: New file.
421 * Makefile.in: Regenerate.
422 * configure: Regenerate.
423 * po/POTFILES.in: Regenerate.
424 * po/opcodes.pot: Regenerate.
425
f995bbe8
PA		 4262017-04-05 Pedro Alves <palves@redhat.com>
427
428 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
429 * arm-dis.c (parse_arm_disassembler_options): Constify.
430 * ppc-dis.c (powerpc_init_dialect): Constify local.
431 * vax-dis.c (parse_disassembler_options): Constify.
432
b5292032
PD		 4332017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
434
435 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
436 RISCV_GP_SYMBOL.
437
f96bd6c2
PC		 4382017-03-30 Pip Cet <pipcet@gmail.com>
439
440 * configure.ac: Add (empty) bfd_wasm32_arch target.
441 * configure: Regenerate
442 * po/opcodes.pot: Regenerate.
443
f7c514a3
JM		 4442017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
445
446 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
447 OSA2015.
448 * opcodes/sparc-opc.c (asi_table): New ASIs.
449
52be03fd
AM		 4502017-03-29 Alan Modra <amodra@gmail.com>
451
452 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
453 "raw" option.
454 (lookup_powerpc): Don't special case -1 dialect. Handle
455 PPC_OPCODE_RAW.
456 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
457 lookup_powerpc call, pass it on second.
458
9b753937
AM		 4592017-03-27 Alan Modra <amodra@gmail.com>
460
461 PR 21303
462 * ppc-dis.c (struct ppc_mopt): Comment.
463 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
464
c0c31e91
RZ		 4652017-03-27 Rinat Zelig <rinat@mellanox.com>
466
467 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
468 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
469 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
470 (insert_nps_misc_imm_offset): New function.
471 (extract_nps_misc imm_offset): New function.
472 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
473 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
474
2253c8f0
AK		 4752017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
476
477 * s390-mkopc.c (main): Remove vx2 check.
478 * s390-opc.txt: Remove vx2 instruction flags.
479
645d3342
RZ		 4802017-03-21 Rinat Zelig <rinat@mellanox.com>
481
482 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
483 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
484 (insert_nps_imm_offset): New function.
485 (extract_nps_imm_offset): New function.
486 (insert_nps_imm_entry): New function.
487 (extract_nps_imm_entry): New function.
488
4b94dd2d
AM		 4892017-03-17 Alan Modra <amodra@gmail.com>
490
491 PR 21248
492 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
493 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
494 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
495
b416fe87
KC		 4962017-03-14 Kito Cheng <kito.cheng@gmail.com>
497
498 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
499 <c.andi>: Likewise.
500 <c.addiw> Likewise.
501
03b039a5
KC		 5022017-03-14 Kito Cheng <kito.cheng@gmail.com>
503
504 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
505
2c232b83
AW		 5062017-03-13 Andrew Waterman <andrew@sifive.com>
507
508 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
509 <srl> Likewise.
510 <srai> Likewise.
511 <sra> Likewise.
512
86fa6981
L		 5132017-03-09 H.J. Lu <hongjiu.lu@intel.com>
514
515 * i386-gen.c (opcode_modifiers): Replace S with Load.
516 * i386-opc.h (S): Removed.
517 (Load): New.
518 (i386_opcode_modifier): Replace s with load.
519 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
520 and {evex}. Replace S with Load.
521 * i386-tbl.h: Regenerated.
522
c1fe188b
L		 5232017-03-09 H.J. Lu <hongjiu.lu@intel.com>
524
525 * i386-opc.tbl: Use CpuCET on rdsspq.
526 * i386-tbl.h: Regenerated.
527
4b8b687e
PB		 5282017-03-08 Peter Bergner <bergner@vnet.ibm.com>
529
530 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
531 <vsx>: Do not use PPC_OPCODE_VSX3;
532
1437d063
PB		 5332017-03-08 Peter Bergner <bergner@vnet.ibm.com>
534
535 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
536
603555e5
L		 5372017-03-06 H.J. Lu <hongjiu.lu@intel.com>
538
539 * i386-dis.c (REG_0F1E_MOD_3): New enum.
540 (MOD_0F1E_PREFIX_1): Likewise.
541 (MOD_0F38F5_PREFIX_2): Likewise.
542 (MOD_0F38F6_PREFIX_0): Likewise.
543 (RM_0F1E_MOD_3_REG_7): Likewise.
544 (PREFIX_MOD_0_0F01_REG_5): Likewise.
545 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
546 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
547 (PREFIX_0F1E): Likewise.
548 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
549 (PREFIX_0F38F5): Likewise.
550 (dis386_twobyte): Use PREFIX_0F1E.
551 (reg_table): Add REG_0F1E_MOD_3.
552 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
553 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
554 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
555 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
556 (three_byte_table): Use PREFIX_0F38F5.
557 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
558 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
559 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
560 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
561 PREFIX_MOD_3_0F01_REG_5_RM_2.
562 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
563 (cpu_flags): Add CpuCET.
564 * i386-opc.h (CpuCET): New enum.
565 (CpuUnused): Commented out.
566 (i386_cpu_flags): Add cpucet.
567 * i386-opc.tbl: Add Intel CET instructions.
568 * i386-init.h: Regenerated.
569 * i386-tbl.h: Likewise.
570
73f07bff
AM		 5712017-03-06 Alan Modra <amodra@gmail.com>
572
573 PR 21124
574 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
575 (extract_raq, extract_ras, extract_rbx): New functions.
576 (powerpc_operands): Use opposite corresponding insert function.
577 (Q_MASK): Define.
578 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
579 register restriction.
580
65b48a81
PB		 5812017-02-28 Peter Bergner <bergner@vnet.ibm.com>
582
583 * disassemble.c Include "safe-ctype.h".
584 (disassemble_init_for_target): Handle s390 init.
585 (remove_whitespace_and_extra_commas): New function.
586 (disassembler_options_cmp): Likewise.
587 * arm-dis.c: Include "libiberty.h".
588 (NUM_ELEM): Delete.
589 (regnames): Use long disassembler style names.
590 Add force-thumb and no-force-thumb options.
591 (NUM_ARM_REGNAMES): Rename from this...
592 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
593 (get_arm_regname_num_options): Delete.
594 (set_arm_regname_option): Likewise.
595 (get_arm_regnames): Likewise.
596 (parse_disassembler_options): Likewise.
597 (parse_arm_disassembler_option): Rename from this...
598 (parse_arm_disassembler_options): ...to this. Make static.
599 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
600 (print_insn): Use parse_arm_disassembler_options.
601 (disassembler_options_arm): New function.
602 (print_arm_disassembler_options): Handle updated regnames.
603 * ppc-dis.c: Include "libiberty.h".
604 (ppc_opts): Add "32" and "64" entries.
605 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
606 (powerpc_init_dialect): Add break to switch statement.
607 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
608 (disassembler_options_powerpc): New function.
609 (print_ppc_disassembler_options): Use ARRAY_SIZE.
610 Remove printing of "32" and "64".
611 * s390-dis.c: Include "libiberty.h".
612 (init_flag): Remove unneeded variable.
613 (struct s390_options_t): New structure type.
614 (options): New structure.
615 (init_disasm): Rename from this...
616 (disassemble_init_s390): ...to this. Add initializations for
617 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
618 (print_insn_s390): Delete call to init_disasm.
619 (disassembler_options_s390): New function.
620 (print_s390_disassembler_options): Print using information from
621 struct 'options'.
622 * po/opcodes.pot: Regenerate.
623
15c7c1d8
JB		 6242017-02-28 Jan Beulich <jbeulich@suse.com>
625
626 * i386-dis.c (PCMPESTR_Fixup): New.
627 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
628 (prefix_table): Use PCMPESTR_Fixup.
629 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
630 PCMPESTR_Fixup.
631 (vex_w_table): Delete VPCMPESTR{I,M} entries.
632 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
633 Split 64-bit and non-64-bit variants.
634 * opcodes/i386-tbl.h: Re-generate.
635
582e12bf
RS		 6362017-02-24 Richard Sandiford <richard.sandiford@arm.com>
637
638 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
639 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
640 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
641 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
642 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
643 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
644 (OP_SVE_V_HSD): New macros.
645 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
646 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
647 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
648 (aarch64_opcode_table): Add new SVE instructions.
649 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
650 for rotation operands. Add new SVE operands.
651 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
652 (ins_sve_quad_index): Likewise.
653 (ins_imm_rotate): Split into...
654 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
655 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
656 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
657 functions.
658 (aarch64_ins_sve_addr_ri_s4): New function.
659 (aarch64_ins_sve_quad_index): Likewise.
660 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
661 * aarch64-asm-2.c: Regenerate.
662 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
663 (ext_sve_quad_index): Likewise.
664 (ext_imm_rotate): Split into...
665 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
666 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
667 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
668 functions.
669 (aarch64_ext_sve_addr_ri_s4): New function.
670 (aarch64_ext_sve_quad_index): Likewise.
671 (aarch64_ext_sve_index): Allow quad indices.
672 (do_misc_decoding): Likewise.
673 * aarch64-dis-2.c: Regenerate.
674 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
675 aarch64_field_kinds.
676 (OPD_F_OD_MASK): Widen by one bit.
677 (OPD_F_NO_ZR): Bump accordingly.
678 (get_operand_field_width): New function.
679 * aarch64-opc.c (fields): Add new SVE fields.
680 (operand_general_constraint_met_p): Handle new SVE operands.
681 (aarch64_print_operand): Likewise.
682 * aarch64-opc-2.c: Regenerate.
683
f482d304
RS		 6842017-02-24 Richard Sandiford <richard.sandiford@arm.com>
685
686 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
687 (aarch64_feature_compnum): ...this.
688 (SIMD_V8_3): Replace with...
689 (COMPNUM): ...this.
690 (CNUM_INSN): New macro.
691 (aarch64_opcode_table): Use it for the complex number instructions.
692
7db2c588
JB		 6932017-02-24 Jan Beulich <jbeulich@suse.com>
694
695 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
696
1e9d41d4
SL		 6972017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
698
699 Add support for associating SPARC ASIs with an architecture level.
700 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
701 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
702 decoding of SPARC ASIs.
703
53c4d625
JB		 7042017-02-23 Jan Beulich <jbeulich@suse.com>
705
706 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
707 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
708
11648de5
JB		 7092017-02-21 Jan Beulich <jbeulich@suse.com>
710
711 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
712 1 (instead of to itself). Correct typo.
713
f98d33be
AW		 7142017-02-14 Andrew Waterman <andrew@sifive.com>
715
716 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
717 pseudoinstructions.
718
773fb663
RS		 7192017-02-15 Richard Sandiford <richard.sandiford@arm.com>
720
721 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
722 (aarch64_sys_reg_supported_p): Handle them.
723
cc07cda6
CZ		 7242017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
725
726 * arc-opc.c (UIMM6_20R): Define.
727 (SIMM12_20): Use above.
728 (SIMM12_20R): Define.
729 (SIMM3_5_S): Use above.
730 (UIMM7_A32_11R_S): Define.
731 (UIMM7_9_S): Use above.
732 (UIMM3_13R_S): Define.
733 (SIMM11_A32_7_S): Use above.
734 (SIMM9_8R): Define.
735 (UIMM10_A32_8_S): Use above.
736 (UIMM8_8R_S): Define.
737 (W6): Use above.
738 (arc_relax_opcodes): Use all above defines.
739
66a5a740
VG		 7402017-02-15 Vineet Gupta <vgupta@synopsys.com>
741
742 * arc-regs.h: Distinguish some of the registers different on
743 ARC700 and HS38 cpus.
744
7e0de605
AM		 7452017-02-14 Alan Modra <amodra@gmail.com>
746
747 PR 21118
748 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
749 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
750
54064fdb
AM		 7512017-02-11 Stafford Horne <shorne@gmail.com>
752 Alan Modra <amodra@gmail.com>
753
754 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
755 Use insn_bytes_value and insn_int_value directly instead. Don't
756 free allocated memory until function exit.
757
dce75bf9
NP		 7582017-02-10 Nicholas Piggin <npiggin@gmail.com>
759
760 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
761
1b7e3d2f
NC		 7622017-02-03 Nick Clifton <nickc@redhat.com>
763
764 PR 21096
765 * aarch64-opc.c (print_register_list): Ensure that the register
766 list index will fir into the tb buffer.
767 (print_register_offset_address): Likewise.
768 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
769
8ec5cf65
AD		 7702017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
771
772 PR 21056
773 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
774 instructions when the previous fetch packet ends with a 32-bit
775 instruction.
776
a1aa5e81
DD		 7772017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
778
779 * pru-opc.c: Remove vague reference to a future GDB port.
780
add3afb2
NC		 7812017-01-20 Nick Clifton <nickc@redhat.com>
782
783 * po/ga.po: Updated Irish translation.
784
c13a63b0
SN		 7852017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
786
787 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
788
9608051a
YQ		 7892017-01-13 Yao Qi <yao.qi@linaro.org>
790
791 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
792 if FETCH_DATA returns 0.
793 (m68k_scan_mask): Likewise.
794 (print_insn_m68k): Update code to handle -1 return value.
795
f622ea96
YQ		 7962017-01-13 Yao Qi <yao.qi@linaro.org>
797
798 * m68k-dis.c (enum print_insn_arg_error): New.
799 (NEXTBYTE): Replace -3 with
800 PRINT_INSN_ARG_MEMORY_ERROR.
801 (NEXTULONG): Likewise.
802 (NEXTSINGLE): Likewise.
803 (NEXTDOUBLE): Likewise.
804 (NEXTDOUBLE): Likewise.
805 (NEXTPACKED): Likewise.
806 (FETCH_ARG): Likewise.
807 (FETCH_DATA): Update comments.
808 (print_insn_arg): Update comments. Replace magic numbers with
809 enum.
810 (match_insn_m68k): Likewise.
811
620214f7
IT		 8122017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
813
814 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
815 * i386-dis-evex.h (evex_table): Updated.
816 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
817 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
818 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
819 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
820 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
821 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
822 * i386-init.h: Regenerate.
823 * i386-tbl.h: Ditto.
824
d95014a2
YQ		 8252017-01-12 Yao Qi <yao.qi@linaro.org>
826
827 * msp430-dis.c (msp430_singleoperand): Return -1 if
828 msp430dis_opcode_signed returns false.
829 (msp430_doubleoperand): Likewise.
830 (msp430_branchinstr): Return -1 if
831 msp430dis_opcode_unsigned returns false.
832 (msp430x_calla_instr): Likewise.
833 (print_insn_msp430): Likewise.
834
0ae60c3e
NC		 8352017-01-05 Nick Clifton <nickc@redhat.com>
836
837 PR 20946
838 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
839 could not be matched.
840 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
841 NULL.
842
d74d4880
SN		 8432017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
844
845 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
846 (aarch64_opcode_table): Use RCPC_INSN.
847
cc917fd9
KC		 8482017-01-03 Kito Cheng <kito.cheng@gmail.com>
849
850 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
851 extension.
852 * riscv-opcodes/all-opcodes: Likewise.
853
b52d3cfc
DP		 8542017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
855
856 * riscv-dis.c (print_insn_args): Add fall through comment.
857
f90c58d5
NC		 8582017-01-03 Nick Clifton <nickc@redhat.com>
859
860 * po/sr.po: New Serbian translation.
861 * configure.ac (ALL_LINGUAS): Add sr.
862 * configure: Regenerate.
863
f47b0d4a
AM		 8642017-01-02 Alan Modra <amodra@gmail.com>
865
866 * epiphany-desc.h: Regenerate.
867 * epiphany-opc.h: Regenerate.
868 * fr30-desc.h: Regenerate.
869 * fr30-opc.h: Regenerate.
870 * frv-desc.h: Regenerate.
871 * frv-opc.h: Regenerate.
872 * ip2k-desc.h: Regenerate.
873 * ip2k-opc.h: Regenerate.
874 * iq2000-desc.h: Regenerate.
875 * iq2000-opc.h: Regenerate.
876 * lm32-desc.h: Regenerate.
877 * lm32-opc.h: Regenerate.
878 * m32c-desc.h: Regenerate.
879 * m32c-opc.h: Regenerate.
880 * m32r-desc.h: Regenerate.
881 * m32r-opc.h: Regenerate.
882 * mep-desc.h: Regenerate.
883 * mep-opc.h: Regenerate.
884 * mt-desc.h: Regenerate.
885 * mt-opc.h: Regenerate.
886 * or1k-desc.h: Regenerate.
887 * or1k-opc.h: Regenerate.
888 * xc16x-desc.h: Regenerate.
889 * xc16x-opc.h: Regenerate.
890 * xstormy16-desc.h: Regenerate.
891 * xstormy16-opc.h: Regenerate.
892
2571583a
AM		 8932017-01-02 Alan Modra <amodra@gmail.com>
894
895 Update year range in copyright notice of all files.
896
5c1ad6b5 897For older changes see ChangeLog-2016
3499769a 898\f
5c1ad6b5 899Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 900
901Copying and distribution of this file, with or without modification,
902are permitted in any medium without royalty provided the copyright
903notice and this notice are preserved.
904
905Local Variables:
906mode: change-log
907left-margin: 8
908fill-column: 74
909version-control: never
910End:
GDB Binutils - Deliverables
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