projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Range of element index is too large on MIPS MSA element selection instructions.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
e269fea7
AB		 12013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
2
3 * micromips-opc.c (decode_micromips_operand): Reduced range of +o, +u,
4 +v and +w.
5 (micromips_opcodes): Reduced element index range for sldi, splati,
6 copy_s, copy_u, insert and insve instructions.
7 * opcodes/mips-opc.c (decode_mips_operand): Reduced range of +o, +u,
8 +v and +w.
9 (mips_builtin_opcodes): Reduced element index range for sldi, splati,
10 copy_s, copy_u, insert and insve instructions.
11
1332de01
JBG		 122013-12-13 Jan-Benedict Glaw <jbglaw@lug-owl.de>
13
14 * nds32-dis.c (mnemonic_96): Fix typo.
15
35c08157
KLC		 162013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
17 Wei-Cheng Wang <cole945@gmail.com>
18
19 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nds32-asm.c
20 and nds32-dis.c.
21 * Makefile.in: Regenerate.
22 * configure.in: Add case for bfd_nds32_arch.
23 * configure: Regenerate.
24 * disassemble.c (ARCH_nds32): Define.
25 * nds32-asm.c: New file for nds32.
26 * nds32-asm.h: New file for nds32.
27 * nds32-dis.c: New file for nds32.
28 * nds32-opc.h: New file for nds32.
29
61d4014c
NC		 302013-12-05 Nick Clifton <nickc@redhat.com>
31
32 * s390-mkopc.c (dumpTable): Provide a format string to printf so
33 that compiling with -Werror=format-security does not produce an
34 error.
35
87b8eed7
YZ		 362013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
37
38 * aarch64-opc.c (aarch64_pstatefields): Update.
39
8f8c3854
CM		 402013-11-19 Catherine Moore <clm@codesourcery.com>
41
42 * micromips-opc.c (LM): Define.
43 (micromips_opcodes): Add LM to load instructions.
44 * mips-opc.c (prefe): Add LM attribute.
45
a203d9b7
YZ		 462013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
47
48 Revert
49
50 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
51
52 * aarch64-opc.c (CPENT): New define.
53 (F_READONLY, F_WRITEONLY): Likewise.
54 (aarch64_sys_regs): Add trace unit registers.
55 (aarch64_sys_reg_readonly_p): New function.
56 (aarch64_sys_reg_writeonly_p): Ditto.
57
75468c93
YZ		 582013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
59
60 * aarch64-opc.c (CPENT): New define.
61 (F_READONLY, F_WRITEONLY): Likewise.
62 (aarch64_sys_regs): Add trace unit registers.
63 (aarch64_sys_reg_readonly_p): New function.
64 (aarch64_sys_reg_writeonly_p): Ditto.
65
caeba11c
MR		 662013-11-15 Maciej W. Rozycki <macro@codesourcery.com>
67
68 * mips-opc.c (mips_builtin_opcodes): Add RD_2 to "mfcr" and
69 "mtcr".
70
b83a9376
CM		 712013-11-11 Catherine Moore <clm@codesourcery.com>
72
73 * mips-dis.c (print_insn_mips): Use
74 INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY.
75 (print_insn_micromips): Likewise.
76 * mips-opc.c (LDD): Remove.
77 (CLD): Include INSN_LOAD_MEMORY.
78 (LM): New.
79 (mips_builtin_opcodes): Use LM instead of LDD.
80 Add LM to load instructions.
81
d56da83e
L		 822013-11-08 H.J. Lu <hongjiu.lu@intel.com>
83
84 PR gas/16140
85 * i386-gen.c (cpu_flag_init): Remove CpuNop from CPU_K6_2_FLAGS.
86 * i386-init.h: Regenerated.
87
49eec193
YZ		 882013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
89
90 * aarch64-opc.c (F_DEPRECATED): New macro.
91 (aarch64_sys_regs): Update; flag "spsr_svc" and "spsr_hyp" with
92 F_DEPRECATED.
93 (aarch64_print_operand): Call aarch64_sys_reg_deprecated_p on
94 AARCH64_OPND_SYSREG.
95
68a64283
YZ		 962013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
97
98 * aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'.
99 (convert_from_csel): Likewise.
100 * aarch64-opc.c (operand_general_constraint_met_p): Handle
101 AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1.
102 (aarch64_print_operand): Handle AARCH64_OPND_COND1.
103 * aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of
104 COND for cinc, cset, cinv, csetm and cneg.
105 (AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1.
106 * aarch64-asm-2.c: Re-generated.
107 * aarch64-dis-2.c: Ditto.
108 * aarch64-opc-2.c: Ditto.
109
4e50d5f8
YZ		 1102013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
111
112 * aarch64-opc.c (set_syntax_error): New function.
113 (operand_general_constraint_met_p): Replace set_other_error
114 with set_syntax_error.
115
7d4a7d10
AA		 1162013-10-30 Andreas Arnez <arnez@linux.vnet.ibm.com>
117
118 * s390-dis.c (init_disasm): Default to full 'zarch' opcode
119 availability even for 31-bit programs.
120
85181173
RR		 1212013-10-15 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
122
123 * arm-dis.c (neon_opcodes): Adjust print string for vshll.
124
4edbb8e3
CF		 1252013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
126
127 * micromips-opc.c (decode_micromips_operand): Add +T, +U, +V, +W,
128 +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +x,
129 +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
130 (MSA): New define.
131 (MSA64): New define.
132 (micromips_opcodes): Add MSA instructions.
133 * mips-dis.c (msa_control_names): New array.
134 (mips_abi_choice): Add ASE_MSA to mips32r2.
135 Remove ASE_MDMX from mips64r2.
136 Add ASE_MSA and ASE_MSA64 to mips64r2.
137 (parse_mips_dis_option): Handle -Mmsa.
138 (print_reg): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL.
139 (print_insn_arg): Handle cases for OP_IMM_INDEX and OP_REG_INDEX.
140 (print_mips_disassembler_options): Print -Mmsa.
141 * mips-opc.c (decode_mips_operand): Add +T, +U, +V, +W, +d, +e, +h, +k,
142 +l, +n, +o, +u, +v, +w, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
143 (MSA): New define.
144 (MSA64): New define.
145 (mips_builtin_op): Add MSA instructions.
146
ae335a4e
SL		 1472013-10-13 Sandra Loosemore <sandra@codesourcery.com>
148
149 * nios2-opc.c (nios2_builtin_reg): Use "sstatus" rather than "ba"
150 as the primary name of r30.
151
6c75cc62
L		 1522013-10-12 Jan Beulich <jbeulich@suse.com>
153
154 * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
155 default case.
156 (OP_E_register): Move v_bnd_mode alongside m_mode.
157 * i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
158 Drop Reg16 and Disp16. Add NoRex64.
159 (bndmk, bndmov, bndldx, bndstx): Drop Disp16.
160 * i386-tbl.h: Re-generate.
161
0e1c2434
SK		 1622013-10-10 Sean Keys <skeys@ipdatasys.com>
163
164 * xgate-opc.c (xgate_opcode): Remove short_hand field from opcode
165 table.
166 * xgate-dis.c (print_insn): Refactor to work with table change.
167
7903e530
RM		 1682013-10-10 Roland McGrath <mcgrathr@google.com>
169
9ce09ba2
RM		 170 * i386-dis.c (oappend_maybe_intel): New function.
171 (OP_ST, OP_STi, append_seg, OP_I, OP_I64, OP_sI, OP_ESreg): Use it.
172 (OP_C, OP_T, CMP_Fixup, OP_EX_VexImmW): Likewise.
173 (VCMP_Fixup, VPCMP_Fixup, PCLMUL_Fixup): Likewise.
174
2b4e983c
RM		 175 * cr16-opc.c (REG): Cast NAME to 'reg' enum type to suppress
176 possible compiler warnings when the union's initializer is
177 actually meant for the 'preg' enum typed member.
178 * crx-opc.c (REG): Likewise.
179
7903e530
RM		 180 * v850-dis.c (v850_cacheop_codes, v850_prefop_codes):
181 Remove duplicate const qualifier.
182
79e0e31d
JB		 1832013-10-08 Jan Beulich <jbeulich@suse.com>
184
185 * i386-opc.tbl (invlpg): Use Anysize instead of Unspecified.
186 (clflush): Use Anysize instead of Byte|Unspecified.
187 (prefetch*): Likewise.
188 * i386-tbl.h: Re-generate.
189
45099dfa
CF		 1902013-10-07 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
191
192 * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
193
916fae91
L		 1942013-09-30 H.J. Lu <hongjiu.lu@intel.com>
195
196 * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
197 * i386-init.h: Regenerated.
198
c7b0bd56
SE		 1992013-09-30 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
200
201 * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
202 * i386-init.h: Regenerated.
203
cc9afea3
AM		 2042013-09-20 Alan Modra <amodra@gmail.com>
205
206 * configure: Regenerate.
207
e3f9e852
RS		 2082013-09-17 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
209
210 * s390-opc.txt (clih): Make the immediate unsigned.
211
74db7efb
NC		 2122013-09-04 Roland McGrath <mcgrathr@google.com>
213
214 PR gas/15914
215 * arm-dis.c (arm_opcodes): Add udf.
216 (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
217 (thumb32_opcodes): Add udf.w.
218 (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
219
c8094e01
AK		 2202013-09-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
221
222 * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
223 For the load fp integer instructions only the suppression flag was
224 new with z196 version.
225
7e105031
NC		 2262013-08-28 Nick Clifton <nickc@redhat.com>
227
228 * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
229 immediate is not suitable for the 32-bit ABI.
230
fb6f3895
MR		 2312013-08-23 Maciej W. Rozycki <macro@codesourcery.com>
232
233 * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
234 replacing NODS.
235
9aff4b7a
NC		 2362013-08-23 Yuri Chornoivan <yurchor@ukr.net>
237
238 PR binutils/15834
239 * aarch64-asm.c: Fix typos.
240 * aarch64-dis.c: Likewise.
241 * msp430-dis.c: Likewise.
242
5e0dc5ba
RS		 2432013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
244
245 * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
246 macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
247 Use +H rather than +C for the real "dext".
248 * mips-opc.c (mips_builtin_opcodes): Likewise.
249
0f35dbc4
RS		 2502013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
251
252 * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
253 * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
254 and OPTIONAL_MAPPED_REG.
255 * mips-opc.c (decode_mips_operand): Likewise.
256 * mips16-opc.c (decode_mips16_operand): Likewise.
257 * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
258
79ceb7cb
L		 2592013-08-19 H.J. Lu <hongjiu.lu@intel.com>
260
261 * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
262 (PREFIX_EVEX_0F3A3F): Likewise.
263 * i386-dis-evex.h (evex_table): Updated.
264
ee5734f0
RS		 2652013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
266
267 * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
268 VCLIPW.
269
d6787ef9
EB		 2702013-08-05 Eric Botcazou <ebotcazou@adacore.com>
271 Konrad Eisele <konrad@gaisler.com>
272
273 * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
274 bfd_mach_sparc.
275 * sparc-opc.c (MASK_LEON): Define.
276 (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
277 (letandleon): New macro.
278 (v9andleon): Likewise.
279 (sparc_opc): Add leon.
280 (umac): Enable for letandleon.
281 (smac): Likewise.
282 (casa): Enable for v9andleon.
283 (cas): Likewise.
284 (casl): Likewise.
285
14daeee3
RS		 2862013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
287 Richard Sandiford <rdsandiford@googlemail.com>
288
289 * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
290 OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
291 (print_vu0_channel): New function.
292 (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
293 (print_insn_args): Handle '#'.
294 (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
295 * mips-opc.c (mips_vu0_channel_mask): New constant.
296 (decode_mips_operand): Handle new VU0 operand types.
297 (VU0, VU0CH): New macros.
298 (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
299 for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
300 Use "+6" rather than "G" for QMFC2 and QMTC2.
301
3ccad066
RS		 3022013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
303
304 * mips-formats.h (PCREL): Reorder parameters and update the definition
305 to match new mips_pcrel_operand layout.
306 (JUMP, JALX, BRANCH): Update accordingly.
307 * mips16-opc.c (decode_mips16_operand): Likewise.
308
df34fbcc
RS		 3092013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
310
311 * micromips-opc.c (WR_s): Delete.
312
fc76e730
RS		 3132013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
314
315 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
316 New macros.
317 (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
318 (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
319 (mips_builtin_opcodes): Use the new position-based read-write flags
320 instead of field-based ones. Use UDI for "udi..." instructions.
321 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
322 New macros.
323 (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
324 (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
325 (WR_SP, RD_16): New macros.
326 (RD_SP): Redefine as an INSN2_* flag.
327 (MOD_SP): Redefine in terms of RD_SP and WR_SP.
328 (mips16_opcodes): Use the new position-based read-write flags
329 instead of field-based ones. Use RD_16 for "nop". Move RD_SP to
330 pinfo2 field.
331 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
332 New macros.
333 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
334 (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
335 (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
336 (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
337 (micromips_opcodes): Use the new position-based read-write flags
338 instead of field-based ones.
339 * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
340 (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
341 of field-based flags.
342
26545944
RS		 3432013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
344
345 * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
346 (WR_SP): Replace with...
347 (MOD_SP): ...this.
348 (mips16_opcodes): Update accordingly.
349 * mips-dis.c (print_insn_mips16): Likewise.
350
a8d92fc6
RS		 3512013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
352
353 * mips16-opc.c (mips16_opcodes): Reformat.
354
6a819047
RS		 3552013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
356
357 * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
358 for operands that are hard-coded to $0.
359 * micromips-opc.c (micromips_opcodes): Likewise.
360
344c74a6
RS		 3612013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
362
363 * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
364 for the single-operand forms of JALR and JALR.HB.
365 * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
366 and JALRS.HB.
367
41989114
RS		 3682013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
369
370 * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
371 instructions. Fix them to use WR_MACC instead of WR_CC and
372 add missing RD_MACCs.
373
6d075bce
RS		 3742013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
375
376 * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
377
4f6ffcd3
PB		 3782013-07-29 Peter Bergner <bergner@vnet.ibm.com>
379
380 * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
381
43234a1e
L		 3822013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
383 Alexander Ivchenko <alexander.ivchenko@intel.com>
384 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
385 Sergey Lega <sergey.s.lega@intel.com>
386 Anna Tikhonova <anna.tikhonova@intel.com>
387 Ilya Tocar <ilya.tocar@intel.com>
388 Andrey Turetskiy <andrey.turetskiy@intel.com>
389 Ilya Verbin <ilya.verbin@intel.com>
390 Kirill Yukhin <kirill.yukhin@intel.com>
391 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
392
393 * i386-dis-evex.h: New.
394 * i386-dis.c (OP_Rounding): New.
395 (VPCMP_Fixup): New.
396 (OP_Mask): New.
397 (Rdq): New.
398 (XMxmmq): New.
399 (EXdScalarS): New.
400 (EXymm): New.
401 (EXEvexHalfBcstXmmq): New.
402 (EXxmm_mdq): New.
403 (EXEvexXGscat): New.
404 (EXEvexXNoBcst): New.
405 (VPCMP): New.
406 (EXxEVexR): New.
407 (EXxEVexS): New.
408 (XMask): New.
409 (MaskG): New.
410 (MaskE): New.
411 (MaskR): New.
412 (MaskVex): New.
413 (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
414 evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
415 evex_rounding_mode, evex_sae_mode, mask_mode.
416 (USE_EVEX_TABLE): New.
417 (EVEX_TABLE): New.
418 (EVEX enum): New.
419 (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
420 REG_EVEX_0F38C7.
421 (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
422 MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
423 MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
424 MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
425 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
426 MOD_EVEX_0F38C7_REG_6.
427 (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
428 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
429 PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
430 PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
431 PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
432 PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
433 PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
434 PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
435 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
436 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
437 PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
438 PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
439 PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
440 PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
441 PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
442 PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
443 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
444 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
445 PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
446 PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
447 PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
448 PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
449 PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
450 PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
451 PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
452 PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
453 PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
454 PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
455 PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
456 PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
457 PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
458 PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
459 PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
460 PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
461 PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
462 PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
463 PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
464 PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
465 PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
466 PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
467 PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
468 PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
469 PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
470 PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
471 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
472 PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
473 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
474 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
475 PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
476 PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
477 PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
478 PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
479 PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
480 PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
481 PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
482 PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
483 PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
484 PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
485 PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
486 PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
487 PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
488 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
489 PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
490 PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
491 PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
492 PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
493 PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
494 PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
495 PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
496 PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
497 PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
498 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
499 PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
500 PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
501 PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
502 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
503 PREFIX_EVEX_0F3A55.
504 (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
505 VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
506 VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
507 VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
508 VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
509 VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
510 VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
511 VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
512 VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
513 VEX_W_0F3A32_P_2_LEN_0.
514 (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
515 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
516 EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
517 EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
518 EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
519 EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
520 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
521 EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
522 EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
523 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
524 EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
525 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
526 EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
527 EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
528 EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
529 EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
530 EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
531 EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
532 EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
533 EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
534 EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
535 EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
536 EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
537 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
538 EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
539 EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
540 EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
541 EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
542 EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
543 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
544 EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
545 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
546 EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
547 EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
548 EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
549 EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
550 EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
551 EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
552 EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
553 EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
554 EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
555 EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
556 EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
557 EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
558 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
559 EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
560 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
561 EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
562 EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
563 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
564 EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
565 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
566 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
567 EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
568 (struct vex): Add fields evex, r, v, mask_register_specifier,
569 zeroing, ll, b.
570 (intel_names_xmm): Add upper 16 registers.
571 (att_names_xmm): Ditto.
572 (intel_names_ymm): Ditto.
573 (att_names_ymm): Ditto.
574 (names_zmm): New.
575 (intel_names_zmm): Ditto.
576 (att_names_zmm): Ditto.
577 (names_mask): Ditto.
578 (intel_names_mask): Ditto.
579 (att_names_mask): Ditto.
580 (names_rounding): Ditto.
581 (names_broadcast): Ditto.
582 (x86_64_table): Add escape to evex-table.
583 (reg_table): Include reg_table evex-entries from
584 i386-dis-evex.h. Fix prefetchwt1 instruction.
585 (prefix_table): Add entries for new instructions.
586 (vex_table): Ditto.
587 (vex_len_table): Ditto.
588 (vex_w_table): Ditto.
589 (mod_table): Ditto.
590 (get_valid_dis386): Properly handle new instructions.
591 (print_insn): Handle zmm and mask registers, print mask operand.
592 (intel_operand_size): Support EVEX, new modes and sizes.
593 (OP_E_register): Handle new modes.
594 (OP_E_memory): Ditto.
595 (OP_G): Ditto.
596 (OP_XMM): Ditto.
597 (OP_EX): Ditto.
598 (OP_VEX): Ditto.
599 * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
600 CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
601 CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
602 (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
603 CpuAVX512PF and CpuVREX.
604 (operand_type_init): Add OPERAND_TYPE_REGZMM,
605 OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
606 (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
607 StaticRounding, SAE, Disp8MemShift, NoDefMask.
608 (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
609 * i386-init.h: Regenerate.
610 * i386-opc.h (CpuAVX512F): New.
611 (CpuAVX512CD): New.
612 (CpuAVX512ER): New.
613 (CpuAVX512PF): New.
614 (CpuVREX): New.
615 (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
616 cpuavx512pf and cpuvrex fields.
617 (VecSIB): Add VecSIB512.
618 (EVex): New.
619 (Masking): New.
620 (VecESize): New.
621 (Broadcast): New.
622 (StaticRounding): New.
623 (SAE): New.
624 (Disp8MemShift): New.
625 (NoDefMask): New.
626 (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
627 staticrounding, sae, disp8memshift and nodefmask.
628 (RegZMM): New.
629 (Zmmword): Ditto.
630 (Vec_Disp8): Ditto.
631 (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
632 fields.
633 (RegVRex): New.
634 * i386-opc.tbl: Add AVX512 instructions.
635 * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
636 registers, mask registers.
637 * i386-tbl.h: Regenerate.
638
1d2db237
RS		 6392013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
640
641 PR gas/15220
642 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
643 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
644
a0046408
L		 6452013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
646
647 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
648 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
649 PREFIX_0F3ACC.
650 (prefix_table): Updated.
651 (three_byte_table): Likewise.
652 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
653 (cpu_flags): Add CpuSHA.
654 (i386_cpu_flags): Add cpusha.
655 * i386-init.h: Regenerate.
656 * i386-opc.h (CpuSHA): New.
657 (CpuUnused): Restored.
658 (i386_cpu_flags): Add cpusha.
659 * i386-opc.tbl: Add SHA instructions.
660 * i386-tbl.h: Regenerate.
661
7e8b059b
L		 6622013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
663 Kirill Yukhin <kirill.yukhin@intel.com>
664 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
665
666 * i386-dis.c (BND_Fixup): New.
667 (Ebnd): New.
668 (Ev_bnd): New.
669 (Gbnd): New.
670 (BND): New.
671 (v_bnd_mode): New.
672 (bnd_mode): New.
c623f86c
L		 673 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
674 MOD_0F1B_PREFIX_1.
675 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
7e8b059b
L		 676 (dis tables): Replace XX with BND for near branch and call
677 instructions.
678 (prefix_table): Add new entries.
679 (mod_table): Likewise.
680 (names_bnd): New.
681 (intel_names_bnd): New.
682 (att_names_bnd): New.
683 (BND_PREFIX): New.
684 (prefix_name): Handle BND_PREFIX.
685 (print_insn): Initialize names_bnd.
686 (intel_operand_size): Handle new modes.
687 (OP_E_register): Likewise.
688 (OP_E_memory): Likewise.
689 (OP_G): Likewise.
690 * i386-gen.c (cpu_flag_init): Add CpuMPX.
691 (cpu_flags): Add CpuMPX.
692 (operand_type_init): Add RegBND.
693 (opcode_modifiers): Add BNDPrefixOk.
694 (operand_types): Add RegBND.
695 * i386-init.h: Regenerate.
696 * i386-opc.h (CpuMPX): New.
697 (CpuUnused): Comment out.
698 (i386_cpu_flags): Add cpumpx.
699 (BNDPrefixOk): New.
700 (i386_opcode_modifier): Add bndprefixok.
701 (RegBND): New.
702 (i386_operand_type): Add regbnd.
703 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
704 Add MPX instructions and bnd prefix.
705 * i386-reg.tbl: Add bnd0-bnd3 registers.
706 * i386-tbl.h: Regenerate.
707
b56e23fb
RS		 7082013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
709
710 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
711 ATTRIBUTE_UNUSED.
712
e7ae278d
RS		 7132013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
714
715 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
716 special rules.
717 * Makefile.in: Regenerate.
718 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
719 all fields. Reformat.
720
c3c07478
RS		 7212013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
722
723 * mips16-opc.c: Include mips-formats.h.
724 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
725 static arrays.
726 (decode_mips16_operand): New function.
727 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
728 (print_insn_arg): Handle OP_ENTRY_EXIT list.
729 Abort for OP_SAVE_RESTORE_LIST.
730 (print_mips16_insn_arg): Change interface. Use mips_operand
731 structures. Delete GET_OP_S. Move GET_OP definition to...
732 (print_insn_mips16): ...here. Call init_print_arg_state.
733 Update the call to print_mips16_insn_arg.
734
ab902481
RS		 7352013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
736
737 * mips-formats.h: New file.
738 * mips-opc.c: Include mips-formats.h.
739 (reg_0_map): New static array.
740 (decode_mips_operand): New function.
741 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
742 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
743 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
744 (int_c_map): New static arrays.
745 (decode_micromips_operand): New function.
746 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
747 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
748 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
749 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
750 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
751 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
752 (micromips_imm_b_map, micromips_imm_c_map): Delete.
753 (print_reg): New function.
754 (mips_print_arg_state): New structure.
755 (init_print_arg_state, print_insn_arg): New functions.
756 (print_insn_args): Change interface and use mips_operand structures.
757 Delete GET_OP_S. Move GET_OP definition to...
758 (print_insn_mips): ...here. Update the call to print_insn_args.
759 (print_insn_micromips): Use print_insn_args.
760
cc537e56
RS		 7612013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
762
763 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
764 in macros.
765
7a5f87ce
RS		 7662013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
767
768 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
769 ADDA.S, MULA.S and SUBA.S.
770
41741fa4
L		 7712013-07-08 H.J. Lu <hongjiu.lu@intel.com>
772
773 PR gas/13572
774 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
775 * i386-tbl.h: Regenerated.
776
f2ae14a1
RS		 7772013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
778
779 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
780 and SD A(B) macros up.
781 * micromips-opc.c (micromips_opcodes): Likewise.
782
04c9d415
RS		 7832013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
784
785 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
786 instructions.
787
5c324c16
RS		 7882013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
789
790 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
791 MDMX-like instructions.
792 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
793 printing "Q" operands for INSN_5400 instructions.
794
23e69e47
RS		 7952013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
796
797 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
798 "+S" for "cins".
799 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
800 Combine cases.
801
27c5c572
RS		 8022013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
803
804 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
805 "jalx".
806 * mips16-opc.c (mips16_opcodes): Likewise.
807 * micromips-opc.c (micromips_opcodes): Likewise.
808 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
809 (print_insn_mips16): Handle "+i".
810 (print_insn_micromips): Likewise. Conditionally preserve the
811 ISA bit for "a" but not for "+i".
812
e76ff5ab
RS		 8132013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
814
815 * micromips-opc.c (WR_mhi): Rename to..
816 (WR_mh): ...this.
817 (micromips_opcodes): Update "movep" entry accordingly. Replace
818 "mh,mi" with "mh".
819 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
820 (micromips_to_32_reg_h_map1): ...this.
821 (micromips_to_32_reg_i_map): Rename to...
822 (micromips_to_32_reg_h_map2): ...this.
823 (print_micromips_insn): Remove "mi" case. Print both registers
824 in the pair for "mh".
825
fa7616a4
RS		 8262013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
827
828 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
829 * micromips-opc.c (micromips_opcodes): Likewise.
830 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
831 and "+T" handling. Check for a "0" suffix when deciding whether to
832 use coprocessor 0 names. In that case, also check for ",H" selectors.
833
fb798c50
AK		 8342013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
835
836 * s390-opc.c (J12_12, J24_24): New macros.
837 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
838 (MASK_MII_UPI): Rename to MASK_MII_UPP.
839 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
840
58ae08f2
AM		 8412013-07-04 Alan Modra <amodra@gmail.com>
842
843 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
844
b5e04c2b
NC		 8452013-06-26 Nick Clifton <nickc@redhat.com>
846
847 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
848 field when checking for type 2 nop.
849 * rx-decode.c: Regenerate.
850
833794fc
MR		 8512013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
852
853 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
854 and "movep" macros.
855
1bbce132
MR		 8562013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
857
858 * mips-dis.c (is_mips16_plt_tail): New function.
859 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
860 word.
861 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
862
34c911a4
NC		 8632013-06-21 DJ Delorie <dj@redhat.com>
864
865 * msp430-decode.opc: New.
866 * msp430-decode.c: New/generated.
867 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
868 (MAINTAINER_CLEANFILES): Likewise.
869 Add rule to build msp430-decode.c frommsp430decode.opc
870 using the opc2c program.
871 * Makefile.in: Regenerate.
872 * configure.in: Add msp430-decode.lo to msp430 architecture files.
873 * configure: Regenerate.
874
b9eead84
YZ		 8752013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
876
877 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
878 (SYMTAB_AVAILABLE): Removed.
879 (#include "elf/aarch64.h): Ditto.
880
7f3c4072
CM		 8812013-06-17 Catherine Moore <clm@codesourcery.com>
882 Maciej W. Rozycki <macro@codesourcery.com>
883 Chao-Ying Fu <fu@mips.com>
884
885 * micromips-opc.c (EVA): Define.
886 (TLBINV): Define.
887 (micromips_opcodes): Add EVA opcodes.
888 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
889 (print_insn_args): Handle EVA offsets.
890 (print_insn_micromips): Likewise.
891 * mips-opc.c (EVA): Define.
892 (TLBINV): Define.
893 (mips_builtin_opcodes): Add EVA opcodes.
894
de40ceb6
AM		 8952013-06-17 Alan Modra <amodra@gmail.com>
896
897 * Makefile.am (mips-opc.lo): Add rules to create automatic
898 dependency files. Pass archdefs.
899 (micromips-opc.lo, mips16-opc.lo): Likewise.
900 * Makefile.in: Regenerate.
901
3531d549
DD		 9022013-06-14 DJ Delorie <dj@redhat.com>
903
904 * rx-decode.opc (rx_decode_opcode): Bit operations on
905 registers are 32-bit operations, not 8-bit operations.
906 * rx-decode.c: Regenerate.
907
ba92f7fb
CF		 9082013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
909
910 * micromips-opc.c (IVIRT): New define.
911 (IVIRT64): New define.
912 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
913 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
914
915 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
916 dmtgc0 to print cp0 names.
917
9daf7bab
SL		 9182013-06-09 Sandra Loosemore <sandra@codesourcery.com>
919
920 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
921 argument.
922
d301a56b
RS		 9232013-06-08 Catherine Moore <clm@codesourcery.com>
924 Richard Sandiford <rdsandiford@googlemail.com>
925
926 * micromips-opc.c (D32, D33, MC): Update definitions.
927 (micromips_opcodes): Initialize ase field.
928 * mips-dis.c (mips_arch_choice): Add ase field.
929 (mips_arch_choices): Initialize ase field.
930 (set_default_mips_dis_options): Declare and setup mips_ase.
931 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
932 MT32, MC): Update definitions.
933 (mips_builtin_opcodes): Initialize ase field.
934
a3dcb6c5
RS		 9352013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
936
937 * s390-opc.txt (flogr): Require a register pair destination.
938
6cf1d90c
AK		 9392013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
940
941 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
942 instruction format.
943
c77c0862
RS		 9442013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
945
946 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
947
c0637f3a
PB		 9482013-05-20 Peter Bergner <bergner@vnet.ibm.com>
949
950 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
951 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
952 XLS_MASK, PPCVSX2): New defines.
953 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
954 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
955 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
956 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
957 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
958 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
959 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
960 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
961 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
962 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
963 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
964 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
965 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
966 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
967 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
968 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
969 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
970 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
971 <lxvx, stxvx>: New extended mnemonics.
972
4934fdaf
AM		 9732013-05-17 Alan Modra <amodra@gmail.com>
974
975 * ia64-raw.tbl: Replace non-ASCII char.
976 * ia64-waw.tbl: Likewise.
977 * ia64-asmtab.c: Regenerate.
978
6091d651
SE		 9792013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
980
981 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
982 * i386-init.h: Regenerated.
983
d2865ed3
YZ		 9842013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
985
986 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
987 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
988 check from [0, 255] to [-128, 255].
989
b015e599
AP		 9902013-05-09 Andrew Pinski <apinski@cavium.com>
991
992 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
993 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
994 (parse_mips_dis_option): Handle the virt option.
995 (print_insn_args): Handle "+J".
996 (print_mips_disassembler_options): Print out message about virt64.
997 * mips-opc.c (IVIRT): New define.
998 (IVIRT64): New define.
999 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
1000 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
1001 Move rfe to the bottom as it conflicts with tlbgp.
1002
9f0682fe
AM		 10032013-05-09 Alan Modra <amodra@gmail.com>
1004
1005 * ppc-opc.c (extract_vlesi): Properly sign extend.
1006 (extract_vlensi): Likewise. Comment reason for setting invalid.
1007
13761a11
NC		 10082013-05-02 Nick Clifton <nickc@redhat.com>
1009
1010 * msp430-dis.c: Add support for MSP430X instructions.
1011
e3031850
SL		 10122013-04-24 Sandra Loosemore <sandra@codesourcery.com>
1013
1014 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
1015 to "eccinj".
1016
17310e56
NC		 10172013-04-17 Wei-chen Wang <cole945@gmail.com>
1018
1019 PR binutils/15369
1020 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
1021 of CGEN_CPU_ENDIAN.
1022 (hash_insns_list): Likewise.
1023
731df338
JK		 10242013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
1025
1026 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
1027 warning workaround.
1028
5f77db52
JB		 10292013-04-08 Jan Beulich <jbeulich@suse.com>
1030
1031 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
1032 * i386-tbl.h: Re-generate.
1033
0afd1215
DM		 10342013-04-06 David S. Miller <davem@davemloft.net>
1035
1036 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
1037 of an opcode, prefer the one with F_PREFERRED set.
1038 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
1039 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
1040 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
1041 mark existing mnenomics as aliases. Add "cc" suffix to edge
1042 instructions generating condition codes, mark existing mnenomics
1043 as aliases. Add "fp" prefix to VIS compare instructions, mark
1044 existing mnenomics as aliases.
1045
41702d50
NC		 10462013-04-03 Nick Clifton <nickc@redhat.com>
1047
1048 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
1049 destination address by subtracting the operand from the current
1050 address.
1051 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
1052 a positive value in the insn.
1053 (extract_u16_loop): Do not negate the returned value.
1054 (D16_LOOP): Add V850_INVERSE_PCREL flag.
1055
1056 (ceilf.sw): Remove duplicate entry.
1057 (cvtf.hs): New entry.
1058 (cvtf.sh): Likewise.
1059 (fmaf.s): Likewise.
1060 (fmsf.s): Likewise.
1061 (fnmaf.s): Likewise.
1062 (fnmsf.s): Likewise.
1063 (maddf.s): Restrict to E3V5 architectures.
1064 (msubf.s): Likewise.
1065 (nmaddf.s): Likewise.
1066 (nmsubf.s): Likewise.
1067
55cf16e1
L		 10682013-03-27 H.J. Lu <hongjiu.lu@intel.com>
1069
1070 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
1071 check address mode.
1072 (print_insn): Pass sizeflag to get_sib.
1073
51dcdd4d
NC		 10742013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
1075
1076 PR binutils/15068
1077 * tic6x-dis.c: Add support for displaying 16-bit insns.
1078
795b8e6b
NC		 10792013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
1080
1081 PR gas/15095
1082 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
1083 individual msb and lsb halves in src1 & src2 fields. Discard the
1084 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
1085 follow what Ti SDK does in that case as any value in the src1
1086 field yields the same output with SDK disassembler.
1087
314d60dd
ME		 10882013-03-12 Michael Eager <eager@eagercon.com>
1089
795b8e6b 1090 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd 1091
dad60f8e
SL		 10922013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
1093
1094 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
1095
f5cb796a
SL		 10962013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
1097
1098 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
1099
21fde85c
SL		 11002013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
1101
1102 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
1103
dd5181d5
KT		 11042013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1105
1106 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
1107 (thumb32_opcodes): Likewise.
1108 (print_insn_thumb32): Handle 'S' control char.
1109
87a8d6cb
NC		 11102013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
1111
1112 * lm32-desc.c: Regenerate.
1113
99dce992
L		 11142013-03-01 H.J. Lu <hongjiu.lu@intel.com>
1115
1116 * i386-reg.tbl (riz): Add RegRex64.
1117 * i386-tbl.h: Regenerated.
1118
e60bb1dd
YZ		 11192013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
1120
1121 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
1122 (aarch64_feature_crc): New static.
1123 (CRC): New macro.
1124 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
1125 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
1126 * aarch64-asm-2.c: Re-generate.
1127 * aarch64-dis-2.c: Ditto.
1128 * aarch64-opc-2.c: Ditto.
1129
c7570fcd
AM		 11302013-02-27 Alan Modra <amodra@gmail.com>
1131
1132 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
1133 * rl78-decode.c: Regenerate.
1134
151fa98f
NC		 11352013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
1136
1137 * rl78-decode.opc: Fix encoding of DIVWU insn.
1138 * rl78-decode.c: Regenerate.
1139
5c111e37
L		 11402013-02-19 H.J. Lu <hongjiu.lu@intel.com>
1141
1142 PR gas/15159
1143 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
1144
1145 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
1146 (cpu_flags): Add CpuSMAP.
1147
1148 * i386-opc.h (CpuSMAP): New.
1149 (i386_cpu_flags): Add cpusmap.
1150
1151 * i386-opc.tbl: Add clac and stac.
1152
1153 * i386-init.h: Regenerated.
1154 * i386-tbl.h: Likewise.
1155
9d1df426
NC		 11562013-02-15 Markos Chandras <markos.chandras@imgtec.com>
1157
1158 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
1159 which also makes the disassembler output be in little
1160 endian like it should be.
1161
a1ccaec9
YZ		 11622013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
1163
1164 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
1165 fields to NULL.
1166 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
1167
ef068ef4 11682013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e
MR		 1169
1170 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
1171 section disassembled.
1172
6fe6ded9
RE		 11732013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1174
1175 * arm-dis.c: Update strht pattern.
1176
0aa27725
RS		 11772013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
1178
1179 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
1180 single-float. Disable ll, lld, sc and scd for EE. Disable the
1181 trunc.w.s macro for EE.
1182
36591ba1
SL		 11832013-02-06 Sandra Loosemore <sandra@codesourcery.com>
1184 Andrew Jenner <andrew@codesourcery.com>
1185
1186 Based on patches from Altera Corporation.
1187
1188 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
1189 nios2-opc.c.
1190 * Makefile.in: Regenerated.
1191 * configure.in: Add case for bfd_nios2_arch.
1192 * configure: Regenerated.
1193 * disassemble.c (ARCH_nios2): Define.
1194 (disassembler): Add case for bfd_arch_nios2.
1195 * nios2-dis.c: New file.
1196 * nios2-opc.c: New file.
1197
545093a4
AM		 11982013-02-04 Alan Modra <amodra@gmail.com>
1199
1200 * po/POTFILES.in: Regenerate.
1201 * rl78-decode.c: Regenerate.
1202 * rx-decode.c: Regenerate.
1203
e30181a5
YZ		 12042013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
1205
1206 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
1207 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
1208 * aarch64-asm.c (convert_xtl_to_shll): New function.
1209 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1210 calling convert_xtl_to_shll.
1211 * aarch64-dis.c (convert_shll_to_xtl): New function.
1212 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1213 calling convert_shll_to_xtl.
1214 * aarch64-gen.c: Update copyright year.
1215 * aarch64-asm-2.c: Re-generate.
1216 * aarch64-dis-2.c: Re-generate.
1217 * aarch64-opc-2.c: Re-generate.
1218
78c8d46c
NC		 12192013-01-24 Nick Clifton <nickc@redhat.com>
1220
1221 * v850-dis.c: Add support for e3v5 architecture.
1222 * v850-opc.c: Likewise.
1223
f5555712
YZ		 12242013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
1225
1226 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1227 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1228 * aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c 1229 AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712
YZ		 1230 alignment check; change to call set_sft_amount_out_of_range_error
1231 instead of set_imm_out_of_range_error.
1232 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1233 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1234 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1235 SIMD_IMM_SFT.
1236
2f81ff92
L		 12372013-01-16 H.J. Lu <hongjiu.lu@intel.com>
1238
1239 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1240
1241 * i386-init.h: Regenerated.
1242 * i386-tbl.h: Likewise.
1243
dd42f060
NC		 12442013-01-15 Nick Clifton <nickc@redhat.com>
1245
1246 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1247 values.
1248 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1249
a4533ed8
NC		 12502013-01-14 Will Newton <will.newton@imgtec.com>
1251
1252 * metag-dis.c (REG_WIDTH): Increase to 64.
1253
5817ffd1
PB		 12542013-01-10 Peter Bergner <bergner@vnet.ibm.com>
1255
1256 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1257 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1258 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1259 (SH6): Update.
1260 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1261 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1262 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1263 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1264
a3c62988
NC		 12652013-01-10 Will Newton <will.newton@imgtec.com>
1266
1267 * Makefile.am: Add Meta.
1268 * configure.in: Add Meta.
1269 * disassemble.c: Add Meta support.
1270 * metag-dis.c: New file.
1271 * Makefile.in: Regenerate.
1272 * configure: Regenerate.
1273
73335eae
NC		 12742013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
1275
1276 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1277 (match_opcode): Rename to cr16_match_opcode.
1278
e407c74b
NC		 12792013-01-04 Juergen Urban <JuergenUrban@gmx.de>
1280
1281 * mips-dis.c: Add names for CP0 registers of r5900.
1282 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1283 instructions sq and lq.
1284 Add support for MIPS r5900 CPU.
1285 Add support for 128 bit MMI (Multimedia Instructions).
1286 Add support for EE instructions (Emotion Engine).
1287 Disable unsupported floating point instructions (64 bit and
1288 undefined compare operations).
1289 Enable instructions of MIPS ISA IV which are supported by r5900.
1290 Disable 64 bit co processor instructions.
1291 Disable 64 bit multiplication and division instructions.
1292 Disable instructions for co-processor 2 and 3, because these are
1293 not supported (preparation for later VU0 support (Vector Unit)).
1294 Disable cvt.w.s because this behaves like trunc.w.s and the
1295 correct execution can't be ensured on r5900.
1296 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1297 will confuse less developers and compilers.
1298
a32c3ff8
NC		 12992013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1300
fb098a1e
YZ		 1301 * aarch64-opc.c (aarch64_print_operand): Change to print
1302 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1303 in comment.
1304 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1305 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1306 OP_MOV_IMM_WIDE.
1307
13082013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1309
1310 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1311 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8 1312
62658407
L		 13132013-01-02 H.J. Lu <hongjiu.lu@intel.com>
1314
1315 * i386-gen.c (process_copyright): Update copyright year to 2013.
1316
bab4becb 13172013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7 1318
bab4becb
NC		 1319 * cr16-dis.c (match_opcode,make_instruction): Remove static
1320 declaration.
1321 (dwordU,wordU): Moved typedefs to opcode/cr16.h
1322 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7 1323
bab4becb 1324For older changes see ChangeLog-2012
252b5132 1325\f
bab4becb 1326Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC		 1327
1328Copying and distribution of this file, with or without modification,
1329are permitted in any medium without royalty provided the copyright
1330notice and this notice are preserved.
1331
252b5132 1332Local Variables:
2f6d2f85
NC		 1333mode: change-log
1334left-margin: 8
1335fill-column: 74
252b5132
RH		 1336version-control: never
1337End:
GDB Binutils - Deliverables
This page took 0.693466 seconds and 4 git commands to generate.