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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
71300e2c
NC		 12018-06-24 Nick Clifton <nickc@redhat.com>
2
3 * configure: Regenerate.
4 * po/opcodes.pot: Regenerate.
5
719d8288
NC		 62018-06-24 Nick Clifton <nickc@redhat.com>
7
8 2.31 branch created.
9
514cd3a0
TC		 102018-06-19 Tamar Christina <tamar.christina@arm.com>
11
12 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
13 * aarch64-asm-2.c: Regenerate.
14 * aarch64-dis-2.c: Likewise.
15
385e4d0f
MR		 162018-06-21 Maciej W. Rozycki <macro@mips.com>
17
18 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
19 `-M ginv' option description.
20
160d1b3d
SH		 212018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
22
23 PR gas/23305
24 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
25 la and lla.
26
d0ac1c44
SM		 272018-06-19 Simon Marchi <simon.marchi@ericsson.com>
28
29 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
30 * configure.ac: Remove AC_PREREQ.
31 * Makefile.in: Re-generate.
32 * aclocal.m4: Re-generate.
33 * configure: Re-generate.
34
6f20c942
FS		 352018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
36
37 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
38 mips64r6 descriptors.
39 (parse_mips_ase_option): Handle -Mginv option.
40 (print_mips_disassembler_options): Document -Mginv.
41 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
42 (GINV): New macro.
43 (mips_opcodes): Define ginvi and ginvt.
44
730c3174
SE		 452018-06-13 Scott Egerton <scott.egerton@imgtec.com>
46 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
47
48 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
49 * mips-opc.c (CRC, CRC64): New macros.
50 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
51 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
52 crc32cd for CRC64.
53
cb366992
EB		 542018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
55
56 PR 20319
57 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
58 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
59
ce72cd46
AM		 602018-06-06 Alan Modra <amodra@gmail.com>
61
62 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
63 setjmp. Move init for some other vars later too.
64
4b8e28c7
MF		 652018-06-04 Max Filippov <jcmvbkbc@gmail.com>
66
67 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
68 (dis_private): Add new fields for property section tracking.
69 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
70 (xtensa_instruction_fits): New functions.
71 (fetch_data): Bump minimal fetch size to 4.
72 (print_insn_xtensa): Make struct dis_private static.
73 Load and prepare property table on section change.
74 Don't disassemble literals. Don't disassemble instructions that
75 cross property table boundaries.
76
55e99962
L		 772018-06-01 H.J. Lu <hongjiu.lu@intel.com>
78
79 * configure: Regenerated.
80
733bd0ab
JB		 812018-06-01 Jan Beulich <jbeulich@suse.com>
82
83 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
84 * i386-tbl.h: Re-generate.
85
dfd27d41
JB		 862018-06-01 Jan Beulich <jbeulich@suse.com>
87
88 * i386-opc.tbl (sldt, str): Add NoRex64.
89 * i386-tbl.h: Re-generate.
90
64795710
JB		 912018-06-01 Jan Beulich <jbeulich@suse.com>
92
93 * i386-opc.tbl (invpcid): Add Oword.
94 * i386-tbl.h: Re-generate.
95
030157d8
AM		 962018-06-01 Alan Modra <amodra@gmail.com>
97
98 * sysdep.h (_bfd_error_handler): Don't declare.
99 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
100 * rl78-decode.opc: Likewise.
101 * msp430-decode.c: Regenerate.
102 * rl78-decode.c: Regenerate.
103
a9660a6f
AP		 1042018-05-30 Amit Pawar <Amit.Pawar@amd.com>
105
106 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
107 * i386-init.h : Regenerated.
108
277eb7f6
AM		 1092018-05-25 Alan Modra <amodra@gmail.com>
110
111 * Makefile.in: Regenerate.
112 * po/POTFILES.in: Regenerate.
113
98553ad3
PB		 1142018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
115
116 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
117 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
118 (insert_bab, extract_bab, insert_btab, extract_btab,
119 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
120 (BAT, BBA VBA RBS XB6S): Delete macros.
121 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
122 (BB, BD, RBX, XC6): Update for new macros.
123 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
124 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
125 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
126 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
127
7b4ae824
JD		 1282018-05-18 John Darrington <john@darrington.wattle.id.au>
129
130 * Makefile.am: Add support for s12z architecture.
131 * configure.ac: Likewise.
132 * disassemble.c: Likewise.
133 * disassemble.h: Likewise.
134 * Makefile.in: Regenerate.
135 * configure: Regenerate.
136 * s12z-dis.c: New file.
137 * s12z.h: New file.
138
29e0f0a1
AM		 1392018-05-18 Alan Modra <amodra@gmail.com>
140
141 * nfp-dis.c: Don't #include libbfd.h.
142 (init_nfp3200_priv): Use bfd_get_section_contents.
143 (nit_nfp6000_mecsr_sec): Likewise.
144
809276d2
NC		 1452018-05-17 Nick Clifton <nickc@redhat.com>
146
147 * po/zh_CN.po: Updated simplified Chinese translation.
148
ff329288
TC		 1492018-05-16 Tamar Christina <tamar.christina@arm.com>
150
151 PR binutils/23109
152 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
153 * aarch64-dis-2.c: Regenerate.
154
f9830ec1
TC		 1552018-05-15 Tamar Christina <tamar.christina@arm.com>
156
157 PR binutils/21446
158 * aarch64-asm.c (opintl.h): Include.
159 (aarch64_ins_sysreg): Enforce read/write constraints.
160 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
161 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
162 (F_REG_READ, F_REG_WRITE): New.
163 * aarch64-opc.c (aarch64_print_operand): Generate notes for
164 AARCH64_OPND_SYSREG.
165 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
166 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
167 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
168 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
169 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
170 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
171 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
172 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
173 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
174 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
175 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
176 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
177 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
178 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
179 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
180 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
181 msr (F_SYS_WRITE), mrs (F_SYS_READ).
182
7d02540a
TC		 1832018-05-15 Tamar Christina <tamar.christina@arm.com>
184
185 PR binutils/21446
186 * aarch64-dis.c (no_notes: New.
187 (parse_aarch64_dis_option): Support notes.
188 (aarch64_decode_insn, print_operands): Likewise.
189 (print_aarch64_disassembler_options): Document notes.
190 * aarch64-opc.c (aarch64_print_operand): Support notes.
191
561a72d4
TC		 1922018-05-15 Tamar Christina <tamar.christina@arm.com>
193
194 PR binutils/21446
195 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
196 and take error struct.
197 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
198 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
199 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
200 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
201 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
202 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
203 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
204 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
205 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
206 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
207 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
208 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
209 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
210 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
211 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
212 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
213 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
214 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
215 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
216 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
217 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
218 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
219 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
220 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
221 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
222 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
223 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
224 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
225 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
226 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
227 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
228 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
229 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
230 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
231 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
232 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
233 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
234 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
235 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
236 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
237 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
238 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
239 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
240 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
241 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
242 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
243 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
244 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
245 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
246 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
247 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
248 (determine_disassembling_preference, aarch64_decode_insn,
249 print_insn_aarch64_word, print_insn_data): Take errors struct.
250 (print_insn_aarch64): Use errors.
251 * aarch64-asm-2.c: Regenerate.
252 * aarch64-dis-2.c: Regenerate.
253 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
254 boolean in aarch64_insert_operan.
255 (print_operand_extractor): Likewise.
256 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
257
1678bd35
FT		 2582018-05-15 Francois H. Theron <francois.theron@netronome.com>
259
260 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
261
06cfb1c8
L		 2622018-05-09 H.J. Lu <hongjiu.lu@intel.com>
263
264 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
265
84f9f8c3
AM		 2662018-05-09 Sebastian Rasmussen <sebras@gmail.com>
267
268 * cr16-opc.c (cr16_instruction): Comment typo fix.
269 * hppa-dis.c (print_insn_hppa): Likewise.
270
e6f372ba
JW		 2712018-05-08 Jim Wilson <jimw@sifive.com>
272
273 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
274 (match_c_slli64, match_srxi_as_c_srxi): New.
275 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
276 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
277 <c.slli, c.srli, c.srai>: Use match_s_slli.
278 <c.slli64, c.srli64, c.srai64>: New.
279
f413a913
AM		 2802018-05-08 Alan Modra <amodra@gmail.com>
281
282 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
283 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
284 partition opcode space for index lookup.
285
a87a6478
PB		 2862018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
287
288 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
289 <insn_length>: ...with this. Update usage.
290 Remove duplicate call to *info->memory_error_func.
291
c0a30a9f
L		 2922018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
293 H.J. Lu <hongjiu.lu@intel.com>
294
295 * i386-dis.c (Gva): New.
296 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
297 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
298 (prefix_table): New instructions (see prefix above).
299 (mod_table): New instructions (see prefix above).
300 (OP_G): Handle va_mode.
301 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
302 CPU_MOVDIR64B_FLAGS.
303 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
304 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
305 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
306 * i386-opc.tbl: Add movidir{i,64b}.
307 * i386-init.h: Regenerated.
308 * i386-tbl.h: Likewise.
309
75c0a438
L		 3102018-05-07 H.J. Lu <hongjiu.lu@intel.com>
311
312 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
313 AddrPrefixOpReg.
314 * i386-opc.h (AddrPrefixOp0): Renamed to ...
315 (AddrPrefixOpReg): This.
316 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
317 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
318
2ceb7719
PB		 3192018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
320
321 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
322 (vle_num_opcodes): Likewise.
323 (spe2_num_opcodes): Likewise.
324 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
325 initialization loop.
326 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
327 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
328 only once.
329
b3ac5c6c
TC		 3302018-05-01 Tamar Christina <tamar.christina@arm.com>
331
332 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
333
fe944acf
FT		 3342018-04-30 Francois H. Theron <francois.theron@netronome.com>
335
336 Makefile.am: Added nfp-dis.c.
337 configure.ac: Added bfd_nfp_arch.
338 disassemble.h: Added print_insn_nfp prototype.
339 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
340 nfp-dis.c: New, for NFP support.
341 po/POTFILES.in: Added nfp-dis.c to the list.
342 Makefile.in: Regenerate.
343 configure: Regenerate.
344
e2195274
JB		 3452018-04-26 Jan Beulich <jbeulich@suse.com>
346
347 * i386-opc.tbl: Fold various non-memory operand AVX512VL
348 templates into their base ones.
349 * i386-tlb.h: Re-generate.
350
59ef5df4
JB		 3512018-04-26 Jan Beulich <jbeulich@suse.com>
352
353 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
354 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
355 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
356 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
357 * i386-init.h: Re-generate.
358
6e041cf4
JB		 3592018-04-26 Jan Beulich <jbeulich@suse.com>
360
361 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
362 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
363 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
364 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
365 comment.
366 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
367 and CpuRegMask.
368 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
369 CpuRegMask: Delete.
370 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
371 cpuregzmm, and cpuregmask.
372 * i386-init.h: Re-generate.
373 * i386-tbl.h: Re-generate.
374
0e0eea78
JB		 3752018-04-26 Jan Beulich <jbeulich@suse.com>
376
377 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
378 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
379 * i386-init.h: Re-generate.
380
2f1bada2
JB		 3812018-04-26 Jan Beulich <jbeulich@suse.com>
382
383 * i386-gen.c (VexImmExt): Delete.
384 * i386-opc.h (VexImmExt, veximmext): Delete.
385 * i386-opc.tbl: Drop all VexImmExt uses.
386 * i386-tlb.h: Re-generate.
387
bacd1457
JB		 3882018-04-25 Jan Beulich <jbeulich@suse.com>
389
390 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
391 register-only forms.
392 * i386-tlb.h: Re-generate.
393
10bba94b
TC		 3942018-04-25 Tamar Christina <tamar.christina@arm.com>
395
396 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
397
c48935d7
IT		 3982018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
399
400 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
401 PREFIX_0F1C.
402 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
403 (cpu_flags): Add CpuCLDEMOTE.
404 * i386-init.h: Regenerate.
405 * i386-opc.h (enum): Add CpuCLDEMOTE,
406 (i386_cpu_flags): Add cpucldemote.
407 * i386-opc.tbl: Add cldemote.
408 * i386-tbl.h: Regenerate.
409
211dc24b
AM		 4102018-04-16 Alan Modra <amodra@gmail.com>
411
412 * Makefile.am: Remove sh5 and sh64 support.
413 * configure.ac: Likewise.
414 * disassemble.c: Likewise.
415 * disassemble.h: Likewise.
416 * sh-dis.c: Likewise.
417 * sh64-dis.c: Delete.
418 * sh64-opc.c: Delete.
419 * sh64-opc.h: Delete.
420 * Makefile.in: Regenerate.
421 * configure: Regenerate.
422 * po/POTFILES.in: Regenerate.
423
a9a4b302
AM		 4242018-04-16 Alan Modra <amodra@gmail.com>
425
426 * Makefile.am: Remove w65 support.
427 * configure.ac: Likewise.
428 * disassemble.c: Likewise.
429 * disassemble.h: Likewise.
430 * w65-dis.c: Delete.
431 * w65-opc.h: Delete.
432 * Makefile.in: Regenerate.
433 * configure: Regenerate.
434 * po/POTFILES.in: Regenerate.
435
04cb01fd
AM		 4362018-04-16 Alan Modra <amodra@gmail.com>
437
438 * configure.ac: Remove we32k support.
439 * configure: Regenerate.
440
c2bf1eec
AM		 4412018-04-16 Alan Modra <amodra@gmail.com>
442
443 * Makefile.am: Remove m88k support.
444 * configure.ac: Likewise.
445 * disassemble.c: Likewise.
446 * disassemble.h: Likewise.
447 * m88k-dis.c: Delete.
448 * Makefile.in: Regenerate.
449 * configure: Regenerate.
450 * po/POTFILES.in: Regenerate.
451
6793974d
AM		 4522018-04-16 Alan Modra <amodra@gmail.com>
453
454 * Makefile.am: Remove i370 support.
455 * configure.ac: Likewise.
456 * disassemble.c: Likewise.
457 * disassemble.h: Likewise.
458 * i370-dis.c: Delete.
459 * i370-opc.c: Delete.
460 * Makefile.in: Regenerate.
461 * configure: Regenerate.
462 * po/POTFILES.in: Regenerate.
463
e82aa794
AM		 4642018-04-16 Alan Modra <amodra@gmail.com>
465
466 * Makefile.am: Remove h8500 support.
467 * configure.ac: Likewise.
468 * disassemble.c: Likewise.
469 * disassemble.h: Likewise.
470 * h8500-dis.c: Delete.
471 * h8500-opc.h: Delete.
472 * Makefile.in: Regenerate.
473 * configure: Regenerate.
474 * po/POTFILES.in: Regenerate.
475
fceadf09
AM		 4762018-04-16 Alan Modra <amodra@gmail.com>
477
478 * configure.ac: Remove tahoe support.
479 * configure: Regenerate.
480
ae1d3843
L		 4812018-04-15 H.J. Lu <hongjiu.lu@intel.com>
482
483 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
484 umwait.
485 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
486 64-bit mode.
487 * i386-tbl.h: Regenerated.
488
de89d0a3
IT		 4892018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
490
491 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
492 PREFIX_MOD_1_0FAE_REG_6.
493 (va_mode): New.
494 (OP_E_register): Use va_mode.
495 * i386-dis-evex.h (prefix_table):
496 New instructions (see prefixes above).
497 * i386-gen.c (cpu_flag_init): Add WAITPKG.
498 (cpu_flags): Likewise.
499 * i386-opc.h (enum): Likewise.
500 (i386_cpu_flags): Likewise.
501 * i386-opc.tbl: Add umonitor, umwait, tpause.
502 * i386-init.h: Regenerate.
503 * i386-tbl.h: Likewise.
504
a8eb42a8
AM		 5052018-04-11 Alan Modra <amodra@gmail.com>
506
507 * opcodes/i860-dis.c: Delete.
508 * opcodes/i960-dis.c: Delete.
509 * Makefile.am: Remove i860 and i960 support.
510 * configure.ac: Likewise.
511 * disassemble.c: Likewise.
512 * disassemble.h: Likewise.
513 * Makefile.in: Regenerate.
514 * configure: Regenerate.
515 * po/POTFILES.in: Regenerate.
516
caf0678c
L		 5172018-04-04 H.J. Lu <hongjiu.lu@intel.com>
518
519 PR binutils/23025
520 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
521 to 0.
522 (print_insn): Clear vex instead of vex.evex.
523
4fb0d2b9
NC		 5242018-04-04 Nick Clifton <nickc@redhat.com>
525
526 * po/es.po: Updated Spanish translation.
527
c39e5b26
JB		 5282018-03-28 Jan Beulich <jbeulich@suse.com>
529
530 * i386-gen.c (opcode_modifiers): Delete VecESize.
531 * i386-opc.h (VecESize): Delete.
532 (struct i386_opcode_modifier): Delete vecesize.
533 * i386-opc.tbl: Drop VecESize.
534 * i386-tlb.h: Re-generate.
535
8e6e0792
JB		 5362018-03-28 Jan Beulich <jbeulich@suse.com>
537
538 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
539 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
540 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
541 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
542 * i386-tlb.h: Re-generate.
543
9f123b91
JB		 5442018-03-28 Jan Beulich <jbeulich@suse.com>
545
546 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
547 Fold AVX512 forms
548 * i386-tlb.h: Re-generate.
549
9646c87b
JB		 5502018-03-28 Jan Beulich <jbeulich@suse.com>
551
552 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
553 (vex_len_table): Drop Y for vcvt*2si.
554 (putop): Replace plain 'Y' handling by abort().
555
c8d59609
NC		 5562018-03-28 Nick Clifton <nickc@redhat.com>
557
558 PR 22988
559 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
560 instructions with only a base address register.
561 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
562 handle AARHC64_OPND_SVE_ADDR_R.
563 (aarch64_print_operand): Likewise.
564 * aarch64-asm-2.c: Regenerate.
565 * aarch64_dis-2.c: Regenerate.
566 * aarch64-opc-2.c: Regenerate.
567
b8c169f3
JB		 5682018-03-22 Jan Beulich <jbeulich@suse.com>
569
570 * i386-opc.tbl: Drop VecESize from register only insn forms and
571 memory forms not allowing broadcast.
572 * i386-tlb.h: Re-generate.
573
96bc132a
JB		 5742018-03-22 Jan Beulich <jbeulich@suse.com>
575
576 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
577 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
578 sha256*): Drop Disp<N>.
579
9f79e886
JB		 5802018-03-22 Jan Beulich <jbeulich@suse.com>
581
582 * i386-dis.c (EbndS, bnd_swap_mode): New.
583 (prefix_table): Use EbndS.
584 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
585 * i386-opc.tbl (bndmov): Move misplaced Load.
586 * i386-tlb.h: Re-generate.
587
d6793fa1
JB		 5882018-03-22 Jan Beulich <jbeulich@suse.com>
589
590 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
591 templates allowing memory operands and folded ones for register
592 only flavors.
593 * i386-tlb.h: Re-generate.
594
f7768225
JB		 5952018-03-22 Jan Beulich <jbeulich@suse.com>
596
597 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
598 256-bit templates. Drop redundant leftover Disp<N>.
599 * i386-tlb.h: Re-generate.
600
0e35537d
JW		 6012018-03-14 Kito Cheng <kito.cheng@gmail.com>
602
603 * riscv-opc.c (riscv_insn_types): New.
604
b4a3689a
NC		 6052018-03-13 Nick Clifton <nickc@redhat.com>
606
607 * po/pt_BR.po: Updated Brazilian Portuguese translation.
608
d3d50934
L		 6092018-03-08 H.J. Lu <hongjiu.lu@intel.com>
610
611 * i386-opc.tbl: Add Optimize to clr.
612 * i386-tbl.h: Regenerated.
613
bd5dea88
L		 6142018-03-08 H.J. Lu <hongjiu.lu@intel.com>
615
616 * i386-gen.c (opcode_modifiers): Remove OldGcc.
617 * i386-opc.h (OldGcc): Removed.
618 (i386_opcode_modifier): Remove oldgcc.
619 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
620 instructions for old (<= 2.8.1) versions of gcc.
621 * i386-tbl.h: Regenerated.
622
e771e7c9
JB		 6232018-03-08 Jan Beulich <jbeulich@suse.com>
624
625 * i386-opc.h (EVEXDYN): New.
626 * i386-opc.tbl: Fold various AVX512VL templates.
627 * i386-tlb.h: Re-generate.
628
ed438a93
JB		 6292018-03-08 Jan Beulich <jbeulich@suse.com>
630
631 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
632 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
633 vpexpandd, vpexpandq): Fold AFX512VF templates.
634 * i386-tlb.h: Re-generate.
635
454172a9
JB		 6362018-03-08 Jan Beulich <jbeulich@suse.com>
637
638 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
639 Fold 128- and 256-bit VEX-encoded templates.
640 * i386-tlb.h: Re-generate.
641
36824150
JB		 6422018-03-08 Jan Beulich <jbeulich@suse.com>
643
644 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
645 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
646 vpexpandd, vpexpandq): Fold AVX512F templates.
647 * i386-tlb.h: Re-generate.
648
e7f5c0a9
JB		 6492018-03-08 Jan Beulich <jbeulich@suse.com>
650
651 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
652 64-bit templates. Drop Disp<N>.
653 * i386-tlb.h: Re-generate.
654
25a4277f
JB		 6552018-03-08 Jan Beulich <jbeulich@suse.com>
656
657 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
658 and 256-bit templates.
659 * i386-tlb.h: Re-generate.
660
d2224064
JB		 6612018-03-08 Jan Beulich <jbeulich@suse.com>
662
663 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
664 * i386-tlb.h: Re-generate.
665
1b193f0b
JB		 6662018-03-08 Jan Beulich <jbeulich@suse.com>
667
668 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
669 Drop NoAVX.
670 * i386-tlb.h: Re-generate.
671
f2f6a710
JB		 6722018-03-08 Jan Beulich <jbeulich@suse.com>
673
674 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
675 * i386-tlb.h: Re-generate.
676
38e314eb
JB		 6772018-03-08 Jan Beulich <jbeulich@suse.com>
678
679 * i386-gen.c (opcode_modifiers): Delete FloatD.
680 * i386-opc.h (FloatD): Delete.
681 (struct i386_opcode_modifier): Delete floatd.
682 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
683 FloatD by D.
684 * i386-tlb.h: Re-generate.
685
d53e6b98
JB		 6862018-03-08 Jan Beulich <jbeulich@suse.com>
687
688 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
689
2907c2f5
JB		 6902018-03-08 Jan Beulich <jbeulich@suse.com>
691
692 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
693 * i386-tlb.h: Re-generate.
694
73053c1f
JB		 6952018-03-08 Jan Beulich <jbeulich@suse.com>
696
697 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
698 forms.
699 * i386-tlb.h: Re-generate.
700
52fe4420
AM		 7012018-03-07 Alan Modra <amodra@gmail.com>
702
703 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
704 bfd_arch_rs6000.
705 * disassemble.h (print_insn_rs6000): Delete.
706 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
707 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
708 (print_insn_rs6000): Delete.
709
a6743a54
AM		 7102018-03-03 Alan Modra <amodra@gmail.com>
711
712 * sysdep.h (opcodes_error_handler): Define.
713 (_bfd_error_handler): Declare.
714 * Makefile.am: Remove stray #.
715 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
716 EDIT" comment.
717 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
718 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
719 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
720 opcodes_error_handler to print errors. Standardize error messages.
721 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
722 and include opintl.h.
723 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
724 * i386-gen.c: Standardize error messages.
725 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
726 * Makefile.in: Regenerate.
727 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
728 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
729 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
730 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
731 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
732 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
733 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
734 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
735 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
736 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
737 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
738 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
739 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
740
8305403a
L		 7412018-03-01 H.J. Lu <hongjiu.lu@intel.com>
742
743 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
744 vpsub[bwdq] instructions.
745 * i386-tbl.h: Regenerated.
746
e184813f
AM		 7472018-03-01 Alan Modra <amodra@gmail.com>
748
749 * configure.ac (ALL_LINGUAS): Sort.
750 * configure: Regenerate.
751
5b616bef
TP		 7522018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
753
754 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
755 macro by assignements.
756
b6f8c7c4
L		 7572018-02-27 H.J. Lu <hongjiu.lu@intel.com>
758
759 PR gas/22871
760 * i386-gen.c (opcode_modifiers): Add Optimize.
761 * i386-opc.h (Optimize): New enum.
762 (i386_opcode_modifier): Add optimize.
763 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
764 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
765 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
766 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
767 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
768 vpxord and vpxorq.
769 * i386-tbl.h: Regenerated.
770
e95b887f
AM		 7712018-02-26 Alan Modra <amodra@gmail.com>
772
773 * crx-dis.c (getregliststring): Allocate a large enough buffer
774 to silence false positive gcc8 warning.
775
0bccfb29
JW		 7762018-02-22 Shea Levy <shea@shealevy.com>
777
778 * disassemble.c (ARCH_riscv): Define if ARCH_all.
779
6b6b6807
L		 7802018-02-22 H.J. Lu <hongjiu.lu@intel.com>
781
782 * i386-opc.tbl: Add {rex},
783 * i386-tbl.h: Regenerated.
784
75f31665
MR		 7852018-02-20 Maciej W. Rozycki <macro@mips.com>
786
787 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
788 (mips16_opcodes): Replace `M' with `m' for "restore".
789
e207bc53
TP		 7902018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
791
792 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
793
87993319
MR		 7942018-02-13 Maciej W. Rozycki <macro@mips.com>
795
796 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
797 variable to `function_index'.
798
68d20676
NC		 7992018-02-13 Nick Clifton <nickc@redhat.com>
800
801 PR 22823
802 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
803 about truncation of printing.
804
d2159fdc
HW		 8052018-02-12 Henry Wong <henry@stuffedcow.net>
806
807 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
808
f174ef9f
NC		 8092018-02-05 Nick Clifton <nickc@redhat.com>
810
811 * po/pt_BR.po: Updated Brazilian Portuguese translation.
812
be3a8dca
IT		 8132018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
814
815 * i386-dis.c (enum): Add pconfig.
816 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
817 (cpu_flags): Add CpuPCONFIG.
818 * i386-opc.h (enum): Add CpuPCONFIG.
819 (i386_cpu_flags): Add cpupconfig.
820 * i386-opc.tbl: Add PCONFIG instruction.
821 * i386-init.h: Regenerate.
822 * i386-tbl.h: Likewise.
823
3233d7d0
IT		 8242018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
825
826 * i386-dis.c (enum): Add PREFIX_0F09.
827 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
828 (cpu_flags): Add CpuWBNOINVD.
829 * i386-opc.h (enum): Add CpuWBNOINVD.
830 (i386_cpu_flags): Add cpuwbnoinvd.
831 * i386-opc.tbl: Add WBNOINVD instruction.
832 * i386-init.h: Regenerate.
833 * i386-tbl.h: Likewise.
834
e925c834
JW		 8352018-01-17 Jim Wilson <jimw@sifive.com>
836
837 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
838
d777820b
IT		 8392018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
840
841 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
842 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
843 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
844 (cpu_flags): Add CpuIBT, CpuSHSTK.
845 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
846 (i386_cpu_flags): Add cpuibt, cpushstk.
847 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
848 * i386-init.h: Regenerate.
849 * i386-tbl.h: Likewise.
850
f6efed01
NC		 8512018-01-16 Nick Clifton <nickc@redhat.com>
852
853 * po/pt_BR.po: Updated Brazilian Portugese translation.
854 * po/de.po: Updated German translation.
855
2721d702
JW		 8562018-01-15 Jim Wilson <jimw@sifive.com>
857
858 * riscv-opc.c (match_c_nop): New.
859 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
860
616dcb87
NC		 8612018-01-15 Nick Clifton <nickc@redhat.com>
862
863 * po/uk.po: Updated Ukranian translation.
864
3957a496
NC		 8652018-01-13 Nick Clifton <nickc@redhat.com>
866
867 * po/opcodes.pot: Regenerated.
868
769c7ea5
NC		 8692018-01-13 Nick Clifton <nickc@redhat.com>
870
871 * configure: Regenerate.
872
faf766e3
NC		 8732018-01-13 Nick Clifton <nickc@redhat.com>
874
875 2.30 branch created.
876
888a89da
IT		 8772018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
878
879 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
880 * i386-tbl.h: Regenerate.
881
cbda583a
JB		 8822018-01-10 Jan Beulich <jbeulich@suse.com>
883
884 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
885 * i386-tbl.h: Re-generate.
886
c9e92278
JB		 8872018-01-10 Jan Beulich <jbeulich@suse.com>
888
889 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
890 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
891 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
892 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
893 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
894 Disp8MemShift of AVX512VL forms.
895 * i386-tbl.h: Re-generate.
896
35fd2b2b
JW		 8972018-01-09 Jim Wilson <jimw@sifive.com>
898
899 * riscv-dis.c (maybe_print_address): If base_reg is zero,
900 then the hi_addr value is zero.
901
91d8b670
JG		 9022018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
903
904 * arm-dis.c (arm_opcodes): Add csdb.
905 (thumb32_opcodes): Add csdb.
906
be2e7d95
JG		 9072018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
908
909 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
910 * aarch64-asm-2.c: Regenerate.
911 * aarch64-dis-2.c: Regenerate.
912 * aarch64-opc-2.c: Regenerate.
913
704a705d
L		 9142018-01-08 H.J. Lu <hongjiu.lu@intel.com>
915
916 PR gas/22681
917 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
918 Remove AVX512 vmovd with 64-bit operands.
919 * i386-tbl.h: Regenerated.
920
35eeb78f
JW		 9212018-01-05 Jim Wilson <jimw@sifive.com>
922
923 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
924 jalr.
925
219d1afa
AM		 9262018-01-03 Alan Modra <amodra@gmail.com>
927
928 Update year range in copyright notice of all files.
929
1508bbf5
JB		 9302018-01-02 Jan Beulich <jbeulich@suse.com>
931
932 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
933 and OPERAND_TYPE_REGZMM entries.
934
1e563868 935For older changes see ChangeLog-2017
3499769a 936\f
1e563868 937Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 938
939Copying and distribution of this file, with or without modification,
940are permitted in any medium without royalty provided the copyright
941notice and this notice are preserved.
942
943Local Variables:
944mode: change-log
945left-margin: 8
946fill-column: 74
947version-control: never
948End:
GDB Binutils - Deliverables
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