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Add the endian reversing versions of load/store instructions;
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
e692c217
ME		 12012-11-14 Edgar E. Iglesias <edgar.iglesias@gmail.com>
2
3 * microblaze-opc.h: Increase MAX_OPCODES (op_code_struct): add lbur,
4 lhur, lwr, sbr, shr, swr
5 * microblaze-opcm.h (microblaze_instr): add lbur, lhur, lwr, sbr, shr,
6 swr
7
de863c74
NC		 82012-11-09 Nick Clifton <nickc@redhat.com>
9
10 * configure.in: Add bfd_v850_rh850_arch.
11 * configure: Regenerate.
12 * disassemble.c (disassembler): Likewise.
13
5bb3703f
L		 142012-11-09 H.J. Lu <hongjiu.lu@intel.com>
15
16 * aarch64-opc.h (gen_mask): Remove trailing redundant `;'.
17 * ia64-gen.c (fetch_insn_class): Likewise.
18
6febeb74
AM		 192012-11-08 Alan Modra <amodra@gmail.com>
20
21 * po/POTFILES.in: Regenerate.
22
d17dce55
AM		 232012-11-05 Alan Modra <amodra@gmail.com>
24
25 * configure.in: Apply 2012-09-10 change to config.in here.
26
aac129d7
AK		 272012-10-26 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
28
29 * s390-mkopc.c: Accept empty lines in s390-opc.txt.
d17dce55
AM		 30 * s390-opc.c: Add M_20OPT field. New instruction formats RRF_RURR2
31 and RRF_RMRR.
aac129d7
AK		 32 * s390-opc.txt: Add new instructions. New instruction type for lptea.
33
747a4ac1
CG		 342012-10-26 Christian Groessler <chris@groessler.org>
35
36 * z8kgen.c (struct op): Fix encoding for translate opcodes (trdb,
37 trdrb, trib, trirb, trtdb, trtdrb, trtib, trtirb). Remove
38 non-existing opcode trtrb.
39 * z8k-opc.h: Regenerate.
40
62082a42
AM		 412012-10-26 Alan Modra <amodra@gmail.com>
42
43 * ppc-opc (powerpc_opcodes): "lfdp" and "stfdp" use DS offset.
44
6c067bbb
RM		 452012-10-24 Roland McGrath <mcgrathr@google.com>
46
47 * i386-dis.c (ckprefix): When bailing out for fwait with prefixes,
48 set rex_used to rex.
49
ab4437c3
PB		 502012-10-22 Peter Bergner <bergner@vnet.ibm.com>
51
52 * ppc-opc.c (powerpc_opcodes) <vcfpsxws>: Fix opcode spelling.
53
9a176a4a
TT		 542012-10-18 Tom Tromey <tromey@redhat.com>
55
56 * tic54x-dis.c (print_instruction): Don't use K&R style.
57 (print_parallel_instruction, sprint_dual_address)
58 (sprint_indirect_address, sprint_direct_address, sprint_mmr)
59 (sprint_cc2, sprint_condition): Likewise.
60
4ad3b7ef
KT		 612012-10-18 Kai Tietz <ktietz@redhat.com>
62
63 * aarch64-asm.c (aarch64_ins_ldst_reglist): Initialize
64 value with a default.
65 (do_special_encoding): Likewise.
66 (aarch64_ins_ldst_elemlist): Pre-initialize QSsize, and opcodeh2
67 variables with default.
68 * arc-dis.c (write_comments_): Don't use strncat due
69 size of state->commentBuffer pointer isn't predictable.
70
b7a54b55
YZ		 712012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
72
73 * aarch64-opc.c (aarch64_sys_regs): Add rmr_el1, rmr_el2 and
74 rmr_el3; remove daifset and daifclr.
75
9b61754a
YZ		 762012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
77
78 * aarch64-opc.c (operand_general_constraint_met_p): Change to check
79 the alignment of addr.offset.imm instead of that of shifter.amount for
80 operand type AARCH64_OPND_ADDR_UIMM12.
81
f8ece37f
RE		 822012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
83
84 * arm-dis.c: Use preferred form of vrint instruction variants
85 for disassembly.
86
5e5c50d3
NE		 872012-10-09 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
88
89 * i386-gen.c (cpu_flag_init): Add CPU_BDVER3_FLAGS.
90 * i386-init.h: Regenerated.
91
c7a5aa9c
PB		 922012-10-05 Peter Bergner <bergner@vnet.ibm.com>
93
94 * ppc-dis.c (ppc_opts) <altivec>: Use PPC_OPCODE_ALTIVEC2;
95 * ppc-opc.c (VBA): New define.
96 (powerpc_opcodes) <vcuxwfp, vcsxwfp, vcfpuxws, vcfpsxsw, vmr, vnot,
97 mfppr, mfppr32, mtppr, mtppr32>: New extended mnemonics.
98
04ee5257
NC		 992012-10-04 Nick Clifton <nickc@redhat.com>
100
101 * v850-dis.c (disassemble): Place square parentheses around second
102 register operand of clr1, not1, set1 and tst1 instructions.
103
cfc72779
AK		 1042012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
105
106 * s390-mkopc.c: Support new option zEC12.
107 * s390-opc.c: Add new instruction formats.
108 * s390-opc.txt: Add new instructions for zEC12.
109
1415a2a7
AG		 1102012-09-27 Anthony Green <green@moxielogic.com>
111
112 * moxie-dis.c (print_insn_moxie): Print 'bad' instructions.
113 * moxie-opc.c: All 'bad' instructions have the itype MOXIE_BAD.
114
160a30bb
L		 1152012-09-25 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
116
04ee5257
NC		 117 * i386-gen.c (cpu_flag_init): Add missing Cpu flags in
118 CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS
160a30bb
L		 119 and CPU_BTVER2_FLAGS.
120 * i386-init.h: Regenerated.
121
60aa667e
L		 1222012-09-20 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
123
124 * i386-gen.c (cpu_flag_init): Add CpuCX16 to CPU_NOCONA_FLAGS,
125 CPU_CORE_FLAGS, CPU_CORE2_FLAGS, CPU_COREI7_FLAGS,
126 CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS,
127 CPU_BTVER2_FLAGS. Add CPU_CX16_FLAGS.
128 (cpu_flags): Add CpuCX16.
129 * i386-opc.h (CpuCX16): New.
130 (i386_cpu_flags): Add cpucx16.
131 * i386-opc.tbl: Replace CpuSSE3 with CpuCX16 for cmpxchg16b.
132 * i386-tbl.h: Regenerate.
133 * i386-init.h: Likewise.
134
4b8c8c02
RE		 1352012-09-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
136
60aa667e 137 * arm-dis.c: Changed ldra and strl-form mnemonics
4b8c8c02
RE		 138 to lda and stl-form.
139
83ea18d0
MR		 1402012-09-18 Chao-ying Fu <fu@mips.com>
141
142 * micromips-opc.c (micromips_opcodes): Correct the encoding of
143 the "swxc1" instruction.
144
062f38fa
RE		 1452012-09-17 Yufeng Zhang <yufeng.zhang@arm.com>
146
147 * aarch64-asm.c (aarch64_ins_imm_half): Remove ATTRIBUTE_UNUSED from
148 the parameter 'inst'.
149 (aarch64_ins_addr_simm): Add ATTRIBUTE_UNUSED to the parameter 'inst'.
150 (convert_mov_to_movewide): Change to assert (0) when
151 aarch64_wide_constant_p returns FALSE.
152
b132a67d
DE		 1532012-09-14 David Edelsohn <dje.gcc@gmail.com>
154
155 * configure: Regenerate.
156
1f9b75dd
AG		 1572012-09-14 Anthony Green <green@moxielogic.com>
158
159 * moxie-dis.c (print_insn_moxie): Branch targets are relative to
160 the address after the branch instruction.
161
e202fa84
AG		 1622012-09-13 Anthony Green <green@moxielogic.com>
163
164 * moxie-dis.c (print_insn_moxie): Handle bi-endian encodings.
165
00716ab1
AM		 1662012-09-10 Matthias Klose <doko@ubuntu.com>
167
168 * config.in: Disable sanity check for kfreebsd.
169
6d2920c8
L		 1702012-09-10 H.J. Lu <hongjiu.lu@intel.com>
171
172 * configure: Regenerated.
173
b3e14eda
L		 1742012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
175
176 * ia64-asmtab.h (completer_index): Extend bitfield to full uint.
177 * ia64-gen.c: Promote completer index type to longlong.
178 (irf_operand): Add new register recognition.
179 (in_iclass_mov_x): Add an entry for the new mov_* instruction type.
180 (lookup_specifier): Add new resource recognition.
181 (insert_bit_table_ent): Relax abort condition according to the
182 changed completer index type.
183 (print_dis_table): Fix printf format for completer index.
184 * ia64-ic.tbl: Add a new instruction class.
185 * ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions.
186 * ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions.
187 * ia64-opc.h: Define short names for new operand types.
188 * ia64-raw.tbl: Add new RAW resource for DAHR register.
189 * ia64-waw.tbl: Add new WAW resource for DAHR register.
190 * ia64-asmtab.c: Regenerate.
191
382c72e9
PB		 1922012-08-29 Peter Bergner <bergner@vnet.ibm.com>
193
194 * ppc-opc.c (VXASHB_MASK): New define.
195 (powerpc_opcodes) <vsldoi>: Use VXASHB_MASK.
196
fb048c26
PB		 1972012-08-28 Peter Bergner <bergner@vnet.ibm.com>
198
199 * ppc-opc.c (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK,
200 VXVDVA_MASK, VXUIMM4_MASK, VXUIMM3_MASK, VXUIMM2_MASK): New defines.
201 (powerpc_opcodes) <vexptefp, vlogefp, vrefp, vrfim, vrfin, vrfip,
202 vrfiz, vrsqrtefp, vupkhpx, vupkhsb, vupkhsh, vupklpx, vupklsb,
203 vupklsh>: Use VXVA_MASK.
204 <vspltisb, vspltish, vspltisw>: Use VXVB_MASK.
205 <mfvscr>: Use VXVAVB_MASK.
206 <mtvscr>: Use VXVDVA_MASK.
207 <vspltb>: Use VXUIMM4_MASK.
208 <vsplth>: Use VXUIMM3_MASK.
209 <vspltw>: Use VXUIMM2_MASK.
210
3c9017d2
MGD		 2112012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
212
213 * arm-dis.c (neon_opcodes): Add 2 operand sha instructions.
214
48adcd8e
MGD		 2152012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
216
217 * arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
218
4f51b4bd
MGD		 2192012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
220
221 * arm-dis.c (neon_opcodes): Handle VMULL.P64.
222
91ff7894
MGD		 2232012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
224
225 * arm-dis.c (neon_opcodes): Add support for AES instructions.
226
c70a8987
MGD		 2272012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
228
229 * arm-dis.c (coprocessor_opcodes): Add support for HP/DP
230 conversions.
231
30bdf752
MGD		 2322012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
233
234 * arm-dis.c (coprocessor_opcodes): Add VRINT.
235 (neon_opcodes): Likewise.
236
7e8e6784
MGD		 2372012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
238
239 * arm-dis.c (coprocessor_opcodes): Add support for new VCVT
240 variants.
241 (neon_opcodes): Likewise.
242
73924fbc
MGD		 2432012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
244
245 * arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
246 (neon_opcodes): Likewise.
247
33399f07
MGD		 2482012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
249
250 * arm-dis.c (coprocessor_opcodes): Add VSEL.
251 (print_insn_coprocessor): Add new %<>c bitfield format
252 specifier.
253
9eb6c0f1
MGD		 2542012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
255
256 * arm-dis.c (arm_opcodes): Add LDRA/STRL instructions.
257 (thumb32_opcodes): Likewise.
258 (print_arm_insn): Add support for %<>T formatter.
259
8884b720
MGD		 2602012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
261
262 * arm-dis.c (arm_opcodes): Add HLT.
263 (thumb_opcodes): Likewise.
264
b79f7053
MGD		 2652012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
266
267 * arm-dis.c (thumb32_opcodes): Add DCPS instruction.
268
53c4b28b
MGD		 2692012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
270
271 * arm-dis.c (arm_opcodes): Add SEVL.
272 (thumb_opcodes): Likewise.
273 (thumb32_opcodes): Likewise.
274
e797f7e0
MGD		 2752012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
276
277 * arm-dis.c (data_barrier_option): New function.
278 (print_insn_arm): Use data_barrier_option.
279 (print_insn_thumb32): Use data_barrier_option.
280
e2efe87d
MGD		 2812012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com
282
283 * arm-dis.c (COND_UNCOND): New constant.
284 (print_insn_coprocessor): Add support for %u format specifier.
285 (print_insn_neon): Likewise.
286
2c63854f
DM		 2872012-08-21 David S. Miller <davem@davemloft.net>
288
289 * sparc-opc.c (4-argument crypto instructions): Fix encoding using
290 F3F4 macro.
291
e67ed0e8
AM		 2922012-08-20 Edmar Wienskoski <edmar@freescale.com>
293
294 * ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub,
295 vabsduh, vabsduw, mviwsplt.
296
7b458c12
L		 2972012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
298
299 * i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and
300 CPU_BTVER2_FLAGS.
301
e67ed0e8 302 * i386-opc.h: Update CpuPRFCHW comment.
7b458c12
L		 303
304 * i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW.
305 * i386-init.h: Regenerated.
306 * i386-tbl.h: Likewise.
307
eb80cb87
NC		 3082012-08-17 Nick Clifton <nickc@redhat.com>
309
310 * po/uk.po: New Ukranian translation.
311 * configure.in (ALL_LINGUAS): Add uk.
312 * configure: Regenerate.
313
8baf7b78
PB		 3142012-08-16 Peter Bergner <bergner@vnet.ibm.com>
315
316 * ppc-opc.c (powerpc_opcodes) <"lswx">: Use RAX for the second and
317 RBX for the third operand.
318 <"lswi">: Use RAX for second and NBI for the third operand.
319
3d557b4c
DD		 3202012-08-15 DJ Delorie <dj@redhat.com>
321
322 * rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01]
323 operands, so that data addresses can be corrected when not
324 ES-overridden.
325 * rl78-decode.c: Regenerate.
326 * rl78-dis.c (print_insn_rl78): Make order of modifiers
327 irrelevent. When the 'e' specifier is used on an operand and no
328 ES prefix is provided, adjust address to make it absolute.
329
588925d0
PB		 3302012-08-15 Peter Bergner <bergner@vnet.ibm.com>
331
332 * ppc-opc.c <RSQ, RTQ>: Use PPC_OPERAND_GPR.
333
9f6a6cc0
PB		 3342012-08-15 Peter Bergner <bergner@vnet.ibm.com>
335
336 * ppc-opc.c <xnop, yield, mdoio, mdoom>: New extended mnemonics.
337
fc8c4fd1
MR		 3382012-08-14 Maciej W. Rozycki <macro@codesourcery.com>
339
340 * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local
341 macros, use local variables for info struct member accesses,
342 update the type of the variable used to hold the instruction
343 word.
344 (print_insn_mips, print_mips16_insn_arg): Likewise.
345 (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use
346 local variables for info struct member accesses.
347 (print_insn_micromips): Add GET_OP_S local macro.
348 (_print_insn_mips): Update the type of the variable used to hold
349 the instruction word.
350
a06ea964 3512012-08-13 Ian Bolton <ian.bolton@arm.com>
e67ed0e8
AM		 352 Laurent Desnogues <laurent.desnogues@arm.com>
353 Jim MacArthur <jim.macarthur@arm.com>
354 Marcus Shawcroft <marcus.shawcroft@arm.com>
355 Nigel Stephens <nigel.stephens@arm.com>
356 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
357 Richard Earnshaw <rearnsha@arm.com>
358 Sofiane Naci <sofiane.naci@arm.com>
359 Tejas Belagod <tejas.belagod@arm.com>
360 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 361
362 * Makefile.am: Add AArch64.
363 * Makefile.in: Regenerate.
364 * aarch64-asm.c: New file.
365 * aarch64-asm.h: New file.
366 * aarch64-dis.c: New file.
367 * aarch64-dis.h: New file.
368 * aarch64-gen.c: New file.
369 * aarch64-opc.c: New file.
370 * aarch64-opc.h: New file.
371 * aarch64-tbl.h: New file.
372 * configure.in: Add AArch64.
373 * configure: Regenerate.
374 * disassemble.c: Add AArch64.
375 * aarch64-asm-2.c: New file (automatically generated).
376 * aarch64-dis-2.c: New file (automatically generated).
377 * aarch64-opc-2.c: New file (automatically generated).
378 * po/POTFILES.in: Regenerate.
379
35d0a169
MR		 3802012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
381
382 * micromips-opc.c (micromips_opcodes): Update comment.
383 * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor
384 instructions for IOCT as appropriate.
385 * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with
386 opcode_is_member.
387 * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with
388 the result of a check for the -Wno-missing-field-initializers
389 GCC option.
390 * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable.
391 (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to
392 compilation.
393 (mips16-opc.lo): Likewise.
394 (micromips-opc.lo): Likewise.
395 * aclocal.m4: Regenerate.
396 * configure: Regenerate.
397 * Makefile.in: Regenerate.
398
5c5acbbd
L		 3992012-08-11 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
400
401 PR gas/14423
402 * i386-gen.c (cpu_flag_init): Add CpuFMA in CPU_BDVER2_FLAGS.
403 * i386-init.h: Regenerated.
404
3c892704
NC		 4052012-08-09 Nick Clifton <nickc@redhat.com>
406
407 * po/vi.po: Updated Vietnamese translation.
408
d7189fa5
RM		 4092012-08-07 Roland McGrath <mcgrathr@google.com>
410
411 * i386-dis.c (reg_table): Fill out REG_0F0D table with
412 AMD-reserved cases as "prefetch".
413 (MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants.
414 (MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise.
415 (reg_table): Use those under REG_0F18.
416 (mod_table): Add those cases as "nop/reserved".
417
4c692bc7
JB		 4182012-08-07 Jan Beulich <jbeulich@suse.com>
419
420 * i386-opc.tbl: Remove "FIXME" comments from SVME instructions.
421
de882298
RM		 4222012-08-06 Roland McGrath <mcgrathr@google.com>
423
424 * i386-dis.c (print_insn): Print spaces between multiple excess
425 prefixes. Return actual number of excess prefixes consumed,
426 not always one.
427
428 * i386-dis.c (OP_REG): Ignore REX_B for segment register cases.
429
7bb15c6f
RM		 4302012-08-06 Roland McGrath <mcgrathr@google.com>
431 Victor Khimenko <khim@google.com>
432 H.J. Lu <hongjiu.lu@intel.com>
433
434 * i386-dis.c (OP_sI): In b_T_mode and v_mode, REX_W trumps DFLAG.
435 (putop): For 'T', 'U', and 'V', treat REX_W like DFLAG.
436 (intel_operand_size): For stack_v_mode, treat REX_W like DFLAG.
437 (OP_E_register): Likewise.
438 (OP_REG): For low 8 whole registers, treat REX_W like DFLAG.
439
3843081d
JBG		 4402012-08-02 Jan-Benedict Glaw <jbglaw@lug-owl.de>
441
442 * configure.in: Formatting.
443 * configure: Regenerate.
444
48891606
AM		 4452012-08-01 Alan Modra <amodra@gmail.com>
446
447 * h8300-dis.c: Fix printf arg warnings.
448 * i960-dis.c: Likewise.
449 * mips-dis.c: Likewise.
450 * pdp11-dis.c: Likewise.
451 * sh-dis.c: Likewise.
452 * v850-dis.c: Likewise.
453 * configure.in: Formatting.
454 * configure: Regenerate.
455 * rl78-decode.c: Regenerate.
456 * po/POTFILES.in: Regenerate.
457
03f66e8a 4582012-07-31 Chao-Ying Fu <fu@mips.com>
e67ed0e8
AM		 459 Catherine Moore <clm@codesourcery.com>
460 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 461
462 * micromips-opc.c (WR_a, RD_a, MOD_a): New macros.
463 (DSP_VOLA): Likewise.
464 (D32, D33): Likewise.
465 (micromips_opcodes): Add DSP ASE instructions.
48891606 466 * mips-dis.c (print_insn_micromips) <'2', '3'>: New cases.
03f66e8a
MR		 467 <'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise.
468
94948e64
JB		 4692012-07-31 Jan Beulich <jbeulich@suse.com>
470
471 * i386-opc.tbl (vmovntdqa): Move up into 256-bit integer AVX2
472 instruction group. Mark as requiring AVX2.
473 * i386-tbl.h: Re-generate.
474
a6dc81d2
NC		 4752012-07-30 Nick Clifton <nickc@redhat.com>
476
477 * po/opcodes.pot: Updated template.
478 * po/es.po: Updated Spanish translation.
479 * po/fi.po: Updated Finnish translation.
480
c4dd807e
MF		 4812012-07-27 Mike Frysinger <vapier@gentoo.org>
482
483 * configure.in (BFD_VERSION): Run bfd/configure --version and
484 parse the output of that.
485 * configure: Regenerate.
486
03edbe3b
JL		 4872012-07-25 James Lemke <jwlemke@codesourcery.com>
488
489 * ppc-opc.c (powerpc_opcodes): Add/remove PPCVLE for some 32-bit insns.
490
63d08c68
NC		 4912012-07-24 Stephan McCamant <smcc@cs.berkeley.edu>
492 Dr David Alan Gilbert <dave@treblig.org>
d908c8af
NC		 493
494 PR binutils/13135
495 * arm-dis.c: Add necessary casts for printing integer values.
496 Use %s when printing string values.
497 * hppa-dis.c: Likewise.
498 * m68k-dis.c: Likewise.
499 * microblaze-dis.c: Likewise.
500 * mips-dis.c: Likewise.
501 * sparc-dis.c: Likewise.
502
ff688e1f
L		 5032012-07-19 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
504
505 PR binutils/14355
506 * i386-dis.c (VEX_LEN_0FXOP_08_CC): New.
507 (VEX_LEN_0FXOP_08_CD): Likewise.
508 (VEX_LEN_0FXOP_08_CE): Likewise.
509 (VEX_LEN_0FXOP_08_CF): Likewise.
510 (VEX_LEN_0FXOP_08_EC): Likewise.
511 (VEX_LEN_0FXOP_08_ED): Likewise.
512 (VEX_LEN_0FXOP_08_EE): Likewise.
513 (VEX_LEN_0FXOP_08_EF): Likewise.
514 (xop_table): Fix entries for vpcomb, vpcomw, vpcomd, vpcomq,
515 vpcomub, vpcomuw, vpcomud, vpcomuq.
516 (vex_len_table): Add entries for VEX_LEN_0FXOP_08_CC,
517 VEX_LEN_0FXOP_08_CD, VEX_LEN_0FXOP_08_CE, VEX_LEN_0FXOP_08_CF,
518 VEX_LEN_0FXOP_08_EC, VEX_LEN_0FXOP_08_ED, VEX_LEN_0FXOP_08_EE,
519 VEX_LEN_0FXOP_08_EF.
520
e2e1fcde
L		 5212012-07-16 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
522
523 * i386-dis.c (PREFIX_0F38F6): New.
524 (prefix_table): Add adcx, adox instructions.
525 (three_byte_table): Use PREFIX_0F38F6.
526 (mod_table): Add rdseed instruction.
527 * i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW.
528 (cpu_flags): Likewise.
529 * i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW.
530 (i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw.
531 * i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend
532 prefetchw.
533 * i386-tbl.h: Regenerate.
534 * i386-init.h: Likewise.
535
8b99bf0b
TS		 5362012-07-05 Thomas Schwinge <thomas@codesourcery.com>
537
f4263ca2 538 * mips-dis.c: Remove gratuitous newline.
8b99bf0b 539
416cf80a
SK		 5402012-07-05 Sean Keys <skeys@ipdatasys.com>
541
542 * xgate-dis.c: Removed an IF statement that will
e67ed0e8
AM		 543 always be false due to overlapping operand masks.
544 * xgate-opc.c: Corrected 'com' opcode entry and
545 fixed spacing.
416cf80a 546
9fa0f14a
RM		 5472012-07-02 Roland McGrath <mcgrathr@google.com>
548
549 * i386-opc.tbl: Add RepPrefixOk to nop.
550 * i386-tbl.h: Regenerate.
551
4c6a93d3
NC		 5522012-06-28 Nick Clifton <nickc@redhat.com>
553
554 * po/vi.po: Updated Vietnamese translation.
555
29c048b6
RM		 5562012-06-22 Roland McGrath <mcgrathr@google.com>
557
fe13e45b
RM		 558 * i386-opc.tbl: Add RepPrefixOk to ret.
559 * i386-tbl.h: Regenerate.
560
29c048b6
RM		 561 * i386-opc.h (RepPrefixOk): New enum constant.
562 (i386_opcode_modifier): New bitfield 'repprefixok'.
563 * i386-gen.c (opcode_modifiers): Add RepPrefixOk.
564 * i386-opc.tbl: Add RepPrefixOk to bsf, bsr, and to all
565 instructions that have IsString.
566 * i386-tbl.h: Regenerate.
567
c7a8dbf9
AS		 5682012-06-11 Andreas Schwab <schwab@linux-m68k.org>
569
570 * ppc-opc.c (lvsl, lvebx, isellt, icbt, ldepx, lwepx, lvsr, lvehx)
571 (iselgt, lvewx, iseleq, isel, dcbst, dcbstep, dcbfl, dcbf, lbepx)
572 (lvx, dcbfep, dcbtstls, stvebx, dcbtstlse, stdepx, stwepx, dcbtls)
573 (stvehx, dcbtlse, stvewx, stbepx, icblc, stvx, dcbtstt, dcbtst)
574 (dcbtst, dcbtstep, dcbtt, dcbt, dcbt, lhepx, eciwx, dcbtep)
575 (dcread, lxvdsx, lvxl, dcblc, sthepx, ecowx, dcbi, dcread, icbtls)
576 (stvxl, lxsdx, lfdepx, stxsdx, stfdepx, dcba, dcbal, lxvw4x)
577 (tlbivax, lfdpx, lxvd2x, tlbsrx., stxvw4x, tlbsx, tlbsx., stfdpx)
578 (stfqx, stxvd2x, icbi, icbiep, icread, dcbzep): Change RA to RA0.
579
94caa966
AM		 5802012-05-19 Alan Modra <amodra@gmail.com>
581
582 * ppc-dis.c: Don't include elf32-ppc.h, do include elf/ppc.h.
583 (get_powerpc_dialect): Detect VLE sections from ELF sh_flags.
584
5eb3690e
AM		 5852012-05-18 Alan Modra <amodra@gmail.com>
586
71fe7bab
AM		 587 * ia64-opc.c: Remove #include "ansidecl.h".
588 * z8kgen.c: Include sysdep.h first.
589
5eb3690e
AM		 590 * arc-dis.c: Include sysdep.h first, remove some redundant includes.
591 * bfin-dis.c: Likewise.
592 * i860-dis.c: Likewise.
593 * ia64-dis.c: Likewise.
594 * ia64-gen.c: Likewise.
595 * m68hc11-dis.c: Likewise.
596 * mmix-dis.c: Likewise.
597 * msp430-dis.c: Likewise.
598 * or32-dis.c: Likewise.
599 * rl78-dis.c: Likewise.
600 * rx-dis.c: Likewise.
601 * tic4x-dis.c: Likewise.
602 * tilegx-opc.c: Likewise.
603 * tilepro-opc.c: Likewise.
604 * rx-decode.c: Regenerate.
605
a4ebc835
AM		 6062012-05-17 James Lemke <jwlemke@codesourcery.com>
607
608 * ppc-opc.c (powerpc_macros): Add entries for e_extlwi to e_clrlslwi.
609
98c76446
AM		 6102012-05-17 James Lemke <jwlemke@codesourcery.com>
611
612 * ppc-opc.c (extract_sprg): Use ALLOW8_SPRG to include VLE.
613
df7b86aa
NC		 6142012-05-17 Daniel Richard G. <skunk@iskunk.org>
615 Nick Clifton <nickc@redhat.com>
616
617 PR 14072
618 * configure.in: Add check that sysdep.h has been included before
619 any system header files.
620 * configure: Regenerate.
621 * config.in: Regenerate.
622 * sysdep.h: Generate an error if included before config.h.
623 * alpha-opc.c: Include sysdep.h before any other header file.
624 * alpha-dis.c: Likewise.
625 * avr-dis.c: Likewise.
626 * cgen-opc.c: Likewise.
627 * cr16-dis.c: Likewise.
628 * cris-dis.c: Likewise.
629 * crx-dis.c: Likewise.
630 * d10v-dis.c: Likewise.
631 * d10v-opc.c: Likewise.
632 * d30v-dis.c: Likewise.
633 * d30v-opc.c: Likewise.
634 * h8500-dis.c: Likewise.
635 * i370-dis.c: Likewise.
636 * i370-opc.c: Likewise.
637 * m10200-dis.c: Likewise.
638 * m10300-dis.c: Likewise.
639 * micromips-opc.c: Likewise.
640 * mips-opc.c: Likewise.
641 * mips61-opc.c: Likewise.
642 * moxie-dis.c: Likewise.
643 * or32-opc.c: Likewise.
644 * pj-dis.c: Likewise.
645 * ppc-dis.c: Likewise.
646 * ppc-opc.c: Likewise.
647 * s390-dis.c: Likewise.
648 * sh-dis.c: Likewise.
649 * sh64-dis.c: Likewise.
650 * sparc-dis.c: Likewise.
651 * sparc-opc.c: Likewise.
652 * spu-dis.c: Likewise.
653 * tic30-dis.c: Likewise.
654 * tic54x-dis.c: Likewise.
655 * tic80-dis.c: Likewise.
656 * tic80-opc.c: Likewise.
657 * tilegx-dis.c: Likewise.
658 * tilepro-dis.c: Likewise.
659 * v850-dis.c: Likewise.
660 * v850-opc.c: Likewise.
661 * vax-dis.c: Likewise.
662 * w65-dis.c: Likewise.
663 * xgate-dis.c: Likewise.
664 * xtensa-dis.c: Likewise.
665 * rl78-decode.opc: Likewise.
666 * rl78-decode.c: Regenerate.
667 * rx-decode.opc: Likewise.
668 * rx-decode.c: Regenerate.
669
e1dad58d
AM		 6702012-05-17 Alan Modra <amodra@gmail.com>
671
672 * ppc_dis.c: Don't include elf/ppc.h.
673
101af531
NC		 6742012-05-16 Meador Inge <meadori@codesourcery.com>
675
676 * arm-dis.c (arm_opcodes): Don't disassemble STMFD/LDMIA sp!, {reg}
677 to PUSH/POP {reg}.
678
6927f982
NC		 6792012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
680 Stephane Carrez <stcarrez@nerim.fr>
681
682 * configure.in: Add S12X and XGATE co-processor support to m68hc11
683 target.
684 * disassemble.c: Likewise.
685 * configure: Regenerate.
686 * m68hc11-dis.c: Make objdump output more consistent, use hex
687 instead of decimal and use 0x prefix for hex.
688 * m68hc11-opc.c: Add S12X and XGATE opcodes.
689
b9c361e0
JL		 6902012-05-14 James Lemke <jwlemke@codesourcery.com>
691
692 * ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
693 (PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines.
694 (vle_opcd_indices): New array.
695 (lookup_vle): New function.
696 (disassemble_init_powerpc): Revise for second (VLE) opcode table.
697 (print_insn_powerpc): Likewise.
698 * ppc-opc.c: Likewise.
699
7002012-05-14 Catherine Moore <clm@codesourcery.com>
701 Maciej W. Rozycki <macro@codesourcery.com>
702 Rhonda Wittels <rhonda@codesourcery.com>
703 Nathan Froyd <froydnj@codesourcery.com>
704
705 * ppc-opc.c (insert_arx, extract_arx): New functions.
706 (insert_ary, extract_ary): New functions.
707 (insert_li20, extract_li20): New functions.
708 (insert_rx, extract_rx): New functions.
709 (insert_ry, extract_ry): New functions.
710 (insert_sci8, extract_sci8): New functions.
711 (insert_sci8n, extract_sci8n): New functions.
712 (insert_sd4h, extract_sd4h): New functions.
713 (insert_sd4w, extract_sd4w): New functions.
714 (insert_vlesi, extract_vlesi): New functions.
715 (insert_vlensi, extract_vlensi): New functions.
716 (insert_vleui, extract_vleui): New functions.
717 (insert_vleil, extract_vleil): New functions.
718 (BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT.
719 (BI16, BI32, BO32, B8): New.
720 (B15, B24, CRD32, CRS): New.
721 (CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG.
722 (DB, IMM20, RD, Rx, ARX, RY, RZ): New.
723 (ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New.
724 (SH6_MASK): Use PPC_OPSHIFT_INV.
725 (SI8, UI5, OIMM5, UI7, BO16): New.
726 (VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New.
727 (XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV.
728 (ALLOW8_SPRG): New.
729 (insert_sprg, extract_sprg): Check ALLOW8_SPRG.
730 (OPVUP, OPVUP_MASK OPVUP): New
731 (BD8, BD8_MASK, BD8IO, BD8IO_MASK): New.
732 (EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New.
733 (BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New.
734 (BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New.
735 (IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New.
736 (IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New.
737 (SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New.
738 (SE_IM5, SE_IM5_MASK): New.
739 (SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New.
740 (EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New.
741 (BO32DNZ, BO32DZ): New.
742 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE.
743 (PPCVLE): New.
744 (powerpc_opcodes): Add new VLE instructions. Update existing
745 instruction to include PPCVLE if supported.
746 * ppc-dis.c (ppc_opts): Add vle entry.
747 (get_powerpc_dialect): New function.
748 (powerpc_init_dialect): VLE support.
749 (print_insn_big_powerpc): Call get_powerpc_dialect.
750 (print_insn_little_powerpc): Likewise.
751 (operand_value_powerpc): Handle negative shift counts.
752 (print_insn_powerpc): Handle 2-byte instruction lengths.
753
208a4923
NC		 7542012-05-11 Daniel Richard G. <skunk@iskunk.org>
755
756 PR binutils/14028
757 * configure.in: Invoke ACX_HEADER_STRING.
758 * configure: Regenerate.
759 * config.in: Regenerate.
760 * sysdep.h: If STRINGS_WITH_STRING is defined then include both
761 string.h and strings.h.
762
6750a3a7
NC		 7632012-05-11 Nick Clifton <nickc@redhat.com>
764
765 PR binutils/14006
766 * arm-dis.c (print_insn): Fix detection of instruction mode in
767 files containing multiple executable sections.
768
f6c1a2d5
NC		 7692012-05-03 Sean Keys <skeys@ipdatasys.com>
770
771 * Makefile.in, configure: regenerate
772 * disassemble.c (disassembler): Recognize ARCH_XGATE.
773 * xgate-dis.c (read_memory, print_insn, print_insn_xgate):
774 New functions.
775 * configure.in: Recognize xgate.
776 * xgate-dis.c, xgate-opc.c: New files for support of xgate
777 * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
778 and opcode generation for xgate.
779
78e98aab
DD		 7802012-04-30 DJ Delorie <dj@redhat.com>
781
782 * rx-decode.opc (MOV): Do not sign-extend immediates which are
783 already the maximum bit size.
784 * rx-decode.c: Regenerate.
785
ec668d69
DM		 7862012-04-27 David S. Miller <davem@davemloft.net>
787
2e52845b
DM		 788 * sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
789 * sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.
790
58004e23
DM		 791 * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
792 * sparc-dis.c (v9a_asr_reg_names): Add 'pause'.
793
698544e1
DM		 794 * sparc-opc.c (CBCOND): New define.
795 (CBCOND_XCC): Likewise.
796 (cbcond): New helper macro.
797 (sparc_opcodes): Add compare-and-branch instructions.
798
6cda1326
DM		 799 * sparc-dis.c (print_insn_sparc): Handle ')'.
800 * sparc-opc.c (sparc_opcodes): Add crypto instructions.
801
ec668d69
DM		 802 * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
803 into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
804
2615994e
DM		 8052012-04-12 David S. Miller <davem@davemloft.net>
806
807 * sparc-dis.c (X_DISP10): Define.
808 (print_insn_sparc): Handle '='.
809
5de10af0
MF		 8102012-04-01 Mike Frysinger <vapier@gentoo.org>
811
812 * bfin-dis.c (fmtconst): Replace decimal handling with a single
813 sprintf call and the '*' field width.
814
55a36193
MK		 8152012-03-23 Maxim Kuvyrkov <maxim@codesourcery.com>
816
817 * mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.
818
d6688282
AM		 8192012-03-16 Alan Modra <amodra@gmail.com>
820
821 * ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete.
822 (powerpc_opcd_indices): Bump array size.
823 (disassemble_init_powerpc): Set powerpc_opcd_indices entries
824 corresponding to unused opcodes to following entry.
825 (lookup_powerpc): New function, extracted and optimised from..
826 (print_insn_powerpc): ..here.
827
b240011a
AM		 8282012-03-15 Alan Modra <amodra@gmail.com>
829 James Lemke <jwlemke@codesourcery.com>
830
831 * disassemble.c (disassemble_init_for_target): Handle ppc init.
832 * ppc-dis.c (private): New var.
833 (powerpc_init_dialect): Don't return calloc failure, instead use
834 private.
835 (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
836 (powerpc_opcd_indices): New array.
837 (disassemble_init_powerpc): New function.
838 (print_insn_big_powerpc): Don't init dialect here.
839 (print_insn_little_powerpc): Likewise.
840 (print_insn_powerpc): Start search using powerpc_opcd_indices.
841
aea77599
AM		 8422012-03-10 Edmar Wienskoski <edmar@freescale.com>
843
844 * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
845 * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
846 (PPCVEC2, PPCTMR, E6500): New short names.
847 (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
848 mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
849 lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
850 lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
851 lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
852 optional operands on sync instruction for E6500 target.
853
5333187a
AK		 8542012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
855
856 * s390-opc.txt: Set instruction type of pku to SS_L2RDRD.
857
a597d2d3
AM		 8582012-02-27 Alan Modra <amodra@gmail.com>
859
860 * mt-dis.c: Regenerate.
861
3f26eb3a
AM		 8622012-02-27 Alan Modra <amodra@gmail.com>
863
864 * v850-opc.c (extract_v8): Rearrange to make it obvious this
865 is the inverse of corresponding insert function.
866 (extract_d22, extract_u9, extract_r4): Likewise.
867 (extract_d9): Correct sign extension.
868 (extract_d16_15): Don't assume "long" is 32 bits, and don't
869 rely on implementation defined behaviour for shift right of
870 signed types.
871 (extract_d16_16, extract_d17_16, extract_i9): Likewise.
872 (extract_d23): Likewise, and correct mask.
873
1f42f8b3
AM		 8742012-02-27 Alan Modra <amodra@gmail.com>
875
876 * crx-dis.c (print_arg): Mask constant to 32 bits.
877 * crx-opc.c (cst4_map): Use int array.
878
cdb06235
AM		 8792012-02-27 Alan Modra <amodra@gmail.com>
880
881 * arc-dis.c (BITS): Don't use shifts to mask off bits.
882 (FIELDD): Sign extend with xor,sub.
883
6f7be959
WL		 8842012-02-25 Walter Lee <walt@tilera.com>
885
886 * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
887 * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
888 TILEPRO_OPC_LW_TLS_SN.
889
82c2def5
L		 8902012-02-21 H.J. Lu <hongjiu.lu@intel.com>
891
892 * i386-opc.h (HLEPrefixNone): New.
893 (HLEPrefixLock): Likewise.
894 (HLEPrefixAny): Likewise.
895 (HLEPrefixRelease): Likewise.
896
42164a71
L		 8972012-02-08 H.J. Lu <hongjiu.lu@intel.com>
898
899 * i386-dis.c (HLE_Fixup1): New.
900 (HLE_Fixup2): Likewise.
901 (HLE_Fixup3): Likewise.
902 (Ebh1): Likewise.
903 (Evh1): Likewise.
904 (Ebh2): Likewise.
905 (Evh2): Likewise.
906 (Ebh3): Likewise.
907 (Evh3): Likewise.
908 (MOD_C6_REG_7): Likewise.
909 (MOD_C7_REG_7): Likewise.
910 (RM_C6_REG_7): Likewise.
911 (RM_C7_REG_7): Likewise.
912 (XACQUIRE_PREFIX): Likewise.
913 (XRELEASE_PREFIX): Likewise.
914 (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
915 cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
916 Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
917 (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
918 not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
919 MOD_C6_REG_7 and MOD_C7_REG_7.
920 (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
921 (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
922 xtest.
923 (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
924 (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
925
926 * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
927 CPU_RTM_FLAGS.
928 (cpu_flags): Add CpuHLE and CpuRTM.
929 (opcode_modifiers): Add HLEPrefixOk.
930
931 * i386-opc.h (CpuHLE): New.
932 (CpuRTM): Likewise.
933 (HLEPrefixOk): Likewise.
934 (i386_cpu_flags): Add cpuhle and cpurtm.
935 (i386_opcode_modifier): Add hleprefixok.
936
937 * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
938 add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
939 sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
940 operand. Add xacquire, xrelease, xabort, xbegin, xend and
941 xtest.
942 * i386-init.h: Regenerated.
943 * i386-tbl.h: Likewise.
944
21abe33a
DD		 9452012-01-24 DJ Delorie <dj@redhat.com>
946
947 * rl78-decode.opc (rl78_decode_opcode): Add NOT1.
948 * rl78-decode.c: Regenerate.
949
e20cc039
AM		 9502012-01-17 James Murray <jsm@jsm-net.demon.co.uk>
951
952 PR binutils/10173
953 * cr16-dis.c (print_arg): Test symtab_size not num_symbols.
954
e143d25c
AS		 9552012-01-17 Andreas Schwab <schwab@linux-m68k.org>
956
957 * m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx
958 register and move them after pmove with PSR/PCSR register.
959
8729a6f6
L		 9602012-01-13 H.J. Lu <hongjiu.lu@intel.com>
961
962 * i386-dis.c (mod_table): Add vmfunc.
963
964 * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
965 (cpu_flags): CpuVMFUNC.
966
967 * i386-opc.h (CpuVMFUNC): New.
968 (i386_cpu_flags): Add cpuvmfunc.
969
970 * i386-opc.tbl: Add vmfunc.
971 * i386-init.h: Regenerated.
972 * i386-tbl.h: Likewise.
5011093d 973
23e1d329 974For older changes see ChangeLog-2011
252b5132
RH		 975\f
976Local Variables:
2f6d2f85
NC		 977mode: change-log
978left-margin: 8
979fill-column: 74
252b5132
RH		 980version-control: never
981End:
GDB Binutils - Deliverables
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