Align natural-format register values to the same column
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
be3a8dca
IT
12018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2
3 * i386-dis.c (enum): Add pconfig.
4 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
5 (cpu_flags): Add CpuPCONFIG.
6 * i386-opc.h (enum): Add CpuPCONFIG.
7 (i386_cpu_flags): Add cpupconfig.
8 * i386-opc.tbl: Add PCONFIG instruction.
9 * i386-init.h: Regenerate.
10 * i386-tbl.h: Likewise.
11
3233d7d0
IT
122018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
13
14 * i386-dis.c (enum): Add PREFIX_0F09.
15 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
16 (cpu_flags): Add CpuWBNOINVD.
17 * i386-opc.h (enum): Add CpuWBNOINVD.
18 (i386_cpu_flags): Add cpuwbnoinvd.
19 * i386-opc.tbl: Add WBNOINVD instruction.
20 * i386-init.h: Regenerate.
21 * i386-tbl.h: Likewise.
22
e925c834
JW
232018-01-17 Jim Wilson <jimw@sifive.com>
24
25 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
26
d777820b
IT
272018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
28
29 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
30 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
31 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
32 (cpu_flags): Add CpuIBT, CpuSHSTK.
33 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
34 (i386_cpu_flags): Add cpuibt, cpushstk.
35 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
36 * i386-init.h: Regenerate.
37 * i386-tbl.h: Likewise.
38
f6efed01
NC
392018-01-16 Nick Clifton <nickc@redhat.com>
40
41 * po/pt_BR.po: Updated Brazilian Portugese translation.
42 * po/de.po: Updated German translation.
43
2721d702
JW
442018-01-15 Jim Wilson <jimw@sifive.com>
45
46 * riscv-opc.c (match_c_nop): New.
47 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
48
616dcb87
NC
492018-01-15 Nick Clifton <nickc@redhat.com>
50
51 * po/uk.po: Updated Ukranian translation.
52
3957a496
NC
532018-01-13 Nick Clifton <nickc@redhat.com>
54
55 * po/opcodes.pot: Regenerated.
56
769c7ea5
NC
572018-01-13 Nick Clifton <nickc@redhat.com>
58
59 * configure: Regenerate.
60
faf766e3
NC
612018-01-13 Nick Clifton <nickc@redhat.com>
62
63 2.30 branch created.
64
888a89da
IT
652018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
66
67 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
68 * i386-tbl.h: Regenerate.
69
cbda583a
JB
702018-01-10 Jan Beulich <jbeulich@suse.com>
71
72 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
73 * i386-tbl.h: Re-generate.
74
c9e92278
JB
752018-01-10 Jan Beulich <jbeulich@suse.com>
76
77 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
78 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
79 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
80 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
81 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
82 Disp8MemShift of AVX512VL forms.
83 * i386-tbl.h: Re-generate.
84
35fd2b2b
JW
852018-01-09 Jim Wilson <jimw@sifive.com>
86
87 * riscv-dis.c (maybe_print_address): If base_reg is zero,
88 then the hi_addr value is zero.
89
91d8b670
JG
902018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
91
92 * arm-dis.c (arm_opcodes): Add csdb.
93 (thumb32_opcodes): Add csdb.
94
be2e7d95
JG
952018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
96
97 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
98 * aarch64-asm-2.c: Regenerate.
99 * aarch64-dis-2.c: Regenerate.
100 * aarch64-opc-2.c: Regenerate.
101
704a705d
L
1022018-01-08 H.J. Lu <hongjiu.lu@intel.com>
103
104 PR gas/22681
105 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
106 Remove AVX512 vmovd with 64-bit operands.
107 * i386-tbl.h: Regenerated.
108
35eeb78f
JW
1092018-01-05 Jim Wilson <jimw@sifive.com>
110
111 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
112 jalr.
113
219d1afa
AM
1142018-01-03 Alan Modra <amodra@gmail.com>
115
116 Update year range in copyright notice of all files.
117
1508bbf5
JB
1182018-01-02 Jan Beulich <jbeulich@suse.com>
119
120 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
121 and OPERAND_TYPE_REGZMM entries.
122
1e563868 123For older changes see ChangeLog-2017
3499769a 124\f
1e563868 125Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM
126
127Copying and distribution of this file, with or without modification,
128are permitted in any medium without royalty provided the copyright
129notice and this notice are preserved.
130
131Local Variables:
132mode: change-log
133left-margin: 8
134fill-column: 74
135version-control: never
136End:
This page took 0.131847 seconds and 4 git commands to generate.