[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/20154
	* i386-gen.c (main): Fail if CpuMax is incorrect.
	* i386-opc.h (CpuMax): Set to CpuIntel64.
	* i386-tbl.h: Regenerated.

2016-05-27  Nick Clifton  <nickc@redhat.com>

	PR target/20150
	* msp430-dis.c (msp430dis_read_two_bytes): New function.
	(msp430dis_opcode_unsigned): New function.
	(msp430dis_opcode_signed): New function.
	(msp430_singleoperand): Use the new opcode reading functions.
	Only disassenmble bytes if they were successfully read.
	(msp430_doubleoperand): Likewise.
	(msp430_branchinstr): Likewise.
	(msp430x_callx_instr): Likewise.
	(print_insn_msp430): Check that it is safe to read bytes before
	attempting disassembly.  Use the new opcode reading functions.

2016-05-26  Peter Bergner <bergner@vnet.ibm.com>

	* ppc-opc.c (CY): New define.  Document it.
	(powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.

2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
	CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
	and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
	CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
	CPU_ANY_AVX_FLAGS.
	* i386-init.h: Regenerated.

2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/20141
	* i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
	CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
	* i386-init.h: Regenerated.

2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
	CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
	* i386-init.h: Regenerated.

2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
	information.
	(print_insn_arc): Set insn_type information.
	* arc-opc.c (C_CC): Add F_CLASS_COND.
	* arc-tbl.h (bbit0, bbit1): Update subclass to COND.
	(beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
	(ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
	(breq, breq_s, brge, brhs, brlo, brlt): Likewise.
	(brne, brne_s, jeq_s, jne_s): Likewise.

2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-tbl.h (neg): New instruction variant.

2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>

	* arc-dis.c (find_format, find_format, get_auxreg)
	(print_insn_arc): Changed.
	* arc-ext.h (INSERT_XOP): Likewise.

2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* tic54x-dis.c (sprint_mmr): Adjust.
	* tic54x-opc.c: Likewise.

2016-05-19  Alan Modra  <amodra@gmail.com>

	* ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.

2016-05-19  Alan Modra  <amodra@gmail.com>

	* ppc-opc.c: Formatting.
	(NSISIGNOPT): Define.
	(powerpc_opcodes <subis>): Use NSISIGNOPT.

2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>

	* mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
	replacing references to `micromips_ase' throughout.
	(_print_insn_mips): Don't use file-level microMIPS annotation to
	determine the disassembly mode with the symbol table.

2016-05-13  Peter Bergner <bergner@vnet.ibm.com>

	* ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.

2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>

	* mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
	mips64r6.
	* mips-opc.c (D34): New macro.
	(mips_builtin_opcodes): Define bposge32c for DSPr3.

2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>

	* i386-dis.c (prefix_table): Add RDPID instruction.
	* i386-gen.c (cpu_flag_init): Add RDPID flag.
	(cpu_flags): Add RDPID bitfield.
	* i386-opc.h (enum): Add RDPID element.
	(i386_cpu_flags): Add RDPID field.
	* i386-opc.tbl: Add RDPID instruction.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Regenerate.

2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
	branch type of a symbol.
	(print_insn): Likewise.

2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
	Mainline Security Extensions instructions.
	(thumb_opcodes): Add entries for narrow ARMv8-M Security
	Extensions instructions.
	(thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
	instructions.
	(psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
	special registers.

2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.

2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
	(arcExtMap_genOpcode): Likewise.
	* arc-opc.c (arg_32bit_rc): Define new variable.
	(arg_32bit_u6): Likewise.
	(arg_32bit_limm): Likewise.

2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* aarch64-gen.c (VERIFIER): Define.
	* aarch64-opc.c (VERIFIER): Define.
	(verify_ldpsw): Use static linkage.
	* aarch64-opc.h (verify_ldpsw): Remove.
	* aarch64-tbl.h: Use VERIFIER for verifiers.

2016-04-28  Nick Clifton  <nickc@redhat.com>

	PR target/19722
	* aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
	* aarch64-opc.c (verify_ldpsw): New function.
	* aarch64-opc.h (verify_ldpsw): New prototype.
	* aarch64-tbl.h: Add initialiser for verifier field.
	(LDPSW): Set verifier to verify_ldpsw.

2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutils/19983
	PR binutils/19984
	* i386-dis.c (print_insn): Return -1 if size of bfd_vma is
	smaller than address size.

2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* alpha-dis.c: Regenerate.
	* crx-dis.c: Likewise.
	* disassemble.c: Likewise.
	* epiphany-opc.c: Likewise.
	* fr30-opc.c: Likewise.
	* frv-opc.c: Likewise.
	* ip2k-opc.c: Likewise.
	* iq2000-opc.c: Likewise.
	* lm32-opc.c: Likewise.
	* lm32-opinst.c: Likewise.
	* m32c-opc.c: Likewise.
	* m32r-opc.c: Likewise.
	* m32r-opinst.c: Likewise.
	* mep-opc.c: Likewise.
	* mt-opc.c: Likewise.
	* or1k-opc.c: Likewise.
	* or1k-opinst.c: Likewise.
	* tic80-opc.c: Likewise.
	* xc16x-opc.c: Likewise.
	* xstormy16-opc.c: Likewise.

2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>

	* arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
	fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
	calcsd, and calcxd instructions.
	* arc-opc.c (insert_nps_bitop_size): Delete.
	(extract_nps_bitop_size): Delete.
	(MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
	(extract_nps_qcmp_m3): Define.
	(extract_nps_qcmp_m2): Define.
	(extract_nps_qcmp_m1): Define.
	(arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
	(arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
	(arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
	NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
	NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
	NPS_QCMP_M3.

2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>

	* arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.

2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	* Makefile.in: Regenerated with automake 1.11.6.
	* aclocal.m4: Likewise.

2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>

	* arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
	instructions.
	* arc-opc.c (insert_nps_cmem_uimm16): New function.
	(extract_nps_cmem_uimm16): New function.
	(arc_operands): Add NPS_XLDST_UIMM16 operand.

2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>

	* arc-dis.c (arc_insn_length): New function.
	(print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
	(find_format): Change insnLen parameter to unsigned.

2016-04-13  Nick Clifton  <nickc@redhat.com>

	PR target/19937
	* v850-opc.c (v850_opcodes): Correct masks for long versions of
	the LD.B and LD.BU instructions.

2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-dis.c (find_format): Check for extension flags.
	(print_flags): New function.
	(print_insn_arc): Update for .extCondCode, .extCoreRegister and
	.extAuxRegister.
	* arc-ext.c (arcExtMap_coreRegName): Use
	LAST_EXTENSION_CORE_REGISTER.
	(arcExtMap_coreReadWrite): Likewise.
	(dump_ARC_extmap): Update printing.
	* arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
	(arc_aux_regs): Add cpu field.
	* arc-regs.h: Add cpu field, lower case name aux registers.

2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-tbl.h: Add rtsc, sleep with no arguments.

2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
	Initialize.
	(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
	(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
	(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
	(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
	(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
	(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
	(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
	(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
	(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
	(arc_opcode arc_opcodes): Null terminate the array.
	(arc_num_opcodes): Remove.
	* arc-ext.h (INSERT_XOP): Define.
	(extInstruction_t): Likewise.
	(arcExtMap_instName): Delete.
	(arcExtMap_insn): New function.
	(arcExtMap_genOpcode): Likewise.
	* arc-ext.c (ExtInstruction): Remove.
	(create_map): Zero initialize instruction fields.
	(arcExtMap_instName): Remove.
	(arcExtMap_insn): New function.
	(dump_ARC_extmap): More info while debuging.
	(arcExtMap_genOpcode): New function.
	* arc-dis.c (find_format): New function.
	(print_insn_arc): Use find_format.
	(arc_get_disassembler): Enable dump_ARC_extmap only when
	debugging.

2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>

	* mips-dis.c (print_mips16_insn_arg): Mask unused extended
	instruction bits out.

2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>

	* arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
	* arc-opc.c (arc_flag_operands): Add new flags.
	(arc_flag_classes): Add new classes.

2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>

	* arc-opc.c (arc_opcodes): Extend comment to discus table layout.

2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>

	* arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
	encode1, rflt, crc16, and crc32 instructions.
	* arc-opc.c (arc_flag_operands): Add F_NPS_R.
	(arc_flag_classes): Add C_NPS_R.
	(insert_nps_bitop_size_2b): New function.
	(extract_nps_bitop_size_2b): Likewise.
	(insert_nps_bitop_uimm8): Likewise.
	(extract_nps_bitop_uimm8): Likewise.
	(arc_operands): Add new operand entries.

2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-regs.h: Add a new subclass field.  Add double assist
	accumulator register values.
	* arc-tbl.h: Use DPA subclass to mark the double assist
	instructions.  Use DPX/SPX subclas to mark the FPX instructions.
	* arc-opc.c (RSP): Define instead of SP.
	(arc_aux_regs): Add the subclass field.

2016-04-05  Jiong Wang  <jiong.wang@arm.com>

	* arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).

2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>

	* arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
	NPS_R_SRC1.

2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>

	* arc-nps400-tbl.h: Add a header comment, and fix some whitespace
	issues.  No functional changes.

2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
	(AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
	(RTT): Remove duplicate.
	(LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
	(PCT_CONFIG*): Remove.
	(D1L, D1H, D2H, D2L): Define.

2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.

2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-tbl.h (invld07): Remove.
	* arc-ext-tbl.h: New file.
	* arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
	* arc-opc.c (arc_opcodes): Add ext-tbl include.

2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>

	Fix -Wstack-usage warnings.
	* aarch64-dis.c (print_operands): Substitute size.
	* aarch64-opc.c (print_register_offset_address): Substitute tblen.

2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
	to get a proper diagnostic when an invalid ASR register is used.

2016-03-22  Nick Clifton  <nickc@redhat.com>

	* configure: Regenerate.

2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>

	* arc-nps400-tbl.h: New file.
	* arc-opc.c: Add top level comment.
	(insert_nps_3bit_dst): New function.
	(extract_nps_3bit_dst): New function.
	(insert_nps_3bit_src2): New function.
	(extract_nps_3bit_src2): New function.
	(insert_nps_bitop_size): New function.
	(extract_nps_bitop_size): New function.
	(arc_flag_operands): Add nps400 entries.
	(arc_flag_classes): Add nps400 entries.
	(arc_operands): Add nps400 entries.
	(arc_opcodes): Add nps400 include.

2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>

	* arc-opc.c (arc_flag_classes): Convert all flag classes to use
	the new class enum values.

2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>

	* arc-dis.c (print_insn_arc): Handle nps400.

2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>

	* arc-opc.c (BASE): Delete.

2016-03-18  Nick Clifton  <nickc@redhat.com>

	PR target/19721
	* aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
	of MOV insn that aliases an ORR insn.

2016-03-16  Jiong Wang  <jiong.wang@arm.com>

	* arm-dis.c (neon_opcodes): Support new FP16 instructions.

2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* mcore-opc.h: Add const qualifiers.
	* microblaze-opc.h (struct op_code_struct): Likewise.
	* sh-opc.h: Likewise.
	* tic4x-dis.c (tic4x_print_indirect): Likewise.
	(tic4x_print_op): Likewise.

2016-03-02  Alan Modra  <amodra@gmail.com>

	* or1k-desc.h: Regenerate.
	* fr30-ibld.c: Regenerate.
	* rl78-decode.c: Regenerate.

2016-03-01  Nick Clifton  <nickc@redhat.com>

	PR target/19747
	* rl78-dis.c (print_insn_rl78_common): Fix typo.

2016-02-24  Renlin Li  <renlin.li@arm.com>

	* arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
	(print_insn_coprocessor): Support fp16 instructions.

2016-02-24  Renlin Li  <renlin.li@arm.com>

	* arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
	vminnm, vrint(mpna).

2016-02-24  Renlin Li  <renlin.li@arm.com>

	* arm-dis.c (print_insn_coprocessor): Check co-processor number for
	cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.

2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (print_insn): Parenthesize expression to prevent
	truncated addresses.
	(OP_J): Likewise.

2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
	    Janek van Oirschot  <jvanoirs@synopsys.com>

	* arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
	variable.

2016-02-04  Nick Clifton  <nickc@redhat.com>

	PR target/19561
	* msp430-dis.c (print_insn_msp430): Add a special case for
	decoding an RRC instruction with the ZC bit set in the extension
	word.

2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>

	* cgen-ibld.in (insert_normal): Rework calculation of shift.
	* epiphany-ibld.c: Regenerate.
	* fr30-ibld.c: Regenerate.
	* frv-ibld.c: Regenerate.
	* ip2k-ibld.c: Regenerate.
	* iq2000-ibld.c: Regenerate.
	* lm32-ibld.c: Regenerate.
	* m32c-ibld.c: Regenerate.
	* m32r-ibld.c: Regenerate.
	* mep-ibld.c: Regenerate.
	* mt-ibld.c: Regenerate.
	* or1k-ibld.c: Regenerate.
	* xc16x-ibld.c: Regenerate.
	* xstormy16-ibld.c: Regenerate.

2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>

	* epiphany-dis.c: Regenerated from latest cpu files.

2016-02-01  Michael McConville  <mmcco@mykolab.com>

	* cgen-dis.c (count_decodable_bits): Use unsigned value for mask
	test bit.

2016-01-25  Renlin Li  <renlin.li@arm.com>

	* arm-dis.c (mapping_symbol_for_insn): New function.
	(find_ifthen_state): Call mapping_symbol_for_insn().

2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (operand_general_constraint_met_p): Check validity
	of MSR UAO immediate operand.

2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>

	* mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
	instruction support.

2016-01-17  Alan Modra  <amodra@gmail.com>

	* configure: Regenerate.

2016-01-14  Nick Clifton  <nickc@redhat.com>

	* rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
	instructions that can support stack pointer operations.
	* rl78-decode.c: Regenerate.
	* rl78-dis.c: Fix display of stack pointer in MOVW based
	instructions.

2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
	testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
	erxtatus_el1 and erxaddr_el1.

2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>

	* arm-dis.c (arm_opcodes): Add "esb".
	(thumb_opcodes): Likewise.

2016-01-11  Peter Bergner <bergner@vnet.ibm.com>

	* ppc-opc.c <xscmpnedp>: Delete.
	<xvcmpnedp>: Likewise.
	<xvcmpnedp.>: Likewise.
	<xvcmpnesp>: Likewise.
	<xvcmpnesp.>: Likewise.

2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>

	PR gas/13050
	* m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
	addition to ISA_A.

2016-01-01  Alan Modra  <amodra@gmail.com>

	Update year range in copyright notice of all files.

For older changes see ChangeLog-2015
\f
Copyright (C) 2016 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
e89c5eaa L	1	2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
	2
	3	PR gas/20154
	4	* i386-gen.c (main): Fail if CpuMax is incorrect.
	5	* i386-opc.h (CpuMax): Set to CpuIntel64.
	6	* i386-tbl.h: Regenerated.
	7
77d66e7b NC	8	2016-05-27 Nick Clifton <nickc@redhat.com>
	9
	10	PR target/20150
	11	* msp430-dis.c (msp430dis_read_two_bytes): New function.
	12	(msp430dis_opcode_unsigned): New function.
	13	(msp430dis_opcode_signed): New function.
	14	(msp430_singleoperand): Use the new opcode reading functions.
	15	Only disassenmble bytes if they were successfully read.
	16	(msp430_doubleoperand): Likewise.
	17	(msp430_branchinstr): Likewise.
	18	(msp430x_callx_instr): Likewise.
	19	(print_insn_msp430): Check that it is safe to read bytes before
	20	attempting disassembly. Use the new opcode reading functions.
	21
19dfcc89 PB	22	2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
	23
	24	* ppc-opc.c (CY): New define. Document it.
	25	(powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
	26
f3ad7637 L	27	2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
	28
	29	* i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
	30	CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
	31	and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
	32	CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
	33	CPU_ANY_AVX_FLAGS.
	34	* i386-init.h: Regenerated.
	35
f1360d58 L	36	2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
	37
	38	PR gas/20141
	39	* i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
	40	CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
	41	* i386-init.h: Regenerated.
	42
293f5f65 L	43	2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
	44
	45	* i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
	46	CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
	47	* i386-init.h: Regenerated.
	48
d9eca1df CZ	49	2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
	50
	51	* arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
	52	information.
	53	(print_insn_arc): Set insn_type information.
	54	* arc-opc.c (C_CC): Add F_CLASS_COND.
	55	* arc-tbl.h (bbit0, bbit1): Update subclass to COND.
	56	(beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
	57	(ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
	58	(breq, breq_s, brge, brhs, brlo, brlt): Likewise.
	59	(brne, brne_s, jeq_s, jne_s): Likewise.
	60
87789e08 CZ	61	2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
	62
	63	* arc-tbl.h (neg): New instruction variant.
	64
c810e0b8 CZ	65	2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
	66
	67	* arc-dis.c (find_format, find_format, get_auxreg)
	68	(print_insn_arc): Changed.
	69	* arc-ext.h (INSERT_XOP): Likewise.
	70
3d207518 TS	71	2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
	72
	73	* tic54x-dis.c (sprint_mmr): Adjust.
	74	* tic54x-opc.c: Likewise.
	75
514e58b7 AM	76	2016-05-19 Alan Modra <amodra@gmail.com>
	77
	78	* ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
	79
e43de63c AM	80	2016-05-19 Alan Modra <amodra@gmail.com>
	81
	82	* ppc-opc.c: Formatting.
	83	(NSISIGNOPT): Define.
	84	(powerpc_opcodes <subis>): Use NSISIGNOPT.
	85
1401d2fe MR	86	2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
	87
	88	* mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
	89	replacing references to `micromips_ase' throughout.
	90	(_print_insn_mips): Don't use file-level microMIPS annotation to
	91	determine the disassembly mode with the symbol table.
	92
1178da44 PB	93	2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
	94
	95	* ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
	96
8f4f9071 MF	97	2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
	98
	99	* mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
	100	mips64r6.
	101	* mips-opc.c (D34): New macro.
	102	(mips_builtin_opcodes): Define bposge32c for DSPr3.
	103
8bc52696 AF	104	2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
	105
	106	* i386-dis.c (prefix_table): Add RDPID instruction.
	107	* i386-gen.c (cpu_flag_init): Add RDPID flag.
	108	(cpu_flags): Add RDPID bitfield.
	109	* i386-opc.h (enum): Add RDPID element.
	110	(i386_cpu_flags): Add RDPID field.
	111	* i386-opc.tbl: Add RDPID instruction.
	112	* i386-init.h: Regenerate.
	113	* i386-tbl.h: Regenerate.
	114
39d911fc TP	115	2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
	116
	117	* arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
	118	branch type of a symbol.
	119	(print_insn): Likewise.
	120
16a1fa25 TP	121	2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
	122
	123	* arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
	124	Mainline Security Extensions instructions.
	125	(thumb_opcodes): Add entries for narrow ARMv8-M Security
	126	Extensions instructions.
	127	(thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
	128	instructions.
	129	(psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
	130	special registers.
	131
d751b79e JM	132	2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
	133
	134	* sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
	135
945e0f82 CZ	136	2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
	137
	138	* arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
	139	(arcExtMap_genOpcode): Likewise.
	140	* arc-opc.c (arg_32bit_rc): Define new variable.
	141	(arg_32bit_u6): Likewise.
	142	(arg_32bit_limm): Likewise.
	143
20f55f38 SN	144	2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
	145
	146	* aarch64-gen.c (VERIFIER): Define.
	147	* aarch64-opc.c (VERIFIER): Define.
	148	(verify_ldpsw): Use static linkage.
	149	* aarch64-opc.h (verify_ldpsw): Remove.
	150	* aarch64-tbl.h: Use VERIFIER for verifiers.
	151
4bd13cde NC	152	2016-04-28 Nick Clifton <nickc@redhat.com>
	153
	154	PR target/19722
	155	* aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
	156	* aarch64-opc.c (verify_ldpsw): New function.
	157	* aarch64-opc.h (verify_ldpsw): New prototype.
	158	* aarch64-tbl.h: Add initialiser for verifier field.
	159	(LDPSW): Set verifier to verify_ldpsw.
	160
c0f92bf9 L	161	2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
	162
	163	PR binutils/19983
	164	PR binutils/19984
	165	* i386-dis.c (print_insn): Return -1 if size of bfd_vma is
	166	smaller than address size.
	167
e6c7cdec TS	168	2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
	169
	170	* alpha-dis.c: Regenerate.
	171	* crx-dis.c: Likewise.
	172	* disassemble.c: Likewise.
	173	* epiphany-opc.c: Likewise.
	174	* fr30-opc.c: Likewise.
	175	* frv-opc.c: Likewise.
	176	* ip2k-opc.c: Likewise.
	177	* iq2000-opc.c: Likewise.
	178	* lm32-opc.c: Likewise.
	179	* lm32-opinst.c: Likewise.
	180	* m32c-opc.c: Likewise.
	181	* m32r-opc.c: Likewise.
	182	* m32r-opinst.c: Likewise.
	183	* mep-opc.c: Likewise.
	184	* mt-opc.c: Likewise.
	185	* or1k-opc.c: Likewise.
	186	* or1k-opinst.c: Likewise.
	187	* tic80-opc.c: Likewise.
	188	* xc16x-opc.c: Likewise.
	189	* xstormy16-opc.c: Likewise.
	190
537aefaf AB	191	2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
	192
	193	* arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
	194	fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
	195	calcsd, and calcxd instructions.
	196	* arc-opc.c (insert_nps_bitop_size): Delete.
	197	(extract_nps_bitop_size): Delete.
	198	(MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
	199	(extract_nps_qcmp_m3): Define.
	200	(extract_nps_qcmp_m2): Define.
	201	(extract_nps_qcmp_m1): Define.
	202	(arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
	203	(arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
	204	(arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
	205	NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
	206	NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
	207	NPS_QCMP_M3.
	208
c8f785f2 AB	209	2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
	210
	211	* arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
	212
6fd8e7c2 L	213	2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
	214
	215	* Makefile.in: Regenerated with automake 1.11.6.
	216	* aclocal.m4: Likewise.
	217
4b0c052e AB	218	2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
	219
	220	* arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
	221	instructions.
	222	* arc-opc.c (insert_nps_cmem_uimm16): New function.
	223	(extract_nps_cmem_uimm16): New function.
	224	(arc_operands): Add NPS_XLDST_UIMM16 operand.
	225
cb040366 AB	226	2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
	227
	228	* arc-dis.c (arc_insn_length): New function.
	229	(print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
	230	(find_format): Change insnLen parameter to unsigned.
	231
accc0180 NC	232	2016-04-13 Nick Clifton <nickc@redhat.com>
	233
	234	PR target/19937
	235	* v850-opc.c (v850_opcodes): Correct masks for long versions of
	236	the LD.B and LD.BU instructions.
	237
f36e33da CZ	238	2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
	239
	240	* arc-dis.c (find_format): Check for extension flags.
	241	(print_flags): New function.
	242	(print_insn_arc): Update for .extCondCode, .extCoreRegister and
	243	.extAuxRegister.
	244	* arc-ext.c (arcExtMap_coreRegName): Use
	245	LAST_EXTENSION_CORE_REGISTER.
	246	(arcExtMap_coreReadWrite): Likewise.
	247	(dump_ARC_extmap): Update printing.
	248	* arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
	249	(arc_aux_regs): Add cpu field.
	250	* arc-regs.h: Add cpu field, lower case name aux registers.
	251
1c2e355e CZ	252	2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
	253
	254	* arc-tbl.h: Add rtsc, sleep with no arguments.
	255
b99747ae CZ	256	2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
	257
	258	* arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
	259	Initialize.
	260	(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
	261	(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
	262	(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
	263	(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
	264	(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
	265	(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
	266	(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
	267	(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
	268	(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
	269	(arc_opcode arc_opcodes): Null terminate the array.
	270	(arc_num_opcodes): Remove.
	271	* arc-ext.h (INSERT_XOP): Define.
	272	(extInstruction_t): Likewise.
	273	(arcExtMap_instName): Delete.
	274	(arcExtMap_insn): New function.
	275	(arcExtMap_genOpcode): Likewise.
	276	* arc-ext.c (ExtInstruction): Remove.
	277	(create_map): Zero initialize instruction fields.
	278	(arcExtMap_instName): Remove.
	279	(arcExtMap_insn): New function.
	280	(dump_ARC_extmap): More info while debuging.
	281	(arcExtMap_genOpcode): New function.
	282	* arc-dis.c (find_format): New function.
	283	(print_insn_arc): Use find_format.
	284	(arc_get_disassembler): Enable dump_ARC_extmap only when
	285	debugging.
	286
92708cec MR	287	2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
	288
	289	* mips-dis.c (print_mips16_insn_arg): Mask unused extended
	290	instruction bits out.
	291
a42a4f84 AB	292	2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
	293
	294	* arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
	295	* arc-opc.c (arc_flag_operands): Add new flags.
	296	(arc_flag_classes): Add new classes.
	297
1328504b AB	298	2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
	299
	300	* arc-opc.c (arc_opcodes): Extend comment to discus table layout.
	301
820f03ff AB	302	2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
	303
	304	* arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
	305	encode1, rflt, crc16, and crc32 instructions.
	306	* arc-opc.c (arc_flag_operands): Add F_NPS_R.
	307	(arc_flag_classes): Add C_NPS_R.
	308	(insert_nps_bitop_size_2b): New function.
	309	(extract_nps_bitop_size_2b): Likewise.
	310	(insert_nps_bitop_uimm8): Likewise.
	311	(extract_nps_bitop_uimm8): Likewise.
	312	(arc_operands): Add new operand entries.
	313
8ddf6b2a CZ	314	2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
8ddf6b2a CZ	315
b99747ae CZ	316	* arc-regs.h: Add a new subclass field. Add double assist
	317	accumulator register values.
	318	* arc-tbl.h: Use DPA subclass to mark the double assist
	319	instructions. Use DPX/SPX subclas to mark the FPX instructions.
	320	* arc-opc.c (RSP): Define instead of SP.
	321	(arc_aux_regs): Add the subclass field.
8ddf6b2a	322
589a7d88 JW	323	2016-04-05 Jiong Wang <jiong.wang@arm.com>
	324
	325	* arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
	326
0a191de9	327	2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7 AB	328
	329	* arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
	330	NPS_R_SRC1.
	331
0a106562 AB	332	2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
	333
	334	* arc-nps400-tbl.h: Add a header comment, and fix some whitespace
	335	issues. No functional changes.
	336
bd05ac5f CZ	337	2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
bd05ac5f CZ	338
b99747ae CZ	339	* arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
	340	(AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
	341	(RTT): Remove duplicate.
	342	(LCDINSTR, LCDDATA, LCDSTAT, CC_, PCT_COUNT, PCT_SNAP*)
	343	(PCT_CONFIG*): Remove.
	344	(D1L, D1H, D2H, D2L): Define.
bd05ac5f	345
9885948f CZ	346	2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
9885948f CZ	347
b99747ae	348	* arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f	349
f2dd8838 CZ	350	2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
f2dd8838 CZ	351
b99747ae CZ	352	* arc-tbl.h (invld07): Remove.
	353	* arc-ext-tbl.h: New file.
	354	* arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
	355	* arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838	356
0d2f91fe JK	357	2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
	358
	359	Fix -Wstack-usage warnings.
	360	* aarch64-dis.c (print_operands): Substitute size.
	361	* aarch64-opc.c (print_register_offset_address): Substitute tblen.
	362
a6b71f42 JM	363	2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
	364
	365	* sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
	366	to get a proper diagnostic when an invalid ASR register is used.
	367
9780e045 NC	368	2016-03-22 Nick Clifton <nickc@redhat.com>
	369
	370	* configure: Regenerate.
	371
e23e8ebe AB	372	2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
	373
	374	* arc-nps400-tbl.h: New file.
	375	* arc-opc.c: Add top level comment.
	376	(insert_nps_3bit_dst): New function.
	377	(extract_nps_3bit_dst): New function.
	378	(insert_nps_3bit_src2): New function.
	379	(extract_nps_3bit_src2): New function.
	380	(insert_nps_bitop_size): New function.
	381	(extract_nps_bitop_size): New function.
	382	(arc_flag_operands): Add nps400 entries.
	383	(arc_flag_classes): Add nps400 entries.
	384	(arc_operands): Add nps400 entries.
	385	(arc_opcodes): Add nps400 include.
	386
1ae8ab47 AB	387	2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
	388
	389	* arc-opc.c (arc_flag_classes): Convert all flag classes to use
	390	the new class enum values.
	391
8699fc3e AB	392	2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
	393
	394	* arc-dis.c (print_insn_arc): Handle nps400.
	395
24740d83 AB	396	2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
	397
	398	* arc-opc.c (BASE): Delete.
	399
8678914f NC	400	2016-03-18 Nick Clifton <nickc@redhat.com>
	401
	402	PR target/19721
	403	* aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
	404	of MOV insn that aliases an ORR insn.
	405
cc933301 JW	406	2016-03-16 Jiong Wang <jiong.wang@arm.com>
	407
	408	* arm-dis.c (neon_opcodes): Support new FP16 instructions.
	409
f86f5863 TS	410	2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
	411
	412	* mcore-opc.h: Add const qualifiers.
	413	* microblaze-opc.h (struct op_code_struct): Likewise.
	414	* sh-opc.h: Likewise.
	415	* tic4x-dis.c (tic4x_print_indirect): Likewise.
	416	(tic4x_print_op): Likewise.
	417
62de1c63 AM	418	2016-03-02 Alan Modra <amodra@gmail.com>
62de1c63 AM	419
d11698cd	420	* or1k-desc.h: Regenerate.
62de1c63	421	* fr30-ibld.c: Regenerate.
c697cf0b	422	* rl78-decode.c: Regenerate.
62de1c63	423
020efce5 NC	424	2016-03-01 Nick Clifton <nickc@redhat.com>
	425
	426	PR target/19747
	427	* rl78-dis.c (print_insn_rl78_common): Fix typo.
	428
b0c11777 RL	429	2016-02-24 Renlin Li <renlin.li@arm.com>
	430
	431	* arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
	432	(print_insn_coprocessor): Support fp16 instructions.
	433
3e309328 RL	434	2016-02-24 Renlin Li <renlin.li@arm.com>
	435
	436	* arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
	437	vminnm, vrint(mpna).
	438
8afc7bea RL	439	2016-02-24 Renlin Li <renlin.li@arm.com>
	440
	441	* arm-dis.c (print_insn_coprocessor): Check co-processor number for
	442	cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
	443
4fd7268a L	444	2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
	445
	446	* i386-dis.c (print_insn): Parenthesize expression to prevent
	447	truncated addresses.
	448	(OP_J): Likewise.
	449
4670103e CZ	450	2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
	451	Janek van Oirschot <jvanoirs@synopsys.com>
	452
b99747ae CZ	453	* arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
b99747ae CZ	454	variable.
4670103e	455
c1d9289f NC	456	2016-02-04 Nick Clifton <nickc@redhat.com>
	457
	458	PR target/19561
	459	* msp430-dis.c (print_insn_msp430): Add a special case for
	460	decoding an RRC instruction with the ZC bit set in the extension
	461	word.
	462
a143b004 AB	463	2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
	464
	465	* cgen-ibld.in (insert_normal): Rework calculation of shift.
	466	* epiphany-ibld.c: Regenerate.
	467	* fr30-ibld.c: Regenerate.
	468	* frv-ibld.c: Regenerate.
	469	* ip2k-ibld.c: Regenerate.
	470	* iq2000-ibld.c: Regenerate.
	471	* lm32-ibld.c: Regenerate.
	472	* m32c-ibld.c: Regenerate.
	473	* m32r-ibld.c: Regenerate.
	474	* mep-ibld.c: Regenerate.
	475	* mt-ibld.c: Regenerate.
	476	* or1k-ibld.c: Regenerate.
	477	* xc16x-ibld.c: Regenerate.
	478	* xstormy16-ibld.c: Regenerate.
	479
b89807c6 AB	480	2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
	481
	482	* epiphany-dis.c: Regenerated from latest cpu files.
	483
d8c823c8 MM	484	2016-02-01 Michael McConville <mmcco@mykolab.com>
	485
	486	* cgen-dis.c (count_decodable_bits): Use unsigned value for mask
	487	test bit.
	488
5bc5ae88 RL	489	2016-01-25 Renlin Li <renlin.li@arm.com>
	490
	491	* arm-dis.c (mapping_symbol_for_insn): New function.
	492	(find_ifthen_state): Call mapping_symbol_for_insn().
	493
0bff6e2d MW	494	2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
	495
	496	* aarch64-opc.c (operand_general_constraint_met_p): Check validity
	497	of MSR UAO immediate operand.
	498
100b4f2e MR	499	2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
	500
	501	* mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
	502	instruction support.
	503
5c14705f AM	504	2016-01-17 Alan Modra <amodra@gmail.com>
	505
	506	* configure: Regenerate.
	507
4d82fe66 NC	508	2016-01-14 Nick Clifton <nickc@redhat.com>
	509
	510	* rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
	511	instructions that can support stack pointer operations.
	512	* rl78-decode.c: Regenerate.
	513	* rl78-dis.c: Fix display of stack pointer in MOVW based
	514	instructions.
	515
651657fa MW	516	2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
	517
	518	* aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
	519	testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
	520	erxtatus_el1 and erxaddr_el1.
	521
105bde57 MW	522	2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
	523
	524	* arm-dis.c (arm_opcodes): Add "esb".
	525	(thumb_opcodes): Likewise.
	526
afa8d405 PB	527	2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
	528
	529	* ppc-opc.c <xscmpnedp>: Delete.
	530	<xvcmpnedp>: Likewise.
	531	<xvcmpnedp.>: Likewise.
	532	<xvcmpnesp>: Likewise.
	533	<xvcmpnesp.>: Likewise.
	534
83c3256e AS	535	2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
	536
	537	PR gas/13050
	538	* m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
	539	addition to ISA_A.
	540
6f2750fe AM	541	2016-01-01 Alan Modra <amodra@gmail.com>
	542
	543	Update year range in copyright notice of all files.
	544
3499769a AM	545	For older changes see ChangeLog-2015
	546	\f
	547	Copyright (C) 2016 Free Software Foundation, Inc.
	548
	549	Copying and distribution of this file, with or without modification,
	550	are permitted in any medium without royalty provided the copyright
	551	notice and this notice are preserved.
	552
	553	Local Variables:
	554	mode: change-log
	555	left-margin: 8
	556	fill-column: 74
	557	version-control: never
	558	End: